14. Block interconnect

14.1 Peripheral interconnect

14.1.1 Introduction

Several peripherals have direct connections between them.

This enables autonomous communication and synchronization between peripherals, thus saving CPU resources and power consumption.

These hardware connections remove software latency, allow the design of a predictable system and result in a reduction of the number of pins and GPIOs.

14.1.2 Connection overview

There are several types of connections.

• • Asynchronous connections (A)
  The source output signal is sampled by the destination clock, leading to introduction of a possible jitter in the latency between the source output event and the destination event detection
• • Synchronous connections (S)
  Both source and destination are synchronous (they run on the same clock), and the latency from the source to the destination is deterministic. No jitter is introduced.
• • Immediate connections (I)
  Either the source or the destination is an analog signal.
• • Break/fault connection for TIM/HRTIM outputs (B)
  The source output signal disables the timer outputs through a pure combinational logic path, without any latency.

1. 1. Letters in the table correspond to the type of connection described in Section 14.1.2: Connection overview
2. 2. The “-” symbol in a gray cell means no interconnect.

Table 101. Peripherals interconnect matrix (D3 domain) ^{(1) (2)}

1. 1. Letters in the table correspond to the type of connection described in Section 14.1.2: Connection overview .
2. 2. The “-” symbol in a gray cell means no interconnect.

Table 102. Peripherals interconnect matrix details ⁽¹⁾ (continued)

Table 102. Peripherals interconnect matrix details ⁽¹⁾ (continued)

Table 102. Peripherals interconnect matrix details ⁽¹⁾ (continued)

Table 102. Peripherals interconnect matrix details ⁽¹⁾ (continued)

1. 1. Letters in the table correspond to the type of connection described in Section 14.1.2: Connection overview .
2. 2. comp1_out and comp2_out are connected to the inputs of an OR gate. The output of this OR gate is connected to the The lptim2_in1_mux3 input.

14.2 Wakeup from low power modes

The Extended interrupt and event controller module (EXTI) allows to wake up the system from Stop mode and/or a CPU from CStop mode. Wakeup events are coming from peripherals.

These events are handled by the EXTI either as Configurable events ( C ), or as Direct events ( D ). See Type column in Table 103 . Refer to Section 21: Extended interrupt and event controller (EXTI) for further details.

Three types of peripheral output signals are connected to the EXTI input events:

• • The wake up signals. These signals can be generated by the peripheral without any bus interface clock, they are referred to as xxx_wkup in Table 103 . Some peripherals do not have this capability.
• • The interrupt signals. These signals can be generated only if the peripheral bus interface clock is running. These interrupt signals are generally directly connected to the NVIC of CPU. They are referred to as xxx_it.
• • The signals, i.e. the pulses generated by the peripheral. Once a peripheral has generated a signal, no action (flag clearing) is required at peripheral level.

Each EXTI input event has a different wakeup capability or possible target (see Target column in Table 103 ):

• • CPU1 wakeup ( CPU1 ): the input event can be enabled to wake up the CPU1
• • CPU2 wakeup ( CPU2 ): the input event can be enabled to wake up the CPU2
• • CPU1 and CPU2 wakeups ( CPU ): the input event can be enabled to wake up the CPU1 only, the CPU2 only, or both CPU1 and CPU2
• • CPU1, CPU2 and D3 domain wakeup for autonomous Run mode ( ANY ): the input event can be enabled to wake up the CPU1 only, the CPU2 only, both CPU1 and CPU2, or the D3 domain only for an autonomous Run mode phase.

1. 1. The source peripheral needs its bus clock in order to generate the event. This is either PCLK4 or HCLK4 in D3 domain, PCLK3 in D1 domain.
2. 2. The source peripheral signal is not connected to the NVIC.

The Extended Interrupt and Event Controller (EXTI) module event inputs able to wake up the D3 domain for autonomous Run mode have a pending request logic that can be cleared by 4 different input sources ( Table 104 ). Refer to Section 21: Extended interrupt and event controller (EXTI) for further details.

Table 104. EXTI pending requests clear inputs

14.3 DMA

In D1 domain, the MDMA allows the memory to transfer data. It can be triggered by software or by hardware, according to the connections described in Section 14.3.1 .

DMA Multiplexer in D2 domain (DMAMUX1) allows to map any peripheral DMA request to any stream of the DMA1 or the DMA2. In addition to this, The DMAMUX provides two other functionalities:

• • It's possible to synchronize a peripheral DMA request with a timer, with an external pin or with a DMA transfer complete of another stream.
• • DMA requests can be generated on a stream by the DMAMUX1 itself. This event can be triggered by a timer, by an external pin event, or by a DMA transfer complete of another stream. The number of DMA requests generated is configurable.

The connections on DMAMUX1 and DMA1/DMA2 are described in Section 18: DMA request multiplexer (DMAMUX) , Section 16: Direct memory access controller (DMA) and Section 17: Basic direct memory access controller (BDMA) .

DMA Multiplexer in D3 domain (DMAMUX2) has the same functionality of DMAMUX1, it is connected to the basic DMA (BDMA).

The connections on DMAMUX2 and BDMA are described in Section 14.3.3: DMAMUX2, BDMA (D3 domain) . Refer to Section 14.3.3: DMAMUX2, BDMA (D3 domain) and Section 17: Basic direct memory access controller (BDMA) for more details.

14.3.1 MDMA (D1 domain)

Table 105. MDMA

Table 105. MDMA (continued)

14.3.2 DMAMUX1, DMA1 and DMA2 (D2 domain)

Table 106. DMAMUX1, DMA1 and DMA2 connections ⁽¹⁾

1. The “-” symbol in grayed cells means no interconnect.

14.3.3 DMAMUX2, BDMA (D3 domain)

Table 107. DMAMUX2 and BDMA connections

Table 107. DMAMUX2 and BDMA connections (continued)

Table 107. DMAMUX2 and BDMA connections (continued)