9. Reset and Clock Control (RCC)

The RCC block manages the clock and reset generation for the whole microcontroller, which embeds two CPUs: an Arm® Cortex®-M7 and an Arm® Cortex®-M4, called CPU1 and CPU2, respectively.

The RCC block is located in the D3 domain (refer to Section 7: Power control (PWR) for a detailed description).

The operating modes this section refers to are defined in Section 7.6.1: Operating modes of the PWR block.

9.1 RCC main features

Reset block

• • Generation of local and system reset
• • Bidirectional pin reset allowing to reset the microcontroller or external devices
• • Hold Boot function
• • WWDG reset supported

Clock generation block

• • Generation and dispatching of clocks for the complete device
• • 3 separate PLLs using integer or fractional ratios
• • Possibility to change the PLL fractional ratios on-the-fly
• • Smart clock gating to reduce power dissipation
• • 2 external oscillators:
  • – High-speed external oscillator (HSE) supporting a wide range of crystals from 4 to 48 MHz frequency
  • – Low-speed external oscillator (LSE) for the 32 kHz crystals
• • 4 internal oscillators
  • – High-speed internal oscillator (HSI)
  • – 48 MHz RC oscillator (HSI48)
  • – Low-power Internal oscillator (CSI)
  • – Low-speed internal oscillator (LSI)
• • Buffered clock outputs for external devices
• • Generation of two types of interrupts lines:
  • – Dedicated interrupt lines for clock security management
  • – One general interrupt line for other events
• • Clock generation handling in Stop and Standby mode
• • D3 domain Autonomous mode

9.2 RCC block diagram

Figure 48 shows the RCC block diagram.

Figure 48. RCC Block diagram

9.3 RCC pins and internal signals

Table 54 lists the RCC inputs and output signals connected to package pins or balls.

Table 54. RCC input/output signals connected to package pins or balls

The RCC exchanges a lot of internal signals with all components of the product, for that reason, the Table 54 only shows the most significant internal signals.

9.4 RCC reset block functional description

Several sources can generate a reset:

• • An external device via NRST pin
• • A failure on the supply voltage applied to \( V_{DD} \)
• • A watchdog timeout
• • A software command

The reset scope depends on the source that generates the reset. Three reset categories exist:

• • Power-on/off reset
• • System reset
• • Local resets

9.4.1 Power-on/off reset

The power-on/off reset ( pwr_por_rst ) is generated by the power controller block (PWR). It is activated when the input voltage ( \( V_{DD} \) ) is below a threshold level. This is the most complete reset since it resets the whole circuit, except for the backup domain. The power-on/off reset function can be disabled through PDR_ON pin (see Section 7.5: Power supply supervision ).

Refer to Table 56: Reset distribution summary for details.

9.4.2 System reset

A system reset ( nreset ) resets all registers to their reset values unless otherwise specified in the register description.

A system reset can be generated from one of the following sources:

• • A reset from NRST pin (external reset)
• • A reset from the power-on/off reset block ( pwr_por_rst )
• • A reset from the brownout reset block ( pwr_bor_rst )
  Refer to Section 7.5.2: Brownout reset (BOR) for a detailed description of the BOR function.
• • A reset from the independent watchdogs ( iwdg[2:1]_out_rst )
• • A software reset from the Cortex ^® -M4 core
  It is generated via the SYSRESETREQ signal issued by the Cortex ^® -M4 core. This signal is also named SFT2RESET in this document.
• • A software reset from the Cortex ^® -M7 core
  It is generated via the SYSRESETREQ signal issued by the Cortex ^® -M7 core. This signal is also named SFT1RESET in this document.
• • A reset from the window watchdogs ( wwdg[2:1]_out_rst )
• • A reset from the low-power mode security reset, depending on option byte configuration ( lpwr[2:1]_rst )

Note: The SYSRESETREQ bit in Cortex ^® -M7 Application Interrupt and Reset Control Register must be set to force a software reset on the device. Refer to the Cortex ^® -M7 with FPU technical reference manual for more details (see http://infocenter.arm.com ).

As shown in Figure 49 , some internal sources (such as pwr_por_rst , pwr_bor_rst , iwdg[2:1]_out_rst ) perform a system reset of the circuit, which is also propagated to the NRST pin to reset the connected external devices. The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal reset source. In case of an external reset, the reset pulse is generated while the NRST pin is asserted Low.

Note: It is not recommended to let the NRST pin unconnected. When it is not used, connect this pin to ground via a 10 to 100 nF capacitor ( \( C_R \) in Figure 49 ).

Figure 49. System reset circuit

9.4.3 Local resets

Domain reset

Some resets also dependent on the domain status. For example, when D1 domain exits from DStandby, it is reset ( d1_rst ). The same mechanism applies to D2.

When the system exits from Standby mode, an stby_rst reset is applied. The stby_rst signal generates a reset of the complete V _CORE domain as long the V _CORE voltage provided by the internal regulator is not valid.

Table 56 gives a detailed overview of reset sources and scopes.

Table 56. Reset distribution summary

Table 56. Reset distribution summary (continued)

Table 56. Reset distribution summary (continued)

9.4.4 Reset source identification

Each CPU can identify the reset source by checking the reset flags in the RCC_C1_RSR and RCC_C2_RSR registers:

• • CPU1 can check the reset source by reading either RCC_RSR or RCC_C1_RSR registers.
• • CPU2 can check the reset the source by reading either RCC_RSR or RCC_C2_RSR registers.

Each CPU can reset the flags of its own register by setting RMVF bit without interfering with the other CPU (refer to RCC reset status register (RCC_RSR) for a detailed description).

Table 57 shows how the status bits of RCC_RSR register behaves, according to the situation that generated the reset. For example when an IWDG1 timeout occurs (line #10), if the CPU is reading the RCC_RSR register during the boot phase, both PINRSTF and IWDG1RSTF bits are set, indicating that the IWDG1 also generated a pin reset.

1. Grayed cells highlight the register bits that are set.

9.4.5 Low-power mode security reset (lpwr[2:1]_rst)

To prevent critical applications from mistakenly enter a low-power mode, two low-power mode security resets are available. When enabled through nRST_STOP_C[2:1] option bytes, a system reset is generated if the following conditions are met:

• • CPU1 and/or CPU2 accidentally enters CStop mode
  This type of reset is enabled by resetting nRST_STOP_C[2:1] user option bytes. In this case, whenever a CPU1/2 CStop mode entry sequence is successfully executed, a system reset is generated.
• • D1 domain and/or D2 accidentally enters DStandby mode
  This type of reset is enabled by resetting nRST_STDBY_D[2:1] user option bytes. In this case, whenever a domain D1 or D2 DStandby mode entry sequence is successfully executed, a system reset is generated.

LPWR[2:1]RSTF bits in RCC reset status register (RCC_RSR) indicate that a low-power mode security reset occurred (see line #14 and #15 in Table 57 ).

lpwr1_rst is activated when a low-power mode security reset due to D1 or CPU1 occurred, while lpwr2_rst is activated when a low-power mode security reset due to D2 or CPU2 occurred.

Refer to Section 4.4: FLASH option bytes for additional information.

9.4.6 Backup domain reset

A backup domain reset is generated when one of the following events occurs:

• • A software reset, triggered by setting BDRST bit in the RCC Backup domain control register (RCC_BDCR) . All RTC registers and the RCC_BDCR register are reset to their default values. The backup RAM is not affected.
• • \( V_{SW} \) voltage is outside the operating range. All RTC registers and the RCC_BDCR register are reset to their default values. In this case the content of the backup RAM is no longer valid.

There are two ways to reset the backup RAM:

• • through the Flash memory interface by requesting a protection level change from 1 to 0
• • when a tamper event occurs.

Refer to Section 7.4.4: Backup domain section of PWR block for additional information.

9.4.7 Power-on and wakeup sequences

For detailed diagrams refer to Section 7.4.1: System supply startup in the PWR section.

The time interval between the event which exits the product from a low-power and the moment where the CPUs are able to execute code, depends on the system state and on its configuration. Figure 50 shows the most usual examples.

Power-on wakeup sequence

The power-on wakeup sequence shown in Figure 50 gives the most significant phases of the power-on sequence. It is the longest sequence since the circuit was not powered. Note that this sequence remains unchanged, whatever \( V_{BAT} \) was present or not.

Boot from pin reset

When a pin reset occurs, \( V_{DD} \) is still present. As a result:

• • The regulator settling time is faster since the reference voltage is already stable.
• • The HSI restart delay may be needed if the HSI was not enabled when the NRST occurred, otherwise this restart delay phase is skipped.
• • The Flash memory power recovery delay can also be skipped if the Flash memory was enabled when the NRST occurred.

Note: The boot sequence is similar for pwr_bor_rst, lpwrx_rst, STFxRESET, iwdgx_out_rst and wwdgx_out_rst.

Boot from system Standby

When waking up from system Standby, the reference voltage is stable since \( V_{DD} \) has not been removed. As a result, the regulator settling time is fast. Since \( V_{CORE} \) was not present, the restart delay for the HSI, the Flash memory power recovery and the option byte reloading cannot be skipped.

Restart from system Stop

When restarting from system Stop, \( V_{DD} \) is still present. As a result, the sequence is mainly composed of two steps:

1. 1. Regulator settling time to reach VOS3 (default voltage)
2. 2. HSI/CSI restart delay. This step can be skipped if HSIKERON or CSIKERON bit, in RCC source control register (RCC_CR) is set to '1'.

Boot from domain DStandby

The boot sequence of a domain from domain DStandby is mainly composed of two steps:

1. 1. The power switch settling time (the regulator is already activated).
2. 2. The Flash memory power recovery, if the domain which exits from DStandby is D1, otherwise this step is skipped.

Restart from domain DStop

The restart sequence of a domain from domain DStop is mainly composed of the handshake between the RCC, EXTI and PWR blocks.

Figure 50. Boot sequences versus system states

Hold boot function

It is possible to put one of the two CPUs on hold after a system reset or when the device exits from Standby. This function is controlled by two option bytes, BCM4 and BCM7, and two bits, BOOT_C1 and BOOT_C2, located in the RCC global control register (RCC_GCR) :

• • When BCM4 or BCM7 option byte is set to '1', the corresponding CPU is allowed to boot after a system reset or when the device exits from Standby.
• • When BCM4 or BCM7 option byte is set to '0', the corresponding CPU is not allowed to boot, and remains on hold as long as the corresponding BOOT_Cx bit is set to '0'.
• • CPUx will be allowed to boot when BOOT_Cx is set to '1'. A protection mechanism insures that at least one of the 2 CPUs will boot (see Table 58 ).

The hold boot function is provided in order to support configurations where one CPU is master of the system and shall complete the initialization of the whole device (system clock, voltage scaling...) before activating the second CPU.

Note: After a system reset or system Standby, the BOOT_C1 and BOOT_C2 bits are set to '0'.

1. Setting both BCM4 and BCM7 bits to '0' forces the boot from CPU1.

9.5 RCC clock block functional description

The RCC provides a wide choice of clock generators:

• • HSI (High-speed internal oscillator) clock: ~ 8, 16, 32 or 64 MHz
• • HSE (High-speed external oscillator) clock: 4 to 48 MHz
• • LSE (Low-speed external oscillator) clock: 32 kHz
• • LSI (Low-speed internal oscillator) clock: ~ 32 kHz
• • CSI (Low-power internal oscillator) clock: ~4 MHz
• • HSI48 (High-speed 48 MHz internal oscillator) clock: ~48 MHz

It offers a high flexibility for the application to select the appropriate clock for CPUs and peripherals, in particular for peripherals that require a specific clock such as Ethernet, USB OTG-FS and HS, SPI/I2S, SAI and SDMMC.

To optimize the power consumption, each clock source can be switched ON or OFF independently.

The RCC provides up to 3 PLLs; each of them can be configured with integer or fractional ratios.

As shown in the Figure 51 , the RCC offers 2 clock outputs (MCO1 and MCO2), with a great flexibility on the clock selection and frequency adjustment.

The SCGU block (System Clock Generation Unit) contains several prescalers used to configure the CPU and bus matrix clock frequencies.

The PKSU block (Peripheral Kernel clock Selection Unit) provides several dynamic switches allowing a large choice of kernel clock distribution to peripherals.

The PKEU (Peripheral Kernel clock Enable Unit) and SCEU (System Clock Enable Unit) blocks perform the peripheral kernel clock gating, and the bus interface/cores/bus matrix clock gating, respectively.

Figure 51. Top-level clock tree

9.5.1 Clock naming convention

The RCC provides clocks to the complete circuit. To avoid misunderstanding, the following terms are used in this document:

• • Peripheral clocks

The peripheral clocks are the clocks provided by the RCC to the peripherals. Two kinds of clock are available:

• – The bus interface clocks
• – The kernel clocks

A peripheral receives from the RCC a bus interface clock in order to access its registers, and thus control the peripheral operation. This clock is generally the AHB, APB or AXI clock depending on which bus the peripheral is connected to. Some peripherals only need a bus interface clock (e.g. RNG, TIMx).

Some peripherals also require a dedicated clock to handle the interface function. This clock is named “kernel clock”. As an example, peripherals such as SAI have to generate specific and accurate master clock frequencies, which require dedicated kernel clock frequencies. Another advantage of decoupling the bus interface clock from the specific interface needs, is that the bus clock can be changed without reprogramming the peripheral.

• • CPU clocks

The CPU clock is the clock provided to the CPUs. It is derived from the system clock ( sys_ck ).

• • Bus matrix clocks

The bus matrix clocks are the clocks provided to the different bridges (APB, AHB or AXI). These clocks are derived from the system clock ( sys_ck ).

9.5.2 Oscillators description

HSE oscillator

The HSE block can generate a clock from two possible sources:

• • External crystal/ceramic resonator
• • External clock source

Figure 52. HSE/LSE clock source

External clock source (HSE bypass)

In this mode, an external clock source must be provided to OSC_IN pin. This mode is selected by setting the HSEBYP and HSEON bits of the RCC source control register (RCC_CR) to '1'. The external clock source (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin.

External crystal/ceramic resonator

The oscillator is enabled by setting the HSEBYP bit to '0' and HSEON bit to '1'.

The HSE can be used when the product requires a very accurate high-speed clock.

The associated hardware configuration is shown in Figure 52 : the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected crystal or ceramic resonator. Refer to the electrical characteristics section of the datasheet for more details.

The HSERDY flag of the RCC source control register (RCC_CR) , indicates whether the HSE oscillator is stable or not. At startup, the hse_ck clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock source interrupt enable register (RCC_CIER) .

The HSE can be switched ON and OFF through the HSEON bit. Note that the HSE cannot be switched OFF if one of the two conditions is met:

• • The HSE is used directly (via software mux) as system clock
• • The HSE is selected as reference clock for PLL1, with PLL1 enabled and selected to provide the system clock (via software mux).

In that case the hardware does not allow programming the HSEON bit to '0'.

The HSE is automatically disabled by hardware, when the system enters Stop or Standby mode (refer to Section 9.5.7: Handling clock generators in Stop and Standby mode for additional information).

In addition, the HSE clock can be driven to the MCO1 and MCO2 outputs and used as clock source for other application components.

LSE oscillator

The LSE block can generate a clock from two possible sources:

• • External crystal/ceramic resonator
• • External user clock

External clock source (LSE bypass)

In this mode, an external clock source must be provided to OSC32_IN pin. The input clock can have a frequency up to 1 MHz. This mode is selected by setting the LSEBYP and LSEON bits of RCC Backup domain control register (RCC_BDCR) to '1'. The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC32_IN pin.

External crystal/ceramic resonator (LSE crystal)

The LSE clock is generated from a 32.768 kHz crystal or ceramic resonator. It has the advantage to provide a low-power highly accurate clock source to the real-time clock (RTC) for clock/calendar or other timing functions.

The LSERDY flag of the RCC Backup domain control register (RCC_BDCR) indicates whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock source interrupt enable register (RCC_CIER) .

The LSE oscillator is switched ON and OFF using the LSEON bit. The LSE remains enabled when the system enters Stop or Standby mode.

In addition, the LSE clock can be driven to the MCO1 output and used as clock source for other application components.

The LSE also offers a programmable driving capability (LSEDRV[1:0]) that can be used to modulate the amplifier driving capability. The driving capability cannot be changed when the LSE oscillator is ON.

HSI oscillator

The HSI block provides the default clock to the product.

The HSI is a high-speed internal RC oscillator which can be used directly as system clock, peripheral clock, or as PLL input. A prescaler allows the application to select an HSI output frequency of 8, 16, 32 or 64 MHz. This prescaler is controlled by the HSIDIV.

The HSI advantages are the following:

• • Low-cost clock source since no external crystal is required
• • Faster startup time than HSE (a few microseconds)

The HSI frequency, even with frequency calibration, is less accurate than an external crystal oscillator or ceramic resonator.

The HSI can be switched ON and OFF using the HSION bit. Note that the HSI cannot be switched OFF if one of the two conditions is met:

• • The HSI is used directly (via software mux) as system clock
• • The HSI is selected as reference clock for PLL1, with PLL1 enabled and selected to provide the system clock (via software mux).

In that case the hardware does not allow programming the HSION bit to '0'.

Note that the HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to '1'). In that case the hardware does not update the HSIDIV with the new value. However it is possible to change the HSIDIV if the HSI is used directly as system clock.

The HSIRDY flag indicates if the HSI is stable or not. At startup, the HSI output clock is not released until this bit is set by hardware.

The HSI clock can also be used as a backup source (auxiliary clock) if the HSE fails (refer to Section : CSS on HSE ). The HSI can be disabled or not when the system enters Stop mode, please refer to Section 9.5.7: Handling clock generators in Stop and Standby mode for additional information.

In addition, the HSI clock can be driven to the MCO1 output and used as clock source for other application components.

Care must be taken when the HSI is used as kernel clock for communication peripherals, the application must take into account the following parameters:

• • the time interval between the moment where the peripheral generates a kernel clock request and the moment where the clock is really available,
• • the frequency accuracy.

Note: The HSI can remain enabled when the system is in Stop mode (see Section 9.5.7 for additional information ).

HSION, HSIRDY and HSIDIV bits are located in the RCC source control register (RCC_CR) .

HSI calibration

RC oscillator frequencies can vary from one chip to another due to manufacturing process variations. That is why each device is factory calibrated by STMicroelectronics to improve accuracy (refer to the product datasheet for more information).

After a power-on reset, the factory calibration value is loaded in the HSICAL[11:0] bits.

If the application is subject to voltage or temperature variations, this may affect the RC oscillator frequency. The user application can trim the HSI frequency using the HSITRIM[6:0] bits.

Note: HSICAL[11:0] and HSITRIM[6:0] bits are located in the RCC HSI configuration register (RCC_HSICFGR) .

CSI oscillator

The CSI is a low-power RC oscillator which can be used directly as system clock, peripheral clock, or PLL input.

The CSI advantages are the following:

• • Low-cost clock source since no external crystal is required
• • Faster startup time than HSE (a few microseconds)
• • Very low-power consumption,

The CSI provides a clock frequency of about 4 MHz, while the HSI is able to provide a clock up to 64 MHz.

CSI frequency, even with frequency calibration, is less accurate than an external crystal oscillator or ceramic resonator.

The CSI can be switched ON and OFF through the CSION bit. The CSIRDY flag indicates whether the CSI is stable or not. At startup, the CSI output clock is not released until this bit is set by hardware.

The CSI cannot be switched OFF if one of the two conditions is met:

• • The CSI is used directly (via software mux) as system clock
• • The CSI is selected as reference clock for PLL1, with PLL1 enabled and selected to provide the system clock (via software mux).

In that case the hardware does not allow programming the CSION bit to '0'.

The CSI can be disabled or not when the system enters Stop mode (refer to Section 9.5.7: Handling clock generators in Stop and Standby mode for additional information).

In addition, the CSI clock can be driven to the MCO2 output and used as clock source for other application components.

Even if the CSI settling time is faster than the HSI, care must be taken when the CSI is used as kernel clock for communication peripherals: the application has to take into account the following parameters:

• • the time interval between the moment where the peripheral generates a kernel clock request and the moment where the clock is really available,
• • the frequency precision.

Note: CSION and CSIRDY bits are located in the RCC source control register (RCC_CR) .

CSI calibration

RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by STMicroelectronics to improve accuracy (refer to the product datasheet for more information).

After reset, the factory calibration value is loaded in the CSICAL[9:0] bits.

If the application is subject to voltage or temperature variations, this may affect the RC oscillator frequency. The user application can trim the CSI frequency using the CSITRIM[5:0] bits.

Note: CSICAL[9:0] and CSITRIM[5:0] bits are located into the RCC CSI configuration register (RCC_CSICFG)

HSI48 oscillator

The HSI48 is an RC oscillator that delivers a 48 MHz clock that can be used directly as kernel clock for some peripherals.

The internal HSI48 oscillator mainly aims at providing a high precision clock to the USB peripheral by means of a special Clock Recovery System (CRS) circuitry, which could use the USB SOF signal, the LSE, or an external signal, to automatically adjust the oscillator frequency on-the-fly, in very small granularity.

The HSI48 oscillator is disabled as soon as the system enters Stop or Standby mode. When the CRS is not used, this oscillator is free running and thus subject to manufacturing process variations. That is why each device is factory calibrated by STMicroelectronics to achieve an accuracy of ACC _HSI48 (refer to the product datasheet for more information).

For more details on how to configure and use the CRS, please refer to Section 10: Clock recovery system (CRS) .

The HSI48RDY flag indicates whether the HSI48 oscillator is stable or not. At startup, the HSI48 output clock is not released until this bit is set by hardware.

The HSI48 can be switched ON and OFF using the HSI48ON bit.

The HSI48 clock can also be driven to the MCO1 multiplexer and used as clock source for other application components.

Note: HSI48ON and HSI48RDY bits are located in the RCC source control register (RCC_CR) .

LSI oscillator

The LSI acts as a low-power clock source that can be kept running when the system is in Stop or Standby mode for the independent watchdog (IWDG) and Auto-Wakeup Unit (AWU). The clock frequency is around 32 kHz. For more details, refer to the electrical characteristics section of the datasheet.

The LSI can be switched ON and OFF using the LSION bit. The LSIRDY flag indicates whether the LSI oscillator is stable or not. If an independent watchdog is started either by hardware or software, the LSI is forced ON and cannot be disabled.

The LSI remains enabled when the system enters Stop or Standby mode (refer to Section 9.5.7: Handling clock generators in Stop and Standby mode for additional information).

At LSI startup, the clock is not provided until the hardware sets the LSIRDY bit. An interrupt can be generated if enabled in the RCC clock source interrupt enable register (RCC_CIER) .

In addition, the LSI clock can be driven to the MCO2 output and used as a clock source for other application components.

Note: Bits LSION and LSIRDY are located into the RCC clock control and status register (RCC_CSR) .

9.5.3 Clock Security System (CSS)

CSS on HSE

The clock security system can be enabled by software via the HSECSSON bit. The HSECSSON bit can be enabled even when the HSEON is set to '0'.

The CSS on HSE is enabled by the hardware when the HSE is enabled and ready, and HSECSSON set to '1'.

The CSS on HSE is disabled when the HSE is disabled. As a result, this function does not work when the system is in Stop mode.

It is not possible to clear directly the HSECSSON bit by software.

The HSECSSON bit is cleared by hardware when a system reset occurs or when the system enters Standby mode (see Section 9.4.2: System reset ).

If a failure is detected on the HSE clock, the system automatically switches to the HSI in order to provide a safe clock. The HSE is then automatically disabled, a clock failure event is sent to the break inputs of advanced-control timers (TIM1, TIM8, TIM15, TIM16, and TIM17), and an interrupt is generated to inform the software about the failure (CSS interrupt: rcc_hsecss_it ), thus allowing the MCU to perform rescue operations. If the HSE output was used as clock source for PLLs when the failure occurred, the PLLs are also disabled.

If an HSE clock failure occurs when the CSS is enabled, the CSS generates an interrupt which causes the automatic generation of an NMI. The HSECSSF flag in RCC clock source interrupt flag register (RCC_CIFR) is set to '1' to allow the application to identify the failure source. The NMI routine is executed indefinitely until the HSECSSF bit is cleared. As a consequence, the application has to clear the HSECSSF flag in the NMI ISR by setting the HSECSSC bit in the RCC clock source interrupt clear register (RCC_CICR) .

CSS on LSE

A clock security system on the LSE oscillator can be enabled by software by programming the LSECSSON bit in the RCC Backup domain control register (RCC_BDCR) .

This bit can be disabled only by hardware when the following conditions are met:

• • after a pwr_vsw_rst ( \( V_{SW} \) software reset)
• • or after a failure detection on LSE.

LSECSSON bit must be written after the LSE is enabled (LSEON bit set by software) and ready (LSERDY set by hardware), and after the RTC clock has been selected through the RTCSEL bit.

The CSS on LSE works in all modes (Run, Stop and Standby) except VBAT.

If an LSE failure is detected, the LSE clock is no more delivered to the RTC but the value of RTCSEL, LSECSSON and LSEON bits are not changed by the hardware.

A wakeup is generated in Standby mode. In other modes an interrupt ( rcc_lsecss_it ) can be sent to wake up the software. The software must then disable the LSECSSON bit, stop the defective LSE (clear LSEON bit), and can change the RTC clock source (no clock or LSI or HSE) through RTCSEL bits, or take any required action to secure the application.

9.5.4 Clock output generation (MCO1/MCO2)

Two micro-controller clock output (MCO) pins, MCO1 and MCO2, are available. A clock source can be selected for each output. The selected clock can be divided thanks to configurable prescaler (refer to Figure 51 for additional information on signal selection).

MCO1 and MCO2 outputs are controlled via MCO1PRE[3:0], MCO1SEL[2:0], MCO2PRE[3:0] and MCO2SEL[2:0] located in the RCC clock configuration register (RCC_CFGR) .

The GPIO port corresponding to each MCO pin, has to be programmed in alternate function mode.

The clock provided to the MCOs outputs must not exceed the maximum pin speed (refer to the product datasheet for information on the supported pin speed).

9.5.5 PLL description

The RCC features three PLLs:

• • A main PLL, PLL1, which is generally used to provide clocks to the CPUs and to some peripherals.
• • Two dedicated PLLs, PLL2 and PLL3, which are used to generate the kernel clock for peripherals.

The PLLs integrated into the RCC are completely independent. They offer the following features:

• • Two embedded VCOs:
  • – A wide-range VCO (VCOH)
  • – A low-frequency VCO (VCOL)
• • Input frequency range:
  • – 1 to 2 MHz when VCOL is used
  • – 2 to 16 MHz when VCOH is used
• • Capability to work either in integer or Fractional mode
• • 13-bit Sigma-Delta modulator, allowing to fine-tune the VCO frequency by steps of 11 to 0.3 ppm.
• • The Sigma-Delta modulator can be updated on-the-fly, without generating frequency overshoots on PLLs outputs.
• • Each PLL offer 3 outputs with post-dividers

Figure 53. PLL block diagram

The PLLs are controlled via RCC_PLLxDIVR, RCC_PLLxFRACR, RCC_PLLCFGGR and RCC_CR registers.

The frequency of the reference clock provided to the PLLs ( refx_ck ) must range from 1 to 16 MHz. The user application has to program properly the DIVMx dividers of the RCC PLLs clock source selection register (RCC_PLLCKSELR) in order to match this condition. In addition, the PLLxRGE of the RCC PLL configuration register (RCC_PLLCFGGR) field must be set according to the reference input frequency to guarantee an optimal performance of the PLL.

The user application can then configure the proper VCO: if the frequency of the reference clock is lower or equal to 2 MHz, then VCOL must be selected, otherwise VCOH must be chosen. To reduce the power consumption, it is recommended to configure the VCO output to the lowest frequency.

DIVNx loop divider has to be programmed to achieve the expected frequency at VCO output. In addition, the VCO output range must be respected.

The PLLs operate in integer mode when the value of SH_REG (FRACNx shadow register) is set to '0'. The SH_REG is updated with the FRACNx value when PLLxFRACEN bit goes from '0' to '1'. The Sigma-Delta modulator is designed in order to minimize the jitter impact while allowing very small frequency steps.

The PLLs can be enabled by setting PLLxON to '1'. The bits PLLxRDY indicate that the PLL is ready (i.e. locked).

Note: Before enabling the PLLs, make sure that the reference frequency ( refx_ck ) provided to the PLL is stable, so the hardware does not allow changing DIVMx when the PLLx is ON and it is also not possible to change PLLSRC when one of the PLL is ON.

The hardware prevents writing PLL1ON to '0' if the PLL1 is currently used to deliver the system clock. There are other hardware protections on the clock generators (refer to sections HSE oscillator , HSI oscillator and CSI oscillator ).

The following PLL parameters cannot be changed once the PLL is enabled: DIVNx, PLLxRGE, PLLxVCOSEL, DIVPx, DIVQx, DIVRx, DIVPxEN, DIVQxEN and DIVRxEN.

To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) is not used, the application shall set the enable bit (DIVyEN) as well as the corresponding post-divider bits (DIVP, DIVQ or DIVR) to '0'.

If the above rules are not respected, the PLL output frequency is not guaranteed.

Output frequency computation

When the PLL is configured in integer mode (SH_REG = '0'), the VCO frequency ( \( F_{VCO} \) ) is given by the following expression:

When the PLL is configured in fractional mode (SH_REG different from '0'), the DIVN divider must be initialized before enabling the PLLs. However, it is possible to change the value of FRACNx on-the-fly without disturbing the PLL output.

This feature can be used either to generate a specific frequency from any crystal value with a good accuracy, or to fine-tune the frequency on-the-fly.

For each PLL, the VCO frequency is given by the following formula:

Note: For PLL1, DIVP can only take odd values.

The PLLs are disabled by hardware when:

• • The system enters Stop or Standby mode.
• • An HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock.

PLL initialization phase

Figure 54 shows the recommended PLL initialization sequence in integer and fractional mode. The PLLx are supposed to be disabled at the start of the initialization sequence:

1. 1. Initialize the PLLs registers according to the required frequency.
   • – Set PLLxFRACEN of RCC PLL configuration register (RCC_PLLCFGR) to '0' for integer mode.
   • – For fractional mode, set FRACN to the required initial value (FracInitValue) and then set PLLxFRACEN to '1'.
2. 2. Once the PLLxON bit is set to '1', the user application has to wait until PLLxRDY bit is set to '1'. If the PLLx is in fractional mode, the PLLxFRACEN bit must not be set back to '0' as long as PLLxRDY = '0'.
3. 3. Once the PLLxRDY bit is set to '1', the PLLx is ready to be used.
4. 4. If the application intends to tune the PLLx frequency on-the-fly (possible only in fractional mode), then:
   1. a) PLLxFRACEN must be set to '0',
      When PLLxFRACEN = '0', the Sigma-Delta modulator is still operating with the value latched into SH_REG.
      Application must wait for 3 refx_ck clock periods (PLLxFRACEN bit propagation delay)
   2. b) A new value must be uploaded into PLLxFRACR (FracValue(n)).
   3. c) PLLxFRACEN must be set to '1', in order to latch the content of PLLxFRACR into its shadow register.
      The new value is considered after 3 clock periods of refx_ck (PLLxFRACEN bit propagation delay)

Note: When the PLLxRDY goes to '1', it means that the difference between the PLLx output frequency and the target value is lower than \( \pm 2\% \) .

Figure 54. PLLs Initialization Flowchart

graph TD
    subgraph IntegerMode [ ]
        I1([PLL enable sequence
integer mode]) --> I2[Select clock source (RCC_CKSELR)
- (PLLSRC)]
        I2 --> I3[Init pre-divider (RCC_CKSELR)
- DIVMx]
        I3 --> I4["PLLx config (RCC_PLLCFGR)
- PLLxVCOSEL, PLLxRGE
- PLLxFRACEN = 0
- DIVPxEN, DIVQxEN, DIVRxEN
Init PLLx dividers (RCC_PLLxDIVR)
- DIVNx, DIVPx, DIVQx, DIVRx"]
        I4 --> I5[Enable PLLx (RCC_CR)
- PLLxON = 1]
        I5 --> I6{PLLxRDY = 1 ?}
        I6 -- No --> I6
        I6 -- Yes --> I7([Ready for use in integer
mode])
    end

    subgraph FractionalMode [ ]
        F1([PLL enable sequence
fractional mode]) --> F2[Select clock source (RCC_CKSELR)
- (PLLSRC)]
        F2 --> F3[Init pre-divider (RCC_CKSELR)
- DIVMx]
        F3 --> F4["Init fractional value (RCC_PLLxFRACR)
- FRACN = FracInitValue
PLLx config (RCC_PLLCFGR)
- PLLxVCOSEL, PLLxRGE
- PLLxFRACEN = 1
- DIVPxEN, DIVQxEN, DIVRxEN
Init PLLx dividers (RCC_PLLxDIVR)
- DIVNx, DIVPx, DIVQx, DIVRx"]
        F4 --> F5[Enable PLLx (RCC_CR)
- PLLxON = 1]
        F5 --> F6{PLLxRDY = 1 ?}
        F6 -- No --> F6
        F6 -- Yes --> F7([Ready for use in
fractional mode])
    end

    F7 --> F8["Disable fractional mode (RCC_PLLCFGR)
- PLLxFRACEN = 0
Init fractional value (RCC_PLLxFRACR)
- FRACN = FracValue(n)
Enable fractional mode (RCC_PLLCFGR)
- PLLxFRACEN = 1"]
    F8 --> F9([Ready for use in
fractional mode])
    F9 --> F8

    style IntegerMode fill:none,stroke:none
    style FractionalMode fill:none,stroke:none

9.5.6 System clock (sys_ck)

System clock selection

After a system reset, the HSI is selected as system clock and all PLLs are switched OFF. When a clock source is used for the system clock, it is not possible for the software to disable the selected source via the xxxON bits.

Of course, the system clock can be stopped by the hardware when the System enters Stop or Standby mode.

When the system is running, the user application can select the system clock ( sys_ck ) among the 4 following sources:

• • HSE
• • HSI
• • CSI
• • or pll1_p_ck

This function is controlled by programming the RCC clock configuration register (RCC_CFGR) . A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source that is not yet ready is selected, the switch occurs when the clock source is ready.

The SWS status bits in the RCC clock configuration register (RCC_CFGR) indicate which clock is currently used as system clock. The other status bits in the RCC_CR register indicate which clock(s) is (are) ready.

System clock generation

Figure 55 shows a simplified view of the clock distribution for the CPUs and busses. All the dividers shown in the block diagram can be changed on-the-fly without generating timing violations. This feature is a very simply solution to adapt the busses frequencies to the application needs, thus optimizing the power consumption.

The D1CPRE divider can be used to adjust CPU1 clock. However this also impacts the clock frequency of all bus matrix, CPU2, and HRTIM.

In the same way, HPRE divider can be used to adjust the clock for D1 domain bus matrix, but this also impacts the clock frequency of bus matrix of D2 and D3 domains, and CPU2.

In addition the CPU clock frequency can be equal to the bus matrix clock frequency, but the maximum frequency for the bus matrix is limited to 200 MHz.

Most of the prescalers are controlled via RCC_D1CFGR, RCC_D2CFGR and RCC_D3CFGR registers.

Figure 55. Core and bus clock generation

This block also provides the clock for the timers ( rcc_timx_ker_ck and rcc_timy_ker_ck ). The frequency of the timers clock depends on the APB prescaler corresponding to the bus to which the timer is connected, and on TIMPRE bit. Table 59 shows how to select the timer clock frequency.

Table 59. Ratio between clock timer and pclk

1. D2PPRE1 and D2PPRE2 belong to RCC domain 2 clock configuration register (RCC_D2CFGR) .

2. TIMPRE belongs to RCC clock configuration register (RCC_CFGR) .

9.5.7 Handling clock generators in Stop and Standby mode

When the whole system enters Stop mode, all the clocks (system and kernel clocks) are stopped as well as the following clock sources:

• • CSI, HSI (depending on HSIKERON, and CSIKERON bits)
• • HSE
• • PLL1, PLL2 and PLL3
• • HSI48

The content of the RCC registers is not altered except for PLL1ON, PLL2ON, PLL3ON, HSEON and HSI48ON which are set to '0'.

Exiting Stop mode

When the microcontroller exits system Stop mode via a wake-up event, the application can select which oscillator (HSI and/or CSI) will be used to restart. The STOPWUCK bit selects the oscillator used as system clock. The STOPKERWUCK bit selects the oscillator used as kernel clock for peripherals. The STOPKERWUCK bit is useful if after a system Stop a peripheral needs a kernel clock generated by an oscillator different from the one used for the system clock.

All these bits belong to the RCC clock configuration register (RCC_CFGR) . Table 60 gives a detailed description of their behavior.

Table 60. STOPWUCK and STOPKERWUCK description

During Stop mode

There are two specific cases where the HSI or CSI can be enabled during system Stop mode:

• • When a dedicated peripheral requests the kernel clock:
  In this case the peripheral will receive the HSI or CSI according to the kernel clock source selected for this peripheral (via PERxSRC).
• • When the bits HSIKERON or CSIKERON are set:
  In this case the HSI and CSI are kept running during Stop mode but the outputs are gated. In that way, the clock will be available immediately when the system exits Stop mode or when a peripheral requests the kernel clock (see Table 61 for details).

HSIKERON and CSIKERON bits belong to RCC source control register (RCC_CR) . Table 61 gives a detailed description of their behavior.

Table 61. HSIKERON and CSIKERON behavior

1. 1. \( t_{su(HSI)} \) and \( t_{su(CSI)} \) are the startup times of the HSI and CSI oscillators (see refer to the product datasheet for the values of these parameters).

When the microcontroller exits system Standby mode, the HSI is selected as system and kernel clock, the RCC registers are reset to their initial values except for the RCC_RSR and RCC_BDCR registers.

Note as well that the HSI and CSI outputs provide two clock paths (see Figure 51 ):

• • one path for the system clock ( hsi_ck or csi_ck )
• • one path for the peripheral kernel clock ( hsi_ker_ck or csi_ker_ck ).

When a peripheral requests the kernel clock in system Stop mode, only the path providing the hsi_ker_ck or csi_ker_ck is activated.

Caution: It is not guaranteed that a CPU will get automatically the same clock frequencies when leaving CStop mode: this mainly depends on the System state. For example CPU2 can switch from time to time from CRun to CStop mode. If the system does not go to Stop or Standby mode, then the system clock is not stopped and CPU2 will operate from it when

leaving CStop mode. However, if the system enters Stop while CPU2 is in CStop mode, then CPU2 will operate from HSI or CSI when it left the CStop mode.

9.5.8 Kernel clock selection

Some peripherals are designed to work with two different clock domains that operate asynchronously:

• • a clock domain synchronous with the register and bus interface ( ckg_bus_perx clock)
• • and a clock domain generally synchronous with the peripheral (kernel clock).

The benefit of having peripherals supporting these two clock domains is that the user application has more freedom to choose optimized clock frequency for the CPUs, bus matrix and for the kernel part of the peripheral.

As a consequence, the user application can change the bus frequency without reprogramming the peripherals. As an example an on-going transfer with UART will not be disturbed if its APB clock is changed on-the-fly.

Table 62 shows the kernel clock that the RCC can deliver to the peripherals. Each row of Table 62 represents a MUX and the peripherals connected to its output. The columns starting from number 4 represent the clock sources. Column 3 gives the maximum allowed frequency at each MUX output. It is up to the user to respect these requirements.

Table 62. Kernel clock distribution overview

Table 62. Kernel clock distribution overview (continued)

1. The bus clocks are the bus interface clocks to which the peripherals are connected, it can be APB, AHB or AXI clocks.

2. The per_ck clock could be hse_ck, hsi_ker_ck or csi_ker_ck according to CKPERSEL selection.

3. For byte lane clock frequency ( \( F_{blclk\_ck} \) ).

4. Clock CSI divided by 122.

5. With a duty cycle close to 50%, meaning that DIV[P/Q/R]x values shall be even. For SDMMCx, the duty cycle shall be 50% when supporting DDR.

6. The RTC is not functional in \( V_{BAT} \) mode when the clock source is lsi_ck or hse_ck.

Figure 56 to Figure 65 provide a more detailed description of kernel clock distribution. To simplify the drawings, the bus interface clocks (pclk, hclk) are not represented, even if they are gated with enable signals. Refer to Section 9.5.11: Peripheral clock gating control for more details.

To reduce the amount of switches, some peripherals share the same kernel clock source. Nevertheless, all peripherals have their dedicated enable signal.

Peripherals dedicated to audio applications

The audio peripherals generally need specific accurate frequencies, except for SPDIFRX. As shown in Figure 56 , the kernel clock of the SAIs or SPI(I2S)s can be generated by:

• • The PLL1 when the amount of active PLLs has to be reduced
• • The PLL2 or 3 for optimal flexibility in frequency generation
• • HSE, HSI or CSI for use-cases where the current consumption is critical
• • I2S_CKIN when an external clock reference need to be used.

Note: The SPDIFRX does not require a specific frequency, but only a kernel clock frequency high enough to make the peripheral work properly. Refer to the SPDIFRX description for more details.

DFSDM1 can use the same clock as SAI1A. This is useful when DFSDM1 is used for audio applications.

To improve the flexibility, SAI4 can use different clock for each sub-block.

The SPI/I2S1, 2, and 3 share the same kernel clock source (see Figure 57 ).

Figure 56. Kernel clock distribution for SAI4 and DFSDM1

1. 1. There is one enable bit and one low-power enable bit from each CPU. X represents the selected MUX input after a system reset.
2. 2. This figure does not show the connection of the bus interface clock to the peripherals. For details on each enable cell, please refer to Section 9.5.11: Peripheral clock gating control .

Peripherals dedicated to control and data transfer

Peripherals such as SPIs, I2Cs, UARTs do not need a specific kernel clock frequency but a clock fast enough to generate the correct baud rate, or the required bit clock on the serial interface. For that purpose the source can be selected among:

• • PLL1 when the amount of active PLLs has to be reduced
• • PLL2 or PLL3 if better flexibility is required. As an example, this solution allows changing the frequency bus via PLL1 without affecting the speed of some serial interfaces.
• • HSI or CSI for low-power use-cases or when the peripheral has to quickly wake up from Stop mode (i.e. UART, I2C...).

Note: UARTs also need the LSE clock when high baud rates are not required.

Figure 57. Kernel clock distribution for SPIs and SPI/I2S

1. 1. There is one enable bit and one low-power enable bit from each CPU. X represents the selected MUX input after a system reset.
2. 2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to Section 9.5.11: Peripheral clock gating control .

Figure 58. Kernel clock distribution for I2Cs

1. 1. There is one enable bit and one low-power enable bit from each CPU. X represents the selected MUX input after a system reset.
2. 2. This figure does not show the connection of the bus interface clock to the peripheral, for details on each enable cell, refer to Section 9.5.11: Peripheral clock gating control .

Figure 59. Kernel clock distribution for USARTs, USARTs and LPUART1

1. 1. There is one enable bit and one low-power enable bit from each CPU. X represents the selected MUX input after a system reset.
2. 2. This figure does not show the connection of the bus interface clock to the peripheral, for details on each enable cell, refer to Section 9.5.11: Peripheral clock gating control .

Section 9.5.11: Peripheral clock gating control.

The DSI block has its own PLL which operates directly from the hse_ck.

Figure 60. Kernel clock distribution for DSI and LTDC

1. 1. There is one enable bit and one low-power enable bit from each CPU. X represents the selected MUX input after a system reset.
2. 2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to Section 9.5.11: Peripheral clock gating control .

The FMC, QUADSPI and SDMMC1/2 can also use a clock different from the bus interface clock for more flexibility.

Figure 61. Kernel clock distribution for SDMMC, QUADSPI and FMC

1. 1. There is one enable bit and one low-power enable bit from each CPU. X represents the selected MUX input after a system reset.
2. 2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to Section 9.5.11: Peripheral clock gating control .

refer to Section 9.5.11: Peripheral clock gating control .

Figure 62 shows the clock distribution for the USB blocks. The USB1ULPI blocks receive its clock from the external PHY.

The USBxOTG blocks receive the clock for USB communications which can be selected among different sources thanks to the MUX controlled by USBSEL.

Figure 62. Kernel clock distribution For USB ⁽²⁾

1. 1. There is one enable bit and one low-power enable bit from each CPU. X represents the selected MUX input after a system reset.
2. 2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to Section 9.5.11: Peripheral clock gating control .

The Ethernet transmit and receive clocks shall be provided from an external Ethernet PHY. The clock selection for the RX and TX path is controlled via the SYSCFG block.

Figure 63. Kernel clock distribution for Ethernet

MSV39376V3

1. 1. There is one enable bit and one low-power enable bit from each CPU. X represents the selected MUX input after a system reset.
2. 2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to Section 9.5.11: Peripheral clock gating control .

1. 1. There is one enable bit and one low-power enable bit from each CPU. X represents the selected MUX input after a system reset.
2. 2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to Section 9.5.11: Peripheral clock gating control .

Figure 65. Kernel clock distribution for LPTIMs and HDMI-CEC (2)

1. 1. There is one enable bit and one low-power enable bit from each CPU. X represents the selected MUX input after a system reset
2. 2. This figure does not show the connection of the bus interface clock to the peripheral. For details on each enable cell, please refer to Section 9.5.11: Peripheral clock gating control .

RTC/AWU clock

The rtc_ck clock source can be:

• • the hse_1M_ck ( hse_ck divided by a programmable prescaler)
• • the lse_ck
• • or the lsi_ck clock

The source clock is selected by programming the RTCSEL[1:0] bits in the RCC Backup domain control register (RCC_BDCR) and the RTCPRE[5:0] bits in the RCC clock configuration register (RCC_CFGR) .

This selection cannot be modified without resetting the Backup domain.

If the LSE is selected as RTC clock, the RTC will work normally even if the backup or the \( V_{DD} \) supply disappears.

The LSE clock is in the Backup domain, whereas the other oscillators are not. As a consequence:

• • If LSE is selected as RTC clock, the RTC continues working even if the \( V_{DD} \) supply is switched OFF, provided the \( V_{BAT} \) supply is maintained.
• • If LSI is selected as the RTC clock, the AWU state is not guaranteed if the \( V_{DD} \) supply is powered off.
• • If the HSE clock is used as RTC clock, the RTC state is not guaranteed if the \( V_{DD} \) supply is powered off or if the \( V_{CORE} \) supply is powered off.

The rtc_ck clock is enabled through RTCEN bit located in the RCC Backup domain control register (RCC_BDCR) .

The RTC bus interface clock (APB clock) is enabled through RTCAPBEN and RTCAPBLPEN bits located in RCC_APB4ENR/LPENR registers.

Note: To read the RTC calendar register when the APB clock frequency is less than seven times the RTC clock frequency ( \( F_{APB} < 7 \times F_{RTCLK} \) ), the software must read the calendar time and date registers twice. The data are correct if the second read access to RTC_TR gives the same result than the first one. Otherwise a third read access must be performed.

Watchdog clocks

The RCC provides the clock for the four watchdog blocks available on the circuit. The two independent watchdogs (IWDG1 and IWDG2) are connected to the LSI. The two window watchdogs (WWDG1 and WWDG2) are connected to the APB clock.

If an independent watchdog is started by either hardware option or software access, the LSI is forced ON and cannot be disabled. After the LSI oscillator setup delay, the clock is provided to the IWDGs.

Caution: Before enabling WWDG1/WWDG2, the application must set the WW1RSC/WW2RSC bit to '1'. If the WW1RSC/WW2RSC remains at '0' when the WWDG1/2 is enabled, the WWDG1/2 behavior is not guaranteed. The WW1RSC and WW2RSC bits are located in RCC global control register (RCC_GCR) .

Clock frequency measurement using TIMx

Most of the clock source generator frequencies can be measured by means of the input capture of TIMx.

• • Calibrating the HSI or CSI with the LSE

The primary purpose of having the LSE connected to a TIMx input capture is to be able to accurately measure the HSI or CSI. This requires to use the HSI or CSI as system clock source either directly or via PLL1. The number of system clock counts between consecutive edges of the LSE signal gives a measurement of the internal clock period. Taking advantage of the high precision of LSE crystals (typically a few tens of ppm) we can determine the internal clock frequency with the same resolution, and trim the

source to compensate for manufacturing-process and/or temperature- and voltage-related frequency deviations.

The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the precision is therefore tightly linked to the ratio between the two clock sources. The greater the ratio is, the more accurate the measurement is.

The HSI and CSI oscillators have dedicated user-accessible calibration bits for this purpose (see RCC HSI configuration register (RCC_HSI CFGR) and RCC CSI configuration register (RCC_CSI CFGR) ).

When the HSI or CSI are used via the PLLx, the system clock can also be fine-tuned by using the fractional divider of the PLLs.

• • Calibrating the LSI with the HSI

The LSI frequency can also be measured: this is useful for applications that do not have a crystal. The ultralow power LSI oscillator has a large manufacturing process deviation. By measuring it versus the HSI clock source, it is possible to determine its frequency with the precision of the HSI. The measured value can be used to have more accurate RTC time base timeouts (when LSI is used as the RTC clock source) and/or an IWDG timeout with an acceptable accuracy.

9.5.9 General clock concept overview

The RCC handles the distribution of the CPUs, bus interface and peripheral clocks for the system (D1, D2 and D3 domains), according to the operating mode of each function (refer to Section 9.5.1: Clock naming convention for details on clock definitions).

For each peripheral, the application can control the activation/deactivation of its kernel and bus interface clock. Prior to use a peripheral, the CPU has to enable it (by setting PERxEN to '1'), and define if this peripheral remains active in CSleep mode (by setting PERxLPEN to '1'). This is called 'allocation' of a peripheral to a CPU (refer to Section 9.5.10: Peripheral allocation for more details).

The peripheral allocation is used by the RCC to automatically control the clock gating according to the CPU and domain modes, and by the PWR to control the supply voltages of D1, D2 and D3 domains. For example if CPU1 enables a peripheral and decides that the kernel clock of this peripheral shall be gated when it goes to CSleep, then CPU2 state has no effect on the clock gating of this peripheral, but the clock gating will obey to CPU1 state. This is true if CPU2 did not allocate this peripheral as well.

Each CPU has dedicated registers where it can allocate individually the peripherals it intends to use in the application.

Figure 66 gives an example of peripheral allocation:

• • CPU1 enabled SDMMC1, SPI5 and SRAM1. AXISRAM, ITCM, DTCM1, DTCM2 and SRAM4 are implicitly allocated to CPU1. The group composed of CPU1, bus matrix 1/2/3 and allocated peripherals makes up sub-system 1 (CPU1_SS).
• • The CPU2 enabled DMA1, I2C2, SAI1, FLASH, ART, I2C4, SAI4. Note that SRAM1, SRAM2, SRAM3 and SRAM4 are implicitly allocated to CPU2. The group composed by the CPU2, bus matrix 1,2 and 3 and peripherals allocated makes up sub-system 2 (CPU2_SS).

Note: SRAM4, IWDG1, IWDG2 and RCC are common resources and are implicitly allocated to both CPU1 and CPU2.

Some memories are implicitly allocated to a given CPU (see Figure 66 ). Refer to Section : Memory handling for more details.

Figure 66. Peripheral allocation example

1. 1. CPU1_SS and CPU2_SS can be spread over the three power domains.

When CPU1 enters CStop mode, the RCC automatically disables the bus interface and kernel clocks of all the peripherals of the CPU1_SS as well as the CPU clock. If CPU2 is always in CRun mode, then the bus matrix 1 is still clocked as well as the CPU2_SS allocated peripherals (ART, FLASH) which are physically connected to this bus matrix. The PLLs, if enabled, are not disabled by the RCC since CPU2 and D3 are still running.

Then, if CPU2 enters CStop mode, the bus matrix 1 is no longer clocked, and the D1 domain can enter DStop as well. In this scenario, D2 domain will also enter DStop mode. D1 and D2 domains will enter DStandby mode if they are allowed to.

A wakeup event will be able to exit D1 and D2 domain from DStandby or DStop mode.

Two additional functions are available to reduce power consumption:

• • D3 domain can be kept in DRun mode while CPU1 and CPU2 are in CStop mode and D1 and D2 domains are in DStop or DStandby mode. This is done by setting RUN_D3 bit in PWR_D1CR or PWR_D2CR registers:
  • – If RUN_D3 of PWR_CPU1CR or PWR_CPU2CR is set to '1', then D3 is maintained in DRun mode, independently from CPU1 and CPU2 modes (see PWR CPU1 control register (PWR_CPU1CR) and PWR CPU2 control register (PWR_CPU2CR) ).
  • – If RUN_D3 of PWR_CPU1CR and RUN_D3 of PWR_CPU2CR are set to '0', then D3 domain enters DStop or DStandby mode when both CPU1 and CPU2 enter CStop mode (see Table 63 ).
• • More autonomy can be given to some peripherals located into D3 domain (refer to Section : D3 domain Autonomous mode for details).

D3 domain Autonomous mode

The Autonomous mode allows to deliver the peripheral clocks to peripherals located in D3, even if the CPU to which they are allocated is in CStop mode. When a peripheral has its autonomous bit enabled, it receives its peripheral clocks according to D3 domain state, if the CPU to which it is allocated is in CStop mode:

• • If the D3 domain is in DRun mode, peripherals with Autonomous mode activated receive their peripheral clocks,
• • If the D3 domain is in DStop mode, no peripheral clock is provided.

The Autonomous mode does not prevent the D3 domain to enter DStop or DStandby mode.

The autonomous bits are located in RCC D3 Autonomous mode register (RCC_D3AMR) .

For example, CPU1 and CPU2 can enter CStop mode, while the SAI4 is filling the SRAM4 with data received from an external device via DMA1. When the amount of received data is reached, the CPU2 can be activated by a wakeup event. This can be done by setting the SAI4, the DMA1, and SRAM4 in Autonomous mode, while keeping D3 in DRun mode (RUN_D3 set to '1'). In this example, the RCC does not switch off the PLLs as the D3 domain is always in DRun mode.

It is possible to go a step further with power consumption reduction by combining the Autonomous mode with the capability of some peripherals (UARTs, I2Cs) to request the kernel clock on their own, without waking-up the CPUs. For example, if the system is expecting messages via I2C4, the whole system can be put in Stop mode. When the I2C4 peripheral detects a START bit, it will generate a “kernel clock request”. This request enables the HSI or CSI, and a kernel clock is provided only to the requester (in our example the I2C4). The I2C4 then decodes the incoming message. Several cases are then possible:

• • If the device address of the message does not match, then I2C4 releases its “kernel clock request” until a new START condition is detected.
• • If the device address of the incoming message matches, it has to be stored into D3 local memory. I2C4 is able to generate a wakeup event on address match to switch the D3 domain to DRun mode. The message is then transferred into memory via DMA1, and the D3 domain go back to DStop mode without any CPU activation.
• • If the device address of the incoming message matches and the peripheral is setup to wake up the CPU, then I2C4 generates a wakeup event to activate CPU1_SS and CPU2_SS.

Please refer to the description of EXTI block in order see which peripheral is able to perform a wake-up event to which domain.

Memory handling

Both CPUs can access all the memory areas available in the product:

• • AXISRAM, ITCM, DTCM1, DTCM2 and FLASH,
• • SRAM1, SRAM2 and SRAM3,
• • SRAM4 and BKPRAM.

As shown in Figure 66 , FLASH, AXISRAM, ITCM, DTCM1 and DTCM2 are implicitly allocated to CPU1. As a result, there is no enable bit allowing CPU1 to allocate these memories.

In the same way, SRAM1, SRAM2 and SRAM3 are implicitly allocated to CPU2, and CPU2 does not need enable bits to allocate them.

The SRAM4 does not need enable bit at all since D3 domain cannot be in DStop or DStandby mode when one of the CPU is running.

The BKPRAM has a dedicated enable bit for each CPU in order to gate the bus interface clock. The CPUs needs to enable the BKPRAM prior to use it.

When CPU1 wants to access a memory area located into D2 domain, the memory must be enabled via RCC AHB2 clock register (RCC_AHB2ENR) . Enabling the memory insures that this memory will still be operating even if CPU2 enters CStop mode.

The same mechanism exists when CPU2 wants to use a memory located into D1 domain.

Note: When a domain is in DRun mode, the memories located into this domain operate for both CPUs, even if memory enable bits are not set (except for the BKPRAM). The memory enable bits prevent the domain where the memory is located to enter DStop mode. The memory interface clocks (Flash and RAM interfaces) can be stopped by software during CSleep mode (via DxSRAMyLPEN bits).

Refer to Peripheral clock gating control and CPU and bus matrix clock gating control sections for details on clock enabling.

System states overview

Table 63 gives an overview of the system states with respect to CPU1, CPU2 and D3 states.

• • The system remains in Run mode as long as D3 is in DRun mode. Several sub-states of system Run exist that are not detailed here (refer Power control (PWR) for more information).
• • D3 can run while D1 and D2 are in DStop/DStandby mode thanks to RUN_D3 bits of PWR_CPU[2:1]CR registers or when D3 is in Autonomous mode.
• • The system remains in Stop mode as long as D3 is in DStop mode. This means implicitly that D1 and D2 are in DStop or DStandby. As soon as D1 or D2 exits DStop or DStandby, D3 switches to DRun mode.
• • The system remains in Standby mode as long as D1, D2 and D3 are in DStandby.
• • Domain states versus CPU states:
  • – When a domain is in DRun mode, it means that its bus matrix is clocked. The CPU of the domain (if any) can be in CRun, CSleep or CStop mode.
  • – When a domain is in DStop mode, it means that its bus matrix is no longer clocked. The CPU of the domain (if any) is in CStop mode.
  • – When a domain is in DStandby mode, it means that the domain including its CPU are powered down.

Table 63. System states overview

9.5.10 Peripheral allocation

Each CPU can allocate a peripheral and hence control its kernel and bus interface clock. Each CPU has dedicated registers in order to perform this peripheral allocation. A peripheral is allocated when its PERxEN bit is set to '1' by the CPU1 and/or CPU2.

CPU1 can allocate a peripheral for itself by setting the dedicated PERxEN bit in:

• • RCC_DnxxxxENR registers or
• • RCC_C1_DnxxxxENR registers.

CPU1 can also allocate a peripheral for CPU2 by setting the dedicated PERxEN bit in registers RCC_C2_DnxxxxENR.

In the same way, CPU2 can allocate a peripheral for itself by setting the dedicated PERxEN bit in:

• • RCC_DnxxxxENR registers or
• • RCC_C2_DnxxxxENR registers.

CPU2 can also allocate a peripheral for CPU1 by setting the dedicated PERxEN bit in registers RCC_C1_DnxxxxENR.

A similar mechanism is implemented to control the peripheral clocks when the CPUs are in CSleep mode (PERxLPEN bits).

Refer to Section 9.7.1: Register mapping overview for additional information.

Note: When CPU1 or CPU2 access RCC_DnxxxxxENR registers, the hardware detects which CPU did the access (core_id) in order to allocate the peripheral to the right CPU.

The peripheral allocation bits (PERxEN bits) are used by the hardware to provide the kernel and bus interface clocks to the peripherals. However they are also used to link peripherals to a CPU (CPU sub-system). In this way, the hardware is able to safely gate the peripheral clocks and bus matrix clocks according to CPU states. The PWR block also uses this information to control properly the domain states.

Clock switches and gating

• • Clock switching delays

The input selected by the kernel clock switches can be changed dynamically without generating spurs or timing violation. As a consequence, switching from the original to the new input can only be performed if a clock is present on both inputs. If it not the case, no clock will be provided to the peripheral. To recover from this situation, the user has to provide a valid clock to both inputs.

During the transition from one input to another, the kernel clock provided to the peripheral will be gated, in the worst case, during 2 clock cycles of the previously selected clock and 2 clock cycles of the new selected clock. As shown in Figure 67 , both input clocks shall be present during transition time.

Figure 67. Kernel Clock switching

• • Clock enabling delays

In the same way, the clock gating logic synchronizes the enable command (coming generally from a kernel clock request or PERxEN bits) with the selected clock, in order to avoid generation of spurs.

• – A maximum delay of two periods of the enabled clock may occur between the enable command and the first rising edge of the clock. The enable command can be the rising edge of the PERxEN bits of RCC_xxxxENR registers, or a kernel clock request asserted by a peripheral.
• – A maximum delay of 1.5 periods of the disabled clock may occur between the disable command and the last falling edge of the clock. The disable command can be the falling edge of the PERxEN bits of RCC_xxxxENR registers, or a kernel clock request released by a peripheral.

Note: Both the kernel clock and the bus interface clock are affected by this re-synchronization delay.

In addition, the clock enabling delay may strongly increase if the application is enabling for the first time a peripheral which is not located in the same domain. This is due to the fact that the domain where the peripheral is located could be in DStop or DStandby mode. The domain must be switched to DRun mode before the application can use this peripheral.

As an example, if CPU1 enables a peripheral located in the D2 domain while the D2 domain is in DStop/DStandby mode, then the power controller (PWR) has first to provide a supply voltage to D2, then the RCC has to wait for an acknowledge from the

PWR before enabling the clocks of the D2 domain. To handle properly this situation the RCC and the PWR blocks feature four flags:

• – D1CKRDY/D2CKRDY located in RCC source control register (RCC_CR)
• – SBF_D1 and SBF_D2 located in PWR CPU1 control register (PWR_CPU1CR) and PWR CPU2 control register (PWR_CPU2CR) , respectively.

The following sequence can be followed to avoid this issue:

1. Enable the peripheral clocks (i.e. allocate the peripheral) by writing the corresponding PERxEN bit to '1' in the RCC_xxxxENR register,
2. Read back the RCC_xxxxENR register to make sure that the previous write operation is not pending into a write buffer.
3. If the peripheral is located in a different domain, perform the two next steps:
   Read DxCKRDY until it is set to '1'.
   Write SBF_Dx to zero and read-back the value, in order to check if the domain where the peripheral is located is still in DStandby. If the corresponding bit is read at '1', it means that the domain is still in DStandby. Repeat this operation until SBF_Dx is equal to '0', then continue the other steps.
4. Perform a dummy read operation into a register of the enabled peripheral. This operation will take at least 2 clock cycles, which is equal to the max delay of the enable command.
5. The peripheral can then be used.

Note: When the bus interface clock is not active, read or write accesses to the peripheral registers are not supported. A read access will return invalid data. A write access will be ignored and will not create any bus errors.

9.5.11 Peripheral clock gating control

As mentioned previously, each peripheral requires a bus interface clock, named rcc_perx_bus_ck (for peripheral 'x'). This clock can be an APB, AHB or AXI clock, according to which bus the peripheral is connected.

The clocks used as bus interface for peripherals located in D1 domain, could be rcc_aclk , rcc_hclk3 or rcc_pclk3 , depending on the bus connected to each peripheral. For simplicity sake, these clocks are named rcc_bus_d1_ck .

In the same way, the signal named rcc_bus_d2_ck represents rcc_hclk1 , rcc_hclk2 , rcc_pclk1 or rcc_pclk2 , depending on the bus connected to each peripheral of D2 domain.

Similarly, the signal rcc_bus_d3_ck represents rcc_hclk4 or rcc_pclk4 for peripherals located in D3.

Some peripherals (SAI, UART...) also require a dedicated clock for their communication interface. This clock is generally asynchronous with respect to the bus interface clock. It is named kernel clock ( perx_ker_ckreq ). Both clocks can be gated according to several conditions detailed hereafter.

As shown in Figure 68 , enabling the kernel and bus interface clocks of each peripheral depends on several input signals:

• • C1_PERxEN and C1_PERxLPEN bits
  C1_PERxEN represents the peripheral enable (allocation) bit for CPU1. CPU1 can write these bits to '1' via RCC_C1_xxxxENR or RCC_DnxxxxENR registers.
• • C2_PERxEN and C2_PERxLPEN bits
  C2_PERxEN represents the peripheral enable (allocation) bit for CPU2. The CPU2 can write these bits to '1' via RCC_C2_xxxxENR or RCC_DnxxxxENR registers.
• • PERxAMEN bits
  The PERxAMEN bits are belong to RCC D3 Autonomous mode register (RCC_D3AMR) .
• • CPU1 state ( c1_sleep and c1_deep sleep signals)
• • CPU2 state ( c2_sleep and c2_deep sleep signals)
• • D3 domain state ( d3_deep sleep signal)
• • The kernel clock request ( perx_ker_ckreq ) of the peripheral itself, when the feature is available.

Refer to Section 9.5.10: Peripheral allocation for more details.

Figure 68. Peripheral kernel clock enable logic details

Table 64 gives a detailed description of the enabling logic of the peripheral clocks for peripherals located in D1 or D2 domain and allocated by CPU1. A similar logic applies to CPU2.

Table 64. Peripheral clock enabling for D1 and D2 peripherals

1. 1. For RNG block, the kernel clock is not delivered if the CPU to which it is allocated is in CStop mode, even if the clock selected is lsi_ck or lse_ck.

As a summary, we can state that the kernel clock is provided to the peripherals located on domains D1 and D2 when the following conditions are met:

1. 1. The CPU to which the peripheral is allocated is in CRun mode.
2. 2. The CPU to which the peripheral is allocated is in CSleep mode and PERxLPEN = '1'.
3. 3. The CPU to which the peripheral is allocated is in CStop mode, with PERxLPEN = '1', the peripheral generates a kernel clock request, and the selected clock is hsi_ker_ck or csi_ker_ck .
4. 4. The CPU to which the peripheral is allocated is in CStop mode, with PERxLPEN = '1', and the kernel source clock of the peripheral is lse_ck or lsi_ck .

The bus interface clock will be provided to the peripherals only when conditions 1 or 2 are met.

Table 65 gives a detailed description of the enabling logic of the kernel clock for all peripherals located in D3 and allocated by CPU1. A similar logic applies to CPU2.

Table 65. Peripheral clock enabling for D3 peripherals ⁽¹⁾

1. The above table is given for the peripherals allocated by CPU1. A similar truth table is applicable in the case of peripherals allocated by CPU2.

As a summary, we can state that the kernel clock is provided to the peripherals of D3 if the following conditions are met:

1. 1. The CPU to which the peripheral is allocated is in CRun mode.
2. 2. The CPU to which the peripheral is allocated is in CSleep mode and PERxLPEN = '1'.
3. 3. The CPU to which the peripheral is allocated is in CStop mode and D3 domain is in DRun mode with PERxAMEN = '1'.
4. 4. The CPU to which the peripheral is allocated is in CStop mode, D3 domain is in DStop mode with PERxAMEN = '1', the peripheral is generating a kernel clock request and the kernel clock source is hsi_ker_ck or csi_ker_ck .
5. 5. The CPU to which the peripheral is allocated is in CStop mode, D3 domain is in DStop mode with PERxAMEN = '1', and the kernel clock source of the peripheral is lse_ck or lsi_ck .

The bus interface clock will be provided to the peripherals only when condition 1, 2 or 3 is met.

Note: When they are set to '1', the autonomous bits indicate that the associated peripheral will receive a kernel clock according to D3 state, and not according to the mode of the CPU to which it is allocated.

Only I2C, U(S)ART and LPUART peripherals are able to request the kernel clock. This feature gives to the peripheral the capability to transfer data with an optimal power consumption.

The autonomous bits dedicated to some peripherals located in D3 domain allow the data transfer with external devices without activating the CPUs.

In order for the LPTIMER to operate with Ise_ck or Isi_ck when the circuit is in Stop mode, the user application has to select the Isi_ck or Ise_ck input via LPTIMxSEL fields, and set bit LPTIMxAMEN and LPTIMxLPEN to '1'.

9.5.12 CPU and bus matrix clock gating control

For each domain it is possible to control the activation/deactivation of the CPU clock and bus matrix clock.

• • The clock of each CPU is controlled by the c[2:1]_sleep signal.
• • The domain bus clock is controlled by the CPU DeepSleep signal and by the other CPU DeepSleep signal when it has allocated peripheral(s).

For information about convention naming, refer to Section 9.5.11: Peripheral clock gating control .

Table 66. Domain bus clock enabling for D1 peripherals

1. c2_per_alloc_d1 represents a logic OR of all RCC_C2_xxxENR.PERxEN bits, for peripherals located in D1 domain.

Table 67 shows the conditions which enable or disable the bus matrix clock on D3.

Table 67. Domain bus clock enabling for D3 peripherals

Note: When all peripherals connected to a same APB bus are disabled, the APB clock bridge is automatically gated as well to reduce the power consumption.

As shown in the Figure 69 , the enabling of the core and bus clock of each domain depends on several input signals:

• • c1_sleep and c1_deep sleep signals from CPU1,
• • c2_sleep and c2_deep sleep signals from CPU2,
• • d3_sleepdeep signal,
• • RCC_C2_xxxENR.PERxEN bits of peripherals located on D1 domain
• • RCC_C1_xxxENR.PERxEN bits of peripherals located on D2 domain

Figure 69. Bus clock enable logic

• • When a CPU is in CRun mode, the corresponding CPU clock and bus clocks are provided to the domain.
• • When a CPU is in CSleep mode, the corresponding bus clocks are provided to the domain, and the CPU clock is stopped.
• • When CPU1 is in CStop mode and the other CPU has no peripherals allocated in the D1 domain, the CPU and bus matrix clocks of the D1 domain are stopped. In the same way, when CPU2 is in CStop mode and the other CPU has no peripherals allocated in the D2 domain, CPU2 and bus matrix clocks of the D2 domain are stopped.
• • When CPU1 is in CStop mode and the other CPU has allocated peripherals on D1 domain, and is in CRun or CSleep, the corresponding bus matrix clock is provided to the D1 domain, and the CPU1 clock is stopped. In the same way, when CPU2 is in CStop mode and the other CPU has allocated peripherals on D2 domain, and is in

CRun or CSleep, the corresponding bus matrix clock is provided to the D2 domain, and the CPU2 clock is stopped.

• • When CPU1 and CPU2 are in CStop mode, the bus matrix and the CPU clocks on both domains are stopped.
• • Whenever CPU1 or CPU2 are in CRun or CSleep mode, the D3 domain bus matrix clock is running.
• • When both CPU1 and CPU2 are in CStop mode, the D3 domain bus matrix clock is stopped, if RUN_D3 bits are set to '0', and d3_deepsleep = '1'.
• • Whenever one of the two RUN_D3 bits is set the D3 domain bus clock is running.
• • Whenever the d3_deepsleep signal is inactive (0), the D3 domain bus clock is running.

9.6 RCC Interrupts

The RCC provides 3 interrupt lines:

• • rcc_it : a general interrupt line, providing events when the PLLs are ready, or when the oscillators are ready.
• • rcc_hsecss_it : an interrupt line dedicated to the failure detection of the HSE Clock Security System.
• • rcc_lsecss_it : an interrupt line dedicated to the failure detection of the LSE Clock Security System.

The interrupt enable is controlled via RCC clock source interrupt enable register (RCC_CIER) , except for the HSE CSS failure. When the HSE CSS feature is enabled, it is not possible to mask the interrupt generation.

The interrupt flags can be checked via RCC clock source interrupt flag register (RCC_CIFR) , and those flags can be cleared via RCC clock source interrupt clear register (RCC_CICR) .

Note: The interrupt flags are not relevant if the corresponding interrupt enable bit is not set.

Table 68 gives a summary of the interrupt sources, and the way to control them.

Table 68. Interrupt sources and control

1. The security system feature must also be enabled (LSECSSON = '1'), in order to generate interrupts.

2. It is not possible to mask this interrupt when the security system feature is enabled (HSECSSON = '1').

9.7 RCC registers

9.7.1 Register mapping overview

The RCC register map is divided into 4 sections.

• • Common registers accessible by both cores and by any other master.
• • Registers mapped at the same address:
  • – When accessed by CPU1, CPU1 register bank is accessed.
  • – When accessed by CPU2, CPU2 register bank is accessed.
• • CPU1 register bank containing the peripheral enable bits (PERxEN), the peripheral low-power enable bits (PERxLPEN) and reset flag status bits for peripheral allocation to CPU1
• • CPU2 register bank containing the peripheral enable bits (PERxEN), the peripheral low-power enable bits (PERxLPEN) and reset flag status bits for peripheral allocation to CPU2.

Note: Any master can access the Common register bank, CPU1 register bank and CPU2 register bank. However, the “same address bank” can only be accessed by CPU1 or CPU2.

Figure 70 shows the RCC mapping overview.

Figure 70. RCC mapping overview

9.7.2 RCC source control register (RCC_CR)

Address offset: 0x000

Reset value: 0x0000 0001

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 PLL3RDY : PLL3 clock ready flag

Set by hardware to indicate that the PLL3 is locked.

0: PLL3 unlocked (default after reset)

1: PLL3 locked

Bit 28 PLL3ON : PLL3 enable

Set and cleared by software to enable PLL3.

Cleared by hardware when entering Stop or Standby mode.

0: PLL3 OFF (default after reset)

1: PLL3 ON

Bit 27 PLL2RDY : PLL2 clock ready flag

Set by hardware to indicate that the PLL2 is locked.

0: PLL2 unlocked (default after reset)

1: PLL2 locked

Bit 26 PLL2ON : PLL2 enable

Set and cleared by software to enable PLL2.

Cleared by hardware when entering Stop or Standby mode.

0: PLL2 OFF (default after reset)

1: PLL2 ON

Bit 25 PLL1RDY : PLL1 clock ready flag

Set by hardware to indicate that the PLL1 is locked.

0: PLL1 unlocked (default after reset)

1: PLL1 locked

Bit 24 PLL1ON : PLL1 enable

Set and cleared by software to enable PLL1.

Cleared by hardware when entering Stop or Standby mode. Note that the hardware prevents writing this bit to '0', if the PLL1 output is used as the system clock.

0: PLL1 OFF (default after reset)

1: PLL1 ON

Bits 23:20 Reserved, must be kept at reset value.

Set by software to enable Clock Security System on HSE.

This bit is “set only” (disabled by a system reset or when the system enters in Standby mode).

When HSECSSON is set, the clock detector is enabled by hardware when the HSE is ready and disabled by hardware if an oscillator failure is detected.

0: Clock Security System on HSE OFF (Clock detector OFF) (default after reset)

1: Clock Security System on HSE ON (Clock detector ON if the HSE oscillator is stable, OFF if not).

Set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit, to be used by the device.

The HSEBYP bit can be written only if the HSE oscillator is disabled.

0: HSE oscillator not bypassed (default after reset)

1: HSE oscillator bypassed with an external clock

Set by hardware to indicate that the HSE oscillator is stable.

0: HSE clock is not ready (default after reset)

1: HSE clock is ready

Set and cleared by software.

Cleared by hardware to stop the HSE when entering Stop or Standby mode.

This bit cannot be cleared if the HSE is used directly (via SW mux) as system clock or if the HSE is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to ‘1’).

0: HSE is OFF (default after reset)

1: HSE is ON

Set by hardware to indicate that the D2 domain clocks (CPU, bus and peripheral) are available.

0: D2 domain clocks are not available (default after reset)

1: D2 domain clocks are available

Set by hardware to indicate that the D1 domain clocks (CPU, bus and peripheral) are available.

0: D1 domain clocks are not available (default after reset)

1: D1 domain clocks are available

Set by hardware to indicate that the HSI48 oscillator is stable.

0: HSI48 clock is not ready (default after reset)

1: HSI48 clock is ready

Set by software and cleared by software or by the hardware when the system enters to Stop or Standby mode.

0: HSI48 is OFF (default after reset)

1: HSI48 is ON

Bits 11:10 Reserved, must be kept at reset value.

Set and reset by software to force the CSI to ON, even in Stop mode, in order to be quickly available as kernel clock for some peripherals. This bit has no effect on the value of CSION.

0: no effect on CSI (default after reset)

1: CSI is forced to ON even in Stop mode

Set by hardware to indicate that the CSI oscillator is stable. This bit is activated only if the RC is enabled by CSION (it is not activated if the CSI is enabled by CSIKERON or by a peripheral request).

0: CSI clock is not ready (default after reset)

1: CSI clock is ready

Set and reset by software to enable/disable CSI clock for system and/or peripheral.

Set by hardware to force the CSI to ON when the system leaves Stop mode, if STOPWUCK = '1' or STOPKERWUCK = '1'.

This bit cannot be cleared if the CSI is used directly (via SW mux) as system clock or if the CSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to '1').

0: CSI is OFF (default after reset)

1: CSI is ON

Bit 6 Reserved, must be kept at reset value.

Set and reset by hardware.

As a write operation to HSIDIV has not an immediate effect on the frequency, this flag indicates the current status of the HSI divider. HSIDIVF will go immediately to '0' when HSIDIV value is changed, and will be set back to '1' when the output frequency matches the value programmed into HSIDIV.

0: new division ratio not yet propagated to hsi(_ker)_ck (default after reset)

1: hsi(_ker)_ck clock frequency reflects the new HSIDIV value

Set and reset by software.

These bits allow selecting a division ratio in order to configure the wanted HSI clock frequency. The HSIDIV cannot be changed if the HSI is selected as reference clock for at least one enabled PLL (PLLxON bit set to '1'). In that case, the new HSIDIV value is ignored.

00: Division by 1, hsi(_ker)_ck = 64 MHz (default after reset)

01: Division by 2, hsi(_ker)_ck = 32 MHz

10: Division by 4, hsi(_ker)_ck = 16 MHz

11: Division by 8, hsi(_ker)_ck = 8 MHz

Set by hardware to indicate that the HSI oscillator is stable.

0: HSI clock is not ready (default after reset)

1: HSI clock is ready

Set and reset by software to force the HSI to ON, even in Stop mode, in order to be quickly available as kernel clock for peripherals. This bit has no effect on the value of HSION.

0: no effect on HSI (default after reset)

1: HSI is forced to ON even in Stop mode

Set and cleared by software.

Set by hardware to force the HSI to ON when the product leaves Stop mode, if STOPWUCK = '0' or STOPKERWUCK = '0'.

Set by hardware to force the HSI to ON when the product leaves Standby mode or in case of a failure of the HSE which is used as the system clock source.

This bit cannot be cleared if the HSI is used directly (via SW mux) as system clock or if the HSI is selected as reference clock for PLL1 with PLL1 enabled (PLL1ON bit set to '1').

0: HSI is OFF

1: HSI is ON (default after reset)

9.7.3 RCC HSI configuration register (RCC_HSICFGR)

Address offset: 0x004

Reset value: 0x4000 0xxx

Bit 31 Reserved, must be kept at reset value.

Bits 30:24 HSITRIM[6:0] : HSI clock trimming

Set by software to adjust calibration.

HSITRIM field is added to the engineering Option Bytes loaded during reset phase (FLASH_HSI_opt) in order to form the calibration trimming value.

HSICAL = HSITRIM + FLASH_HSI_opt.

Note: The reset value of the field is 0x40.

Bits 23:12 Reserved, must be kept at reset value.

Bits 11:0 HSICAL[11:0] : HSI clock calibration

Set by hardware by option byte loading during system reset nreset .

Adjusted by software through trimming bits HSITRIM.

This field represents the sum of engineering Option Byte calibration value and HSITRIM bits value.

9.7.4 RCC clock recovery RC register (RCC_CRRCR)

Address offset: 0x008

Reset value: 0x0000 0xxx

Bits 31:10 Reserved, must be kept at reset value.

Bits 9:0 HSI48CAL[9:0] : Internal RC 48 MHz clock calibration

Set by hardware by option byte loading during system reset nreset .

Read-only.

9.7.5 RCC CSI configuration register (RCC_CSICFGR)

Address offset: 0x00C

Reset value: 0x2000 00xx

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:24 CSITRIM[5:0] : CSI clock trimming

Set by software to adjust calibration.

CSITRIM bitfield is added to the engineering option bytes loaded during the reset phase (FLASH_CSI_opt) in order to build the calibration trimming value.

CSICAL = CSITRIM + FLASH_CSI_opt.

Note: The reset value of this bitfield is 0x10.

Bits 23:8 Reserved, must be kept at reset value.

Bits 9:0 CSICAL[9:0] : CSI clock calibration

Set by hardware by option byte loading during system reset nreset .

Adjusted by software through trimming bits CSITRIM.

This bitfield represents the sum of the engineering option byte calibration value and CSITRIM value.

9.7.6 RCC clock configuration register (RCC_CFGR)

Address offset: 0x010

Reset value: 0x0000 0000

Bits 31:29 MCO2SEL[2:0]: Micro-controller clock output 2

Set and cleared by software. Clock source selection may generate glitches on MCO2.

It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.

000: System clock selected ( sys_ck ) (default after reset)

001: PLL2 oscillator clock selected ( pll2_p_ck )

010: HSE clock selected ( hse_ck )

011: PLL1 clock selected ( pll1_p_ck )

100: CSI clock selected ( csi_ck )

101: LSI clock selected ( lsi_ck )

others: reserved

Bits 28:25 MCO2PRE[3:0]: MCO2 prescaler

Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.

0000: prescaler disabled (default after reset)

0001: division by 1 (bypass)

0010: division by 2

0011: division by 3

0100: division by 4

...

1111: division by 15

Bits 24:22 MCO1SEL[2:0]: Micro-controller clock output 1

Set and cleared by software. Clock source selection may generate glitches on MCO1.

It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs.

000: HSI clock selected ( hsi_ck ) (default after reset)

001: LSE oscillator clock selected ( lse_ck )

010: HSE clock selected ( hse_ck )

011: PLL1 clock selected ( pll1_q_ck )

100: HSI48 clock selected ( hsi48_ck )

others: reserved

Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs.

0000: prescaler disabled (default after reset)

0001: division by 1 (bypass)

0010: division by 2

0011: division by 3

0100: division by 4

...

1111: division by 15

Bits 17:16 Reserved, must be kept at reset value.

This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains.

0: The Timers kernel clock is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2, else it is equal to \( 2 \times F_{\text{rcc\_pclkx\_d2}} \) (default after reset)

1: The Timers kernel clock is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4, else it is equal to \( 4 \times F_{\text{rcc\_pclkx\_d2}} \)

Please refer to Table 59: Ratio between clock timer and pclk

This bit is set and reset by software to control the clock frequency of high resolution the timer (HRTIM).

0: The HRTIM prescaler clock source is the same as other timers. (default after reset)

1: The HRTIM prescaler clock source is the CPU1 clock ( rcc_c1_ck ).

Set and cleared by software to divide the HSE to generate a clock for RTC.

Caution: The software has to set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source.

000000: no clock (default after reset)

000001: no clock

000010: HSE/2

000011: HSE/3

000100: HSE/4

...

111110: HSE/62

111111: HSE/63

Set and reset by software to select the Kernel wakeup clock from system Stop.

0: The HSI is selected as wake up clock from system Stop (default after reset)

1: The CSI is selected as wake up clock from system Stop

See Section 9.5.7: Handling clock generators in Stop and Standby mode for details.

Bit 6 STOPWUCK : System clock selection after a wake up from system Stop

Set and reset by software to select the system wakeup clock from system Stop.

The selected clock is also used as emergency clock for the Clock Security System on HSE.

0: The HSI is selected as wake up clock from system Stop (default after reset)

1: The CSI is selected as wake up clock from system Stop

See Section 9.5.7: Handling clock generators in Stop and Standby mode for details.

Caution: STOPWUCK must not be modified when the Clock Security System is enabled (by HSECSSON bit) and the system clock is HSE (SWS="10") or a switch on HSE is requested (SW="10").

Bits 5:3 SWS[2:0] : System clock switch status

Set and reset by hardware to indicate which clock source is used as system clock.

000: HSI used as system clock ( hsi_ck ) (default after reset)

001: CSI used as system clock ( csi_ck )

010: HSE used as system clock ( hse_ck )

011: PLL1 used as system clock ( pll1_p_ck )

others: Reserved

Bits 2:0 SW[2:0] : System clock switch

Set and reset by software to select system clock source ( sys_ck ).

Set by hardware in order to:

• – force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode
• – force the selection of the HSI in case of failure of the HSE when used directly or indirectly as system clock.

000: HSI selected as system clock ( hsi_ck ) (default after reset)

001: CSI selected as system clock ( csi_ck )

010: HSE selected as system clock ( hse_ck )

011: PLL1 selected as system clock ( pll1_p_ck )

others: Reserved

9.7.7 RCC domain 1 clock configuration register (RCC_D1CFGR)

Address offset: 0x018

Reset value: 0x0000 0000

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:8 D1CPRE[3:0] : D1 domain Core prescaler

Set and reset by software to control D1 domain CPU clock division factor.

Changing this division ratio has an impact on the frequency of CPU1 clock, all bus matrix clocks and CPU2 clock.

The clocks are divided by the new prescaler factor. This factor ranges from 1 to 16 periods of the slowest APB clock among rcc_pclk[4:1] after D1CPRE update. The application can check if the new division factor is taken into account by reading back this register.

0xxx: sys_ck not divided (default after reset)

1000: sys_ck divided by 2

1001: sys_ck divided by 4

1010: sys_ck divided by 8

1011: sys_ck divided by 16

1100: sys_ck divided by 64

1101: sys_ck divided by 128

1110: sys_ck divided by 256

1111: sys_ck divided by 512

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 D1PPRE[2:0] : D1 domain APB3 prescaler

Set and reset by software to control the division factor of rcc_pclk3 .

The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk3 after D1PPRE write.

0xx: rcc_pclk3 = rcc_hclk3 (default after reset)

100: rcc_pclk3 = rcc_hclk3 / 2

101: rcc_pclk3 = rcc_hclk3 / 4

110: rcc_pclk3 = rcc_hclk3 / 8

111: rcc_pclk3 = rcc_hclk3 / 16

Bits 3:0 HPRE[3:0] : D1 domain AHB prescaler

Set and reset by software to control the division factor of rcc_hclk3 and rcc_aclk . Changing this division ratio has an impact on the frequency of all bus matrix clocks and CPU2 clock.

0xxx: rcc_hclk3 = sys_d1cpres_ck (default after reset)

1000: rcc_hclk3 = sys_d1cpres_ck / 2

1001: rcc_hclk3 = sys_d1cpres_ck / 4

1010: rcc_hclk3 = sys_d1cpres_ck / 8

1011: rcc_hclk3 = sys_d1cpres_ck / 16

1100: rcc_hclk3 = sys_d1cpres_ck / 64

1101: rcc_hclk3 = sys_d1cpres_ck / 128

1110: rcc_hclk3 = sys_d1cpres_ck / 256

1111: rcc_hclk3 = sys_d1cpres_ck / 512

Note: The clocks are divided by the new prescaler factor from 1 to 16 periods of the slowest APB clock among rcc_pclk[4:1] after HPRE update.

Note: Note also that rcc_hclk3 = rcc_aclk .

Caution: Care must be taken when using the voltage scaling. Due to the propagation delay of the new division factor, after a prescaler factor change and before lowering the \( V_{CORE} \) voltage, this register must be read in order to check that the new prescaler value has been taken into account.

Depending on the clock source frequency and the voltage range, the software application has to program a correct value in HPRE to make sure that the system frequency does not exceed the maximum frequency.

9.7.8 RCC domain 2 clock configuration register (RCC_D2CFGR)

Address offset: 0x01C

Reset value: 0x0000 0000

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:8 D2PPRE2[2:0] : D2 domain APB2 prescaler

Set and reset by software to control D2 domain APB2 clock division factor.

The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk1 after D2PPRE2 write.

0xx: rcc_pclk2 = rcc_hclk1 (default after reset)

100: rcc_pclk2 = rcc_hclk1 / 2

101: rcc_pclk2 = rcc_hclk1 / 4

110: rcc_pclk2 = rcc_hclk1 / 8

111: rcc_pclk2 = rcc_hclk1 / 16

Bit 7 Reserved, must be kept at reset value.

Bits 6:4 D2PPRE1[2:0] : D2 domain APB1 prescaler

Set and reset by software to control D2 domain APB1 clock division factor.

The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk1 after D2PPRE1 write.

0xx: rcc_pclk1 = rcc_hclk1 (default after reset)

100: rcc_pclk1 = rcc_hclk1 / 2

101: rcc_pclk1 = rcc_hclk1 / 4

110: rcc_pclk1 = rcc_hclk1 / 8

111: rcc_pclk1 = rcc_hclk1 / 16

Bits 3:0 Reserved, must be kept at reset value.

9.7.9 RCC domain 3 clock configuration register (RCC_D3CFGR)

Address offset: 0x020

Reset value: 0x0000 0000

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:4 D3PPRE[2:0] : D3 domain APB4 prescaler

Set and reset by software to control D3 domain APB4 clock division factor.

The clock is divided by the new prescaler factor from 1 to 16 cycles of rcc_hclk4 after D3PPRE write.

0xx: rcc_pclk4 = rcc_hclk4 (default after reset)

100: rcc_pclk4 = rcc_hclk4 / 2

101: rcc_pclk4 = rcc_hclk4 / 4

110: rcc_pclk4 = rcc_hclk4 / 8

111: rcc_pclk4 = rcc_hclk4 / 16

Bits 3:0 Reserved, must be kept at reset value.

9.7.10 RCC PLLs clock source selection register (RCC_PLLCKSEL _R )

Address offset: 0x028

Reset value: 0x0202 0200

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:20 DIVM3[5:0] : Prescaler for PLL3

Set and cleared by software to configure the prescaler of the PLL3.

The hardware does not allow any modification of this prescaler when PLL3 is enabled (PLL3ON = '1').

In order to save power when PLL3 is not used, the value of DIVM3 must be set to '0'.

000000: prescaler disabled

000001: division by 1 (bypass)

000010: division by 2

000011: division by 3

...

100000: division by 32 (default after reset)

...

111111: division by 63

Bits 19:18 Reserved, must be kept at reset value.

Bits 17:12 DIVM2[5:0] : Prescaler for PLL2

Set and cleared by software to configure the prescaler of the PLL2.

The hardware does not allow any modification of this prescaler when PLL2 is enabled (PLL2ON = '1').

In order to save power when PLL2 is not used, the value of DIVM2 must be set to '0'.

000000: prescaler disabled

000001: division by 1 (bypass)

000010: division by 2

000011: division by 3

...

100000: division by 32 (default after reset)

...

111111: division by 63

Bits 11:10 Reserved, must be kept at reset value.

Set and cleared by software to configure the prescaler of the PLL1.

The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = '1').

In order to save power when PLL1 is not used, the value of DIVM1 must be set to '0'.

000000: prescaler disabled

000001: division by 1 (bypass)

000010: division by 2

000011: division by 3

...

100000: division by 32 (default after reset)

...

111111: division by 63

Bits 3:2 Reserved, must be kept at reset value.

Set and reset by software to select the PLL clock source.

These bits can be written only when all PLLs are disabled.

In order to save power, when no PLL is used, the value of PLL SRC must be set to '11'.

00: HSI selected as PLL clock ( hsi_ck ) (default after reset)

01: CSI selected as PLL clock ( csi_ck )

10: HSE selected as PLL clock ( hse_ck )

11: No clock send to DIVMx divider and PLLs

9.7.11 RCC PLL configuration register (RCC_PLLCFGR)

Address offset: 0x02C

Reset value: 0x01FF 0000

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 DIVR3EN : PLL3 DIVR divider output enable

Set and reset by software to enable the pll3_r_ck output of the PLL3.

To save power, DIVR3EN and DIVR3 bits must be set to '0' when the pll3_r_ck is not used.

This bit can be written only when the PLL3 is disabled (PLL3ON = '0' and PLL3RDY = '0').

0: pll3_r_ck output is disabled

1: pll3_r_ck output is enabled (default after reset)

Bit 23 DIVQ3EN : PLL3 DIVQ divider output enable

Set and reset by software to enable the pll3_q_ck output of the PLL3.

To save power, DIVR3EN and DIVR3 bits must be set to '0' when the pll3_r_ck is not used.

This bit can be written only when the PLL3 is disabled (PLL3ON = '0' and PLL3RDY = '0').

0: pll3_q_ck output is disabled

1: pll3_q_ck output is enabled (default after reset)

Bit 22 DIVP3EN : PLL3 DIVP divider output enable

Set and reset by software to enable the pll3_p_ck output of the PLL3.

This bit can be written only when the PLL3 is disabled (PLL3ON = '0' and PLL3RDY = '0').

To save power, DIVR3EN and DIVR3 bits must be set to '0' when the pll3_r_ck is not used.

0: pll3_p_ck output is disabled

1: pll3_p_ck output is enabled (default after reset)

Bit 21 DIVR2EN : PLL2 DIVR divider output enable

Set and reset by software to enable the pll2_r_ck output of the PLL2.

To save power, DIVR3EN and DIVR3 bits must be set to '0' when the pll3_r_ck is not used.

This bit can be written only when the PLL2 is disabled (PLL2ON = '0' and PLL2RDY = '0').

0: pll2_r_ck output is disabled

1: pll2_r_ck output is enabled (default after reset)

Bit 20 DIVQ2EN : PLL2 DIVQ divider output enable

Set and reset by software to enable the pll2_q_ck output of the PLL2.

To save power, DIVR3EN and DIVR3 bits must be set to '0' when the pll3_r_ck is not used.

This bit can be written only when the PLL2 is disabled (PLL2ON = '0' and PLL2RDY = '0').

0: pll2_q_ck output is disabled

1: pll2_q_ck output is enabled (default after reset)

Set and reset by software to enable the pll2_p_ck output of the PLL2.

This bit can be written only when the PLL2 is disabled (PLL2ON = '0' and PLL2RDY = '0').

To save power, DIVR3EN and DIVR3 bits must be set to '0' when the pll3_r_ck is not used.

0: pll2_p_ck output is disabled

1: pll2_p_ck output is enabled (default after reset)

Set and reset by software to enable the pll1_r_ck output of the PLL1.

To save power, DIVR3EN and DIVR3 bits must be set to '0' when the pll3_r_ck is not used.

This bit can be written only when the PLL1 is disabled (PLL1ON = '0' and PLL1RDY = '0').

0: pll1_r_ck output is disabled

1: pll1_r_ck output is enabled (default after reset)

Set and reset by software to enable the pll1_q_ck output of the PLL1.

In order to save power, when the pll1_q_ck output of the PLL1 is not used, the pll1_q_ck must be disabled.

This bit can be written only when the PLL1 is disabled (PLL1ON = '0' and PLL1RDY = '0').

0: pll1_q_ck output is disabled

1: pll1_q_ck output is enabled (default after reset)

Set and reset by software to enable the pll1_p_ck output of the PLL1.

This bit can be written only when the PLL1 is disabled (PLL1ON = '0' and PLL1RDY = '0').

In order to save power, when the pll1_p_ck output of the PLL1 is not used, the pll1_p_ck must be disabled.

0: pll1_p_ck output is disabled

1: pll1_p_ck output is enabled (default after reset)

Bits 15:12 Reserved, must be kept at reset value.

Set and reset by software to select the proper reference frequency range used for PLL3.

These bits must be written before enabling the PLL3.

00: The PLL3 input ( ref3_ck ) clock range frequency is between 1 and 2 MHz (default after reset)

01: The PLL3 input ( ref3_ck ) clock range frequency is between 2 and 4 MHz

10: The PLL3 input ( ref3_ck ) clock range frequency is between 4 and 8 MHz

11: The PLL3 input ( ref3_ck ) clock range frequency is between 8 and 16 MHz

Set and reset by software to select the proper VCO frequency range used for PLL3.

This bit must be written before enabling the PLL3.

0: Wide VCO range: 192 to 960 MHz (default after reset)

1: Medium VCO range: 150 to 420 MHz

Set and reset by software to latch the content of FRACN3 into the Sigma-Delta modulator.

In order to latch the FRACN3 value into the Sigma-Delta modulator, PLL3FRACEN must be set to '0', then set to '1': the transition 0 to 1 transfers the content of FRACN3 into the modulator. Please refer to Section : PLL initialization phase for additional information.

Set and reset by software to select the proper reference frequency range used for PLL2.

These bits must be written before enabling the PLL2.

00: The PLL2 input ( ref2_ck ) clock range frequency is between 1 and 2 MHz (default after reset)

01: The PLL2 input ( ref2_ck ) clock range frequency is between 2 and 4 MHz

10: The PLL2 input ( ref2_ck ) clock range frequency is between 4 and 8 MHz

11: The PLL2 input ( ref2_ck ) clock range frequency is between 8 and 16 MHz

Set and reset by software to select the proper VCO frequency range used for PLL2.

This bit must be written before enabling the PLL2.

0: Wide VCO range: 192 to 960 MHz (default after reset)

1: Medium VCO range: 150 to 420 MHz

Set and reset by software to latch the content of FRACN2 into the Sigma-Delta modulator.

In order to latch the FRACN2 value into the Sigma-Delta modulator, PLL2FRACEN must be set to '0', then set to '1': the transition 0 to 1 transfers the content of FRACN2 into the modulator. Please refer to Section : PLL initialization phase for additional information.

Set and reset by software to select the proper reference frequency range used for PLL1.

This bit must be written before enabling the PLL1.

00: The PLL1 input ( ref1_ck ) clock range frequency is between 1 and 2 MHz (default after reset)

01: The PLL1 input ( ref1_ck ) clock range frequency is between 2 and 4 MHz

10: The PLL1 input ( ref1_ck ) clock range frequency is between 4 and 8 MHz

11: The PLL1 input ( ref1_ck ) clock range frequency is between 8 and 16 MHz

Set and reset by software to select the proper VCO frequency range used for PLL1.

These bits must be written before enabling the PLL1.

0: Wide VCO range: 192 to 960 MHz (default after reset)

1: Medium VCO range: 150 to 420 MHz

Set and reset by software to latch the content of FRACN1 into the Sigma-Delta modulator.

In order to latch the FRACN1 value into the Sigma-Delta modulator, PLL1FRACEN must be set to '0', then set to '1': the transition 0 to 1 transfers the content of FRACN1 into the modulator. Please refer to Section : PLL initialization phase for additional information.

9.7.12 RCC PLL1 dividers configuration register (RCC_PLL1DIVR)

Address offset: 0x030

Reset value: 0x0101 0280

Bit 31 Reserved, must be kept at reset value.

Bits 30:24 DIVR1[6:0] : PLL1 DIVR division factor

Set and reset by software to control the frequency of the pll1_r_ck clock.

These bits can be written only when the PLL1 is disabled (PLL1ON = '0' and PLL1RDY = '0').

0000000: not allowed

0000001: pll1_r_ck = vco1_ck / 2 (default after reset)

0000010: pll1_r_ck = vco1_ck / 3

0000011: pll1_r_ck = vco1_ck / 4

...

1111111: pll1_r_ck = vco1_ck / 128

Bit 23 Reserved, must be kept at reset value.

Bits 22:16 DIVQ1[6:0] : PLL1 DIVQ division factor

Set and reset by software to control the frequency of the pll1_q_ck clock.

These bits can be written only when the PLL1 is disabled (PLL1ON = '0' and PLL1RDY = '0').

0000000: pll1_q_ck = vco1_ck

0000001: pll1_q_ck = vco1_ck / 2 (default after reset)

0000010: pll1_q_ck = vco1_ck / 3

0000011: pll1_q_ck = vco1_ck / 4

...

1111111: pll1_q_ck = vco1_ck / 128

Bits 15:9 DIVP1[6:0] : PLL1 DIVP division factor

Set and reset by software to control the frequency of the pll1_p_ck clock.

These bits can be written only when the PLL1 is disabled (PLL1ON = '0' and PLL1RDY = '0').

Note that odd division factors are not allowed.

0000000: pll1_p_ck = vco1_ck

0000001: pll1_p_ck = vco1_ck / 2 (default after reset)

0000010: Not allowed

0000011: pll1_p_ck = vco1_ck / 4

...

1111111: pll1_p_ck = vco1_ck / 128

Bits 8:0 DIVN1[8:0] : Multiplication factor for PLL1 VCO

Set and reset by software to control the multiplication factor of the VCO.

These bits can be written only when the PLL is disabled (PLL1ON = '0' and PLL1RDY = '0').

0x003: DIVN1 = 4

0x004: DIVN1 = 5

0x005: DIVN1 = 6

...

0x080: DIVN1 = 129 (default after reset)

...

0x1FF: DIVN1 = 512

Others: wrong configurations

Caution: The software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is:

• – 192 to 960 MHz if PLL1VCOSEL = '0'
• – 150 to 420 MHz if PLL1VCOSEL = '1'
• –

VCO output frequency = \( F_{ref1\_ck} \times DIVN1 \) , when fractional value 0 has been loaded into FRACN1, with:

• – DIVN1 between 4 and 512
• – The input frequency \( F_{ref1\_ck} \) between 1MHz and 16 MHz

9.7.13 RCC PLL1 fractional divider register (RCC_PLL1FRACR)

Address offset: 0x034

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:3 FRACN1[12:0] : Fractional part of the multiplication factor for PLL1 VCO

Set and reset by software to control the fractional part of the multiplication factor of the VCO.
These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO.

Caution: The software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is:

• – 192 to 960 MHz if PLL1VCOSEL = ‘0’
• – 150 to 420 MHz if PLL1VCOSEL = ‘1’

VCO output frequency = \( F_{ref1\_ck} \times (DIVN1 + (FRACN1 / 2^{13})) \) , with

• – DIVN1 shall be between 4 and 512
• – FRACN1 can be between 0 and \( 2^{13} - 1 \)
• – The input frequency \( F_{ref1\_ck} \) shall be between 1 and 16 MHz.

To change the FRACN value on-the-fly even if the PLL is enabled, the application has to proceed as follow:

• – set the bit PLL1FRACEN to ‘0’,
• – wait for 3 ref1_ck periods
• – write the new fractional value into FRACN1,
• – set the bit PLL1FRACEN to ‘1’.

where ref1_ck, ref2_ck, or ref3_ck are used depending on FRACNx bit index

Bits 2:0 Reserved, must be kept at reset value.

9.7.14 RCC PLL2 dividers configuration register (RCC_PLL2DIVR)

Address offset: 0x038

Reset value: 0x0101 0280

Bit 31 Reserved, must be kept at reset value.

Bits 30:24 DIVR2[6:0] : PLL2 DIVR division factor

Set and reset by software to control the frequency of the pll2_r_ck clock.

These bits can be written only when the PLL2 is disabled (PLL2ON = '0' and PLL2RDY = '0').

0000000: pll2_r_ck = vco2_ck

0000001: pll2_r_ck = vco2_ck / 2 (default after reset)

0000010: pll2_r_ck = vco2_ck / 3

0000011: pll2_r_ck = vco2_ck / 4

...

1111111: pll2_r_ck = vco2_ck / 128

Bit 23 Reserved, must be kept at reset value.

Bits 22:16 DIVQ2[6:0] : PLL2 DIVQ division factor

Set and reset by software to control the frequency of the pll2_q_ck clock.

These bits can be written only when the PLL2 is disabled (PLL2ON = '0' and PLL2RDY = '0').

0000000: pll2_q_ck = vco2_ck

0000001: pll2_q_ck = vco2_ck / 2 (default after reset)

0000010: pll2_q_ck = vco2_ck / 3

0000011: pll2_q_ck = vco2_ck / 4

...

1111111: pll2_q_ck = vco2_ck / 128

Bits 15:9 DIVP2[6:0] : PLL2 DIVP division factor

Set and reset by software to control the frequency of the pll2_p_ck clock.

These bits can be written only when the PLL2 is disabled (PLL2ON = '0' and PLL2RDY = '0').

0000000: pll2_p_ck = vco2_ck

0000001: pll2_p_ck = vco2_ck / 2 (default after reset)

0000010: pll2_p_ck = vco2_ck / 3

0000011: pll2_p_ck = vco2_ck / 4

...

1111111: pll2_p_ck = vco2_ck / 128

Bits 8:0 DIVN2[8:0] : Multiplication factor for PLL2 VCO

Set and reset by software to control the multiplication factor of the VCO.

These bits can be written only when the PLL is disabled (PLL2ON = '0' and PLL2RDY = '0').

Caution: The software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is:

• – 192 to 960 MHz if PLL2VCOSEL = '0'
• – 150 to 420 MHz if PLL2VCOSEL = '1'

VCO output frequency = \( F_{ref2\_ck} \times DIVN2 \) , when fractional value 0 has been loaded into FRACN2, with

• – DIVN2 between 4 and 512
• – The input frequency \( F_{ref2\_ck} \) between 1MHz and 16MHz

0x003: DIVN2 = 4

0x004: DIVN2 = 5

0x005: DIVN2 = 6

...

0x080: DIVN2 = 129 (default after reset)

...

0x1FF: DIVN2 = 512

Others: wrong configurations

9.7.15 RCC PLL2 fractional divider register (RCC_PLL2FRACR)

Address offset: 0x03C

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:3 FRACN2[12:0] : Fractional part of the multiplication factor for PLL2 VCO

Set and reset by software to control the fractional part of the multiplication factor of the VCO.

These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO.

Caution: The software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is:

• – 192 to 960 MHz if PLL2VCOSEL = '0'
• – 150 to 420 MHz if PLL2VCOSEL = '1'

VCO output frequency = \( F_{ref2\_ck} \times (DIVN2 + (FRACN2 / 2^{13})) \) , with

• – DIVN2 shall be between 4 and 512
• – FRACN2 can be between 0 and \( 2^{13} - 1 \)
• – The input frequency \( F_{ref2\_ck} \) shall be between 1 and 16 MHz

In order to change the FRACN value on-the-fly even if the PLL is enabled, the application has to proceed as follow:

• – set the bit PLL2FRACEN to '0',
• – write the new fractional value into FRACN2,
• – set the bit PLL2FRACEN to '1'.

Bits 2:0 Reserved, must be kept at reset value.

9.7.16 RCC PLL3 dividers configuration register (RCC_PLL3DIVR)

Address offset: 0x040

Reset value: 0x0101 0280

Bit 31 Reserved, must be kept at reset value.

Bits 30:24 DIVR3[6:0] : PLL3 DIVR division factor

Set and reset by software to control the frequency of the pll3_r_ck clock.

These bits can be written only when the PLL3 is disabled (PLL3ON = '0' and PLL3RDY = '0').

0000000: pll3_r_ck = vco3_ck

0000001: pll3_r_ck = vco3_ck / 2 (default after reset)

0000010: pll3_r_ck = vco3_ck / 3

0000011: pll3_r_ck = vco3_ck / 4

...

1111111: pll3_r_ck = vco3_ck / 128

Bit 23 Reserved, must be kept at reset value.

Bits 22:16 DIVQ3[6:0] : PLL3 DIVQ division factor

Set and reset by software to control the frequency of the pll3_q_ck clock.

These bits can be written only when the PLL3 is disabled (PLL3ON = '0' and PLL3RDY = '0').

0000000: pll3_q_ck = vco3_ck

0000001: pll3_q_ck = vco3_ck / 2 (default after reset)

0000010: pll3_q_ck = vco3_ck / 3

0000011: pll3_q_ck = vco3_ck / 4

...

1111111: pll3_q_ck = vco3_ck / 128

Bits 15:9 DIVP3[6:0] : PLL3 DIVP division factor

Set and reset by software to control the frequency of the pll3_p_ck clock.

These bits can be written only when the PLL3 is disabled (PLL3ON = '0' and PLL3RDY = '0').

0000000: pll3_p_ck = vco3_ck

0000001: pll3_p_ck = vco3_ck / 2 (default after reset)

0000010: pll3_p_ck = vco3_ck / 3

0000011: pll3_p_ck = vco3_ck / 4

...

1111111: pll3_p_ck = vco3_ck / 128

Bits 8:0 DIVN3[7:0] : Multiplication factor for PLL3 VCO

Set and reset by software to control the multiplication factor of the VCO.

These bits can be written only when the PLL is disabled (PLL3ON = '0' and PLL3RDY = '0').

Caution: The software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is:

• – 192 to 960 MHz if PLL3VCOSEL = '0'
• – 150 to 420 MHz if PLL3VCOSEL = '1'

VCO output frequency = \( F_{\text{ref3\_ck}} \times \text{DIVN3} \) , when fractional value 0 has been loaded into FRACN3, with

• – DIVN3 between 4 and 512
• – The input frequency \( F_{\text{ref3\_ck}} \) between 1MHz and 16MHz

0x003: DIVN3 = 4

0x004: DIVN3 = 5

0x005: DIVN3 = 6

...

0x080: DIVN3 = 129 (default after reset)

...

0x1FF: DIVN3 = 512

Others: wrong configurations

9.7.17 RCC PLL3 fractional divider register (RCC_PLL3FRACR)

Address offset: 0x044

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:3 FRACN3[12:0] : Fractional part of the multiplication factor for PLL3 VCO

Set and reset by software to control the fractional part of the multiplication factor of the VCO.
These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO.

Caution: The software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is:

• – 192 to 960 MHz if PLL3VCOSEL = ‘0’
• – 150 to 420 MHz if PLL3VCOSEL = ‘1’

VCO output frequency = \( F_{ref3\_ck} \times (DIVN3 + (FRACN3 / 2^{13})) \) , with

• – DIVN3 shall be between 4 and 512
• – FRACN3 can be between 0 and \( 2^{13} - 1 \)
• – The input frequency \( F_{ref3\_ck} \) shall be between 1 and 16 MHz

In order to change the FRACN value on-the-fly even if the PLL is enabled, the application has to proceed as follow:

• – set the bit PLL1FRACEN to ‘0’,
• – write the new fractional value into FRACN1,
• – set the bit PLL1FRACEN to ‘1’.

Bits 2:0 Reserved, must be kept at reset value.

9.7.18 RCC domain 1 kernel clock configuration register (RCC_D1CCIPR)

Address offset: 0x04C

Reset value: 0x0000 0000

1. Changing the clock source on-the-fly is allowed and will not generate any timing violation. However the user has to make use that both the previous and the new clock sources are present during the switching, and during the whole transition time. Please refer to Section : Clock switches and gating .

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 CKPERSEL[1:0] : per_ck clock source selection

• 00: hsi_ker_ck clock selected as per_ck clock (default after reset)
• 01: csi_ker_ck clock selected as per_ck clock
• 10: hse_ck clock selected as per_ck clock
• 11: reserved, the per_ck clock is disabled

Bits 27:17 Reserved, must be kept at reset value.

Bit 16 SDMMCSEL : SDMMC kernel clock source selection

• 0: pll1_q_ck clock is selected as kernel peripheral clock (default after reset)
• 1: pll2_r_ck clock is selected as kernel peripheral clock

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 DSISEL : DSI kernel clock source selection

• 0: DSI clock from PHY is selected as DSI byte lane clock (default after reset)
• 1: pll2_q_ck clock is selected as DSI byte lane clock

Bits 7:6 Reserved, must be kept at reset value.

Bits 5:4 QSPISEL[1:0] : QUADSPI kernel clock source selection

• 00: rcc_hclk3 clock selected as kernel peripheral clock (default after reset)
• 01: pll1_q_ck clock selected as kernel peripheral clock
• 10: pll2_r_ck clock selected as kernel peripheral clock
• 11: per_ck clock selected as kernel peripheral clock

Bits 3:2 Reserved, must be kept at reset value.

Bits 1:0 FMCSEL[1:0] : FMC kernel clock source selection

• 00: rcc_hclk3 clock selected as kernel peripheral clock (default after reset)
• 01: pll1_q_ck clock selected as kernel peripheral clock
• 10: pll2_r_ck clock selected as kernel peripheral clock
• 11: per_ck clock selected as kernel peripheral clock

9.7.19 RCC domain 2 kernel clock configuration register (RCC_D2CCIP1R)

Address offset: 0x050

Reset value: 0x0000 0000

1. 1. Changing the clock source on-the-fly is allowed and will not generate any timing violation. However the user has to make sure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section : Clock switches and gating .

Bit 31 SWPSEL : SWPMI kernel clock source selection

Set and reset by software.

0: pclk is selected as SWPMI kernel clock (default after reset)

1: hsi_ker_ck clock is selected as SWPMI kernel clock

Bit 30 Reserved, must be kept at reset value.

Bits 29:28 FDCANSEL : FDCAN kernel clock source selection

Set and reset by software.

00: hse_ck clock is selected as FDCAN kernel clock (default after reset)

01: pll1_q_ck clock is selected as FDCAN kernel clock

10: pll2_q_ck clock is selected as FDCAN kernel clock

11: reserved, the kernel clock is disabled

Bits 27:25 Reserved, must be kept at reset value.

Bit 24 DFSDM1SEL : DFSDM1 kernel CIk clock source selection

Set and reset by software.

Note: the DFSDM1 Aclk Clock Source Selection is done by SAI1SEL.

0: rcc_pclk2 is selected as DFSDM1 CIk kernel clock (default after reset)

1: sys_ck clock is selected as DFSDM1 CIk kernel clock

Bits 23:22 Reserved, must be kept at reset value.

Bits 21:20 SPDIFSEL[1:0] : SPDIFRX kernel clock source selection

00: pll1_q_ck clock selected as SPDIFRX kernel clock (default after reset)

01: pll2_r_ck clock selected as SPDIFRX kernel clock

10: pll3_r_ck clock selected as SPDIFRX kernel clock

11: hsi_ker_ck clock selected as SPDIFRX kernel clock

Bit 19 Reserved, must be kept at reset value.

Bits 18:16 SPI45SEL[2:0] : SPI4 and 5 kernel clock source selection

Set and reset by software.

000: APB clock is selected as kernel clock (default after reset)

001: pll2_q_ck clock is selected as kernel clock

010: pll3_q_ck clock is selected as kernel clock

011: hsi_ker_ck clock is selected as kernel clock

100: csi_ker_ck clock is selected as kernel clock

101: hse_ck clock is selected as kernel clock

others: reserved, the kernel clock is disabled

Bit 15 Reserved, must be kept at reset value.

Bits 14:12 SPI123SEL[2:0] : SPI/I2S1,2 and 3 kernel clock source selection

Set and reset by software.

Caution: If the selected clock is the external clock and this clock is stopped, it will not be possible to switch to another clock. Refer to Section : Clock switches and gating for additional information.

000: pll1_q_ck clock selected as SPI/I2S1,2 and 3 kernel clock (default after reset)

001: pll2_p_ck clock selected as SPI/I2S1,2 and 3 kernel clock

010: pll3_p_ck clock selected as SPI/I2S1,2 and 3 kernel clock

011: I2S_CKIN clock selected as SPI/I2S1,2 and 3 kernel clock

100: per_ck clock selected as SPI/I2S1,2 and 3 kernel clock

others: reserved, the kernel clock is disabled

Note: I2S_CKIN is an external clock taken from a pin.

Bits 11:9 Reserved, must be kept at reset value.

Bits 8:6 SAI23SEL[2:0] : SAI2 and SAI3 kernel clock source selection

Set and reset by software.

Caution: If the selected clock is the external clock and this clock is stopped, it will not be possible to switch to another clock. Refer to Section : Clock switches and gating for additional information.

000: pll1_q_ck clock selected as SAI2 and SAI3 kernel clock (default after reset)

001: pll2_p_ck clock selected as SAI2 and SAI3 kernel clock

010: pll3_p_ck clock selected as SAI2 and SAI3 kernel clock

011: I2S_CKIN clock selected as SAI2 and SAI3 kernel clock

100: per_ck clock selected as SAI2 and SAI3 kernel clock

others: reserved, the kernel clock is disabled

Note: I2S_CKIN is an external clock taken from a pin.

Bits 5:3 Reserved, must be kept at reset value.

Bits 2:0 SAI1SEL[2:0] : SAI1 and DFSDM1 kernel Aclk clock source selection

Set and reset by software.

Caution: If the selected clock is the external clock and this clock is stopped, it will not be possible to switch to another clock. Refer to Section : Clock switches and gating for additional information.

Note: DFSDM1 Clock Source Selection is done by DFSDM1SEL.

000: pll1_q_ck clock selected as SAI1 and DFSDM1 Aclk kernel clock (default after reset)

001: pll2_p_ck clock selected as SAI1 and DFSDM1 Aclk kernel clock

010: pll3_p_ck clock selected as SAI1 and DFSDM1 Aclk kernel clock

011: I2S_CKIN clock selected as SAI1 and DFSDM1 Aclk kernel clock

100: per_ck clock selected as SAI1 and DFSDM1 Aclk kernel clock

others: reserved, the kernel clock is disabled

Note: I2S_CKIN is an external clock taken from a pin.

9.7.20 RCC domain 2 kernel clock configuration register (RCC_D2CCIP2R)

Address offset: 0x054

Reset value: 0x0000 0000

1. Changing the clock source on-the-fly is allowed and will not generate any timing violation. However the user has to make sure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section : Clock switches and gating .

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 LPTIM1SEL[2:0] : LPTIM1 kernel clock source selection

Set and reset by software.

000: rcc_pclk1 clock selected as kernel peripheral clock (default after reset)

001: pll2_p_ck clock selected as kernel peripheral clock

010: pll3_r_ck clock selected as kernel peripheral clock

011: lse_ck clock selected as kernel peripheral clock

100: lsi_ck clock selected as kernel peripheral clock

101: per_ck clock selected as kernel peripheral clock

others: reserved, the kernel clock is disabled

Bits 27:24 Reserved, must be kept at reset value.

Bits 23:22 CECSEL[1:0] : HDMI-CEC kernel clock source selection

Set and reset by software.

00: lse_ck clock is selected as kernel clock (default after reset)

01: lsi_ck clock is selected as kernel clock

10: csi_ker_ck divided by 122 is selected as kernel clock

11: reserved, the kernel clock is disabled

Bits 21:20 USBSEL[1:0] : USBOTG 1 and 2 kernel clock source selection

Set and reset by software.

00: Disable the kernel clock (default after reset)

01: pll1_q_ck clock is selected as kernel clock

10: pll3_q_ck clock is selected as kernel clock

11: hsi48_ck clock is selected as kernel clock

Bits 19:14 Reserved, must be kept at reset value.

Bits 13:12 I2C123SEL[1:0] : I2C1,2,3 kernel clock source selection

Set and reset by software.

00: rcc_pclk1 clock is selected as kernel clock (default after reset)

01: pll3_r_ck clock is selected as kernel clock

10: hsi_ker_ck clock is selected as kernel clock

11: csi_ker_ck clock is selected as kernel clock

Bits 11:10 Reserved, must be kept at reset value.

Bits 9:8 RNGSEL[1:0] : RNG kernel clock source selection

Set and reset by software.

00: hsi48_ck clock is selected as kernel clock (default after reset)

01: pll1_q_ck clock is selected as kernel clock

10: lse_ck clock is selected as kernel clock

11: lsi_ck clock is selected as kernel clock

Bits 7:6 Reserved, must be kept at reset value.

Bits 5:3 USART16SEL[2:0] : USART1 and 6 kernel clock source selection

Set and reset by software.

000: rcc_pclk2 clock is selected as kernel clock (default after reset)

001: pll2_q_ck clock is selected as kernel clock

010: pll3_q_ck clock is selected as kernel clock

011: hsi_ker_ck clock is selected as kernel clock

100: csi_ker_ck clock is selected as kernel clock

101: lse_ck clock is selected as kernel clock

others: reserved, the kernel clock is disabled

Bits 2:0 USART234578SEL[2:0] : USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection

Set and reset by software.

000: rcc_pclk1 clock is selected as kernel clock (default after reset)

001: pll2_q_ck clock is selected as kernel clock

010: pll3_q_ck clock is selected as kernel clock

011: hsi_ker_ck clock is selected as kernel clock

100: csi_ker_ck clock is selected as kernel clock

101: lse_ck clock is selected as kernel clock

others: reserved, the kernel clock is disabled

9.7.21 RCC domain 3 kernel clock configuration register (RCC_D3CCIPR)

Address offset: 0x058

Reset value: 0x0000 0000

1. Changing the clock source on-the-fly is allowed, and will not generate any timing violation. However the user has to make sure that both the previous and the new clock sources are present during the switching, and for the whole transition time. Please refer to Section : Clock switches and gating .

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 SPI6SEL[2:0] : SPI6 kernel clock source selection

Set and reset by software.

000: rcc_pclk4 clock selected as kernel peripheral clock (default after reset)
001: pll2_q_ck clock selected as kernel peripheral clock
010: pll3_q_ck clock selected as kernel peripheral clock
011: hsi_ker_ck clock selected as kernel peripheral clock
100: csi_ker_ck clock selected as kernel peripheral clock
101: hse_ck clock selected as kernel peripheral clock
others: reserved, the kernel clock is disabled

Bit 27 Reserved, must be kept at reset value.

Bits 26:24 SAI4BSEL[2:0] : Sub-Block B of SAI4 kernel clock source selection

Set and reset by software.

Caution: If the selected clock is the external clock and this clock is stopped, it will not be possible to switch to another clock. Refer to Section : Clock switches and gating for additional information.

000: pll1_q_ck clock selected as kernel peripheral clock (default after reset)
001: pll2_p_ck clock selected as kernel peripheral clock
010: pll3_p_ck clock selected as kernel peripheral clock
011: I2S_CKIN clock selected as kernel peripheral clock
100: per_ck clock selected as kernel peripheral clock
others: reserved, the kernel clock is disabled

Note: I2S_CKIN is an external clock taken from a pin.

Bits 23:21 SAI4ASEL[2:0] : Sub-Block A of SAI4 kernel clock source selection

Set and reset by software.

Caution: If the selected clock is the external clock and this clock is stopped, it will not be possible to switch to another clock. Refer to Section : Clock switches and gating for additional information.

000: pll1_q_ck clock selected as kernel peripheral clock (default after reset)

001: pll2_p_ck clock selected as kernel peripheral clock

010: pll3_p_ck clock selected as kernel peripheral clock

011: I2S_CKIN clock selected as kernel peripheral clock

100: per_ck clock selected as kernel peripheral clock

others: reserved, the kernel clock is disabled

Note: I2S_CKIN is an external clock taken from a pin.

Bits 20:18 Reserved, must be kept at reset value.

Bits 17:16 ADCSEL[1:0] : SAR ADC kernel clock source selection

Set and reset by software.

00: pll2_p_ck clock selected as kernel peripheral clock (default after reset)

01: pll3_r_ck clock selected as kernel peripheral clock

10: per_ck clock selected as kernel peripheral clock

others: reserved, the kernel clock is disabled

Bits 15:13 LPTIM345SEL[2:0] : LPTIM3,4,5 kernel clock source selection

Set and reset by software.

000: rcc_pclk4 clock selected as kernel peripheral clock (default after reset)

001: pll2_p_ck clock selected as kernel peripheral clock

010: pll3_r_ck clock selected as kernel peripheral clock

011: lse_ck clock selected as kernel peripheral clock

100: lsi_ck clock selected as kernel peripheral clock

101: per_ck clock selected as kernel peripheral clock

others: reserved, the kernel clock is disabled

Bits 12:10 LPTIM2SEL[2:0] : LPTIM2 kernel clock source selection

Set and reset by software.

000: rcc_pclk4 clock selected as kernel peripheral clock (default after reset)

001: pll2_p_ck clock selected as kernel peripheral clock

010: pll3_r_ck clock selected as kernel peripheral clock

011: lse_ck clock selected as kernel peripheral clock

100: lsi_ck clock selected as kernel peripheral clock

101: per_ck clock selected as kernel peripheral clock

others: reserved, the kernel clock is disabled

Bits 9:8 I2C4SEL[1:0] : I2C4 kernel clock source selection

Set and reset by software.

00: rcc_pclk4 clock selected as kernel peripheral clock (default after reset)

01: pll3_r_ck clock selected as kernel peripheral clock

10: hsi_ker_ck clock selected as kernel peripheral clock

11: csi_ker_ck clock selected as kernel peripheral clock

Bits 7:3 Reserved, must be kept at reset value.

Bits 2:0 LPUART1SEL[2:0] : LPUART1 kernel clock source selection

Set and reset by software.

000: rcc_pclk_d3 clock is selected as kernel peripheral clock (default after reset)

001: pll2_q_ck clock is selected as kernel peripheral clock

010: pll3_q_ck clock is selected as kernel peripheral clock

011: hsi_ker_ck clock is selected as kernel peripheral clock

100: csi_ker_ck clock is selected as kernel peripheral clock

101: lse_ck clock is selected as kernel peripheral clock

others: reserved, the kernel clock is disabled

9.7.22 RCC clock source interrupt enable register (RCC_CIER)

Address offset: 0x060

Reset value: 0x0000 0000

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 LSECSSIE : LSE clock security system Interrupt Enable

Set and reset by software to enable/disable interrupt caused by the Clock Security System on external 32 kHz oscillator.

0: LSE CSS interrupt disabled (default after reset)

1: LSE CSS interrupt enabled

Bit 8 PLL3RDYIE : PLL3 ready Interrupt Enable

Set and reset by software to enable/disable interrupt caused by PLL3 lock.

0: PLL3 lock interrupt disabled (default after reset)

1: PLL3 lock interrupt enabled

Bit 7 PLL2RDYIE : PLL2 ready Interrupt Enable

Set and reset by software to enable/disable interrupt caused by PLL2 lock.

0: PLL2 lock interrupt disabled (default after reset)

1: PLL2 lock interrupt enabled

Bit 6 PLL1RDYIE : PLL1 ready Interrupt Enable

Set and reset by software to enable/disable interrupt caused by PLL1 lock.

0: PLL1 lock interrupt disabled (default after reset)

1: PLL1 lock interrupt enabled

Bit 5 HSI48RDYIE : HSI48 ready Interrupt Enable

Set and reset by software to enable/disable interrupt caused by the HSI48 oscillator stabilization.

0: HSI48 ready interrupt disabled (default after reset)

1: HSI48 ready interrupt enabled

Bit 4 CSIRDYIE : CSI ready Interrupt Enable

Set and reset by software to enable/disable interrupt caused by the CSI oscillator stabilization.

0: CSI ready interrupt disabled (default after reset)

1: CSI ready interrupt enabled

Bit 3 HSERDYIE : HSE ready Interrupt Enable

Set and reset by software to enable/disable interrupt caused by the HSE oscillator stabilization.

0: HSE ready interrupt disabled (default after reset)

1: HSE ready interrupt enabled

Set and reset by software to enable/disable interrupt caused by the HSI oscillator stabilization.

0: HSI ready interrupt disabled (default after reset)

1: HSI ready interrupt enabled

Set and reset by software to enable/disable interrupt caused by the LSE oscillator stabilization.

0: LSE ready interrupt disabled (default after reset)

1: LSE ready interrupt enabled

Set and reset by software to enable/disable interrupt caused by the LSI oscillator stabilization.

0: LSI ready interrupt disabled (default after reset)

1: LSI ready interrupt enabled

9.7.23 RCC clock source interrupt flag register (RCC_CIFR)

Address offset: 0x64

Reset value: 0x0000 0000

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 HSECSSF : HSE clock security system Interrupt Flag

Reset by software by writing HSECSSC bit.

Set by hardware in case of HSE clock failure.

0: No clock security interrupt caused by HSE clock failure (default after reset)

1: Clock security interrupt caused by HSE clock failure

Bit 9 LSECSSF : LSE clock security system Interrupt Flag

Reset by software by writing LSECSSC bit.

Set by hardware when a failure is detected on the external 32 kHz oscillator and LSECSSIE is set.

0: No failure detected on the external 32 kHz oscillator (default after reset)

1: A failure is detected on the external 32 kHz oscillator

Bit 8 PLL3RDYF : PLL3 ready Interrupt Flag

Reset by software by writing PLL3RDYC bit.

Set by hardware when the PLL3 locks and PLL3RDYIE is set.

0: No clock ready interrupt caused by PLL3 lock (default after reset)

1: Clock ready interrupt caused by PLL3 lock

Bit 7 PLL2RDYF : PLL2 ready Interrupt Flag

Reset by software by writing PLL2RDYC bit.

Set by hardware when the PLL2 locks and PLL2RDYIE is set.

0: No clock ready interrupt caused by PLL2 lock (default after reset)

1: Clock ready interrupt caused by PLL2 lock

Bit 6 PLL1RDYF : PLL1 ready Interrupt Flag

Reset by software by writing PLL1RDYC bit.

Set by hardware when the PLL1 locks and PLL1RDYIE is set.

0: No clock ready interrupt caused by PLL1 lock (default after reset)

1: Clock ready interrupt caused by PLL1 lock

Bit 5 HSI48RDYF : HSI48 ready Interrupt Flag

Reset by software by writing HSI48RDYC bit.

Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set.

0: No clock ready interrupt caused by the HSI48 oscillator (default after reset)

1: Clock ready interrupt caused by the HSI48 oscillator

Reset by software by writing CSIRDYC bit.

Set by hardware when the CSI clock becomes stable and CSIRDYIE is set.

0: No clock ready interrupt caused by the CSI (default after reset)

1: Clock ready interrupt caused by the CSI

Reset by software by writing HSERDYC bit.

Set by hardware when the HSE clock becomes stable and HSERDYIE is set.

0: No clock ready interrupt caused by the HSE (default after reset)

1: Clock ready interrupt caused by the HSE

Reset by software by writing HSIRDYC bit.

Set by hardware when the HSI clock becomes stable and HSIRDYIE is set.

0: No clock ready interrupt caused by the HSI (default after reset)

1: Clock ready interrupt caused by the HSI

Reset by software by writing LSERDYC bit.

Set by hardware when the LSE clock becomes stable and LSERDYIE is set.

0: No clock ready interrupt caused by the LSE (default after reset)

1: Clock ready interrupt caused by the LSE

Reset by software by writing LSIRDYC bit.

Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.

0: No clock ready interrupt caused by the LSI (default after reset)

1: Clock ready interrupt caused by the LSI

9.7.24 RCC clock source interrupt clear register (RCC_CICR)

Address offset: 0x68

Reset value: 0x0000 0000

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 HSECSSC : HSE clock security system Interrupt Clear

Set by software to clear HSECSSF.

Reset by hardware when clear done.

0: HSECSSF no effect (default after reset)

1: HSECSSF cleared

Bit 9 LSECSSC : LSE clock security system Interrupt Clear

Set by software to clear LSECSSF.

Reset by hardware when clear done.

0: LSECSSF no effect (default after reset)

1: LSECSSF cleared

Bit 8 PLL3RDYC : PLL3 ready Interrupt Clear

Set by software to clear PLL3RDYF.

Reset by hardware when clear done.

0: PLL3RDYF no effect (default after reset)

1: PLL3RDYF cleared

Bit 7 PLL2RDYC : PLL2 ready Interrupt Clear

Set by software to clear PLL2RDYF.

Reset by hardware when clear done.

0: PLL2RDYF no effect (default after reset)

1: PLL2RDYF cleared

Bit 6 PLL1RDYC : PLL1 ready Interrupt Clear

Set by software to clear PLL1RDYF.

Reset by hardware when clear done.

0: PLL1RDYF no effect (default after reset)

1: PLL1RDYF cleared

Bit 5 HSI48RDYC : HSI48 ready Interrupt Clear

Set by software to clear HSI48RDYF.

Reset by hardware when clear done.

0: HSI48RDYF no effect (default after reset)

1: HSI48RDYF cleared

1. Bit 4 CSIRDYC : CSI ready Interrupt Clear
   Set by software to clear CSIRDYF.
   Reset by hardware when clear done.
   0: CSIRDYF no effect (default after reset)
   1: CSIRDYF cleared
2. Bit 3 HSERDYC : HSE ready Interrupt Clear
   Set by software to clear HSERDYF.
   Reset by hardware when clear done.
   0: HSERDYF no effect (default after reset)
   1: HSERDYF cleared
3. Bit 2 HSIRDYC : HSI ready Interrupt Clear
   Set by software to clear HSIRDYF.
   Reset by hardware when clear done.
   0: HSIRDYF no effect (default after reset)
   1: HSIRDYF cleared
4. Bit 1 LSERDYC : LSE ready Interrupt Clear
   Set by software to clear LSERDYF.
   Reset by hardware when clear done.
   0: LSERDYF no effect (default after reset)
   1: LSERDYF cleared
5. Bit 0 LSIRDYC : LSI ready Interrupt Clear
   Set by software to clear LSIRDYF.
   Reset by hardware when clear done.
   0: LSIRDYF no effect (default after reset)
   1: LSIRDYF cleared

9.7.25 RCC Backup domain control register (RCC_BDCR)

Address offset: 0x070

Reset value: 0x0000 0000, reset by Backup domain reset.

Access: \( 0 \leq \text{wait state} \leq 7 \) , word, half-word and byte access. Wait states are inserted in case of successive accesses to this register.

After a system reset, the RCC_BDCR register is write-protected. To modify this register, the DBP bit in the PWR CPU1 control register (PWR_CPU1CR) has to be set to '1'.

RCC_BDCR bits are only reset after a backup domain reset (see Section 9.4.6: Backup domain reset ). Any other internal or external reset will not have any effect on these bits.

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 BDRST : Backup domain software reset

• Set and reset by software.
• 0: Reset not activated (default after backup domain reset)
• 1: Resets the entire VSW domain

Bit 15 RTCEN : RTC clock enable

• Set and reset by software.
• 0: rtc_ck clock is disabled (default after backup domain reset)
• 1: rtc_ck clock enabled

Bits 14:10 Reserved, must be kept at reset value.

Bits 9:8 RTCSEL[1:0] : RTC clock source selection

Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The BDRST bit can be used to reset them, then it can be written one time again.

If HSE is selected as RTC clock: this clock is lost when the system is in Stop mode or in case of a pin reset (NRST).

• 00: No clock (default after backup domain reset)
• 01: LSE clock used as RTC clock
• 10: LSI clock used as RTC clock
• 11: HSE clock divided by RTCPRE value is used as RTC clock

Bit 7 Reserved, must be kept at reset value.

Set by hardware to indicate when a failure has been detected by the Clock Security System on the external 32 kHz oscillator.

0: No failure detected on 32 kHz oscillator (default after backup domain reset)

1: Failure detected on 32 kHz oscillator

Set by software to enable the Clock Security System on 32 kHz oscillator.

LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware), and after RTCSEL is selected.

Once enabled this bit cannot be disabled, except after a LSE failure detection (LSECSSD = '1'). In that case the software must disable LSECSSON.

0: Clock Security System on 32 kHz oscillator OFF (default after backup domain reset)

1: Clock Security System on 32 kHz oscillator ON

Set by software to select the driving capability of the LSE oscillator.

00: Lowest drive (default after backup domain reset)

01: Medium low drive

10: Medium high drive

11: Highest drive

Note: The driving capability cannot be changed after LSEON has been set to 1.

Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = '1')

0: LSE oscillator not bypassed (default after backup domain reset)

1: LSE oscillator bypassed

Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to '0'.

0: LSE oscillator not ready (default after backup domain reset)

1: LSE oscillator ready

Set and reset by software.