RM0399-STM32H745-755-747-757

Introduction

This reference manual targets application developers. It provides complete information on how to use the STM32H745/55/47/57xx microcontroller memory and peripherals.

The STM32H745/755 and STM32H747/757 lines include microcontrollers with different memory sizes, packages and peripherals.

The devices include ST state-of-the-art patented technology.

For ordering information, mechanical, and electrical device characteristics refer to the corresponding datasheets.

For information on the Arm ® Cortex ® -M4 with FPU and Arm ® Cortex ® -M7 with FPU cores, refer to the corresponding Arm Technical Reference Manuals .

Contents

3.3.1RAMECC block diagram .....146
3.3.2RAMECC internal signals .....148
3.3.3RAMECC monitor mapping .....148
3.4RAMECC registers .....149
3.4.1RAMECC interrupt enable register (RAMECC_IER) .....149
3.4.2RAMECC monitor x configuration register (RAMECC_MxCR) .....150
3.4.3RAMECC monitor x status register (RAMECC_MxSR) .....150
3.4.4RAMECC monitor x failing address register (RAMECC_MxFAR) .....151
3.4.5RAMECC monitor x failing data low register (RAMECC_MxFDRL) .....151
3.4.6RAMECC monitor x failing data high register (RAMECC_MxFDRH) .....152
3.4.7RAMECC monitor x failing ECC error code register
RAMECC_MxFECR) .....		152
3.4.8RAMECC register map .....153
4Embedded flash memory (FLASH) .....154
4.1Introduction .....154
4.2FLASH main features .....154
4.3FLASH functional description .....155
4.3.1FLASH block diagram .....155
4.3.2FLASH internal signals .....156
4.3.3FLASH architecture and integration in the system .....156
4.3.4Flash memory architecture and usage .....158
4.3.5FLASH system performance enhancements .....162
4.3.6FLASH data protection schemes .....162
4.3.7Overview of FLASH operations .....163
4.3.8FLASH read operations .....164
4.3.9FLASH program operations .....167
4.3.10FLASH erase operations .....171
4.3.11FLASH parallel operations .....174
4.3.12Flash memory error protections .....174
4.3.13Flash bank and register swapping .....176
4.3.14FLASH reset and clocks .....179
4.4FLASH option bytes .....179
4.4.1About option bytes .....179
4.4.2Option byte loading .....180
4.4.3Option byte modification .....180
4.4.4Option bytes overview .....183
4.4.5Description of user and system option bytes . . . . .185
4.4.6Description of data protection option bytes . . . . .187
4.4.7Description of boot address option bytes . . . . .188
4.5FLASH protection mechanisms . . . . .188
4.5.1FLASH configuration protection . . . . .188
4.5.2Write protection . . . . .190
4.5.3Readout protection (RDP) . . . . .191
4.5.4Proprietary code readout protection (PCROP) . . . . .195
4.5.5Secure access mode . . . . .196
4.6FLASH low-power modes . . . . .198
4.6.1Introduction . . . . .198
4.6.2Managing the FLASH domain switching to DStop or DStandby . . . . .198
4.7FLASH error management . . . . .200
4.7.1Introduction . . . . .200
4.7.2Write protection error (WRPERR) . . . . .200
4.7.3Programming sequence error (PGSERR) . . . . .201
4.7.4Strobe error (STRBERR) . . . . .202
4.7.5Inconsistency error (INCERR) . . . . .202
4.7.6Operation error (OPERR) . . . . .203
4.7.7Error correction code error (SNECCERR/DBECCERR) . . . . .203
4.7.8Read protection error (RDPERR) . . . . .204
4.7.9Read secure error (RDSERR) . . . . .204
4.7.10CRC read error (CRCRDERR) . . . . .204
4.7.11Option byte change error (OPTCHANGEERR) . . . . .205
4.7.12Miscellaneous HardFault errors . . . . .205
4.8FLASH interrupts . . . . .205
4.9FLASH registers . . . . .208
4.9.1FLASH access control register (FLASH_ACR) . . . . .208
4.9.2FLASH key register for bank 1 (FLASH_KEYR1) . . . . .208
4.9.3FLASH option key register (FLASH_OPTKEYR) . . . . .209
4.9.4FLASH control register for bank 1 (FLASH_CR1) . . . . .209
4.9.5FLASH status register for bank 1 (FLASH_SR1) . . . . .214
4.9.6FLASH clear control register for bank 1 (FLASH_CCR1) . . . . .217
4.9.7FLASH option control register (FLASH_OPTCR) . . . . .218
4.9.8FLASH option status register (FLASH_OPTSR_CUR) . . . . .219
4.9.9FLASH option status register (FLASH_OPTSR_PRG) . . . . .222
4.9.10FLASH option clear control register (FLASH_OPTCCR) . . . . .224
4.9.11FLASH protection address for bank 1 (FLASH_PRAR_CUR1) . . . . .225
4.9.12FLASH protection address for bank 1 (FLASH_PRAR_PRG1) . . . . .225
4.9.13FLASH secure address for bank 1 (FLASH_SCAR_CUR1) . . . . .226
4.9.14FLASH secure address for bank 1 (FLASH_SCAR_PRG1) . . . . .227
4.9.15FLASH write sector protection for bank 1
(FLASH_WPSN_CUR1R) . . . . .		227
4.9.16FLASH write sector protection for bank 1
(FLASH_WPSN_PRG1R) . . . . .		228
4.9.17FLASH register boot address (for Arm® Cortex®-M7 core
(FLASH_BOOT7_CURR) . . . . .		228
4.9.18FLASH register boot address for Arm® Cortex®-M7 core
(FLASH_BOOT7_PRGR) . . . . .		229
4.9.19FLASH register boot address for Arm® Cortex®-M4 core
(FLASH_BOOT4_CURR) . . . . .		229
4.9.20FLASH register boot address for Arm® Cortex®-M4 core
(FLASH_BOOT4_PRGR) . . . . .		230
4.9.21FLASH CRC control register for bank 1 (FLASH_CRCCR1) . . . . .230
4.9.22FLASH CRC start address register for bank 1
(FLASH_CRCSADD1R) . . . . .		232
4.9.23FLASH CRC end address register for bank 1
(FLASH_CRCEADD1R) . . . . .		232
4.9.24FLASH CRC data register (FLASH_CRCDATAR) . . . . .232
4.9.25FLASH ECC fail address for bank 1 (FLASH_ECC_FA1R) . . . . .233
4.9.26FLASH key register for bank 2 (FLASH_KEYR2) . . . . .233
4.9.27FLASH control register for bank 2 (FLASH_CR2) . . . . .234
4.9.28FLASH status register for bank 2 (FLASH_SR2) . . . . .238
4.9.29FLASH clear control register for bank 2 (FLASH_CCR2) . . . . .241
4.9.30FLASH protection address for bank 2 (FLASH_PRAR_CUR2) . . . . .242
4.9.31FLASH protection address for bank 2 (FLASH_PRAR_PRG2) . . . . .242
4.9.32FLASH secure address for bank 2 (FLASH_SCAR_CUR2) . . . . .243
4.9.33FLASH secure address for bank 2 (FLASH_SCAR_PRG2) . . . . .244
4.9.34FLASH write sector protection for bank 2
(FLASH_WPSN_CUR2R) . . . . .		245
4.9.35FLASH write sector protection for bank 2
(FLASH_WPSN_PRG2R) . . . . .		245
4.9.36FLASH CRC control register for bank 2 (FLASH_CRCCR2) . . . . .246
4.9.37FLASH CRC start address register for bank 2
(FLASH_CRCSADD2R) . . . . .		247
4.9.38FLASH CRC end address register for bank 2
(FLASH_CRCEADD2R) . . . . .		248
7.4.4Backup domain . . . . .282
7.4.5VBAT battery charging . . . . .284
7.4.6Analog supply . . . . .284
7.4.7USB regulator . . . . .285
7.4.8DSI regulator . . . . .285
7.5Power supply supervision . . . . .286
7.5.1Power-on reset (POR)/power-down reset (PDR) . . . . .287
7.5.2Brownout reset (BOR) . . . . .287
7.5.3Programmable voltage detector (PVD) . . . . .288
7.5.4Analog voltage detector (AVD) . . . . .290
7.5.5Battery voltage thresholds . . . . .291
7.5.6Temperature thresholds . . . . .292
7.5.7VCORE maximum voltage level detector . . . . .292
7.6Power management . . . . .293
7.6.1Operating modes . . . . .294
7.6.2Voltage scaling . . . . .297
7.6.3Power control modes . . . . .299
7.6.4Power management examples . . . . .303
7.7Low-power modes . . . . .310
7.7.1Slowing down system clocks . . . . .310
7.7.2Controlling peripheral clocks . . . . .310
7.7.3Entering low-power modes . . . . .310
7.7.4Exiting from low-power modes . . . . .311
7.7.5CSleep mode . . . . .312
7.7.6CStop mode . . . . .312
7.7.7DStop mode . . . . .313
7.7.8Stop mode . . . . .315
7.7.9DStandby mode . . . . .320
7.7.10Standby mode . . . . .322
7.7.11Monitoring low-power modes . . . . .324
7.8PWR registers . . . . .325
7.8.1PWR control register 1 (PWR_CR1) . . . . .325
7.8.2PWR control status register 1 (PWR_CSR1) . . . . .327
7.8.3PWR control register 2 (PWR_CR2) . . . . .328
7.8.4PWR control register 3 (PWR_CR3) . . . . .329
7.8.5PWR CPU1 control register (PWR_CPU1CR) . . . . .331
7.8.6PWR CPU2 control register (PWR_CPU2CR) . . . . .333
9.5.4Clock output generation (MCO1/MCO2) . . . . .372
9.5.5PLL description . . . . .372
9.5.6System clock (sys_ck) . . . . .377
9.5.7Handling clock generators in Stop and Standby mode . . . . .379
9.5.8Kernel clock selection . . . . .381
9.5.9General clock concept overview . . . . .395
9.5.10Peripheral allocation . . . . .400
9.5.11Peripheral clock gating control . . . . .403
9.5.12CPU and bus matrix clock gating control . . . . .409
9.6RCC Interrupts . . . . .413
9.7RCC registers . . . . .414
9.7.1Register mapping overview . . . . .414
9.7.2RCC source control register (RCC_CR) . . . . .415
9.7.3RCC HSI configuration register (RCC_HSI CFGR) . . . . .419
9.7.4RCC clock recovery RC register (RCC_CRR CR) . . . . .420
9.7.5RCC CSI configuration register (RCC_CSI CFGR) . . . . .421
9.7.6RCC clock configuration register (RCC_CFGR) . . . . .422
9.7.7RCC domain 1 clock configuration register (RCC_D1 CFGR) . . . . .425
9.7.8RCC domain 2 clock configuration register (RCC_D2 CFGR) . . . . .427
9.7.9RCC domain 3 clock configuration register (RCC_D3 CFGR) . . . . .428
9.7.10RCC PLLs clock source selection register (RCC_PLLCKSEL R) . . . . .429
9.7.11RCC PLL configuration register (RCC_PLL CFGR) . . . . .431
9.7.12RCC PLL1 dividers configuration register (RCC_PLL1 DIVR) . . . . .434
9.7.13RCC PLL1 fractional divider register (RCC_PLL1 FRACR) . . . . .436
9.7.14RCC PLL2 dividers configuration register (RCC_PLL2 DIVR) . . . . .437
9.7.15RCC PLL2 fractional divider register (RCC_PLL2 FRACR) . . . . .439
9.7.16RCC PLL3 dividers configuration register (RCC_PLL3 DIVR) . . . . .440
9.7.17RCC PLL3 fractional divider register (RCC_PLL3 FRACR) . . . . .442
9.7.18RCC domain 1 kernel clock configuration register (RCC_D1 CCIPR) . . . . .443
9.7.19RCC domain 2 kernel clock configuration register (RCC_D2 CCIP1R) . . . . .444
9.7.20RCC domain 2 kernel clock configuration register (RCC_D2 CCIP2R) . . . . .447
9.7.21RCC domain 3 kernel clock configuration register (RCC_D3 CCIPR) . . . . .449
9.7.22RCC clock source interrupt enable register (RCC_CIER) . . . . .452
9.7.23RCC clock source interrupt flag register (RCC_CIFR) . . . . .454
9.7.24RCC clock source interrupt clear register (RCC_CICR) . . . . .456
9.7.25RCC Backup domain control register (RCC_BDCR) . . . . .458
9.7.26RCC clock control and status register (RCC_CSR) . . . . .460
9.7.27RCC AHB3 reset register (RCC_AHB3RSTR) .....461
9.7.28RCC AHB1 peripheral reset register(RCC_AHB1RSTR) .....463
9.7.29RCC AHB2 peripheral reset register (RCC_AHB2RSTR) .....465
9.7.30RCC AHB4 peripheral reset register (RCC_AHB4RSTR) .....466
9.7.31RCC APB3 peripheral reset register (RCC_APB3RSTR) .....468
9.7.32RCC APB1 peripheral reset register (RCC_APB1LRSTR) .....469
9.7.33RCC APB1 peripheral reset register (RCC_APB1HRSTR) .....472
9.7.34RCC APB2 peripheral reset register (RCC_APB2RSTR) .....473
9.7.35RCC APB4 peripheral reset register (RCC_APB4RSTR) .....475
9.7.36RCC global control register (RCC_GCR) .....477
9.7.37RCC D3 Autonomous mode register (RCC_D3AMR) .....478
9.7.38RCC reset status register (RCC_RSR) .....481
9.7.39RCC AHB3 clock register (RCC_AHB3ENR) .....484
9.7.40RCC AHB1 clock register (RCC_AHB1ENR) .....487
9.7.41RCC AHB2 clock register (RCC_AHB2ENR) .....489
9.7.42RCC AHB4 clock register (RCC_AHB4ENR) .....492
9.7.43RCC APB3 clock register (RCC_APB3ENR) .....495
9.7.44RCC APB1 clock register (RCC_APB1LENR) .....496
9.7.45RCC APB1 clock register (RCC_APB1HENR) .....500
9.7.46RCC APB2 clock register (RCC_APB2ENR) .....502
9.7.47RCC APB4 clock register (RCC_APB4ENR) .....505
9.7.48RCC AHB3 Sleep clock register (RCC_AHB3LPENR) .....508
9.7.49RCC AHB1 Sleep clock register (RCC_AHB1LPENR) .....510
9.7.50RCC AHB2 Sleep clock register (RCC_AHB2LPENR) .....512
9.7.51RCC AHB4 Sleep clock register (RCC_AHB4LPENR) .....514
9.7.52RCC APB3 Sleep clock register (RCC_APB3LPENR) .....517
9.7.53RCC APB1 Low Sleep clock register (RCC_APB1LLPENR) .....518
9.7.54RCC APB1 High Sleep clock register (RCC_APB1HLPENR) .....522
9.7.55RCC APB2 Sleep clock register (RCC_APB2LPENR) .....524
9.7.56RCC APB4 Sleep clock register (RCC_APB4LPENR) .....527
9.8RCC register map .....530
10Clock recovery system (CRS) .....542
10.1Introduction .....542
10.2CRS main features .....542
10.3CRS implementation .....542
10.4CRS functional description .....543
10.4.1CRS block diagram . . . . .543
10.5CRS internal signals . . . . .543
10.5.1Synchronization input . . . . .544
10.5.2Frequency error measurement . . . . .544
10.5.3Frequency error evaluation and automatic trimming . . . . .545
10.5.4CRS initialization and configuration . . . . .546
10.6CRS low-power modes . . . . .547
10.7CRS interrupts . . . . .547
10.8CRS registers . . . . .548
10.8.1CRS control register (CRS_CR) . . . . .548
10.8.2CRS configuration register (CRS_CFGR) . . . . .549
10.8.3CRS interrupt and status register (CRS_ISR) . . . . .550
10.8.4CRS interrupt flag clear register (CRS_ICR) . . . . .551
10.8.5CRS register map . . . . .552
11Hardware semaphore (HSEM) . . . . .554
11.1Introduction . . . . .554
11.2Main features . . . . .554
11.3Functional description . . . . .555
11.3.1HSEM block diagram . . . . .555
11.3.2HSEM internal signals . . . . .555
11.3.3HSEM lock procedures . . . . .555
11.3.4HSEM write/read/read lock register address . . . . .557
11.3.5HSEM unlock procedures . . . . .557
11.3.6HSEM COREID semaphore clear . . . . .558
11.3.7HSEM interrupts . . . . .558
11.3.8AHB bus master ID verification . . . . .560
11.4HSEM registers . . . . .561
11.4.1HSEM register semaphore x (HSEM_Rx) . . . . .561
11.4.2HSEM read lock register semaphore x (HSEM_RLRx) . . . . .562
11.4.3HSEM interrupt enable register (HSEM_CnIER) . . . . .563
11.4.4HSEM interrupt clear register (HSEM_CnICR) . . . . .563
11.4.5HSEM interrupt status register (HSEM_CnISR) . . . . .563
11.4.6HSEM interrupt status register (HSEM_CnMISR) . . . . .564
11.4.7HSEM clear register (HSEM_CR) . . . . .564
11.4.8HSEM clear semaphore key register (HSEM_KEYR) . . . . .565
11.4.9HSEM register map .....566
12General-purpose I/Os (GPIO) .....568
12.1Introduction .....568
12.2GPIO main features .....568
12.3GPIO functional description .....568
12.3.1General-purpose I/O (GPIO) .....571
12.3.2I/O pin alternate function multiplexer and mapping .....571
12.3.3I/O port control registers .....572
12.3.4I/O port data registers .....572
12.3.5I/O data bitwise handling .....572
12.3.6GPIO locking mechanism .....573
12.3.7I/O alternate function input/output .....573
12.3.8External interrupt/wake-up lines .....573
12.3.9Input configuration .....574
12.3.10Output configuration .....574
12.3.11I/O compensation cell .....575
12.3.12Alternate function configuration .....575
12.3.13Analog configuration .....576
12.3.14Using the HSE or LSE oscillator pins as GPIOs .....577
12.3.15Using the GPIO pins in the backup supply domain .....577
12.4GPIO registers .....578
12.4.1GPIO port mode register (GPIOx_MODER)
(x = A to K) .....		578
12.4.2GPIO port output type register (GPIOx_OTYPER)
(x = A to K) .....		578
12.4.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to K) .....		579
12.4.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to K) .....		579
12.4.5GPIO port input data register (GPIOx_IDR)
(x = A to K) .....		580
12.4.6GPIO port output data register (GPIOx_ODR)
(x = A to K) .....		580
12.4.7GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to K) .....		581
12.4.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to K) .....		581
12.4.9GPIO alternate function low register (GPIOx_AFRL)
(x = A to K) .....		582
12.4.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to J) .....		583
12.4.11GPIO register map .....584
13System configuration controller (SYSCFG) .....586
13.1Introduction .....586
13.2SYSCFG main features .....586
13.3SYSCFG registers .....586
13.3.1SYSCFG peripheral mode configuration register (SYSCFG_PMCR) .586
13.3.2SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) .....		589
13.3.3SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) .....		589
13.3.4SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) .....		591
13.3.5SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) .....		592
13.3.6SYSCFG configuration register (SYSCFG_CFGR) .....593
13.3.7SYSCFG compensation cell control/status register
(SYSCFG_CCCSR) .....		596
13.3.8SYSCFG compensation cell value register (SYSCFG_CCVR) .....597
13.3.9SYSCFG compensation cell code register (SYSCFG_CCCR) .....597
13.3.10SYSCFG power control register (SYSCFG_PWRRCR) .....598
13.3.11SYSCFG system register (SYSCFG_SR0) .....598
13.3.12SYSCFG package register (SYSCFG_PKGR) .....599
13.3.13SYSCFG user register 0 (SYSCFG_UR0) .....600
13.3.14SYSCFG user register 1 (SYSCFG_UR1) .....601
13.3.15SYSCFG user register 2 (SYSCFG_UR2) .....601
13.3.16SYSCFG user register 3 (SYSCFG_UR3) .....602
13.3.17SYSCFG user register 4 (SYSCFG_UR4) .....602
13.3.18SYSCFG user register 5 (SYSCFG_UR5) .....603
13.3.19SYSCFG user register 6 (SYSCFG_UR6) .....603
13.3.20SYSCFG user register 7 (SYSCFG_UR7) .....604
13.3.21SYSCFG user register 8 (SYSCFG_UR8) .....604
13.3.22SYSCFG user register 9 (SYSCFG_UR9) .....605
13.3.23SYSCFG user register 10 (SYSCFG_UR10) .....605
13.3.24SYSCFG user register 11 (SYSCFG_UR11) .....606
13.3.25SYSCFG user register 12 (SYSCFG_UR12) . . . . .606
13.3.26SYSCFG user register 13 (SYSCFG_UR13) . . . . .607
13.3.27SYSCFG user register 14 (SYSCFG_UR14) . . . . .608
13.3.28SYSCFG user register 15 (SYSCFG_UR15) . . . . .609
13.3.29SYSCFG user register 16 (SYSCFG_UR16) . . . . .610
13.3.30SYSCFG user register 17 (SYSCFG_UR17) . . . . .610
13.3.31SYSCFG register maps . . . . .611
14Block interconnect . . . . .614
14.1Peripheral interconnect . . . . .614
14.1.1Introduction . . . . .614
14.1.2Connection overview . . . . .614
14.2Wakeup from low power modes . . . . .633
14.3DMA . . . . .638
14.3.1MDMA (D1 domain) . . . . .639
14.3.2DMAMUX1, DMA1 and DMA2 (D2 domain) . . . . .641
14.3.3DMAMUX2, BDMA (D3 domain) . . . . .646
15MDMA controller (MDMA) . . . . .649
15.1MDMA introduction . . . . .649
15.2MDMA main features . . . . .649
15.3MDMA functional description . . . . .651
15.3.1MDMA block diagram . . . . .651
15.3.2MDMA internal signals . . . . .651
15.3.3MDMA overview . . . . .651
15.3.4MDMA channel . . . . .653
15.3.5Source, destination and transfer modes . . . . .653
15.3.6Pointer update . . . . .653
15.3.7MDMA buffer transfer . . . . .654
15.3.8Request arbitration . . . . .655
15.3.9FIFO . . . . .655
15.3.10Block transfer . . . . .655
15.3.11Block repeat mode . . . . .656
15.3.12Linked-list mode . . . . .656
15.3.13MDMA transfer completion . . . . .656
15.3.14MDMA transfer suspension . . . . .656
15.3.15Error management . . . . .657
15.4MDMA interrupts . . . . .657
15.5MDMA registers . . . . .658
15.5.1MDMA global interrupt status register (MDMA_GISR0) . . . . .658
15.5.2MDMA channel x interrupt status register (MDMA_CxISR) . . . . .658
15.5.3MDMA channel x interrupt flag clear register (MDMA_CxIFCR) . . . . .660
15.5.4MDMA channel x error status register (MDMA_CxESR) . . . . .660
15.5.5MDMA channel x control register (MDMA_CxCR) . . . . .661
15.5.6MDMA channel x transfer configuration register (MDMA_CxTCR) . . . . .663
15.5.7MDMA channel x block number of data register (MDMA_CxBNDTR) . . . . .667
15.5.8MDMA channel x source address register (MDMA_CxSAR) . . . . .668
15.5.9MDMA channel x destination address register (MDMA_CxDAR) . . . . .669
15.5.10MDMA channel x block repeat address update register
(MDMA_CxBRUR) . . . . .		669
15.5.11MDMA channel x link address register (MDMA_CxLAR) . . . . .670
15.5.12MDMA channel x trigger and bus selection register
(MDMA_CxTBR) . . . . .		671
15.5.13MDMA channel x mask address register (MDMA_CxMAR) . . . . .672
15.5.14MDMA channel x mask data register (MDMA_CxMDR) . . . . .672
15.5.15MDMA register map . . . . .673
16Direct memory access controller (DMA) . . . . .674
16.1DMA introduction . . . . .674
16.2DMA main features . . . . .674
16.3DMA functional description . . . . .676
16.3.1DMA block diagram . . . . .676
16.3.2DMA internal signals . . . . .676
16.3.3DMA overview . . . . .676
16.3.4DMA transactions . . . . .677
16.3.5DMA request mapping . . . . .677
16.3.6Arbiter . . . . .678
16.3.7DMA streams . . . . .678
16.3.8Source, destination and transfer modes . . . . .678
16.3.9Pointer incrementation . . . . .682
16.3.10Circular mode . . . . .683
16.3.11Double-buffer mode . . . . .683
16.3.12Programmable data width, packing/unpacking, endianness . . . . .684
16.3.13Single and burst transfers . . . . .685
17.5BDMA interrupts . . . . .718
17.6BDMA registers . . . . .718
17.6.1BDMA interrupt status register (BDMA_ISR) . . . . .718
17.6.2BDMA interrupt flag clear register (BDMA_IFCR) . . . . .721
17.6.3BDMA channel x configuration register (BDMA_CCRx) . . . . .722
17.6.4BDMA channel x number of data to transfer register
(BDMA_CNDTRx) . . . . .		726
17.6.5BDMA channel x peripheral address register (BDMA_CPARx) . . . . .726
17.6.6BDMA channel x memory 0 address register (BDMA_CM0ARx) . . . . .727
17.6.7BDMA channel x memory 1 address register (BDMA_CM1ARx) . . . . .728
17.6.8BDMA register map . . . . .728
18DMA request multiplexer (DMAMUX) . . . . .731
18.1Introduction . . . . .731
18.2DMAMUX main features . . . . .732
18.3DMAMUX implementation . . . . .732
18.3.1DMAMUX1 and DMAMUX2 instantiation . . . . .732
18.3.2DMAMUX1 mapping . . . . .732
18.3.3DMAMUX2 mapping . . . . .735
18.4DMAMUX functional description . . . . .738
18.4.1DMAMUX block diagram . . . . .738
18.4.2DMAMUX signals . . . . .739
18.4.3DMAMUX channels . . . . .739
18.4.4DMAMUX request line multiplexer . . . . .739
18.4.5DMAMUX request generator . . . . .742
18.5DMAMUX interrupts . . . . .743
18.6DMAMUX registers . . . . .744
18.6.1DMAMUX1 request line multiplexer channel x configuration register
(DMAMUX1_CxCR) . . . . .		744
18.6.2DMAMUX2 request line multiplexer channel x configuration register
(DMAMUX2_CxCR) . . . . .		745
18.6.3DMAMUX1 request line multiplexer interrupt channel status register
(DMAMUX1_CSR) . . . . .		746
18.6.4DMAMUX2 request line multiplexer interrupt channel status register
(DMAMUX2_CSR) . . . . .		746
18.6.5DMAMUX1 request line multiplexer interrupt clear flag register
(DMAMUX1_CFR) . . . . .		747

18.6.6 DMAMUX2 request line multiplexer interrupt clear flag register (DMAMUX2_CFR) . . . . . 747

18.6.7 DMAMUX1 request generator channel x configuration register (DMAMUX1_RGxCR) . . . . . 748

18.6.8 DMAMUX2 request generator channel x configuration register (DMAMUX2_RGxCR) . . . . . 748

18.6.9 DMAMUX1 request generator interrupt status register (DMAMUX1_RGSR) . . . . . 749

18.6.10 DMAMUX2 request generator interrupt status register (DMAMUX2_RGSR) . . . . . 750

18.6.11 DMAMUX1 request generator interrupt clear flag register (DMAMUX1_RGCFR) . . . . . 750

18.6.12 DMAMUX2 request generator interrupt clear flag register (DMAMUX2_RGCFR) . . . . . 751

18.6.13 DMAMUX register map . . . . . 752

19 Chrom-ART Accelerator controller (DMA2D) . . . . . 754

19.1 DMA2D introduction . . . . . 754

19.2 DMA2D main features . . . . . 754

19.3 DMA2D functional description . . . . . 755

19.3.1 General description . . . . . 755

19.3.2 DMA2D internal signals . . . . . 756

19.3.3 DMA2D control . . . . . 756

19.3.4 DMA2D foreground and background FIFOs . . . . . 757

19.3.5 DMA2D foreground and background PFC . . . . . 757

19.3.6 DMA2D foreground and background CLUT interface . . . . . 759

19.3.7 DMA2D blender . . . . . 760

19.3.8 DMA2D output PFC . . . . . 760

19.3.9 DMA2D output FIFO . . . . . 761

19.3.10 DMA2D output FIFO byte reordering . . . . . 762

19.3.11 DMA2D AXI master port timer . . . . . 763

19.3.12 DMA2D transactions . . . . . 763

19.3.13 DMA2D configuration . . . . . 764

19.3.14 YCbCr support . . . . . 768

19.3.15 DMA2D transfer control (start, suspend, abort, and completion) . . . . . 768

19.3.16 Watermark . . . . . 768

19.3.17 Error management . . . . . 768

19.3.18 AXI dead time . . . . . 769

19.4 DMA2D interrupts . . . . . 769

19.5DMA2D registers . . . . .770
19.5.1DMA2D control register (DMA2D_CR) . . . . .770
19.5.2DMA2D interrupt status register (DMA2D_ISR) . . . . .771
19.5.3DMA2D interrupt flag clear register (DMA2D_IFCR) . . . . .772
19.5.4DMA2D foreground memory address register (DMA2D_FGMAR) . . . . .773
19.5.5DMA2D foreground offset register (DMA2D_FGOR) . . . . .773
19.5.6DMA2D background memory address register (DMA2D_BGMAR) . . . . .774
19.5.7DMA2D background offset register (DMA2D_BGOR) . . . . .774
19.5.8DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . .775
19.5.9DMA2D foreground color register (DMA2D_FGCOLR) . . . . .776
19.5.10DMA2D background PFC control register (DMA2D_BGPFCCR) . . . . .777
19.5.11DMA2D background color register (DMA2D_BGCOLR) . . . . .778
19.5.12DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR) . . . . .		779
19.5.13DMA2D background CLUT memory address register
(DMA2D_BGCMAR) . . . . .		779
19.5.14DMA2D output PFC control register (DMA2D_OPFCCR) . . . . .780
19.5.15DMA2D output color register (DMA2D_OCOLR) . . . . .781
19.5.16DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .781
19.5.17DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .782
19.5.18DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .782
19.5.19DMA2D output memory address register (DMA2D_OMAR) . . . . .783
19.5.20DMA2D output offset register (DMA2D_OOR) . . . . .783
19.5.21DMA2D number of line register (DMA2D_NLR) . . . . .784
19.5.22DMA2D line watermark register (DMA2D_LWR) . . . . .784
19.5.23DMA2D AXI master timer configuration register (DMA2D_AMTCR) . . . . .785
19.5.24DMA2D foreground CLUT (DMA2D_FGCLUTx) . . . . .785
19.5.25DMA2D background CLUT (DMA2D_BGCLUTx) . . . . .786
19.5.26DMA2D register map . . . . .786
20Nested vectored interrupt controllers (NVIC1 and NVIC2) . . . . .788
20.1NVIC features . . . . .788
20.1.1SysTick calibration value register . . . . .788
20.1.2Interrupt and exception vectors . . . . .788
21Extended interrupt and event controller (EXTI) . . . . .797
21.1EXTI main features . . . . .797
21.2EXTI block diagram . . . . .797
21.2.1EXTI connections between peripherals, CPU, and D3 domain . . . . .798
21.3EXTI functional description . . . . .799
21.3.1EXTI Configurable event input CPU wakeup . . . . .800
21.3.2EXTI configurable event input Any wakeup . . . . .801
21.3.3EXTI direct event input CPU wakeup . . . . .802
21.3.4EXTI direct event input Any wakeup . . . . .804
21.3.5EXTI D3 pending request clear selection . . . . .805
21.4EXTI event input mapping . . . . .805
21.5EXTI functional behavior . . . . .808
21.5.1EXTI CPU interrupt procedure . . . . .809
21.5.2EXTI CPU event procedure . . . . .810
21.5.3EXTI CPU wakeup procedure . . . . .810
21.5.4EXTI D3 domain wakeup for autonomous Run mode procedure . . . . .810
21.5.5EXTI software interrupt/event trigger procedure . . . . .811
21.6EXTI registers . . . . .812
21.6.1EXTI rising trigger selection register (EXTI_RTSR1) . . . . .812
21.6.2EXTI falling trigger selection register (EXTI_FTSR1) . . . . .812
21.6.3EXTI software interrupt event register (EXTI_SWIER1) . . . . .813
21.6.4EXTI D3 pending mask register (EXTI_D3PMR1) . . . . .813
21.6.5EXTI D3 pending clear selection register low (EXTI_D3PCR1L) . . . . .814
21.6.6EXTI D3 pending clear selection register high (EXTI_D3PCR1H) . . . . .814
21.6.7EXTI rising trigger selection register (EXTI_RTSR2) . . . . .815
21.6.8EXTI falling trigger selection register (EXTI_FTSR2) . . . . .816
21.6.9EXTI software interrupt event register (EXTI_SWIER2) . . . . .816
21.6.10EXTI D3 pending mask register (EXTI_D3PMR2) . . . . .817
21.6.11EXTI D3 pending clear selection register low (EXTI_D3PCR2L) . . . . .818
21.6.12EXTI D3 pending clear selection register high (EXTI_D3PCR2H) . . . . .818
21.6.13EXTI rising trigger selection register (EXTI_RTSR3) . . . . .819
21.6.14EXTI falling trigger selection register (EXTI_FTSR3) . . . . .819
21.6.15EXTI software interrupt event register (EXTI_SWIER3) . . . . .820
21.6.16EXTI D3 pending mask register (EXTI_D3PMR3) . . . . .820
21.6.17EXTI D3 pending clear selection register low (EXTI_D3PCR3L) . . . . .821
21.6.18EXTI D3 pending clear selection register high (EXTI_D3PCR3H) . . . . .821
21.6.19EXTI interrupt mask register (EXTI_CnIMR1) . . . . .822
21.6.20EXTI event mask register (EXTI_CnEMR1) . . . . .822
21.6.21EXTI pending register (EXTI_CnPR1) . . . . .823
21.6.22EXTI interrupt mask register (EXTI_CnIMR2) . . . . .823
21.6.23EXTI event mask register (EXTI_CnEMR2) . . . . .824
21.6.24EXTI pending register (EXTI_CnPR2) . . . . .824
21.6.25EXTI interrupt mask register (EXTI_CnIMR3) . . . . .825
21.6.26EXTI event mask register (EXTI_CnEMR3) . . . . .826
21.6.27EXTI pending register (EXTI_CnPR3) . . . . .826
21.6.28EXTI register map . . . . .827
22Cyclic redundancy check calculation unit (CRC) . . . . .830
22.1Introduction . . . . .830
22.2CRC main features . . . . .830
22.3CRC functional description . . . . .831
22.3.1CRC block diagram . . . . .831
22.3.2CRC internal signals . . . . .831
22.3.3CRC operation . . . . .831
22.4CRC registers . . . . .833
22.4.1CRC data register (CRC_DR) . . . . .833
22.4.2CRC independent data register (CRC_IDR) . . . . .833
22.4.3CRC control register (CRC_CR) . . . . .834
22.4.4CRC initial value (CRC_INIT) . . . . .835
22.4.5CRC polynomial (CRC_POL) . . . . .835
22.4.6CRC register map . . . . .836
23Flexible memory controller (FMC) . . . . .837
23.1FMC main features . . . . .837
23.2FMC block diagram . . . . .838
23.3FMC internal signals . . . . .840
23.4AHB interface . . . . .840
23.5AXI interface . . . . .840
23.5.1Supported memories and transactions . . . . .841
23.6External device address mapping . . . . .842
23.6.1NOR/PSRAM address mapping . . . . .843
23.6.2NAND flash memory address mapping . . . . .844
23.6.3SDRAM address mapping . . . . .844
23.7NOR flash/PSRAM controller . . . . .848
24.3.11QUADSPI configuration . . . . .929
24.3.12QUADSPI use . . . . .929
24.3.13Sending the instruction only once . . . . .931
24.3.14QUADSPI error management . . . . .932
24.3.15QUADSPI busy bit and abort functionality . . . . .932
24.3.16NCS behavior . . . . .932
24.4QUADSPI interrupts . . . . .934
24.5QUADSPI registers . . . . .935
24.5.1QUADSPI control register (QUADSPI_CR) . . . . .935
24.5.2QUADSPI device configuration register (QUADSPI_DCR) . . . . .937
24.5.3QUADSPI status register (QUADSPI_SR) . . . . .938
24.5.4QUADSPI flag clear register (QUADSPI_FCR) . . . . .939
24.5.5QUADSPI data length register (QUADSPI_DLR) . . . . .940
24.5.6QUADSPI communication configuration register (QUADSPI_CCR) . . . . .940
24.5.7QUADSPI address register (QUADSPI_AR) . . . . .942
24.5.8QUADSPI alternate-byte register (QUADSPI_ABR) . . . . .943
24.5.9QUADSPI data register (QUADSPI_DR) . . . . .943
24.5.10QUADSPI polling status mask register (QUADSPI_PSMKR) . . . . .944
24.5.11QUADSPI polling status match register (QUADSPI_PSMAR) . . . . .944
24.5.12QUADSPI polling interval register (QUADSPI_PIR) . . . . .945
24.5.13QUADSPI low-power timeout register (QUADSPI_LPTR) . . . . .945
24.5.14QUADSPI register map . . . . .946
25Delay block (DLYB) . . . . .947
25.1Introduction . . . . .947
25.2DLYB main features . . . . .947
25.3DLYB functional description . . . . .947
25.3.1DLYB diagram . . . . .947
25.3.2DLYB pins and internal signals . . . . .948
25.3.3General description . . . . .948
25.3.4Delay line length configuration procedure . . . . .949
25.3.5Output clock phase configuration procedure . . . . .949
25.4DLYB registers . . . . .950
25.4.1DLYB control register (DLYB_CR) . . . . .950
25.4.2DLYB configuration register (DLYB_CFGR) . . . . .950
25.4.3DLYB register map . . . . .951
26Analog-to-digital converters (ADC) . . . . .952
26.1Introduction . . . . .952
26.2ADC main features . . . . .953
26.3ADC implementation . . . . .954
26.4ADC functional description . . . . .955
26.4.1ADC block diagram . . . . .955
26.4.2ADC pins and internal signals . . . . .956
26.4.3ADC clocks . . . . .957
26.4.4ADC1/2/3 connectivity . . . . .959
26.4.5Slave AHB interface . . . . .962
26.4.6ADC deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) . . . . .962
26.4.7Single-ended and differential input channels . . . . .963
26.4.8Calibration (ADCAL, ADCALDIF, ADCALLIN, ADC_CALFACT) . . . . .963
26.4.9ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .969
26.4.10Constraints when writing the ADC control bits . . . . .970
26.4.11Channel selection (SQRx, JSQRx) . . . . .970
26.4.12Channel preselection register (ADC_PCSEL) . . . . .971
26.4.13Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . .972
26.4.14Single conversion mode (CONT=0) . . . . .973
26.4.15Continuous conversion mode (CONT=1) . . . . .973
26.4.16Starting conversions (ADSTART, JADSTART) . . . . .974
26.4.17Timing . . . . .975
26.4.18Stopping an ongoing conversion (ADSTP, JADSTP) . . . . .975
26.4.19Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . .977
26.4.20Injected channel management . . . . .980
26.4.21Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . .982
26.4.22Queue of context for injected conversions . . . . .983
26.4.23Programmable resolution (RES) - fast conversion mode . . . . .991
26.4.24End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . . . .991
26.4.25End of conversion sequence (EOS, JEOS) . . . . .991
26.4.26Timing diagrams example (single/continuous modes, hardware/software triggers) . . . . .992
26.4.27Data management . . . . .993
26.4.28Managing conversions using the DFSDM . . . . .1001
26.4.29Dynamic low-power features . . . . .1001
26.4.30Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy)1006
26.4.31Oversampler1009
26.4.32Dual ADC modes1015
26.4.33Temperature sensor1029
26.4.34VBAT supply monitoring1030
26.4.35Monitoring the internal voltage reference1031
26.5ADC interrupts1033
26.6ADC registers (for each ADC)1034
26.6.1ADC interrupt and status register (ADC_ISR)1034
26.6.2ADC interrupt enable register (ADC_IER)1037
26.6.3ADC control register (ADC_CR)1039
26.6.4ADC configuration register (ADC_CFGR)1044
26.6.5ADC configuration register 2 (ADC_CFGR2)1048
26.6.6ADC sample time register 1 (ADC_SMPR1)1050
26.6.7ADC sample time register 2 (ADC_SMPR2)1051
26.6.8ADC channel preselection register (ADC_PCSEL)1052
26.6.9ADC watchdog threshold register 1 (ADC_LTR1)1052
26.6.10ADC watchdog threshold register 1 (ADC_HTR1)1053
26.6.11ADC regular sequence register 1 (ADC_SQR1)1054
26.6.12ADC regular sequence register 2 (ADC_SQR2)1055
26.6.13ADC regular sequence register 3 (ADC_SQR3)1056
26.6.14ADC regular sequence register 4 (ADC_SQR4)1057
26.6.15ADC regular Data Register (ADC_DR)1058
26.6.16ADC injected sequence register (ADC_JSQR)1059
26.6.17ADC injected channel y offset register (ADC_OFRy)1061
26.6.18ADC injected channel y data register (ADC_JDRy)1062
26.6.19ADC analog watchdog 2 configuration register (ADC_AWD2CR)1062
26.6.20ADC analog watchdog 3 configuration register (ADC_AWD3CR)1063
26.6.21ADC watchdog lower threshold register 2 (ADC_LTR2)1063
26.6.22ADC watchdog higher threshold register 2 (ADC_HTR2)1064
26.6.23ADC watchdog lower threshold register 3 (ADC_LTR3)1064
26.6.24ADC watchdog higher threshold register 3 (ADC_HTR3)1065
26.6.25ADC differential mode selection register (ADC_DIFSEL)1065
26.6.26ADC calibration factors register (ADC_CALFACT)1066
26.6.27ADC calibration factor register 2 (ADC_CALFACT2)1066
26.7ADC common registers . . . . .1067
26.7.1ADC x common status register (ADCx_CSR) (x=1/2 or 3) . . . . .1067
26.7.2ADC x common control register (ADCx_CCR) (x=1/2 or 3) . . . . .1069
26.7.3ADC x common regular data register for dual mode
(ADCx_CDR) (x=1/2 or 3) . . . . .		1072
26.7.4ADC x common regular data register for 32-bit dual mode
(ADCx_CDR2) (x=1/2 or 3) . . . . .		1072
26.8ADC register map . . . . .1073
27Digital-to-analog converter (DAC) . . . . .1077
27.1Introduction . . . . .1077
27.2DAC main features . . . . .1077
27.3DAC implementation . . . . .1078
27.4DAC functional description . . . . .1079
27.4.1DAC block diagram . . . . .1079
27.4.2DAC pins and internal signals . . . . .1080
27.4.3DAC channel enable . . . . .1081
27.4.4DAC data format . . . . .1081
27.4.5DAC conversion . . . . .1083
27.4.6DAC output voltage . . . . .1083
27.4.7DAC trigger selection . . . . .1083
27.4.8DMA requests . . . . .1084
27.4.9Noise generation . . . . .1084
27.4.10Triangle-wave generation . . . . .1086
27.4.11DAC channel modes . . . . .1087
27.4.12DAC channel buffer calibration . . . . .1090
27.4.13Dual DAC channel conversion modes (if dual channels are
available) . . . . .		1091
27.5DAC in low-power modes . . . . .1095
27.6DAC interrupts . . . . .1096
27.7DAC registers . . . . .1097
27.7.1DAC control register (DAC_CR) . . . . .1097
27.7.2DAC software trigger register (DAC_SWTRGR) . . . . .1100
27.7.3DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . .		1101
27.7.4DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . .		1101
27.7.5DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . .1102
27.7.6DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . .1102
27.7.7DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . .1103
27.7.8DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . .1103
27.7.9Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . .1104
27.7.10Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . .1104
27.7.11Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . .1105
27.7.12DAC channel1 data output register (DAC_DOR1) . . . . .1105
27.7.13DAC channel2 data output register (DAC_DOR2) . . . . .1106
27.7.14DAC status register (DAC_SR) . . . . .1106
27.7.15DAC calibration control register (DAC_CCR) . . . . .1108
27.7.16DAC mode control register (DAC_MCR) . . . . .1108
27.7.17DAC channel1 sample and hold sample time register (DAC_SHSR1) . . . . .1110
27.7.18DAC channel2 sample and hold sample time register (DAC_SHSR2) . . . . .1110
27.7.19DAC sample and hold time register (DAC_SHHR) . . . . .1111
27.7.20DAC sample and hold refresh time register (DAC_SHRR) . . . . .1111
27.7.21DAC register map . . . . .1112
28Voltage reference buffer (VREFBUF) . . . . .1114
28.1Introduction . . . . .1114
28.2VREFBUF functional description . . . . .1114
28.3VREFBUF registers . . . . .1115
28.3.1VREFBUF control and status register (VREFBUF_CSR) . . . . .1115
28.3.2VREFBUF calibration control register (VREFBUF_CCR) . . . . .1116
28.3.3VREFBUF register map . . . . .1116
29Comparator (COMP) . . . . .1117
29.1Introduction . . . . .1117
29.2COMP main features . . . . .1117
29.3COMP functional description . . . . .1118
29.3.1COMP block diagram . . . . .1118
29.3.2COMP pins and internal signals . . . . .1118
29.3.3COMP reset and clocks . . . . .1120
29.3.4Comparator LOCK mechanism . . . . .1120
29.3.5Window comparator . . . . .1120
29.3.6Hysteresis . . . . .1120
29.3.7Comparator output blanking function . . . . .1121
29.3.8Comparator output on GPIOs . . . . .1122
29.3.9Comparator output redirection . . . . .1123
29.3.10COMP power and speed modes . . . . .1123
29.4COMP low-power modes . . . . .1124
29.5COMP interrupts . . . . .1124
29.5.1Interrupt through EXTI block . . . . .1124
29.5.2Interrupt through NVIC of the CPU . . . . .1125
29.6SCALER function . . . . .1125
29.7COMP registers . . . . .1126
29.7.1Comparator status register (COMP_SR) . . . . .1126
29.7.2Comparator interrupt clear flag register (COMP_ICFR) . . . . .1126
29.7.3Comparator option register (COMP_OR) . . . . .1127
29.7.4Comparator configuration register 1 (COMP_CFGR1) . . . . .1127
29.7.5Comparator configuration register 2 (COMP_CFGR2) . . . . .1129
29.7.6COMP register map . . . . .1132
30Operational amplifiers (OPAMP) . . . . .1133
30.1Introduction . . . . .1133
30.2OPAMP main features . . . . .1133
30.3OPAMP functional description . . . . .1133
30.3.1OPAMP reset and clocks . . . . .1133
30.3.2Initial configuration . . . . .1134
30.3.3Signal routing . . . . .1134
30.3.4OPAMP modes . . . . .1135
30.3.5Calibration . . . . .1141
30.4OPAMP low-power modes . . . . .1143
30.5OPAMP PGA gain . . . . .1143
30.6OPAMP registers . . . . .1143
30.6.1OPAMP1 control/status register (OPAMP1_CSR) . . . . .1143
30.6.2OPAMP1 trimming register in normal mode (OPAMP1_OTR) . . . . .1145
30.6.3OPAMP1 trimming register in high-speed mode (OPAMP1_HSOTR)1146
30.6.4OPAMP option register (OPAMP_OR) . . . . .1146
30.6.5OPAMP2 control/status register (OPAMP2_CSR) . . . . .1146
30.6.6OPAMP2 trimming register in normal mode (OPAMP2_OTR) . . . . .1148
30.6.7OPAMP2 trimming register in high-speed mode (OPAMP2_HSOTR)1149
30.6.8OPAMP register map . . . . .1150
31Digital filter for sigma delta modulators (DFSDM) . . . . .1151
31.1Introduction . . . . .1151
31.2DFSDM main features . . . . .1152
31.3DFSDM implementation . . . . .1153
31.4DFSDM functional description . . . . .1154
31.4.1DFSDM block diagram . . . . .1154
31.4.2DFSDM pins and internal signals . . . . .1155
31.4.3DFSDM reset and clocks . . . . .1156
31.4.4Serial channel transceivers . . . . .1157
31.4.5Configuring the input serial interface . . . . .1167
31.4.6Parallel data inputs . . . . .1167
31.4.7Channel selection . . . . .1169
31.4.8Digital filter configuration . . . . .1170
31.4.9Integrator unit . . . . .1171
31.4.10Analog watchdog . . . . .1172
31.4.11Short-circuit detector . . . . .1174
31.4.12Extreme detector . . . . .1175
31.4.13Data unit block . . . . .1175
31.4.14Signed data format . . . . .1176
31.4.15Launching conversions . . . . .1177
31.4.16Continuous and fast continuous modes . . . . .1177
31.4.17Request precedence . . . . .1178
31.4.18Power optimization in run mode . . . . .1179
31.5DFSDM interrupts . . . . .1179
31.6DFSDM DMA transfer . . . . .1181
31.7DFSDM channel y registers (y=0..7) . . . . .1181
31.7.1DFSDM channel y configuration register (DFSDM_CHyCFGR1) . . .1181
31.7.2DFSDM channel y configuration register (DFSDM_CHyCFGR2) . . .1183

32 Digital camera interface (DCMI) . . . . . 1210

32.3.5DCMI physical interface . . . . .1212
32.3.6DCMI synchronization . . . . .1214
32.3.7DCMI capture modes . . . . .1216
32.3.8DCMI crop feature . . . . .1217
32.3.9DCMI JPEG format . . . . .1218
32.3.10DCMI FIFO . . . . .1218
32.3.11DCMI data format description . . . . .1219
32.4DCMI interrupts . . . . .1221
32.5DCMI registers . . . . .1222
32.5.1DCMI control register (DCMI_CR) . . . . .1222
32.5.2DCMI status register (DCMI_SR) . . . . .1224
32.5.3DCMI raw interrupt status register (DCMI_RIS) . . . . .1225
32.5.4DCMI interrupt enable register (DCMI_IER) . . . . .1226
32.5.5DCMI masked interrupt status register (DCMI_MIS) . . . . .1227
32.5.6DCMI interrupt clear register (DCMI_ICR) . . . . .1228
32.5.7DCMI embedded synchronization code register (DCMI_ESCR) . . . . .1228
32.5.8DCMI embedded synchronization unmask register (DCMI_ESUR) . . . . .1229
32.5.9DCMI crop window start (DCMI_CWSTRT) . . . . .1230
32.5.10DCMI crop window size (DCMI_CWSIZE) . . . . .1230
32.5.11DCMI data register (DCMI_DR) . . . . .1231
32.5.12DCMI register map . . . . .1231
33LCD-TFT display controller (LTDC) . . . . .1233
33.1Introduction . . . . .1233
33.2LTDC main features . . . . .1233
33.3LTDC functional description . . . . .1234
33.3.1LTDC block diagram . . . . .1234
33.3.2LTDC pins and internal signals . . . . .1234
33.3.3LTDC reset and clocks . . . . .1235
33.4LTDC programmable parameters . . . . .1237
33.4.1LTDC global configuration parameters . . . . .1237
33.4.2Layer programmable parameters . . . . .1239
33.5LTDC interrupts . . . . .1243
33.6LTDC programming procedure . . . . .1244
33.7LTDC registers . . . . .1245
33.7.1LTDC synchronization size configuration register (LTDC_SSCR) . . . . .1245

33.7.2 LTDC back porch configuration register (LTDC_BPCR) . . . . . 1245

33.7.3 LTDC active width configuration register (LTDC_AWCR) . . . . . 1246

33.7.4 LTDC total width configuration register (LTDC_TWCR) . . . . . 1247

33.7.5 LTDC global control register (LTDC_GCR) . . . . . 1247

33.7.6 LTDC shadow reload configuration register (LTDC_SRCR) . . . . . 1249

33.7.7 LTDC background color configuration register (LTDC_BCCR) . . . . . 1249

33.7.8 LTDC interrupt enable register (LTDC_IER) . . . . . 1250

33.7.9 LTDC interrupt status register (LTDC_ISR) . . . . . 1251

33.7.10 LTDC interrupt clear register (LTDC_ICR) . . . . . 1251

33.7.11 LTDC line interrupt position configuration register (LTDC_LIPCR) . . . . . 1252

33.7.12 LTDC current position status register (LTDC_CPSR) . . . . . 1252

33.7.13 LTDC current display status register (LTDC_CDSR) . . . . . 1253

33.7.14 LTDC layer x control register (LTDC_LxCR) . . . . . 1253

33.7.15 LTDC layer x window horizontal position configuration register
(LTDC_LxWHPER) . . . . . 1254

33.7.16 LTDC layer x window vertical position configuration register
(LTDC_LxWVPER) . . . . . 1255

33.7.17 LTDC layer x color keying configuration register
(LTDC_LxCKCR) . . . . . 1256

33.7.18 LTDC layer x pixel format configuration register
(LTDC_LxPFCR) . . . . . 1256

33.7.19 LTDC layer x constant alpha configuration register
(LTDC_LxCACR) . . . . . 1257

33.7.20 LTDC layer x default color configuration register
(LTDC_LxDCCR) . . . . . 1257

33.7.21 LTDC layer x blending factors configuration register
(LTDC_LxBFCR) . . . . . 1258

33.7.22 LTDC layer x color frame buffer address register
(LTDC_LxCFBAR) . . . . . 1259

33.7.23 LTDC layer x color frame buffer length register
(LTDC_LxCFBLR) . . . . . 1259

33.7.24 LTDC layer x color frame buffer line number register
(LTDC_LxCFBLNR) . . . . . 1260

33.7.25 LTDC layer x CLUT write register (LTDC_LxCLUTWR) . . . . . 1260

33.7.26 LTDC register map . . . . . 1261

34 DSI Host (DSI) . . . . . 1264

34.1 Introduction . . . . . 1264

34.2 Standard and references . . . . . 1264

34.3 DSI Host main features . . . . . 1265

34.4DSI Host functional description . . . . .1266
34.4.1General description . . . . .1266
34.4.2DSI Host pins and internal signals . . . . .1266
34.4.3Supported resolutions and frame rates . . . . .1267
34.4.4System level architecture . . . . .1267
34.5Functional description: video mode on LTDC interface . . . . .1270
34.5.1Video transmission mode . . . . .1271
34.5.2Updating the LTDC interface configuration in video mode . . . . .1273
34.6Functional description: adapted command mode on LTDC interface . . . . .1275
34.7Functional description: APB slave generic interface . . . . .1279
34.7.1Packet transmission using the generic interface . . . . .1279
34.8Functional description: timeout counters . . . . .1283
34.8.1Contention error detection timeout counters . . . . .1283
34.8.2Peripheral response timeout counters . . . . .1284
34.9Functional description: transmission of commands . . . . .1289
34.9.1Transmission of commands in video mode . . . . .1289
34.9.2Transmission of commands in low-power mode . . . . .1291
34.9.3Transmission of commands in high-speed . . . . .1295
34.9.4Read command transmission . . . . .1295
34.9.5Clock lane in low-power mode . . . . .1296
34.10Functional description: virtual channels . . . . .1298
34.11Functional description: video mode pattern generator . . . . .1299
34.11.1Color bar pattern . . . . .1299
34.11.2Color coding . . . . .1301
34.11.3BER testing pattern . . . . .1301
34.11.4Video mode pattern generator resolution . . . . .1302
34.12Functional description: D-PHY management . . . . .1303
34.12.1D-PHY configuration . . . . .1303
34.12.2D-PHY HS2LP and LP2HS durations . . . . .1305
34.12.3Special D-PHY operations . . . . .1305
34.12.4Special low-power D-PHY functions . . . . .1305
34.12.5DSI PLL control . . . . .1306
34.12.6Regulator control . . . . .1307
34.13Functional description: interrupts and errors . . . . .1307
34.13.1DSI Wrapper interrupts . . . . .1307
34.13.2DSI Host interrupts and errors . . . . .1308
34.14Programing procedure . . . . .1315
34.14.1Programing procedure overview . . . . .1315
34.14.2Configuring the D-PHY parameters . . . . .1315
34.14.3Configuring the DSI Host timing . . . . .1316
34.14.4Configuring flow control and DBI interface . . . . .1317
34.14.5Configuring the DSI Host LTDC interface . . . . .1317
34.14.6Configuring the video mode . . . . .1318
34.14.7Configuring the adapted command mode . . . . .1322
34.14.8Configuring the video mode pattern generator . . . . .1322
34.14.9Managing ULPM . . . . .1323
34.15DSI Host registers . . . . .1326
34.15.1DSI Host version register (DSI_VR) . . . . .1326
34.15.2DSI Host control register (DSI_CR) . . . . .1326
34.15.3DSI Host clock control register (DSI_CCR) . . . . .1326
34.15.4DSI Host LTDC VCID register (DSI_LVCIDR) . . . . .1327
34.15.5DSI Host LTDC color coding register (DSI_LCOLCR) . . . . .1327
34.15.6DSI Host LTDC polarity configuration register (DSI_LPCR) . . . . .1328
34.15.7DSI Host low-power mode configuration register (DSI_LPPCR) . . . . .1328
34.15.8DSI Host protocol configuration register (DSI_PCR) . . . . .1329
34.15.9DSI Host generic VCID register (DSI_GVCIDR) . . . . .1330
34.15.10DSI Host mode configuration register (DSI_MCR) . . . . .1330
34.15.11DSI Host video mode configuration register (DSI_VMCR) . . . . .1330
34.15.12DSI Host video packet configuration register (DSI_VPCR) . . . . .1332
34.15.13DSI Host video chunks configuration register (DSI_VCCR) . . . . .1332
34.15.14DSI Host video null packet configuration register (DSI_VNPCR) . . . . .1333
34.15.15DSI Host video HSA configuration register (DSI_VHSACR) . . . . .1333
34.15.16DSI Host video HBP configuration register (DSI_VHBPCR) . . . . .1334
34.15.17DSI Host video line configuration register (DSI_VLCR) . . . . .1334
34.15.18DSI Host video VSA configuration register (DSI_VVSACR) . . . . .1334
34.15.19DSI Host video VBP configuration register (DSI_VVBPCR) . . . . .1335
34.15.20DSI Host video VFP configuration register (DSI_VVFPPCR) . . . . .1335
34.15.21DSI Host video VA configuration register (DSI_VVACR) . . . . .1335
34.15.22DSI Host LTDC command configuration register (DSI_LCCR) . . . . .1336
34.15.23DSI Host command mode configuration register (DSI_CMCR) . . . . .1336
34.15.24DSI Host generic header configuration register (DSI_GHCR) . . . . .1338
34.15.25DSI Host generic payload data register (DSI_GPDR) . . . . .1339
34.15.26DSI Host generic packet status register (DSI_GPSR) . . . . .1339
34.15.27 DSI Host timeout counter configuration register 0 (DSI_TCCR0) . . .1340
34.15.28 DSI Host timeout counter configuration register 1 (DSI_TCCR1) . . .1341
34.15.29 DSI Host timeout counter configuration register 2 (DSI_TCCR2) . . .1341
34.15.30 DSI Host timeout counter configuration register 3 (DSI_TCCR3) . . .1341
34.15.31 DSI Host timeout counter configuration register 4 (DSI_TCCR4) . . .1342
34.15.32 DSI Host timeout counter configuration register 5 (DSI_TCCR5) . . .1342
34.15.33 DSI Host clock lane configuration register (DSI_CLCR) . . . . .1343
34.15.34 DSI Host clock lane timer configuration register (DSI_CLTCR) . . . . .1343
34.15.35 DSI Host data lane timer configuration register (DSI_DLTCR) . . . . .1344
34.15.36 DSI Host PHY control register (DSI_PCTLR) . . . . .1344
34.15.37 DSI Host PHY configuration register (DSI_PCONF) . . . . .1345
34.15.38 DSI Host PHY ULPS control register (DSI_PUCR) . . . . .1345
34.15.39 DSI Host PHY TX triggers configuration register (DSI_PTT) . . . . .1346
34.15.40 DSI Host PHY status register (DSI_PSR) . . . . .1346
34.15.41 DSI Host interrupt and status register 0 (DSI_ISR0) . . . . .1347
34.15.42 DSI Host interrupt and status register 1 (DSI_ISR1) . . . . .1349
34.15.43 DSI Host interrupt enable register 0 (DSI_IER0) . . . . .1350
34.15.44 DSI Host interrupt enable register 1 (DSI_IER1) . . . . .1352
34.15.45 DSI Host force interrupt register 0 (DSI_FIR0) . . . . .1354
34.15.46 DSI Host force interrupt register 1 (DSI_FIR1) . . . . .1355
34.15.47 DSI Host video shadow control register (DSI_VSCR) . . . . .1356
34.15.48 DSI Host LTDC current VCID register (DSI_LCVCIDR) . . . . .1357
34.15.49 DSI Host LTDC current color coding register (DSI_LCCCR) . . . . .1357
34.15.50 DSI Host low-power mode current configuration register
(DSI_LPMCCR) . . . . .		1358
34.15.51 DSI Host video mode current configuration register
(DSI_VMCCR) . . . . .		1358
34.15.52 DSI Host video packet current configuration register
(DSI_VPCCR) . . . . .		1359
34.15.53 DSI Host video chunks current configuration register
(DSI_VCCCR) . . . . .		1360
34.15.54 DSI Host video null packet current configuration register
(DSI_VNPCCR) . . . . .		1360
34.15.55 DSI Host video HSA current configuration register
(DSI_VHSACCR) . . . . .		1361
34.15.56 DSI Host video HBP current configuration register
(DSI_VHBPCCR) . . . . .		1361
34.15.57 DSI Host video line current configuration register (DSI_VLCCR) . . .1361
34.15.58DSI Host video VSA current configuration register (DSI_VVSACCR) . . . . .1362
34.15.59DSI Host video VBP current configuration register (DSI_VBPCCR) . . . . .1362
34.15.60DSI Host video VFP current configuration register (DSI_VVFPCCR) . . . . .1363
34.15.61DSI Host video VA current configuration register (DSI_VVACCR) . . . . .1363
34.16DSI Wrapper registers . . . . .1364
34.16.1DSI Wrapper configuration register (DSI_WCFGR) . . . . .1364
34.16.2DSI Wrapper control register (DSI_WCR) . . . . .1365
34.16.3DSI Wrapper interrupt enable register (DSI_WIER) . . . . .1365
34.16.4DSI Wrapper interrupt and status register (DSI_WISR) . . . . .1366
34.16.5DSI Wrapper interrupt flag clear register (DSI_WIFCR) . . . . .1367
34.16.6DSI Wrapper PHY configuration register 0 (DSI_WPCR0) . . . . .1368
34.16.7DSI Wrapper PHY configuration register 1 (DSI_WPCR1) . . . . .1370
34.16.8DSI Wrapper PHY configuration register 2 (DSI_WPCR2) . . . . .1372
34.16.9DSI Wrapper PHY configuration register 3 (DSI_WPCR3) . . . . .1373
34.16.10DSI Wrapper PHY configuration register 4 (DSI_WPCR4) . . . . .1373
34.16.11DSI Wrapper regulator and PLL control register (DSI_WRPCR) . . . . .1374
34.16.12DSI register map . . . . .1375
35JPEG codec (JPEG) . . . . .1381
35.1Introduction . . . . .1381
35.2JPEG codec main features . . . . .1381
35.3JPEG codec block functional description . . . . .1382
35.3.1General description . . . . .1382
35.3.2JPEG internal signals . . . . .1382
35.3.3JPEG decoding procedure . . . . .1383
35.3.4JPEG encoding procedure . . . . .1384
35.4JPEG codec interrupts . . . . .1386
35.5JPEG codec registers . . . . .1387
35.5.1JPEG codec control register (JPEG_CONF0) . . . . .1387
35.5.2JPEG codec configuration register 1 (JPEG_CONF1) . . . . .1387
35.5.3JPEG codec configuration register 2 (JPEG_CONF2) . . . . .1388
35.5.4JPEG codec configuration register 3 (JPEG_CONF3) . . . . .1389
35.5.5JPEG codec configuration register x (JPEG_CONFx) . . . . .1389
35.5.6JPEG control register (JPEG_CR) . . . . .1390
35.5.7JPEG status register (JPEG_SR) . . . . .1391
35.5.8JPEG clear flag register (JPEG_CFR) . . . . .1392
35.5.9JPEG data input register (JPEG_DIR) . . . . .1393
35.5.10JPEG data output register (JPEG_DOR) . . . . .1393
35.5.11JPEG quantization memory x (JPEG_QMEMx_y) . . . . .1394
35.5.12JPEG Huffman min (JPEG_HUFFMINx_y) . . . . .1394
35.5.13JPEG Huffman min x (JPEG_HUFFMINx_y) . . . . .1395
35.5.14JPEG Huffman base (JPEG_HUFFBASEx) . . . . .1395
35.5.15JPEG Huffman symbol (JPEG_HUFFSYMBx) . . . . .1396
35.5.16JPEG DHT memory (JPEG_DHTMEMx) . . . . .1397
35.5.17JPEG Huffman encoder ACx (JPEG_HUFFENC_ACx_y) . . . . .1397
35.5.18JPEG Huffman encoder DCx (JPEG_HUFFENC_DCx_y) . . . . .1398
35.5.19JPEG codec register map . . . . .1399
36True random number generator (RNG) . . . . .1401
36.1Introduction . . . . .1401
36.2RNG main features . . . . .1401
36.3RNG functional description . . . . .1402
36.3.1RNG block diagram . . . . .1402
36.3.2RNG internal signals . . . . .1402
36.3.3Random number generation . . . . .1403
36.3.4RNG initialization . . . . .1405
36.3.5RNG operation . . . . .1406
36.3.6RNG clocking . . . . .1407
36.3.7Error management . . . . .1407
36.3.8RNG low-power use . . . . .1408
36.4RNG interrupts . . . . .1409
36.5RNG processing time . . . . .1409
36.6RNG entropy source validation . . . . .1409
36.6.1Introduction . . . . .1409
36.6.2Validation conditions . . . . .1409
36.6.3Data collection . . . . .1410
36.7RNG registers . . . . .1410
36.7.1RNG control register (RNG_CR) . . . . .1410
36.7.2RNG status register (RNG_SR) . . . . .1411
36.7.3RNG data register (RNG_DR) . . . . .1412
36.7.4RNG register map . . . . .1412
37Cryptographic processor (CRYP) . . . . .1413
37.1Introduction . . . . .1413
37.2CRYP main features . . . . .1413
37.3CRYP implementation . . . . .1414
37.4CRYP functional description . . . . .1415
37.4.1CRYP block diagram . . . . .1415
37.4.2CRYP internal signals . . . . .1416
37.4.3CRYP DES/TDES cryptographic core . . . . .1416
37.4.4CRYP AES cryptographic core . . . . .1417
37.4.5CRYP procedure to perform a cipher operation . . . . .1423
37.4.6CRYP busy state . . . . .1425
37.4.7Preparing the CRYP AES key for decryption . . . . .1426
37.4.8CRYP stealing and data padding . . . . .1426
37.4.9CRYP suspend/resume operations . . . . .1427
37.4.10CRYP DES/TDES basic chaining modes (ECB, CBC) . . . . .1428
37.4.11CRYP AES basic chaining modes (ECB, CBC) . . . . .1433
37.4.12CRYP AES counter mode (AES-CTR) . . . . .1438
37.4.13CRYP AES Galois/counter mode (GCM) . . . . .1442
37.4.14CRYP AES Galois message authentication code (GMAC) . . . . .1447
37.4.15CRYP AES Counter with CBC-MAC (CCM) . . . . .1448
37.4.16CRYP data registers and data swapping . . . . .1453
37.4.17CRYP key registers . . . . .1457
37.4.18CRYP initialization vector registers . . . . .1458
37.4.19CRYP DMA interface . . . . .1459
37.4.20CRYP error management . . . . .1461
37.5CRYP interrupts . . . . .1461
37.6CRYP processing time . . . . .1462
37.7CRYP registers . . . . .1463
37.7.1CRYP control register (CRYP_CR) . . . . .1463
37.7.2CRYP status register (CRYP_SR) . . . . .1465
37.7.3CRYP data input register (CRYP_DIN) . . . . .1466
37.7.4CRYP data output register (CRYP_DOUT) . . . . .1467
37.7.5CRYP DMA control register (CRYP_DMACR) . . . . .1468
37.7.6CRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . .1468
37.7.7CRYP raw interrupt status register (CRYP_RISR) . . . . .1469
37.7.8CRYP masked interrupt status register (CRYP_MISR) . . . . .1470
37.7.9CRYP key register 0L (CRYP_K0LR) . . . . .1470
37.7.10CRYP key register 0R (CRYP_K0RR) . . . . .1471
37.7.11CRYP key register 1L (CRYP_K1LR) . . . . .1471
37.7.12CRYP key register 1R (CRYP_K1RR) . . . . .1472
37.7.13CRYP key register 2L (CRYP_K2LR) . . . . .1472
37.7.14CRYP key register 2R (CRYP_K2RR) . . . . .1473
37.7.15CRYP key register 3L (CRYP_K3LR) . . . . .1473
37.7.16CRYP key register 3R (CRYP_K3RR) . . . . .1474
37.7.17CRYP initialization vector register 0L (CRYP_IV0LR) . . . . .1474
37.7.18CRYP initialization vector register 0R (CRYP_IV0RR) . . . . .1475
37.7.19CRYP initialization vector register 1L (CRYP_IV1LR) . . . . .1475
37.7.20CRYP initialization vector register 1R (CRYP_IV1RR) . . . . .1476
37.7.21CRYP context swap GCM-CCM registers (CRYP_CSGCMCCMxR) . . . . .1476
37.7.22CRYP context swap GCM registers (CRYP_CSGCMxR) . . . . .1477
37.7.23CRYP register map . . . . .1477
38Hash processor (HASH) . . . . .1480
38.1Introduction . . . . .1480
38.2HASH main features . . . . .1480
38.3HASH implementation . . . . .1481
38.4HASH functional description . . . . .1481
38.4.1HASH block diagram . . . . .1481
38.4.2HASH internal signals . . . . .1482
38.4.3About secure hash algorithms . . . . .1482
38.4.4Message data feeding . . . . .1482
38.4.5Message digest computing . . . . .1484
38.4.6Message padding . . . . .1485
38.4.7HMAC operation . . . . .1487
38.4.8HASH suspend/resume operations . . . . .1489
38.4.9HASH DMA interface . . . . .1491
38.4.10HASH error management . . . . .1491
38.5HASH interrupts . . . . .1491
38.6HASH processing time . . . . .1492
38.7HASH registers . . . . .1493
38.7.1HASH control register (HASH_CR) . . . . .1493
38.7.2HASH data input register (HASH_DIN) . . . . .1495
38.7.3HASH start register (HASH_STR) . . . . .1496
38.7.4HASH digest registers . . . . .1497
38.7.5HASH interrupt enable register (HASH_IMR) . . . . .1498
38.7.6HASH status register (HASH_SR) . . . . .1499
38.7.7HASH context swap registers . . . . .1499
38.7.8HASH register map . . . . .1500
39High-resolution timer (HRTIM) . . . . .1502
39.1Introduction . . . . .1502
39.2Main features . . . . .1503
39.3Functional description . . . . .1504
39.3.1General description . . . . .1504
39.3.2HRTIM pins and internal signals . . . . .1506
39.3.3Clocks . . . . .1507
39.3.4Timer A..E timing units . . . . .1510
39.3.5Master timer . . . . .1527
39.3.6Set/reset events priorities and narrow pulses management . . . . .1528
39.3.7External events global conditioning . . . . .1529
39.3.8External event filtering in timing units . . . . .1534
39.3.9Delayed Protection . . . . .1539
39.3.10Register preload and update management . . . . .1545
39.3.11Events propagation within or across multiple timers . . . . .1548
39.3.12Output management . . . . .1552
39.3.13Burst mode controller . . . . .1554
39.3.14Chopper . . . . .1563
39.3.15Fault protection . . . . .1564
39.3.16Auxiliary outputs . . . . .1567
39.3.17Synchronizing the HRTIM with other timers or HRTIM instances . . . . .1570
39.3.18ADC triggers . . . . .1573
39.3.19DAC triggers . . . . .1574
39.3.20HRTIM Interrupts . . . . .1576
39.3.21DMA . . . . .1578
39.3.22HRTIM initialization . . . . .1581
39.3.23Debug . . . . .1582
39.4Application use cases . . . . .1583
39.4.1Buck converter . . . . .1583
39.4.2Buck converter with synchronous rectification . . . . .1584
39.4.3Multiphase converters . . . . .1585
39.4.4Transition mode Power Factor Correction . . . . .1587
39.5HRTIM registers . . . . .1589
39.5.1HRTIM Master Timer Control Register (HRTIM_MCR) . . . . .1589
39.5.2HRTIM Master Timer Interrupt Status Register (HRTIM_MISR) . . . . .1592
39.5.3HRTIM Master Timer Interrupt Clear Register (HRTIM_MICR) . . . . .1593
39.5.4HRTIM Master Timer DMA / Interrupt Enable Register
(HRTIM_MDIER) . . . . .		1594
39.5.5HRTIM Master Timer Counter Register (HRTIM_MCNTR) . . . . .1596
39.5.6HRTIM Master Timer Period Register (HRTIM_MPER) . . . . .1596
39.5.7HRTIM Master Timer Repetition Register (HRTIM_MREP) . . . . .1597
39.5.8HRTIM Master Timer Compare 1 Register (HRTIM_MCMP1R) . . . . .1597
39.5.9HRTIM Master Timer Compare 2 Register (HRTIM_MCMP2R) . . . . .1598
39.5.10HRTIM Master Timer Compare 3 Register (HRTIM_MCMP3R) . . . . .1598
39.5.11HRTIM Master Timer Compare 4 Register (HRTIM_MCMP4R) . . . . .1599
39.5.12HRTIM Timerx Control Register (HRTIM_TIMxCR) . . . . .1600
39.5.13HRTIM Timerx Interrupt Status Register (HRTIM_TIMxISR) . . . . .1604
39.5.14HRTIM Timerx Interrupt Clear Register (HRTIM_TIMxICR) . . . . .1606
39.5.15HRTIM Timerx DMA / Interrupt Enable Register
(HRTIM_TIMxDIER) . . . . .		1607
39.5.16HRTIM Timerx Counter Register (HRTIM_CNTxR) . . . . .1610
39.5.17HRTIM Timerx Period Register (HRTIM_PERxR) . . . . .1610
39.5.18HRTIM Timerx Repetition Register (HRTIM_REPxR) . . . . .1611
39.5.19HRTIM Timerx Compare 1 Register (HRTIM_CMP1xR) . . . . .1611
39.5.20HRTIM Timerx Compare 1 Compound Register
(HRTIM_CMP1CxR) . . . . .		1612
39.5.21HRTIM Timerx Compare 2 Register (HRTIM_CMP2xR) . . . . .1612
39.5.22HRTIM Timerx Compare 3 Register (HRTIM_CMP3xR) . . . . .1613
39.5.23HRTIM Timerx Compare 4 Register (HRTIM_CMP4xR) . . . . .1613
39.5.24HRTIM Timerx Capture 1 Register (HRTIM_CPT1xR) . . . . .1614
39.5.25HRTIM Timerx Capture 2 Register (HRTIM_CPT2xR) . . . . .1614
39.5.26HRTIM Timerx Deadtime Register (HRTIM_DTxR) . . . . .1615
39.5.27HRTIM Timerx Output1 Set Register (HRTIM_SETx1R) . . . . .1617
39.5.28HRTIM Timerx Output1 Reset Register (HRTIM_RSTx1R) . . . . .1619
39.5.29HRTIM Timerx Output2 Set Register (HRTIM_SETx2R) . . . . .1619
39.5.30HRTIM Timerx Output2 Reset Register (HRTIM_RSTx2R) . . . . .1620
39.5.31HRTIM Timerx External Event Filtering Register 1 (HRTIM_EEFxR1) . . . . .1621
39.5.32HRTIM Timerx External Event Filtering Register 2 (HRTIM_EEFxR2) . . . . .1623
39.5.33HRTIM Timerx Reset Register (HRTIM_RSTxR) . . . . .1624
39.5.34HRTIM Timerx Chopper Register (HRTIM_CHPxR) . . . . .1627
39.5.35HRTIM Timerx Capture 1 Control Register (HRTIM_CPT1xCR) . . . . .1629
39.5.36HRTIM Timerx Capture 2 Control Register (HRTIM_CPT2xCR) . . . . .1630
39.5.37HRTIM Timerx Output Register (HRTIM_OUTxR) . . . . .1633
39.5.38HRTIM Timerx Fault Register (HRTIM_FLTxR) . . . . .1636
39.5.39HRTIM Control Register 1 (HRTIM_CR1) . . . . .1637
39.5.40HRTIM Control Register 2 (HRTIM_CR2) . . . . .1639
39.5.41HRTIM Interrupt Status Register (HRTIM_ISR) . . . . .1640
39.5.42HRTIM Interrupt Clear Register (HRTIM_ICR) . . . . .1641
39.5.43HRTIM Interrupt Enable Register (HRTIM_IER) . . . . .1642
39.5.44HRTIM Output Enable Register (HRTIM_OENR) . . . . .1643
39.5.45HRTIM Output Disable Register (HRTIM_ODISR) . . . . .1644
39.5.46HRTIM Output Disable Status Register (HRTIM_ODSR) . . . . .1645
39.5.47HRTIM Burst Mode Control Register (HRTIM_BMCR) . . . . .1646
39.5.48HRTIM Burst Mode Trigger Register (HRTIM_BMTRGR) . . . . .1648
39.5.49HRTIM Burst Mode Compare Register (HRTIM_BMCMPR) . . . . .1650
39.5.50HRTIM Burst Mode Period Register (HRTIM_BMPER) . . . . .1650
39.5.51HRTIM Timer External Event Control Register 1 (HRTIM_EECR1) . . . . .1651
39.5.52HRTIM Timer External Event Control Register 2 (HRTIM_EECR2) . . . . .1653
39.5.53HRTIM Timer External Event Control Register 3 (HRTIM_EECR3) . . . . .1654
39.5.54HRTIM ADC Trigger 1 Register (HRTIM_ADC1R) . . . . .1655
39.5.55HRTIM ADC Trigger 2 Register (HRTIM_ADC2R) . . . . .1656
39.5.56HRTIM ADC Trigger 3 Register (HRTIM_ADC3R) . . . . .1657
39.5.57HRTIM ADC Trigger 4 Register (HRTIM_ADC4R) . . . . .1659
39.5.58HRTIM Fault Input Register 1 (HRTIM_FLTINR1) . . . . .1661
39.5.59HRTIM Fault Input Register 2 (HRTIM_FLTINR2) . . . . .1663
39.5.60HRTIM Burst DMA Master timer update Register (HRTIM_BDMUPR) . . . . .1665
39.5.61HRTIM Burst DMA Timerx update Register (HRTIM_BDTxUPR) . . . . .1666
39.5.62HRTIM Burst DMA Data Register (HRTIM_BDMADR) . . . . .1667
39.5.63HRTIM register map . . . . .1668
40Advanced-control timers (TIM1/TIM8) . . . . .1677
40.1TIM1/TIM8 introduction . . . . .1677
40.2TIM1/TIM8 main features . . . . .1677
40.3TIM1/TIM8 functional description . . . . .1679
40.3.1Time-base unit . . . . .1679
40.3.2Counter modes . . . . .1681
40.3.3Repetition counter . . . . .1692
40.3.4External trigger input . . . . .1694
40.3.5Clock selection . . . . .1695
40.3.6Capture/compare channels . . . . .1699
40.3.7Input capture mode . . . . .1701
40.3.8PWM input mode . . . . .1702
40.3.9Forced output mode . . . . .1703
40.3.10Output compare mode . . . . .1704
40.3.11PWM mode . . . . .1705
40.3.12Asymmetric PWM mode . . . . .1708
40.3.13Combined PWM mode . . . . .1709
40.3.14Combined 3-phase PWM mode . . . . .1710
40.3.15Complementary outputs and dead-time insertion . . . . .1711
40.3.16Using the break function . . . . .1713
40.3.17Bidirectional break inputs . . . . .1719
40.3.18Clearing the OCxREF signal on an external event . . . . .1719
40.3.196-step PWM generation . . . . .1721
40.3.20One-pulse mode . . . . .1722
40.3.21Retriggerable one pulse mode . . . . .1723
40.3.22Encoder interface mode . . . . .1724
40.3.23UIF bit remapping . . . . .1726
40.3.24Timer input XOR function . . . . .1727
40.3.25Interfacing with Hall sensors . . . . .1727
40.3.26Timer synchronization . . . . .1730
40.3.27ADC synchronization . . . . .1734
40.3.28DMA burst mode . . . . .1734
40.3.29Debug mode . . . . .1735
40.4TIM1/TIM8 registers . . . . .1736
40.4.1TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . .1736
40.4.2TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . .1737
40.4.3TIMx slave mode control register
(TIMx_SMCR)(x = 1, 8) . . . . .		1740
40.4.4TIMx DMA/interrupt enable register
(TIMx_DIER)(x = 1, 8) . . . . .		1742
40.4.5TIMx status register (TIMx_SR)(x = 1, 8) . . . . .1744
40.4.6TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . .1746
40.4.7TIMx capture/compare mode register 1(TIMx_CCMR1)(x = 1, 8) . . .1747
40.4.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . .		1748
40.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 1, 8) . .1751
40.4.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . .		1752
40.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 1, 8) . . . . .		1754
40.4.12TIMx counter (TIMx_CNT)(x = 1, 8) . . . . .1757
40.4.13TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . .1757
40.4.14TIMx auto-reload register (TIMx_ARR)(x = 1, 8) . . . . .1757
40.4.15TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . .1758
40.4.16TIMx capture/compare register 1
(TIMx_CCR1)(x = 1, 8) . . . . .		1758
40.4.17TIMx capture/compare register 2
(TIMx_CCR2)(x = 1, 8) . . . . .		1759
40.4.18TIMx capture/compare register 3
(TIMx_CCR3)(x = 1, 8) . . . . .		1759
40.4.19TIMx capture/compare register 4
(TIMx_CCR4)(x = 1, 8) . . . . .		1760
40.4.20TIMx break and dead-time register
(TIMx_BDTR)(x = 1, 8) . . . . .		1760
40.4.21TIMx DMA control register
(TIMx_DCR)(x = 1, 8) . . . . .		1763
40.4.22TIMx DMA address for full transfer
(TIMx_DMAR)(x = 1, 8) . . . . .		1764
40.4.23TIMx capture/compare mode register 3
(TIMx_CCMR3)(x = 1, 8) . . . . .		1765
40.4.24TIMx capture/compare register 5
(TIMx_CCR5)(x = 1, 8) . . . . .		1766
40.4.25TIMx capture/compare register 6
(TIMx_CCR6)(x = 1, 8) . . . . .		1767
40.4.26TIM1 alternate function option register 1 (TIM1_AF1) . . . . .1767
40.4.27TIM1 Alternate function register 2 (TIM1_AF2) . . . . .1769
40.4.28TIM8 Alternate function option register 1 (TIM8_AF1) . . . . .1770
40.4.29TIM8 Alternate function option register 2 (TIM8_AF2) . . . . .1772
40.4.30TIM1 timer input selection register (TIM1_TISEL) . . . . .1774
40.4.31TIM8 timer input selection register (TIM8_TISEL) . . . . .1774
40.4.32TIM1 register map . . . . .1776
40.4.33TIM8 register map . . . . .1778
41General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . .1781
41.1TIM2/TIM3/TIM4/TIM5 introduction . . . . .1781
41.2TIM2/TIM3/TIM4/TIM5 main features . . . . .1781
41.3TIM2/TIM3/TIM4/TIM5 functional description . . . . .1783
41.3.1Time-base unit . . . . .1783
41.3.2Counter modes . . . . .1785
41.3.3Clock selection . . . . .1795
41.3.4Capture/Compare channels . . . . .1799
41.3.5Input capture mode . . . . .1800
41.3.6PWM input mode . . . . .1801
41.3.7Forced output mode . . . . .1802
41.3.8Output compare mode . . . . .1803
41.3.9PWM mode . . . . .1804
41.3.10Asymmetric PWM mode . . . . .1807
41.3.11Combined PWM mode . . . . .1808
41.3.12Clearing the OCxREF signal on an external event . . . . .1809
41.3.13One-pulse mode . . . . .1811
41.3.14Retriggerable one pulse mode . . . . .1812
41.3.15Encoder interface mode . . . . .1813
41.3.16UIF bit remapping . . . . .1815
41.3.17Timer input XOR function . . . . .1815
41.3.18Timers and external trigger synchronization . . . . .1816
41.3.19Timer synchronization . . . . .1819
41.3.20DMA burst mode . . . . .1824
41.3.21Debug mode . . . . .1825
41.4TIM2/TIM3/TIM4/TIM5 registers . . . . .1826
41.4.1TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . .1826
41.4.2TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . .1827
41.4.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . .1829
41.4.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . .1832
41.4.5TIMx status register (TIMx_SR)(x = 2 to 5) . . . . .1833
41.4.6TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . .1834
41.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) . . . . .1836
41.4.8TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 5) . . . . .		1838
41.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5) . . . . .1840
41.4.10TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 5) . . . . .		1841
41.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 5) . . . . .		1842
41.4.12TIMx counter (TIMx_CNT)(x = 2 to 5) . . . . .1843
41.4.13TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) . . . . .1844
41.4.14TIMx prescaler (TIMx_PSC)(x = 2 to 5) . . . . .1844
41.4.15TIMx auto-reload register (TIMx_ARR)(x = 2 to 5) . . . . .1845
41.4.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) . . . . .1845
41.4.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) . . . . .1846
41.4.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5) . . . . .1846
41.4.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5) . . . . .1847
41.4.20TIMx DMA control register (TIMx_DCR)(x = 2 to 5) . . . . .1848
41.4.21TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) . . . . .1848
41.4.22TIM2 alternate function option register 1 (TIM2_AF1) . . . . .1849
41.4.23TIM3 alternate function option register 1 (TIM3_AF1) . . . . .1849
41.4.24TIM4 alternate function option register 1 (TIM4_AF1) . . . . .1850
41.4.25TIM5 alternate function option register 1 (TIM5_AF1) . . . . .1850
41.4.26TIM2 timer input selection register (TIM2_TISEL) . . . . .1851
41.4.27TIM3 timer input selection register (TIM3_TISEL) . . . . .1851
41.4.28TIM4 timer input selection register (TIM4_TISEL) . . . . .1852
41.4.29TIM5 timer input selection register (TIM5_TISEL) . . . . .1853
41.4.30TIMx register map . . . . .1855
42General-purpose timers (TIM12/TIM13/TIM14) . . . . .1858
42.1TIM12/TIM13/TIM14 introduction . . . . .1858
42.2TIM12/TIM13/TIM14 main features . . . . .1858
42.2.1TIM12 main features . . . . .1858
42.2.2TIM13/TIM14 main features . . . . .1859
42.3TIM12/TIM13/TIM14 functional description . . . . .1861
42.3.1Time-base unit . . . . .1861
42.3.2Counter modes . . . . .1863
42.3.3Clock selection . . . . .1866
42.3.4Capture/compare channels . . . . .1868
42.3.5Input capture mode . . . . .1870
42.3.6PWM input mode (only for TIM12) . . . . .1871
42.3.7Forced output mode . . . . .1872
42.3.8Output compare mode . . . . .1873
42.3.9PWM mode . . . . .1874
42.3.10Combined PWM mode (TIM12 only) . . . . .1875
42.3.11One-pulse mode . . . . .1876
42.3.12Retriggerable one pulse mode (TIM12 only) . . . . .1878
42.3.13UIF bit remapping . . . . .1878
42.3.14Timer input XOR function . . . . .1879
42.3.15TIM12 external trigger synchronization . . . . .1879
42.3.16Slave mode – combined reset + trigger mode . . . . .1882
42.3.17Timer synchronization (TIM12) . . . . .1883
42.3.18Using timer output as trigger for other timers (TIM13/TIM14) . . . . .1883
42.3.19Debug mode . . . . .1883
42.4TIM12 registers . . . . .1883
42.4.1TIM12 control register 1 (TIM12_CR1) . . . . .1883
42.4.2TIM12 control register 2 (TIM12_CR2) . . . . .1884
42.4.3TIM12 slave mode control register (TIM12_SMCR) . . . . .1885
42.4.4TIM12 Interrupt enable register (TIM12_DIER) . . . . .1887
42.4.5TIM12 status register (TIM12_SR) . . . . .1887
42.4.6TIM12 event generation register (TIM12_EGR) . . . . .1888
42.4.7TIM12 capture/compare mode register 1 (TIM12_CCMR1) . . . . .1889
42.4.8TIM12 capture/compare mode register 1 [alternate]
(TIM12_CCMR1) . . . . .		1890
42.4.9TIM12 capture/compare enable register (TIM12_CCER) . . . . .1893
42.4.10TIM12 counter (TIM12_CNT) . . . . .1894
42.4.11TIM12 prescaler (TIM12_PSC) . . . . .1895
42.4.12TIM12 auto-reload register (TIM12_ARR) . . . . .1895
42.4.13TIM12 capture/compare register 1 (TIM12_CCR1) . . . . .1895
42.4.14TIM12 capture/compare register 2 (TIM12_CCR2) . . . . .1896
42.4.15TIM12 timer input selection register (TIM12_TISEL) . . . . .1896
42.4.16TIM12 register map . . . . .1897
42.5TIM13/TIM14 registers . . . . .1899
42.5.1TIMx control register 1 (TIMx_CR1)(x = 13 to 14) . . . . .1899
42.5.2TIMx Interrupt enable register (TIMx_DIER)(x = 13 to 14) . . . . .1900
42.5.3TIMx status register (TIMx_SR)(x = 13 to 14) . . . . .1900
42.5.4TIMx event generation register (TIMx_EGR)(x = 13 to 14) . . . . .1901
42.5.5TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 13 to 14) . . . . .		1902
42.5.6TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 13 to 14) . . . . .		1903
42.5.7TIMx capture/compare enable register
(TIMx_CCER)(x = 13 to 14) . . . . .		1905
42.5.8TIMx counter (TIMx_CNT)(x = 13 to 14) . . . . .1906
42.5.9TIMx prescaler (TIMx_PSC)(x = 13 to 14) . . . . .1907
42.5.10TIMx auto-reload register (TIMx_ARR)(x = 13 to 14) . . . . .1907
42.5.11TIMx capture/compare register 1 (TIMx_CCR1)(x = 13 to 14) . . . . .1907
42.5.12TIM13 timer input selection register (TIM13_TISEL) . . . . .1908
42.5.13TIM14 timer input selection register (TIM14_TISEL) . . . . .1908
42.5.14TIM13/TIM14 register map . . . . .1909
43General-purpose timers (TIM15/TIM16/TIM17) . . . . .1911
43.1TIM15/TIM16/TIM17 introduction . . . . .1911
43.2TIM15 main features . . . . .1911
43.3TIM16/TIM17 main features . . . . .1912
43.4TIM15/TIM16/TIM17 functional description . . . . .1915
43.4.1Time-base unit . . . . .1915
43.4.2Counter modes . . . . .1917
43.4.3Repetition counter . . . . .1921
43.4.4Clock selection . . . . .1922
43.4.5Capture/compare channels . . . . .1924
43.4.6Input capture mode . . . . .1926
43.4.7PWM input mode (only for TIM15) . . . . .1927
43.4.8Forced output mode . . . . .1928
43.4.9Output compare mode . . . . .1929
43.4.10PWM mode . . . . .1930
43.4.11Combined PWM mode (TIM15 only) . . . . .1931
43.4.12Complementary outputs and dead-time insertion . . . . .1932
43.4.13Using the break function . . . . .1934
43.4.146-step PWM generation . . . . .1939
43.4.15One-pulse mode . . . . .1940
43.4.16Retriggerable one pulse mode (TIM15 only) . . . . .1941
43.4.17UIF bit remapping . . . . .1942
43.4.18Timer input XOR function (TIM15 only) . . . . .1943
43.4.19External trigger synchronization (TIM15 only) . . . . .1944
43.4.20Slave mode – combined reset + trigger mode . . . . .1946
43.4.21DMA burst mode . . . . .1946
43.4.22Timer synchronization (TIM15) . . . . .1948
43.4.23Using timer output as trigger for other timers (TIM16/TIM17) . . . . .1948
43.4.24Debug mode . . . . .1948
43.5TIM15 registers . . . . .1949
43.5.1TIM15 control register 1 (TIM15_CR1) . . . . .1949
43.5.2TIM15 control register 2 (TIM15_CR2) . . . . .1950
43.5.3TIM15 slave mode control register (TIM15_SMCR) . . . . .1952
43.5.4TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .1953
43.5.5TIM15 status register (TIM15_SR) . . . . .1954
43.5.6TIM15 event generation register (TIM15_EGR) . . . . .1956
43.5.7TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . .1957
43.5.8TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		1958
43.5.9TIM15 capture/compare enable register (TIM15_CCER) . . . . .1961
43.5.10TIM15 counter (TIM15_CNT) . . . . .1964
43.5.11TIM15 prescaler (TIM15_PSC) . . . . .1964
43.5.12TIM15 auto-reload register (TIM15_ARR) . . . . .1964
43.5.13TIM15 repetition counter register (TIM15_RCR) . . . . .1965
43.5.14TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .1965
43.5.15TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .1966
43.5.16TIM15 break and dead-time register (TIM15_BDTR) . . . . .1966
43.5.17TIM15 DMA control register (TIM15_DCR) . . . . .1969
43.5.18TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .1969
43.5.19TIM15 alternate register 1 (TIM15_AF1) . . . . .1970
43.5.20TIM15 input selection register (TIM15_TISEL) . . . . .1971
43.5.21TIM15 register map . . . . .1972
43.6TIM16/TIM17 registers . . . . .1974
43.6.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .1974
43.6.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .1975
43.6.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .1976
43.6.4TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .1977
43.6.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .1978
43.6.6TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 16 to 17) . . . . .		1979
43.6.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . .		1980
43.6.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . .1982
43.6.9TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .1984
43.6.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .1985
43.6.11TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . .1985
43.6.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .1986
43.6.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .1986
43.6.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . .1987
43.6.15TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .1989
43.6.16TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . .1990
43.6.17TIM16 alternate function register 1 (TIM16_AF1) . . . . .1991
43.6.18TIM16 input selection register (TIM16_TISEL) . . . . .1992
43.6.19TIM17 alternate function register 1 (TIM17_AF1) . . . . .1993
43.6.20TIM17 input selection register (TIM17_TISEL) . . . . .1994
43.6.21TIM16/TIM17 register map . . . . .1995
44Basic timers (TIM6/TIM7) . . . . .1997
44.1TIM6/TIM7 introduction . . . . .1997
44.2TIM6/TIM7 main features . . . . .1997
44.3TIM6/TIM7 functional description . . . . .1998
44.3.1Time-base unit . . . . .1998
44.3.2Counting mode . . . . .2000
44.3.3UIF bit remapping . . . . .2003
44.3.4Clock source . . . . .2003
44.3.5Debug mode . . . . .2004
44.4TIM6/TIM7 registers . . . . .2004
44.4.1TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . .2004
44.4.2TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . .2006
44.4.3TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . .2006
44.4.4TIMx status register (TIMx_SR)(x = 6 to 7) . . . . .2007
44.4.5TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . .2007
44.4.6TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . .2007
44.4.7TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . .2008
44.4.8TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . .2008
44.4.9TIMx register map . . . . .2009
45Low-power timer (LPTIM) . . . . .2010
45.1Introduction . . . . .2010
45.2LPTIM main features . . . . .2010
45.3LPTIM implementation . . . . .2011
45.4LPTIM functional description . . . . .2011
45.4.1LPTIM block diagram . . . . .2011
45.4.2LPTIM pins and internal signals . . . . .2013
45.4.3LPTIM input and trigger mapping . . . . .2013
45.4.4LPTIM reset and clocks . . . . .2016
45.4.5Glitch filter . . . . .2016
45.4.6Prescaler . . . . .2017
45.4.7Trigger multiplexer . . . . .2018
45.4.8Operating mode . . . . .2018
45.4.9Timeout function . . . . .2020
45.4.10Waveform generation . . . . .2020
45.4.11Register update . . . . .2021
45.4.12Counter mode . . . . .2022
45.4.13Timer enable . . . . .2022
45.4.14Timer counter reset . . . . .2023
45.4.15Encoder mode . . . . .2023
45.4.16Debug mode . . . . .2025
45.5LPTIM low-power modes . . . . .2025
45.6LPTIM interrupts . . . . .2026
45.7LPTIM registers . . . . .2026
45.7.1LPTIM interrupt and status register (LPTIM_ISR) . . . . .2027
45.7.2LPTIM interrupt clear register (LPTIM_ICR) . . . . .2028
45.7.3LPTIM interrupt enable register (LPTIM_IER) . . . . .2028
45.7.4LPTIM configuration register (LPTIM_CFGR) . . . . .2029
45.7.5LPTIM control register (LPTIM_CR) . . . . .2032
45.7.6LPTIM compare register (LPTIM_CMP) . . . . .2034
45.7.7LPTIM autoreload register (LPTIM_ARR) . . . . .2034
45.7.8LPTIM counter register (LPTIM_CNT) . . . . .2035
45.7.9LPTIM configuration register 2 (LPTIM_CFGR2) . . . . .2035
45.7.10LPTIM3 configuration register 2 (LPTIM3_CFGR2) . . . . .2036
45.7.11LPTIM register map . . . . .2037
46Watchdog overview . . . . .2038
46.1Watchdog main features . . . . .2038
46.2Watchdog brief functional description . . . . .2038
46.2.1Enabling the watchdog clock . . . . .2040
46.2.2Window watchdog reset scope . . . . .2040
46.2.3Watchdog behavior versus CPU state . . . . .2040
47System window watchdog (WWDG) . . . . .2041
47.1Introduction . . . . .2041
47.2WWDG main features . . . . .2041
47.3WWDG functional description . . . . .2041
47.3.1WWDG block diagram . . . . .2042
47.3.2WWDG internal signals . . . . .2042
47.3.3Enabling the watchdog . . . . .2042
47.3.4Controlling the down-counter . . . . .2042
47.3.5How to program the watchdog timeout . . . . .2043
47.3.6Debug mode . . . . .2044
47.4WWDG interrupts . . . . .2044
47.5WWDG registers . . . . .2044
47.5.1WWDG control register (WWDG_CR) . . . . .2045
47.5.2WWDG configuration register (WWDG_CFR) . . . . .2045
47.5.3WWDG status register (WWDG_SR) . . . . .2046
47.5.4WWDG register map . . . . .2046
48Independent watchdog (IWDG) . . . . .2047
48.1Introduction . . . . .2047
48.2IWDG main features . . . . .2047
48.3IWDG functional description . . . . .2047
48.3.1IWDG block diagram . . . . .2047
48.3.2IWDG internal signals . . . . .2048
48.3.3Window option . . . . .2048
48.3.4Hardware watchdog . . . . .2049
48.3.5Low-power freeze . . . . .2049
48.3.6Register access protection . . . . .2049
48.3.7Debug mode . . . . .2049
48.4IWDG registers . . . . .2050
48.4.1IWDG key register (IWDG_KR) . . . . .2050
48.4.2IWDG prescaler register (IWDG_PR) . . . . .2051
48.4.3IWDG reload register (IWDG_RLR) . . . . .2052
48.4.4IWDG status register (IWDG_SR) . . . . .2053
48.4.5IWDG window register (IWDG_WINR) . . . . .2054
48.4.6IWDG register map . . . . .2055
49Real-time clock (RTC) . . . . .2056
49.1Introduction . . . . .2056
49.2RTC main features . . . . .2057
49.3RTC functional description . . . . .2057
49.3.1RTC block diagram . . . . .2057
49.3.2RTC pins and internal signals . . . . .2060
49.3.3GPIOs controlled by the RTC . . . . .2060
49.3.4Clock and prescalers . . . . .2062
49.3.5Real-time clock and calendar . . . . .2063
49.3.6Programmable alarms . . . . .2063
49.3.7Periodic auto-wake-up . . . . .2063
49.3.8RTC initialization and configuration . . . . .2064
49.3.9Reading the calendar . . . . .2066
49.3.10Resetting the RTC . . . . .2067
49.3.11RTC synchronization . . . . .2067
49.3.12RTC reference clock detection . . . . .2068
49.3.13RTC smooth digital calibration . . . . .2068
49.3.14Time-stamp function . . . . .2070
49.3.15Tamper detection . . . . .2071
49.3.16Calibration clock output . . . . .2073
49.3.17Alarm output . . . . .2074
49.4RTC low-power modes . . . . .2074
49.5RTC interrupts . . . . .2074
49.6RTC registers . . . . .2075
49.6.1RTC time register (RTC_TR) . . . . .2075
49.6.2RTC date register (RTC_DR) . . . . .2076
49.6.3RTC control register (RTC_CR) . . . . .2078
49.6.4RTC initialization and status register (RTC_ISR) . . . . .2081
49.6.5RTC prescaler register (RTC_PRER) . . . . .2084
49.6.6RTC wake-up timer register (RTC_WUTR) . . . . .2085
49.6.7RTC alarm A register (RTC_ALRMAR) . . . . .2086
49.6.8RTC alarm B register (RTC_ALRMBR) . . . . .2087
49.6.9RTC write protection register (RTC_WPR) . . . . .2088
49.6.10RTC sub second register (RTC_SSR) . . . . .2088
49.6.11RTC shift control register (RTC_SHIFTR) . . . . .2089
49.6.12RTC timestamp time register (RTC_TSTR) . . . . .2090
49.6.13RTC timestamp date register (RTC_TSDR) . . . . .2091
49.6.14RTC time-stamp sub second register (RTC_TSSSR) . . . . .2092
49.6.15RTC calibration register (RTC_CALR) . . . . .2093
49.6.16RTC tamper configuration register (RTC_TAMPCR) . . . . .2094
49.6.17RTC alarm A sub second register (RTC_ALRMASSR) . . . . .2097
49.6.18RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .2098
49.6.19RTC option register (RTC_OR) . . . . .2099
49.6.20RTC backup registers (RTC_BKPxR) . . . . .2099
49.6.21RTC register map . . . . .2100
50Inter-integrated circuit (I2C) interface . . . . .2102
50.1Introduction . . . . .2102
50.2I2C main features . . . . .2102
50.3I2C implementation . . . . .2103
50.4I2C functional description . . . . .2103
50.4.1I2C block diagram . . . . .2104
50.4.2I2C pins and internal signals . . . . .2105
50.4.3I2C clock requirements . . . . .2105
50.4.4Mode selection . . . . .2105
50.4.5I2C initialization . . . . .2106
50.4.6Software reset . . . . .2111
50.4.7Data transfer . . . . .2112
50.4.8I2C slave mode . . . . .2114
50.4.9I2C master mode . . . . .2123
50.4.10I2C_TIMINGR register configuration examples . . . . .2134
50.4.11SMBus specific features . . . . .2136
50.4.12SMBus initialization . . . . .2139
50.4.13SMBus: I2C_TIMEOUTR register configuration examples . . . . .2141
50.4.14SMBus slave mode . . . . .2141
50.4.15Wake-up from Stop mode on address match . . . . .2148
50.4.16Error conditions . . . . .2149
50.4.17DMA requests . . . . .2151
50.4.18Debug mode .....2151
50.5I2C low-power modes .....2152
50.6I2C interrupts .....2153
50.7I2C registers .....2155
50.7.1I2C control register 1 (I2C_CR1) .....2155
50.7.2I2C control register 2 (I2C_CR2) .....2157
50.7.3I2C own address 1 register (I2C_OAR1) .....2159
50.7.4I2C own address 2 register (I2C_OAR2) .....2160
50.7.5I2C timing register (I2C_TIMINGR) .....2161
50.7.6I2C timeout register (I2C_TIMEOUTR) .....2162
50.7.7I2C interrupt and status register (I2C_ISR) .....2163
50.7.8I2C interrupt clear register (I2C_ICR) .....2165
50.7.9I2C PEC register (I2C_PECR) .....2166
50.7.10I2C receive data register (I2C_RXDR) .....2167
50.7.11I2C transmit data register (I2C_TXDR) .....2167
50.7.12I2C register map .....2168
51Universal synchronous/asynchronous receiver transmitter (USART/UART) .....2170
51.1USART introduction .....2170
51.2USART main features .....2171
51.3USART extended features .....2172
51.4USART implementation .....2172
51.5USART functional description .....2173
51.5.1USART block diagram .....2173
51.5.2USART signals .....2174
51.5.3USART character description .....2175
51.5.4USART FIFOs and thresholds .....2177
51.5.5USART transmitter .....2177
51.5.6USART receiver .....2181
51.5.7USART baud rate generation .....2188
51.5.8Tolerance of the USART receiver to clock deviation .....2189
51.5.9USART auto baud rate detection .....2191
51.5.10USART multiprocessor communication .....2193
51.5.11USART Modbus communication .....2195
51.5.12USART parity control .....2196
51.5.13USART LIN (local interconnection network) mode . . . . .2197
51.5.14USART synchronous mode . . . . .2199
51.5.15USART single-wire Half-duplex communication . . . . .2203
51.5.16USART receiver timeout . . . . .2203
51.5.17USART Smartcard mode . . . . .2204
51.5.18USART IrDA SIR ENDEC block . . . . .2208
51.5.19Continuous communication using USART and DMA . . . . .2211
51.5.20RS232 Hardware flow control and RS485 Driver Enable . . . . .2213
51.5.21USART low-power management . . . . .2216
51.6USART in low-power modes . . . . .2219
51.7USART interrupts . . . . .2220
51.8USART registers . . . . .2221
51.8.1USART control register 1 (USART_CR1) . . . . .2221
51.8.2USART control register 1 [alternate] (USART_CR1) . . . . .2225
51.8.3USART control register 2 (USART_CR2) . . . . .2228
51.8.4USART control register 3 (USART_CR3) . . . . .2232
51.8.5USART baud rate register (USART_BRR) . . . . .2237
51.8.6USART guard time and prescaler register (USART_GTPR) . . . . .2237
51.8.7USART receiver timeout register (USART_RTOR) . . . . .2238
51.8.8USART request register (USART_RQR) . . . . .2239
51.8.9USART interrupt and status register (USART_ISR) . . . . .2240
51.8.10USART interrupt and status register [alternate] (USART_ISR) . . . . .2246
51.8.11USART interrupt flag clear register (USART_ICR) . . . . .2251
51.8.12USART receive data register (USART_RDR) . . . . .2253
51.8.13USART transmit data register (USART_TDR) . . . . .2253
51.8.14USART prescaler register (USART_PRESC) . . . . .2254
51.8.15USART register map . . . . .2255
52Low-power universal asynchronous receiver transmitter (LPUART) . . . . .2257
52.1LPUART introduction . . . . .2257
52.2LPUART main features . . . . .2258
52.3LPUART implementation . . . . .2259
52.4LPUART functional description . . . . .2260
52.4.1LPUART block diagram . . . . .2260
52.4.2LPUART signals . . . . .2261
52.4.3LPUART character description . . . . .2261
52.4.4LPUART FIFOs and thresholds . . . . .2262
52.4.5LPUART transmitter . . . . .2263
52.4.6LPUART receiver . . . . .2266
52.4.7LPUART baud rate generation . . . . .2270
52.4.8Tolerance of the LPUART receiver to clock deviation . . . . .2271
52.4.9LPUART multiprocessor communication . . . . .2272
52.4.10LPUART parity control . . . . .2274
52.4.11LPUART single-wire Half-duplex communication . . . . .2275
52.4.12Continuous communication using DMA and LPUART . . . . .2275
52.4.13RS232 Hardware flow control and RS485 Driver Enable . . . . .2278
52.4.14LPUART low-power management . . . . .2280
52.5LPUART in low-power modes . . . . .2283
52.6LPUART interrupts . . . . .2284
52.7LPUART registers . . . . .2285
52.7.1LPUART control register 1 (LPUART_CR1) . . . . .2285
52.7.2LPUART control register 1 [alternate] (LPUART_CR1) . . . . .2288
52.7.3LPUART control register 2 (LPUART_CR2) . . . . .2291
52.7.4LPUART control register 3 (LPUART_CR3) . . . . .2293
52.7.5LPUART baud rate register (LPUART_BRR) . . . . .2296
52.7.6LPUART request register (LPUART_RQR) . . . . .2297
52.7.7LPUART interrupt and status register (LPUART_ISR) . . . . .2297
52.7.8LPUART interrupt and status register [alternate] (LPUART_ISR) . . . . .2302
52.7.9LPUART interrupt flag clear register (LPUART_ICR) . . . . .2305
52.7.10LPUART receive data register (LPUART_RDR) . . . . .2306
52.7.11LPUART transmit data register (LPUART_TDR) . . . . .2306
52.7.12LPUART prescaler register (LPUART_PRESC) . . . . .2307
52.7.13LPUART register map . . . . .2308
53Serial peripheral interface (SPI) . . . . .2310
53.1Introduction . . . . .2310
53.2SPI main features . . . . .2311
53.3SPI implementation . . . . .2311
53.4SPI functional description . . . . .2312
53.4.1SPI block diagram . . . . .2312
53.4.2SPI signals . . . . .2313
53.4.3SPI communication general aspects . . . . .2314
53.4.4Communications between one master and one slave . . . . .2314
53.4.5Standard multislave communication . . . . .2316
53.4.6Multimaster communication . . . . .2319
53.4.7Slave select (SS) pin management . . . . .2319
53.4.8Communication formats . . . . .2323
53.4.9Configuration of SPI . . . . .2325
53.4.10Procedure for enabling SPI . . . . .2326
53.4.11SPI data transmission and reception procedures . . . . .2326
53.4.12Procedure for disabling the SPI . . . . .2331
53.4.13Data packing . . . . .2332
53.4.14Communication using DMA (direct memory addressing) . . . . .2333
53.5SPI specific modes and control . . . . .2335
53.5.1TI mode . . . . .2335
53.5.2SPI error flags . . . . .2335
53.5.3CRC computation . . . . .2339
53.6Low-power mode management . . . . .2340
53.7SPI wakeup and interrupts . . . . .2343
53.8I2S main features . . . . .2344
53.9I2S functional description . . . . .2345
53.9.1I2S general description . . . . .2345
53.9.2Pin sharing with SPI function . . . . .2345
53.9.3Bitfields usable in I2S/PCM mode . . . . .2346
53.9.4Slave and master modes . . . . .2347
53.9.5Supported audio protocols . . . . .2347
53.9.6Additional Serial Interface Flexibility . . . . .2353
53.9.7Startup sequence . . . . .2355
53.9.8Stop sequence . . . . .2357
53.9.9Clock generator . . . . .2357
53.9.10Internal FIFOs . . . . .2360
53.9.11FIFOs status flags . . . . .2361
53.9.12Handling of underrun situation . . . . .2361
53.9.13Handling of overrun situation . . . . .2362
53.9.14Frame error detection . . . . .2363
53.9.15DMA Interface . . . . .2364
53.9.16Programing examples . . . . .2366
53.10I2S wakeup and interrupts . . . . .2368
53.11SPI/I2S registers . . . . .2369
53.11.1SPI/I2S control register 1 (SPI_CR1) . . . . .2369
53.11.2SPI control register 2 (SPI_CR2) . . . . .2371
53.11.3SPI configuration register 1 (SPI_CFG1) . . . . .2371
53.11.4SPI configuration register 2 (SPI_CFG2) . . . . .2374
53.11.5SPI/I2S interrupt enable register (SPI_IER) . . . . .2376
53.11.6SPI/I2S status register (SPI_SR) . . . . .2377
53.11.7SPI/I2S interrupt/status flags clear register (SPI_IFCR) . . . . .2380
53.11.8SPI/I2S transmit data register (SPI_TXDR) . . . . .2381
53.11.9SPI/I2S receive data register (SPI_RXDR) . . . . .2381
53.11.10SPI polynomial register (SPI_CRCPOLY) . . . . .2382
53.11.11SPI transmitter CRC register (SPI_TXCRC) . . . . .2382
53.11.12SPI receiver CRC register (SPI_RXCRC) . . . . .2383
53.11.13SPI underrun data register (SPI_UDRDR) . . . . .2384
53.11.14SPI/I2S configuration register (SPI_I2SCFGR) . . . . .2384
53.12SPI register map and reset values . . . . .2387
54Serial audio interface (SAI) . . . . .2389
54.1Introduction . . . . .2389
54.2SAI main features . . . . .2389
54.3SAI implementation . . . . .2390
54.4SAI functional description . . . . .2390
54.4.1SAI block diagram . . . . .2390
54.4.2SAI pins and internal signals . . . . .2392
54.4.3Main SAI modes . . . . .2392
54.4.4SAI synchronization mode . . . . .2393
54.4.5Audio data size . . . . .2394
54.4.6Frame synchronization . . . . .2395
54.4.7Slot configuration . . . . .2398
54.4.8SAI clock generator . . . . .2400
54.4.9Internal FIFOs . . . . .2403
54.4.10PDM interface . . . . .2405
54.4.11AC'97 link controller . . . . .2413
54.4.12SPDIF output . . . . .2415
54.4.13Specific features . . . . .2418
54.4.14Error flags . . . . .2422
54.4.15Disabling the SAI . . . . .2425
54.4.16SAI DMA interface . . . . .2425
54.5SAI interrupts . . . . .2426
54.6SAI registers . . . . .2427
54.6.1SAI global configuration register (SAI_GCR) . . . . .2427
54.6.2SAI configuration register 1 (SAI_ACR1) . . . . .2428
54.6.3SAI configuration register 1 (SAI_BCR1) . . . . .2430
54.6.4SAI configuration register 2 (SAI_ACR2) . . . . .2433
54.6.5SAI configuration register 2 (SAI_BCR2) . . . . .2435
54.6.6SAI frame configuration register (SAI_AFRCR) . . . . .2437
54.6.7SAI frame configuration register (SAI_BFRCR) . . . . .2439
54.6.8SAI slot register (SAI_ASLOTR) . . . . .2440
54.6.9SAI slot register (SAI_BSLOTR) . . . . .2441
54.6.10SAI interrupt mask register (SAI_AIM) . . . . .2442
54.6.11SAI interrupt mask register (SAI_BIM) . . . . .2444
54.6.12SAI status register (SAI_ASR) . . . . .2445
54.6.13SAI status register (SAI_BSR) . . . . .2447
54.6.14SAI clear flag register (SAI_ACLRFR) . . . . .2449
54.6.15SAI clear flag register (SAI_BCLRFR) . . . . .2450
54.6.16SAI data register (SAI_ADR) . . . . .2451
54.6.17SAI data register (SAI_BDR) . . . . .2452
54.6.18SAI PDM control register (SAI_PDMCR) . . . . .2452
54.6.19SAI PDM delay register (SAI_PDMPLY) . . . . .2454
54.6.20SAI register map . . . . .2456
55SPDIFRX receiver interface (SPDIFRX) . . . . .2458
55.1SPDIFRX interface introduction . . . . .2458
55.2SPDIFRX main features . . . . .2458
55.3SPDIFRX functional description . . . . .2458
55.3.1SPDIFRX pins and internal signals . . . . .2459
55.3.2S/PDIF protocol (IEC-60958) . . . . .2460
55.3.3SPDIFRX decoder (SPDIFRX_DC) . . . . .2462
55.3.4SPDIFRX tolerance to clock deviation . . . . .2466
55.3.5SPDIFRX synchronization . . . . .2466
55.3.6SPDIFRX handling . . . . .2468
55.3.7Data reception management . . . . .2470
55.3.8Dedicated control flow . . . . .2472
55.3.9Reception errors . . . . .2473
55.3.10Clocking strategy . . . . .2475
55.3.11DMA interface . . . . .2475
55.3.12Interrupt generation . . . . .2476
55.3.13Register protection . . . . .2477
55.4Programming procedures . . . . .2478
55.4.1Initialization phase . . . . .2478
55.4.2Handling of interrupts coming from SPDIFRX . . . . .2479
55.4.3Handling of interrupts coming from DMA . . . . .2479
55.5SPDIFRX interface registers . . . . .2480
55.5.1SPDIFRX control register (SPDIFRX_CR) . . . . .2480
55.5.2SPDIFRX interrupt mask register (SPDIFRX_IMR) . . . . .2482
55.5.3SPDIFRX status register (SPDIFRX_SR) . . . . .2483
55.5.4SPDIFRX interrupt flag clear register (SPDIFRX_IFCR) . . . . .2485
55.5.5SPDIFRX data input register (SPDIFRX_FMT0_DR) . . . . .2486
55.5.6SPDIFRX data input register (SPDIFRX_FMT1_DR) . . . . .2486
55.5.7SPDIFRX data input register (SPDIFRX_FMT2_DR) . . . . .2487
55.5.8SPDIFRX channel status register (SPDIFRX_CSR) . . . . .2488
55.5.9SPDIFRX debug information register (SPDIFRX_DIR) . . . . .2488
55.5.10SPDIFRX interface register map . . . . .2489
56Single wire protocol master interface (SWPMI) . . . . .2490
56.1Introduction . . . . .2490
56.2SWPMI main features . . . . .2491
56.3SWPMI functional description . . . . .2492
56.3.1SWPMI block diagram . . . . .2492
56.3.2SWPMI pins and internal signals . . . . .2492
56.3.3SWP initialization and activation . . . . .2493
56.3.4SWP bus states . . . . .2494
56.3.5SWPMI_IO (internal transceiver) bypass . . . . .2495
56.3.6SWPMI bit rate . . . . .2495
56.3.7SWPMI frame handling . . . . .2496
56.3.8Transmission procedure . . . . .2496
56.3.9Reception procedure . . . . .2501
56.3.10Error management . . . . .2505
56.3.11Loopback mode . . . . .2507
56.4SWPMI low-power modes . . . . .2507
56.5SWPMI interrupts . . . . .2508
56.6SWPMI registers . . . . .2509
56.6.1SWPMI configuration/control register (SWPMI_CR) . . . . .2509
56.6.2SWPMI Bitrate register (SWPMI_BRR) . . . . .2510
56.6.3SWPMI Interrupt and Status register (SWPMI_ISR) . . . . .2511
56.6.4SWPMI Interrupt Flag Clear register (SWPMI_ICR) . . . . .2512
56.6.5SWPMI Interrupt Enable register (SWPMI_IER) . . . . .2513
56.6.6SWPMI Receive Frame Length register (SWPMI_RFL) . . . . .2515
56.6.7SWPMI Transmit data register (SWPMI_TDR) . . . . .2515
56.6.8SWPMI Receive data register (SWPMI_RDR) . . . . .2515
56.6.9SWPMI Option register (SWPMI_OR) . . . . .2516
56.6.10SWPMI register map and reset value table . . . . .2517
57Management data input/output (MDIOS) . . . . .2518
57.1MDIOS introduction . . . . .2518
57.2MDIOS main features . . . . .2518
57.3MDIOS functional description . . . . .2519
57.3.1MDIOS block diagram . . . . .2519
57.3.2MDIOS pins and internal signals . . . . .2519
57.3.3MDIOS protocol . . . . .2519
57.3.4MDIOS enabling and disabling . . . . .2520
57.3.5MDIOS data . . . . .2521
57.3.6MDIOS APB frequency . . . . .2522
57.3.7Write/read flags and interrupts . . . . .2522
57.3.8MDIOS error management . . . . .2523
57.3.9MDIOS in Stop mode . . . . .2524
57.3.10MDIOS interrupts . . . . .2524
57.4MDIOS registers . . . . .2524
57.4.1MDIOS configuration register (MDIOS_CR) . . . . .2524
57.4.2MDIOS write flag register (MDIOS_WRFR) . . . . .2525
57.4.3MDIOS clear write flag register (MDIOS_CWRFR) . . . . .2526
57.4.4MDIOS read flag register (MDIOS_RDFR) . . . . .2526
57.4.5MDIOS clear read flag register (MDIOS_CRDFR) . . . . .2527
57.4.6MDIOS status register (MDIOS_SR) . . . . .2527
57.4.7MDIOS clear flag register (MDIOS_CLRFR) . . . . .2528
57.4.8MDIOS input data register x (MDIOS_DINRx) . . . . .2528
57.4.9MDIOS output data register x (MDIOS_DOUTRx) . . . . .2529
57.4.10MDIOS register map . . . . .2529
58Secure digital input/output MultiMediaCard interface (SDMMC) . . .2531
58.1SDMMC main features . . . . .2531
58.2SDMMC implementation . . . . .2531
58.3SDMMC bus topology . . . . .2532
58.4SDMMC operation modes . . . . .2534
58.5SDMMC functional description . . . . .2535
58.5.1SDMMC block diagram . . . . .2535
58.5.2SDMMC pins and internal signals . . . . .2535
58.5.3General description . . . . .2536
58.5.4SDMMC adapter . . . . .2538
58.5.5SDMMC AHB slave interface . . . . .2560
58.5.6SDMMC AHB master interface . . . . .2560
58.5.7MDMA request generation . . . . .2562
58.5.8AHB and SDMMC_CK clock relation . . . . .2563
58.6Card functional description . . . . .2564
58.6.1SD I/O mode . . . . .2564
58.6.2CMD12 send timing . . . . .2572
58.6.3Sleep (CMD5) . . . . .2575
58.6.4Interrupt mode (Wait-IRQ) . . . . .2576
58.6.5Boot operation . . . . .2577
58.6.6Response R1b handling . . . . .2580
58.6.7Reset and card cycle power . . . . .2581
58.7Hardware flow control . . . . .2582
58.8Ultra-high-speed phase I (UHS-I) voltage switch . . . . .2583
58.9SDMMC interrupts . . . . .2586
58.10SDMMC registers . . . . .2588
58.10.1SDMMC power control register (SDMMC_POWER) . . . . .2588
58.10.2SDMMC clock control register (SDMMC_CLKCR) . . . . .2589
58.10.3SDMMC argument register (SDMMC_ARGR) . . . . .2591
58.10.4SDMMC command register (SDMMC_CMDR) . . . . .2591
58.10.5SDMMC command response register (SDMMC_RESPCMDR) . . . . .2593
58.10.6SDMMC response x register (SDMMC_RESPxR) . . . . .2594
58.10.7SDMMC data timer register (SDMMC_DTIMER) . . . . .2594
58.10.8SDMMC data length register (SDMMC_DLENR) . . . . .2595
58.10.9SDMMC data control register (SDMMC_DCTRL) . . . . .2596
58.10.10SDMMC data counter register (SDMMC_DCNTR) . . . . .2597
58.10.11SDMMC status register (SDMMC_STAR) . . . . .2598
58.10.12SDMMC interrupt clear register (SDMMC_ICR) . . . . .2601
58.10.13SDMMC mask register (SDMMC_MASKR) . . . . .2603
58.10.14SDMMC acknowledgment timer register (SDMMC_ACKTIMER) . . . . .2606
58.10.15SDMMC data FIFO registers x (SDMMC_FIFORx) . . . . .2606
58.10.16SDMMC DMA control register (SDMMC_IDMACTRLR) . . . . .2607
58.10.17SDMMC IDMA buffer size register (SDMMC_IDMABSIZER) . . . . .2608
58.10.18SDMMC IDMA buffer 0 base address register
(SDMMC_IDMABASE0R) . . . . .		2608
58.10.19SDMMC IDMA buffer 1 base address register
(SDMMC_IDMABASE1R) . . . . .		2609
58.10.20SDMMC register map . . . . .2609
59Controller area network with flexible data rate (FDCAN) . . . . .2612
59.1Introduction . . . . .2612
59.2FDCAN main features . . . . .2615
59.3FDCAN implementation . . . . .2615
59.4FDCAN functional description . . . . .2616
59.4.1Operating modes . . . . .2617
59.4.2Message RAM . . . . .2626
59.4.3FIFO acknowledge handling . . . . .2637
59.4.4Bit timing . . . . .2638
59.4.5Clock calibration on CAN . . . . .2639
59.4.6Application . . . . .2643
59.4.7TT CAN operations (FDCAN1 only) . . . . .2644
59.4.8TT CAN configuration . . . . .2645
59.4.9Message scheduling . . . . .2647
59.4.10TT CAN gap control . . . . .2654
59.4.11Stop watch . . . . .2655
59.4.12Local time, cycle time, global time,
and external clock synchronization . . . . .		2655
59.4.13TT CAN error level . . . . .2658
59.4.14TT CAN message handling . . . . .2659
59.4.15TT CAN interrupt and error handling . . . . .2662
59.4.16Level 0 . . . . .2663
59.4.17Synchronization to external time schedule . . . . .2665
59.4.18FDCAN Rx buffer and FIFO element . . . . .2666
59.4.19FDCAN Tx buffer element . . . . .2668
59.4.20FDCAN Tx event FIFO element . . . . .2670
59.4.21FDCAN standard message ID filter element . . . . .2671
59.4.22FDCAN extended message ID filter element . . . . .2673
59.4.23FDCAN trigger memory element . . . . .2674
59.5FDCAN registers . . . . .2676
59.5.1FDCAN core release register (FDCAN_CREL) . . . . .2676
59.5.2FDCAN Endian register (FDCAN_ENDN) . . . . .2676
59.5.3FDCAN data bit timing and prescaler register (FDCAN_DBTP) . . . . .2677
59.5.4FDCAN test register (FDCAN_TEST) . . . . .2678
59.5.5FDCAN RAM watchdog register (FDCAN_RWD) . . . . .2678
59.5.6FDCAN CC control register (FDCAN_CCCR) . . . . .2679
59.5.7FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) . . . . .2681
59.5.8FDCAN timestamp counter configuration register (FDCAN_TSCC) . . . . .2682
59.5.9FDCAN timestamp counter value register (FDCAN_TSCV) . . . . .2683
59.5.10FDCAN timeout counter configuration register (FDCAN_TOCC) . . . . .2683
59.5.11FDCAN timeout counter value register (FDCAN_TOCV) . . . . .2684
59.5.12FDCAN error counter register (FDCAN_ECR) . . . . .2685
59.5.13FDCAN protocol status register (FDCAN_PSR) . . . . .2685
59.5.14FDCAN transmitter delay compensation register (FDCAN_TDCR) . . . . .2687
59.5.15FDCAN interrupt register (FDCAN_IR) . . . . .2688
59.5.16FDCAN interrupt enable register (FDCAN_IE) . . . . .2691
59.5.17FDCAN interrupt line select register (FDCAN_ILS) . . . . .2693
59.5.18FDCAN interrupt line enable register (FDCAN_ILE) . . . . .2694
59.5.19FDCAN global filter configuration register (FDCAN_GFC) . . . . .2695
59.5.20FDCAN standard ID filter configuration register (FDCAN_SIDFC) . . . . .2696
59.5.21FDCAN extended ID filter configuration register (FDCAN_XIDFC) . . . . .2696
59.5.22FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . .2697
59.5.23FDCAN high priority message status register (FDCAN_HPMS) . . . . .2698
59.5.24FDCAN new data 1 register (FDCAN_NDAT1) . . . . .2698
59.5.25FDCAN new data 2 register (FDCAN_NDAT2) . . . . .2699
59.5.26FDCAN Rx FIFO 0 configuration register (FDCAN_RXF0C) . . . . .2699
59.5.27FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . .2700
59.5.28FDCAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . .2701
59.5.29FDCAN Rx buffer configuration register (FDCAN_RXBC)2701
59.5.30FDCAN Rx FIFO 1 configuration register (FDCAN_RXF1C)2702
59.5.31FDCAN Rx FIFO 1 status register (FDCAN_RXF1S)2703
59.5.32FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A)2704
59.5.33FDCAN Rx buffer element size configuration register
(FDCAN_RXESC)		2704
59.5.34FDCAN Tx buffer configuration register (FDCAN_TXBC)2705
59.5.35FDCAN Tx FIFO/queue status register (FDCAN_TXFQS)2706
59.5.36FDCAN Tx buffer element size configuration register
(FDCAN_TXESC)		2707
59.5.37FDCAN Tx buffer request pending register (FDCAN_TXBRP)2707
59.5.38FDCAN Tx buffer add request register (FDCAN_TXBAR)2708
59.5.39FDCAN Tx buffer cancellation request register (FDCAN_TXBCR)2709
59.5.40FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO)2709
59.5.41FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF)2710
59.5.42FDCAN Tx buffer transmission interrupt enable register
(FDCAN_TXBTIE)		2710
59.5.43FDCAN Tx buffer cancellation finished interrupt enable register
(FDCAN_TXBCIE)		2711
59.5.44FDCAN Tx event FIFO configuration register (FDCAN_TXEFC)2711
59.5.45FDCAN Tx event FIFO status register (FDCAN_TXEFS)2712
59.5.46FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA)2713
59.5.47FDCAN register map2713
59.6TT CAN registers2717
59.6.1FDCAN TT trigger memory configuration register (FDCAN_TTTMC)2717
59.6.2FDCAN TT reference message configuration register
(FDCAN_TTRMC)		2717
59.6.3FDCAN TT operation configuration register (FDCAN_TTOCF)2718
59.6.4FDCAN TT matrix limits register (FDCAN_TTMLM)2720
59.6.5FDCAN TUR configuration register (FDCAN_TURCF)2721
59.6.6FDCAN TT operation control register (FDCAN_TTOCN)2722
59.6.7FDCAN TT global time preset register (FDCAN_TTGTP)2724
59.6.8FDCAN TT time mark register (FDCAN_TTTMK)2724
59.6.9FDCAN TT interrupt register (FDCAN_TTIR)2725
59.6.10FDCAN TT interrupt enable register (FDCAN_TTIE)2727
59.6.11FDCAN TT interrupt line select register (FDCAN_TTILS)2729
59.6.12FDCAN TT operation status register (FDCAN_TTOST)2730
59.6.13FDCAN TUR numerator actual register (FDCAN_TURNA)2732
59.6.14FDCAN TT local and global time register (FDCAN_TTLGT) . . . . .2733
59.6.15FDCAN TT cycle time and count register (FDCAN_TTCTC) . . . . .2733
59.6.16FDCAN TT capture time register (FDCAN_TTCPT) . . . . .2734
59.6.17FDCAN TT cycle sync mark register (FDCAN_TTCSM) . . . . .2734
59.6.18FDCAN TT trigger select register (FDCAN_TTTS) . . . . .2735
59.6.19FDCAN TT register map . . . . .2735
59.7CCU registers . . . . .2737
59.7.1Clock calibration unit core release register (FDCAN_CCU_CREL) . .2737
59.7.2Calibration configuration register (FDCAN_CCU_CCFG) . . . . .2737
59.7.3Calibration status register (FDCAN_CCU_CSTAT) . . . . .2739
59.7.4Calibration watchdog register (FDCAN_CCU_CWD) . . . . .2739
59.7.5Clock calibration unit interrupt register (FDCAN_CCU_IR) . . . . .2740
59.7.6Clock calibration unit interrupt enable register (FDCAN_CCU_IE) . .2741
59.7.7CCU register map . . . . .2741
60USB on-the-go high-speed (OTG_HS) . . . . .2743
60.1Introduction . . . . .2743
60.2OTG_HS main features . . . . .2744
60.2.1General features . . . . .2744
60.2.2Host-mode features . . . . .2745
60.2.3Peripheral-mode features . . . . .2745
60.3OTG_HS implementation . . . . .2746
60.4OTG_HS functional description . . . . .2746
60.4.1OTG_HS block diagram . . . . .2746
60.4.2OTG_HS pin and internal signals . . . . .2748
60.4.3OTG_HS core . . . . .2748
60.4.4Embedded full-speed OTG PHY connected to OTG_HS . . . . .2749
60.4.5OTG detections . . . . .2749
60.4.6High-speed OTG PHY connected to OTG_HS . . . . .2749
60.5OTG_HS dual role device (DRD) . . . . .2750
60.5.1ID line detection . . . . .2750
60.5.2HNP dual role device . . . . .2750
60.5.3SRP dual role device . . . . .2751
60.6OTG_HS as a USB peripheral . . . . .2751
60.6.1SRP-capable peripheral . . . . .2752
60.6.2Peripheral states . . . . .2752
60.6.3Peripheral endpoints . . . . .2753
60.7OTG_HS as a USB host . . . . .2755
60.7.1SRP-capable host . . . . .2756
60.7.2USB host states . . . . .2756
60.7.3Host channels . . . . .2758
60.7.4Host scheduler . . . . .2759
60.8OTG_HS SOF trigger . . . . .2760
60.8.1Host SOFs . . . . .2760
60.8.2Peripheral SOFs . . . . .2760
60.9OTG_HS low-power modes . . . . .2761
60.10OTG_HS Dynamic update of the OTG_HFIR register . . . . .2762
60.11OTG_HS data FIFOs . . . . .2762
60.11.1Peripheral FIFO architecture . . . . .2763
60.11.2Host FIFO architecture . . . . .2764
60.11.3FIFO RAM allocation . . . . .2765
60.12OTG_HS interrupts . . . . .2767
60.13OTG_HS control and status registers . . . . .2769
60.13.1CSR memory map . . . . .2769
60.14OTG_HS registers . . . . .2774
60.14.1OTG control and status register (OTG_GOTGCTL) . . . . .2774
60.14.2OTG interrupt register (OTG_GOTGINT) . . . . .2777
60.14.3OTG AHB configuration register (OTG_GAHBCFG) . . . . .2779
60.14.4OTG USB configuration register (OTG_GUSBCFG) . . . . .2780
60.14.5OTG reset register (OTG_GRSTCTL) . . . . .2783
60.14.6OTG core interrupt register (OTG_GINTSTS) . . . . .2786
60.14.7OTG interrupt mask register (OTG_GINTMSK) . . . . .2790
60.14.8OTG receive status debug read register (OTG_GRXSTSR) . . . . .2794
60.14.9OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . .2795
60.14.10OTG status read and pop registers (OTG_GRXSTSP) . . . . .2796
60.14.11OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . . . .2797
60.14.12OTG receive FIFO size register (OTG_GRXFSIZ) . . . . .2798
60.14.13OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0) . . . . .		2798
60.14.14OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . .		2799
60.14.15OTG general core configuration register (OTG_GCCFG) . . . . .2800
60.14.16OTG core ID register (OTG_CID) . . . . .2802
60.14.17OTG core LPM configuration register (OTG_GLPMCFG) . . . . .2802
60.14.18OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . .		2806
60.14.19OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx) . . . . .		2806
60.14.20Host-mode registers . . . . .2807
60.14.21OTG host configuration register (OTG_HCFG) . . . . .2807
60.14.22OTG host frame interval register (OTG_HFIR) . . . . .2808
60.14.23OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . .		2809
60.14.24OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . .		2810
60.14.25OTG host all channels interrupt register (OTG_HAINT) . . . . .2811
60.14.26OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . .		2811
60.14.27OTG host frame list base address register
(OTG_HFLBADDR) . . . . .		2812
60.14.28OTG host port control and status register (OTG_HPRT) . . . . .2812
60.14.29OTG host channel x characteristics register (OTG_HCCHARx) . . . . .2815
60.14.30OTG host channel x split control register (OTG_HCSPLTx) . . . . .2816
60.14.31OTG host channel x interrupt register (OTG_HCINTx) . . . . .2817
60.14.32OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . . . .2818
60.14.33OTG host channel x transfer size register (OTG_HCTSIZx) . . . . .2820
60.14.34OTG host channel x transfer size register (OTG_HCTSIZSGx) . . . . .2821
60.14.35OTG host channel x DMA address register in buffer DMA [alternate]
(OTG_HCDMAx) . . . . .		2823
60.14.36OTG host channel x DMA address register in scatter/gather DMA
[alternate] (OTG_HCDMASGx) . . . . .		2823
60.14.37OTG host channel-n DMA address buffer register
(OTG_HCDMABx) . . . . .		2824
60.14.38Device-mode registers . . . . .2825
60.14.39OTG device configuration register (OTG_DCFG) . . . . .2825
60.14.40OTG device control register (OTG_DCTL) . . . . .2827
60.14.41OTG device status register (OTG_DSTS) . . . . .2829
60.14.42OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . .		2830
60.14.43OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . .		2831
60.14.44OTG device all endpoints interrupt register (OTG_DAINT) . . . . .2832
60.14.45OTG all endpoints interrupt mask register
(OTG_DAINTRMSK) .....		2833
60.14.46OTG device V BUS discharge time register
(OTG_DVBUSDIS) .....		2834
60.14.47OTG device V BUS pulsing time register
(OTG_DVBUSPULSE) .....		2834
60.14.48OTG device threshold control register (OTG_DTHRCTL) .....2835
60.14.49OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK) .....		2836
60.14.50OTG device each endpoint interrupt register (OTG_DEACHINT) . . .2836
60.14.51OTG device each endpoint interrupt mask register
(OTG_DEACHINTMSK) .....		2837
60.14.52OTG device each IN endpoint-1 interrupt mask register
(OTG_HS_DIEPEACHMSK1) .....		2837
60.14.53OTG device each OUT endpoint-1 interrupt mask register
(OTG_HS_DOEPEACHMSK1) .....		2838
60.14.54OTG device IN endpoint x control register (OTG_DIEPCTLx) . . . . .2840
60.14.55OTG device IN endpoint x interrupt register (OTG_DIEPINTx) . . . . .2842
60.14.56OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0) .....		2844
60.14.57OTG device IN endpoint x DMA address register
(OTG_DIEPDMAX) .....		2844
60.14.58OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) .....		2845
60.14.59OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) . .2845
60.14.60OTG device control OUT endpoint 0 control register
(OTG_DOEPCTL0) .....		2846
60.14.61OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . . .2848
60.14.62OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0) .....		2850
60.14.63OTG device OUT endpoint x DMA address register
(OTG_DOEPDMAX) .....		2851
60.14.64OTG device OUT endpoint x control register
(OTG_DOEPCTLx) .....		2851
60.14.65OTG device OUT endpoint x transfer size register
(OTG_DOEPTSIZx) .....		2854
60.14.66OTG power and clock gating control register (OTG_PCGCCTL) . . .2855
60.14.67OTG_HS register map .....2856
60.15OTG_HS programming model .....2868
60.15.1Core initialization .....2868
60.15.2Host initialization .....2869
60.15.3Device initialization .....2870
60.15.4DMA mode .....2870
60.15.5Host programming model .....2871
60.15.6Device programming model .....2903
60.15.7Worst case response time .....2923
60.15.8OTG programming model .....2925
61Ethernet (ETH): media access control (MAC) with DMA controller .....2931
61.1Ethernet introduction .....2931
61.2Ethernet main features .....2931
61.2.1Standard compliance .....2931
61.2.2MAC features .....2931
61.2.3Transaction layer (MTL) features .....2933
61.2.4DMA block features .....2934
61.2.5Bus interface features .....2934
61.3Ethernet pins and internal signals .....2935
61.4Ethernet architecture .....2936
61.4.1DMA controller .....2937
61.4.2MTL .....2946
61.4.3MAC .....2946
61.5)Ethernet functional description: MAC .....2951
61.5.1Double VLAN processing .....2951
61.5.2Source address and VLAN insertion, replacement, or deletion .....2952
61.5.3Packet filtering .....2954
61.5.4IEEE 1588 timestamp support .....2960
61.5.5Checksum offload engine .....2985
61.5.6TCP segmentation offload .....2991
61.5.7IPv4 ARP offload .....2997
61.5.8Loopback .....2998
61.5.9Flow control .....2999
61.5.10MAC management counters .....3002
61.5.11Interrupts generated by the MAC .....3004
61.5.12MAC and MMC register descriptions .....3004
61.6Ethernet functional description: PHY interfaces .....3005
61.6.1Station management agent (SMA) .....3005
61.6.2Media independent interface (MII) .....3012

62 HDMI-CEC controller (CEC) . . . . . 3208

62.2HDMI-CEC controller main features . . . . .3208
62.3HDMI-CEC functional description . . . . .3209
62.3.1HDMI-CEC pin and internal signals . . . . .3209
62.3.2HDMI-CEC block diagram . . . . .3210
62.3.3Message description . . . . .3210
62.3.4Bit timing . . . . .3211
62.4Arbitration . . . . .3211
62.4.1SFT option bit . . . . .3213
62.5Error handling . . . . .3213
62.5.1Bit error . . . . .3213
62.5.2Message error . . . . .3214
62.5.3Bit rising error (BRE) . . . . .3214
62.5.4Short bit period error (SBPE) . . . . .3214
62.5.5Long bit period error (LBPE) . . . . .3214
62.5.6Transmission error detection (TXERR) . . . . .3216
62.6HDMI-CEC interrupts . . . . .3217
62.7HDMI-CEC registers . . . . .3218
62.7.1CEC control register (CEC_CR) . . . . .3218
62.7.2CEC configuration register (CEC_CFGR) . . . . .3219
62.7.3CEC Tx data register (CEC_TXDR) . . . . .3221
62.7.4CEC Rx data register (CEC_RXDR) . . . . .3221
62.7.5CEC interrupt and status register (CEC_ISR) . . . . .3221
62.7.6CEC interrupt enable register (CEC_IER) . . . . .3223
62.7.7HDMI-CEC register map . . . . .3225
63Debug infrastructure . . . . .3226
63.1Introduction . . . . .3226
63.2Debug infrastructure features . . . . .3227
63.3Debug infrastructure functional description . . . . .3227
63.3.1Debug infrastructure block diagram . . . . .3227
63.3.2Debug infrastructure pins and internal signals . . . . .3228
63.3.3Debug infrastructure powering, clocking and reset . . . . .3230
63.4Debug access port functional description . . . . .3232
63.4.1Serial-wire and JTAG debug port (SWJ-DP) . . . . .3232
63.4.2Access ports . . . . .3246
63.5Trace and debug subsystem functional description . . . . .3252
63.5.1System ROM tables . . . . .3252
63.5.2Global timestamp generator (TSG) . . . . .3261
63.5.3Cross trigger interfaces (CTI) and matrix (CTM) . . . . .3269
63.5.4Trace funnel (CSTF) . . . . .3291
63.5.5Embedded trace FIFO (ETF) . . . . .3301
63.5.6Trace port interface unit (TPIU) . . . . .3323
63.5.7Serial wire output (SWO) and SWO trace funnel (SWTF) . . . . .3341
63.5.8Microcontroller debug unit (DBGMCU) . . . . .3364
63.6Cortex-M7 debug functional description . . . . .3375
63.6.1Cortex-M7 ROM tables . . . . .3375
63.6.2Cortex-M7 data watchpoint and trace unit (DWT) . . . . .3388
63.6.3Cortex-M7 instrumentation trace macrocell (ITM) . . . . .3401
63.6.4Cortex-M7 breakpoint unit (FPB) . . . . .3410
63.6.5Cortex-M7 embedded trace macrocell (ETM) . . . . .3418
63.6.6Cortex-M7 cross trigger interface (CTI) . . . . .3450
63.7Cortex-M4 debug functional description . . . . .3450
63.7.1Cortex-M4 ROM table . . . . .3451
63.7.2Cortex-M4 data watchpoint and trace unit (DWT) . . . . .3457
63.7.3Cortex-M4 instrumentation trace macrocell (ITM) . . . . .3471
63.7.4Cortex-M4 breakpoint unit (FPB) . . . . .3479
63.7.5Cortex-M4 embedded trace macrocell (ETM) . . . . .3486
63.7.6Cortex-M4 cross trigger interface (CTI) . . . . .3508
63.8References for debug infrastructure . . . . .3509
64Device electronic signature . . . . .3510
64.1Unique device ID register (96 bits) . . . . .3510
64.2Flash size . . . . .3512
64.3Line identifier . . . . .3512
64.4Package data register . . . . .3512
65Important security notice . . . . .3513
66Revision history . . . . .3514

List of tables

Table 1.Availability of security features . . . . .107
Table 2.Bus-master-to-bus-slave interconnect . . . . .108
Table 3.ASIB configuration . . . . .115
Table 4.AMIB configuration . . . . .116
Table 5.AXI interconnect register map and reset values . . . . .126
Table 6.Memory map and default device memory area attributes . . . . .135
Table 7.Register boundary addresses . . . . .138
Table 8.Boot order . . . . .144
Table 9.Boot modes . . . . .144
Table 10.RAMECC internal input/output signals . . . . .148
Table 11.ECC controller mapping . . . . .148
Table 12.RAMECC register map and reset values . . . . .153
Table 13.FLASH internal input/output signals . . . . .156
Table 14.Flash memory organization on STM32H745xl/747xl/755xl/757xl devices . . . . .159
Table 15.Flash memory organization on STM32H745xG/STM32H747xG devices . . . . .160
Table 16.FLASH recommended number of wait states and programming delay . . . . .166
Table 17.FLASH parallelism parameter . . . . .170
Table 18.FLASH AXI interface memory map vs swapping option . . . . .176
Table 19.Flash register map vs swapping option . . . . .178
Table 20.Option byte organization . . . . .183
Table 21.Flash interface register protection summary . . . . .189
Table 22.RDP value vs readout protection level . . . . .191
Table 23.Protection vs RDP Level . . . . .192
Table 24.RDP transition and its effects . . . . .194
Table 25.Effect of low-power modes on the embedded flash memory . . . . .198
Table 26.Flash interrupt request . . . . .206
Table 27.Register map and reset value table . . . . .249
Table 28.List of preferred terms . . . . .254
Table 29.RSS API addresses . . . . .258
Table 30.Summary of flash protected areas access rights . . . . .261
Table 31.PWR input/output signals connected to package pins or balls . . . . .270
Table 32.PWR internal input/output signals . . . . .271
Table 33.Supply configuration control . . . . .275
Table 34.Low-power mode summary . . . . .296
Table 35.PDDS_Dn low-power mode control . . . . .300
Table 36.Low-power exit mode flags . . . . .302
Table 37.CSleep mode . . . . .312
Table 38.CStop mode . . . . .313
Table 39.DStop mode overview . . . . .314
Table 40.DStop mode . . . . .315
Table 41.Stop mode operation . . . . .316
Table 42.Stop mode hold control . . . . .317
Table 43.Wakeup hold behavior and associated flags . . . . .319
Table 44.Stop mode . . . . .319
Table 45.DStandby mode . . . . .321
Table 46.Standby and Stop flags . . . . .323
Table 47.Standby mode . . . . .323
Table 48.Low-power modes monitoring pin overview . . . . .324
Table 49.GPIO state according to CPU and domain state . . . . .324
Table 50.Power control register map and reset values . . . . .338
Table 51.BDMA and DMAMUX2 initialization sequence (DMAMUX2_INIT) . . . . .346
Table 52.LPUART1 Initial programming (LPUART1_INIT) . . . . .348
Table 53.LPUART1 start programming (LPUART1_Start) . . . . .348
Table 54.RCC input/output signals connected to package pins or balls . . . . .352
Table 55.RCC internal input/output signals . . . . .353
Table 56.Reset distribution summary . . . . .356
Table 57.Reset source identification (RCC_RSR) . . . . .359
Table 58.Boot enable Function . . . . .363
Table 59.Ratio between clock timer and pclk . . . . .379
Table 60.STOPWUCK and STOPKERWUCK description. . . . .380
Table 61.HSIKERON and CSIKERON behavior . . . . .380
Table 62.Kernel clock distribution overview. . . . .382
Table 63.System states overview . . . . .399
Table 64.Peripheral clock enabling for D1 and D2 peripherals . . . . .405
Table 65.Peripheral clock enabling for D3 peripherals . . . . .406
Table 66.Domain bus clock enabling for D1 peripherals . . . . .409
Table 67.Domain bus clock enabling for D3 peripherals . . . . .410
Table 68.Interrupt sources and control . . . . .413
Table 69.RCC_RSR address offset and reset value . . . . .481
Table 70.RCC_AHB3ENR address offset and reset value . . . . .484
Table 71.RCC_AHB1ENR address offset and reset value . . . . .487
Table 72.RCC_AHB2ENR address offset and reset value . . . . .489
Table 73.RCC_AHB4ENR address offset and reset value . . . . .492
Table 74.RCC_APB3ENR address offset and reset value . . . . .495
Table 75.RCC_APB1ENR address offset and reset value . . . . .496
Table 76.RCC_APB1ENR address offset and reset value . . . . .500
Table 77.RCC_APB2ENR address offset and reset value . . . . .502
Table 78.RCC_APB4ENR address offset and reset value . . . . .505
Table 79.RCC_AHB3LPENR address offset and reset value . . . . .508
Table 80.RCC_AHB1LPENR address offset and reset value . . . . .510
Table 81.RCC_AHB2LPENR address offset and reset value . . . . .512
Table 82.RCC_AHB4LPENR address offset and reset value . . . . .514
Table 83.RCC_APB3LPENR address offset and reset value . . . . .517
Table 84.RCC_APB1LLPENR address offset and reset value . . . . .518
Table 85.RCC_APB1HLPENR address offset and reset value . . . . .522
Table 86.RCC_APB2LPENR address offset and reset value . . . . .524
Table 87.RCC_APB4LPENR address offset and reset value . . . . .527
Table 88.RCC register map and reset values . . . . .530
Table 89.CRS features . . . . .542
Table 90.CRS internal input/output signals . . . . .543
Table 91.Effect of low-power modes on CRS . . . . .547
Table 92.Interrupt control bits . . . . .547
Table 93.CRS register map and reset values . . . . .552
Table 94.HSEM internal input/output signals. . . . .555
Table 95.Authorized AHB bus master IDs . . . . .560
Table 96.HSEM register map and reset values . . . . .566
Table 97.Port bit configuration table . . . . .570
Table 98.GPIO register map and reset values . . . . .584
Table 99.SYSCFG register map and reset values. . . . .611
Table 100.Peripherals interconnect matrix (D2 domain) . . . . .615
Table 101.Peripherals interconnect matrix (D3 domain) . . . . .616
Table 102.Peripherals interconnect matrix details . . . . .617
Table 103.EXTI wakeup inputs . . . . .634
Table 104.EXTI pending requests clear inputs . . . . .637
Table 105.MDMA . . . . .639
Table 106.DMAMUX1, DMA1 and DMA2 connections . . . . .641
Table 107.DMAMUX2 and BDMA connections . . . . .646
Table 108.MDMA internal input/output signals . . . . .651
Table 109.MDMA interrupt requests . . . . .657
Table 110.MDMA register map and reset values . . . . .673
Table 111.DMA internal input/output signals . . . . .676
Table 112.Source and destination address . . . . .678
Table 113.Source and destination address registers in double-buffer mode (DBM = 1) . . . . .684
Table 114.Packing/unpacking and endian behavior (bit PINC = MINC = 1) . . . . .685
Table 115.Restriction on NDT versus PSIZE and MSIZE . . . . .685
Table 116.FIFO threshold configurations . . . . .688
Table 117.Possible DMA configurations . . . . .692
Table 118.DMA interrupt requests . . . . .694
Table 119.DMA register map and reset values . . . . .704
Table 120.BDMA implementation . . . . .709
Table 121.BDMA internal input/output signals . . . . .710
Table 122.Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .716
Table 123.BDMA interrupt requests . . . . .718
Table 124.BDMA register map and reset values . . . . .728
Table 125.DMAMUX1 and DMAMUX2 instantiation . . . . .732
Table 126.DMAMUX1: assignment of multiplexer inputs to resources . . . . .733
Table 127.DMAMUX1: assignment of multiplexer inputs to resources . . . . .734
Table 128.DMAMUX1: assignment of trigger inputs to resources . . . . .735
Table 129.DMAMUX1: assignment of synchronization inputs to resources . . . . .735
Table 130.DMAMUX2: assignment of multiplexer inputs to resources . . . . .736
Table 131.DMAMUX2: assignment of trigger inputs to resources . . . . .736
Table 132.DMAMUX2: assignment of synchronization inputs to resources . . . . .737
Table 133.DMAMUX signals . . . . .739
Table 134.DMAMUX interrupts . . . . .743
Table 135.DMAMUX register map and reset values . . . . .752
Table 136.DMA2D internal input/output signals . . . . .756
Table 137.Supported color mode in input . . . . .757
Table 138.Data order in memory . . . . .758
Table 139.Alpha mode configuration . . . . .759
Table 140.Supported CLUT color mode . . . . .760
Table 141.CLUT data order in memory . . . . .760
Table 142.Supported color mode in output . . . . .761
Table 143.Data order in memory . . . . .761
Table 144.Standard data order in memory . . . . .762
Table 145.Output FIFO byte reordering steps . . . . .763
Table 146.MCU order in memory . . . . .768
Table 147.DMA2D interrupt requests . . . . .769
Table 148.DMA2D register map and reset values . . . . .786
Table 149.NVIC1 (CPU1) and NVIC2 (CPU2) . . . . .789
Table 150.EXTI Event input configurations and register control . . . . .799
Table 151.Configurable Event input Asynchronous Edge detector reset . . . . .801
Table 152.EXTI Event input mapping . . . . .806
Table 153.Masking functionality . . . . .808
Table 154.Asynchronous interrupt/event controller register map and reset values . . . . .827
Table 155.CRC internal input/output signals . . . . .831
Table 156.CRC register map and reset values . . . . .836
Table 157.FMC pins . . . . .840
Table 158.FMC bank mapping options . . . . .843
Table 159.NOR/PSRAM bank selection . . . . .843
Table 160.NOR/PSRAM External memory address . . . . .843
Table 161.NAND memory mapping and timing registers. . . . .844
Table 162.NAND bank selection . . . . .844
Table 163.SDRAM bank selection. . . . .844
Table 164.SDRAM address mapping . . . . .845
Table 165.SDRAM address mapping with 8-bit data bus width. . . . .845
Table 166.SDRAM address mapping with 16-bit data bus width. . . . .846
Table 167.SDRAM address mapping with 32-bit data bus width. . . . .847
Table 168.Programmable NOR/PSRAM access parameters . . . . .849
Table 169.Non-multiplexed I/O NOR flash memory. . . . .849
Table 170.16-bit multiplexed I/O NOR flash memory . . . . .850
Table 171.Non-multiplexed I/Os PSRAM/SRAM . . . . .850
Table 172.16-Bit multiplexed I/O PSRAM . . . . .850
Table 173.NOR flash/PSRAM: Example of supported memories
and transactions . . . . .		851
Table 174.FMC_BCRx bitfields (mode 1) . . . . .854
Table 175.FMC_BTRx bitfields (mode 1) . . . . .855
Table 176.FMC_BCRx bitfields (mode A) . . . . .857
Table 177.FMC_BTRx bitfields (mode A) . . . . .858
Table 178.FMC_BWTRx bitfields (mode A). . . . .858
Table 179.FMC_BCRx bitfields (mode 2/B). . . . .860
Table 180.FMC_BTRx bitfields (mode 2/B). . . . .861
Table 181.FMC_BWTRx bitfields (mode 2/B) . . . . .861
Table 182.FMC_BCRx bitfields (mode C) . . . . .863
Table 183.FMC_BTRx bitfields (mode C) . . . . .864
Table 184.FMC_BWTRx bitfields (mode C). . . . .864
Table 185.FMC_BCRx bitfields (mode D) . . . . .866
Table 186.FMC_BTRx bitfields (mode D) . . . . .866
Table 187.FMC_BWTRx bitfields (mode D). . . . .867
Table 188.FMC_BCRx bitfields (Muxed mode) . . . . .869
Table 189.FMC_BTRx bitfields (Muxed mode) . . . . .869
Table 190.FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .875
Table 191.FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .875
Table 192.FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .876
Table 193.FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .877
Table 194.Programmable NAND flash access parameters . . . . .887
Table 195.8-bit NAND flash memory . . . . .887
Table 196.16-bit NAND flash memory . . . . .888
Table 197.Supported memories and transactions . . . . .888
Table 198.ECC result relevant bits . . . . .898
Table 199.SDRAM signals. . . . .899
Table 200.FMC register map . . . . .916
Table 201.QUADSPI internal signals. . . . .920
Table 202.QUADSPI pins . . . . .920
Table 203.QUADSPI interrupt requests. . . . .934
Table 204.QUADSPI register map and reset values . . . . .946
Table 205.DLYB internal input/output signals . . . . .948
Table 206.Delay block control . . . . .948
Table 207.DLYB register map and reset values . . . . .951
Table 208.ADC features . . . . .954
Table 209.ADC input/output pins . . . . .956
Table 210.ADC internal input/output signals . . . . .956
Table 211.ADC interconnection . . . . .957
Table 212.Configuring the trigger polarity for regular external triggers . . . . .977
Table 213.Configuring the trigger polarity for injected external triggers . . . . .977
Table 214.ADC1, ADC2 and ADC3 - External triggers for regular channels . . . . .978
Table 215.ADC1, ADC2 and ADC3 - External triggers for injected channels . . . . .979
Table 216.TSAR timings depending on resolution . . . . .991
Table 217.Offset computation versus data resolution . . . . .994
Table 218.16-bit data formats . . . . .997
Table 219.Numerical examples for 16-bit format (bold indicates saturation) . . . . .997
Table 220.Analog watchdog channel selection . . . . .1006
Table 221.Analog watchdog 1,2,3 comparison . . . . .1007
Table 222.Oversampler operating modes summary . . . . .1014
Table 223.ADC interrupts per each ADC . . . . .1033
Table 224.DELAY bits versus ADC resolution . . . . .1071
Table 225.ADC global register map . . . . .1073
Table 226.ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC) . . . . .1073
Table 227.ADC register map and reset values (master and slave ADC common registers) offset =0x300) . . . . .1076
Table 228.DAC features . . . . .1078
Table 229.DAC input/output pins . . . . .1080
Table 230.DAC internal input/output signals . . . . .1080
Table 231.DAC interconnection . . . . .1081
Table 232.Sample and refresh timings . . . . .1088
Table 233.Channel output modes summary . . . . .1089
Table 234.Effect of low-power modes on DAC . . . . .1095
Table 235.DAC interrupts . . . . .1096
Table 236.DAC register map and reset values . . . . .1112
Table 237.VREF buffer modes . . . . .1114
Table 238.VREFBUF register map and reset values . . . . .1116
Table 239.COMP input/output internal signals . . . . .1119
Table 240.COMP input/output pins . . . . .1119
Table 241.COMP1_OUT assignment to GPIOs . . . . .1122
Table 242.COMP2_OUT assignment to GPIOs . . . . .1122
Table 243.Comparator behavior in the low-power modes . . . . .1124
Table 244.Interrupt control bits . . . . .1124
Table 245.Interrupt control bits . . . . .1125
Table 246.COMP register map and reset values . . . . .1132
Table 247.Operational amplifier possible connections . . . . .1134
Table 248.Operating modes and calibration . . . . .1141
Table 249.Effect of low-power modes on the OPAMP . . . . .1143
Table 250.OPAMP register map and reset values . . . . .1150
Table 251.DFSDM1 implementation . . . . .1153
Table 252.DFSDM external pins . . . . .1155
Table 253.DFSDM internal signals . . . . .1155
Table 254.DFSDM triggers connection . . . . .1155
Table 255.DFSDM break connection. . . . .1156
Table 256.Filter maximum output resolution (peak data values from filter output) for some FOSR values . . . . .1171
Table 257.Integrator maximum output resolution (peak data values from integrator output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . . .1172
Table 258.DFSDM interrupt requests . . . . .1180
Table 259.DFSDM register map and reset values. . . . .1200
Table 260.DCMI input/output pins . . . . .1211
Table 261.DCMI internal input/output signals . . . . .1211
Table 262.Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .1213
Table 263.Positioning of captured data bytes in 32-bit words (10-bit width) . . . . .1213
Table 264.Positioning of captured data bytes in 32-bit words (12-bit width) . . . . .1213
Table 265.Positioning of captured data bytes in 32-bit words (14-bit width) . . . . .1214
Table 266.Data storage in monochrome progressive video format . . . . .1219
Table 267.Data storage in RGB progressive video format . . . . .1220
Table 268.Data storage in YCbCr progressive video format . . . . .1220
Table 269.Data storage in YCbCr progressive video format - Y extraction mode . . . . .1221
Table 270.DCMI interrupts. . . . .1221
Table 271.DCMI register map and reset values . . . . .1231
Table 272.LTDC external pins . . . . .1234
Table 273.LTDC internal signals . . . . .1235
Table 274.Clock domain for each register . . . . .1235
Table 275.LTDC register access and update durations . . . . .1236
Table 276.Pixel data mapping versus color format . . . . .1240
Table 277.LTDC interrupt requests . . . . .1244
Table 278.LTDC register map and reset values . . . . .1261
Table 279.DSI pins . . . . .1266
Table 280.DSI internal input/output signals . . . . .1267
Table 281.Location of color components in the LTDC interface . . . . .1270
Table 282.Multiplicity of the payload size in pixels for each data type . . . . .1271
Table 283.Contention detection timeout counters configuration . . . . .1283
Table 284.List of events of different categories of the PRESP_TO counter . . . . .1284
Table 285.PRESP_TO counter configuration . . . . .1287
Table 286.Frame requirement configuration registers. . . . .1299
Table 287.RGB components . . . . .1301
Table 288.Slew-rate and delay tuning . . . . .1303
Table 289.Custom lane configuration . . . . .1304
Table 290.Custom timing parameters . . . . .1304
Table 291.HS2LP and LP2HS values . . . . .1305
Table 292.DSI Wrapper interrupt requests . . . . .1308
Table 293.Error causes and recovery . . . . .1309
Table 294.DSI register map and reset values . . . . .1375
Table 295.JPEG internal signals . . . . .1382
Table 296.JPEG codec interrupt requests . . . . .1386
Table 297.JPEG codec register map and reset values . . . . .1399
Table 298.RNG internal input/output signals . . . . .1402
Table 299.RNG interrupt requests . . . . .1409
Table 300.RNG register map and reset map. . . . .1412
Table 301.CRYP internal input/output signals. . . . .1416
Table 302.Counter mode initialization vector. . . . .1440
Table 303.GCM last block definition . . . . .1443
Table 304.GCM mode IV registers initialization. . . . .1443
Table 305.CCM mode IV registers initialization. . . . .1450
Table 306.DES/TDES data swapping example . . . . .1454
Table 307.AES data swapping example . . . . .1455
Table 308.Key endianness in CRYP_KxR/LR registers (AES 128/192/256-bit keys) . . . . .1457
Table 309.Key endianness in CRYP_KxR/LR registers (DES K1 and TDES K1/2/3) . . . . .1458
Table 310.Initialization vector endianness in CRYP_IVx(L/R)R registers (AES) . . . . .1458
Table 311.Initialization vector endianness in CRYP_IVx(L/R)R registers (DES/TDES) . . . . .1458
Table 312.Cryptographic processor configuration for memory-to-peripheral DMA transfers . . . . .1459
Table 313.Cryptographic processor configuration for peripheral-to-memory DMA transfers . . . . .1460
Table 314.CRYP interrupt requests. . . . .1462
Table 315.Processing latency for ECB, CBC and CTR. . . . .1463
Table 316.Processing time (in clock cycle) for GCM and CCM per 128-bit block . . . . .1463
Table 317.CRYP register map and reset values . . . . .1477
Table 318.HASH internal input/output signals . . . . .1482
Table 319.Hash processor outputs . . . . .1485
Table 320.HASH interrupt requests. . . . .1492
Table 321.Processing time (in clock cycle) . . . . .1492
Table 322.HASH register map and reset values . . . . .1500
Table 323.HRTIM Input/output summary. . . . .1506
Table 324.Timer resolution and min. PWM frequency for \( f_{HRTIM} = 400 \) MHz . . . . .1508
Table 325.Period and Compare registers min and max values . . . . .1510
Table 326.Timer operating modes. . . . .1511
Table 327.Events mapping across Timer A to E . . . . .1516
Table 328.Deadtime resolution and max absolute values . . . . .1524
Table 329.External events mapping and associated features . . . . .1531
Table 330.Output set/reset latency and jitter vs external event operating mode. . . . .1532
Table 331.Filtering signals mapping per timer . . . . .1535
Table 332.Windowing signals mapping per timer (EEFLTR[3:0] = 1111) . . . . .1537
Table 333.HRTIM preloadable control registers and associated update sources . . . . .1546
Table 334.Update enable inputs and sources . . . . .1547
Table 335.Master timer update event propagation . . . . .1549
Table 336.TIMx update event propagation . . . . .1549
Table 337.Reset events able to generate an update. . . . .1550
Table 338.Update event propagation for a timer reset . . . . .1551
Table 339.Output state programming, x= A..E, y = 1 or 2 . . . . .1552
Table 340.Timer output programming for burst mode . . . . .1555
Table 341.Burst mode clock sources from general purpose timer. . . . .1557
Table 342.Fault inputs . . . . .1565
Table 343.Sampling rate and filter length vs FLTFxF[3:0] and clock setting . . . . .1566
Table 344.Effect of sync event vs timer operating modes . . . . .1571
Table 345.HRTIM interrupt summary . . . . .1577
Table 346.HRTIM DMA request summary. . . . .1578
Table 347.RTIM global register map . . . . .1668
Table 348.HRTIM Register map and reset values: Master timer. . . . .1668
Table 349.HRTIM Register map and reset values: TIMx (x= A..E) . . . . .1670
Table 350.HRTIM Register map and reset values: Common functions. . . . .1674
Table 351.Behavior of timer outputs versus BRK/BRK2 inputs. . . . .1718
Table 352.Counting direction versus encoder signals . . . . .1725
Table 353.TIMx internal trigger connection . . . . .1742
Table 354.Output control bits for complementary OCx and OCxN channels with break feature . . .1756
Table 355.TIM1 register map and reset values . . . . .1776
Table 356.TIM8 register map and reset values . . . . .1778
Table 357.Counting direction versus encoder signals . . . . .1814
Table 358.TIMx internal trigger connection . . . . .1832
Table 359.Output control bit for standard OCx channels . . . . .1843
Table 360.TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . .1855
Table 361.TIMx internal trigger connection . . . . .1886
Table 362.Output control bit for standard OCx channels . . . . .1894
Table 363.TIM12 register map and reset values . . . . .1897
Table 364.Output control bit for standard OCx channels . . . . .1906
Table 365.TIM13/TIM14 register map and reset values . . . . .1909
Table 366.TIMx Internal trigger connection . . . . .1953
Table 367.Output control bits for complementary OCx and OCxN channels with break feature
(TIM15) . . . . .		1963
Table 368.TIM15 register map and reset values . . . . .1972
Table 369.Output control bits for complementary OCx and OCxN channels with break feature
(TIM16/17) . . . . .		1984
Table 370.TIM16/TIM17 register map and reset values . . . . .1995
Table 371.TIMx register map and reset values . . . . .2009
Table 372.STM32H745/755 and STM32H747/757 LPTIM features . . . . .2011
Table 373.LPTIM input/output pins . . . . .2013
Table 374.LPTIM internal signals . . . . .2013
Table 375.LPTIM1 external trigger connection . . . . .2013
Table 376.LPTIM2 external trigger connection . . . . .2014
Table 377.LPTIM3 external trigger connection . . . . .2014
Table 378.LPTIM4 external trigger connection . . . . .2014
Table 379.LPTIM5 external trigger connection . . . . .2015
Table 380.LPTIM1 input 1 connection . . . . .2015
Table 381.LPTIM1 input 2 connection . . . . .2015
Table 382.LPTIM2 input 1 connection . . . . .2015
Table 383.LPTIM2 input 2 connection . . . . .2016
Table 384.LPTIM3 input 1 connection . . . . .2016
Table 385.Prescaler division ratios . . . . .2017
Table 386.Encoder counting scenarios . . . . .2024
Table 387.Effect of low-power modes on the LPTIM . . . . .2025
Table 388.Interrupt events . . . . .2026
Table 389.LPTIM register map and reset values . . . . .2037
Table 390.WWDG internal input/output signals . . . . .2042
Table 391.WWDG register map and reset values . . . . .2046
Table 392.IWDG internal input/output signals . . . . .2048
Table 393.IWDG register map and reset values . . . . .2055
Table 394.RTC pins and internal signals . . . . .2060
Table 395.RTC pin PC13 configuration . . . . .2060
Table 396.RTC_OUT mapping . . . . .2061
Table 397.RTC functions over modes . . . . .2062
Table 398.Effect of low-power modes on RTC . . . . .2074
Table 399.Interrupt control bits . . . . .2075
Table 400.RTC register map and reset values . . . . .2100
Table 401.STM32H745/755 and STM32H747/757 I2C implementation . . . . .2103
Table 402.I2C input/output pins . . . . .2105
Table 403.I2C internal input/output signals . . . . .2105
Table 404.Comparison of analog vs. digital filters . . . . .2107
Table 405.I2C-SMBus specification data setup and hold times . . . . .2109
Table 406.I2C configuration. . . . .2114
Table 407.I2C-SMBus specification clock timings . . . . .2125
Table 408.Examples of timing settings for fI2CCLK = 8 MHz . . . . .2135
Table 409.Examples of timing settings for fI2CCLK = 16 MHz . . . . .2135
Table 410.Examples of timing settings for fI2CCLK = 48 MHz . . . . .2136
Table 411.SMBus timeout specifications . . . . .2138
Table 412.SMBus with PEC configuration . . . . .2139
Table 413.Examples of TIMEOUTA settings (max t T IMEOUT = 25 ms) . . . . .2141
Table 414.Examples of TIMEOUTB settings . . . . .2141
Table 415.Examples of TIMEOUTA settings (max t D LE = 50 µs) . . . . .2141
Table 416.Effect of low-power modes on the I2C . . . . .2152
Table 417.I2C interrupt requests . . . . .2153
Table 418.I2C register map and reset values . . . . .2168
Table 419.USART / LPUART features . . . . .2172
Table 420.Noise detection from sampled data . . . . .2187
Table 421.Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .2190
Table 422.Tolerance of the USART receiver when BRR[3:0] is different from 0000. . . . .2191
Table 423.USART frame formats . . . . .2196
Table 424.Effect of low-power modes on the USART . . . . .2219
Table 425.USART interrupt requests. . . . .2220
Table 426.USART register map and reset values . . . . .2255
Table 427.USART / LPUART features . . . . .2259
Table 428.Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32.768 kHz . . . . .2270
Table 429.Error calculation for programmed baud rates at fCK = 100 MHz . . . . .2271
Table 430.Tolerance of the LPUART receiver. . . . .2272
Table 432.Effect of low-power modes on the LPUART . . . . .2283
Table 433.LPUART interrupt requests. . . . .2284
Table 434.LPUART register map and reset values . . . . .2308
Table 435.STM32H745/55/47/57xx SPI features . . . . .2311
Table 436.SPI wakeup and interrupt requests. . . . .2343
Table 437.Bitfields usable in PCM/I2S mode . . . . .2346
Table 438.WS and CK level before SPI/I2S is enabled when AFCNTR = 1 . . . . .2354
Table 439.Serial data line swapping . . . . .2354
Table 440.CLKGEN programming examples for usual I2S frequencies . . . . .2359
Table 441.I2S interrupt requests . . . . .2368
Table 442.SPI register map and reset values . . . . .2387
Table 443.STM32H743/753/745/755/747/757 SAI features . . . . .2390
Table 444.SAI internal input/output signals . . . . .2392
Table 445.SAI input/output pins. . . . .2392
Table 446.External synchronization selection . . . . .2394
Table 447.MCLK_x activation conditions. . . . .2400
Table 448.Clock generator programming examples . . . . .2403
Table 449.TDM settings. . . . .2410
Table 450.TDM frame configuration examples . . . . .2412
Table 451.SOPD pattern . . . . .2416
Table 452.Parity bit calculation . . . . .2416
Table 453.Audio sampling frequency versus symbol rates . . . . .2417
Table 454.SAI interrupt sources . . . . .2426
Table 455.SAI register map and reset values . . . . .2456
Table 456.SPDIFRX internal input/output signals . . . . .2459
Table 457.SPDIFRX pins . . . . .2459
Table 458.Transition sequence for preamble . . . . .2465
Table 459.Minimum spdifrx_ker_ck frequency versus audio sampling rate . . . . .2475
Table 460.Bit field property versus SPDIFRX state . . . . .2477
Table 461.SPDIFRX interface register map and reset values . . . . .2489
Table 462.SWPMI input/output signals connected to package pins or balls . . . . .2492
Table 463.SWPMI internal input/output signals . . . . .2493
Table 464.Effect of low-power modes on SWPMI . . . . .2507
Table 465.Interrupt control bits . . . . .2508
Table 466.Buffer modes selection for transmission/reception . . . . .2510
Table 467.SWPMI register map and reset values . . . . .2517
Table 468.MDOIS input/output signals connected to package pins or balls . . . . .2519
Table 469.MDOIS internal input/output signals . . . . .2519
Table 470.Interrupt control bits . . . . .2524
Table 471.MDOIS register map and reset values . . . . .2529
Table 472.SDMMC features . . . . .2531
Table 473.SDMMC operation modes SD and SDIO . . . . .2534
Table 474.SDMMC operation modes e•MMC . . . . .2534
Table 475.SDMMC internal input/output signals . . . . .2535
Table 476.SDMMC pins . . . . .2536
Table 477.SDMMC Command and data phase selection . . . . .2537
Table 478.Command token format . . . . .2543
Table 479.Short response with CRC token format . . . . .2544
Table 480.Short response without CRC token format . . . . .2544
Table 481.Long response with CRC token format . . . . .2544
Table 482.Specific Commands overview . . . . .2545
Table 483.Command path status flags . . . . .2546
Table 484.Command path error handling . . . . .2546
Table 485.Data token format . . . . .2554
Table 486.Data path status flags and clear bits . . . . .2554
Table 487.Data path error handling . . . . .2556
Table 488.Data FIFO access . . . . .2557
Table 489.Transmit FIFO status flags . . . . .2558
Table 490.Receive FIFO status flags . . . . .2559
Table 491.SDMMC connections to MDMA . . . . .2563
Table 492.AHB and SDMMC_CK clock frequency relation . . . . .2563
Table 493.SDIO special operation control . . . . .2564
Table 494.4-bit mode Start, interrupt, and CRC-status Signaling detection . . . . .2568
Table 495.CMD12 use cases . . . . .2572
Table 496.SDMMC interrupts . . . . .2586
Table 497.Response type and SDMMC_RESPxR registers . . . . .2594
Table 498.SDMMC register map . . . . .2609
Table 499.CAN subsystem I/O signals . . . . .2612
Table 500.CAN subsystem I/O pins . . . . .2613
Table 501.Main features . . . . .2615
Table 502.DLC coding in FDCAN . . . . .2620
Table 503.Example of filter configuration for Rx buffers . . . . .2632
Table 504.Example of filter configuration for Debug messages . . . . .2633
Table 505.Possible configurations for frame transmission . . . . .2633
Table 506.Tx buffer/FIFO - queue element size . . . . .2634
Table 507.First byte of level 1 reference message . . . . .2644
Table 508.First four bytes of level 2 reference message . . . . .2645
Table 509.First four bytes of level 0 reference message . . . . .2645
Table 510.TUR configuration example . . . . .2646
Table 511.System matrix, Node A . . . . .2651
Table 512.Trigger list, Node A . . . . .2652
Table 513.Number of data bytes transmitted with a reference message. . . . .2659
Table 514.Rx buffer and FIFO element . . . . .2666
Table 515.Rx buffer and FIFO element description . . . . .2666
Table 516.Tx buffer and FIFO element . . . . .2668
Table 517.Tx buffer element description . . . . .2668
Table 518.Tx Event FIFO element. . . . .2670
Table 519.Tx Event FIFO element description . . . . .2670
Table 520.Standard message ID filter element . . . . .2671
Table 521.Standard message ID filter element field description . . . . .2672
Table 522.Extended message ID filter element. . . . .2673
Table 523.Extended message ID filter element field description . . . . .2673
Table 524.Trigger memory element. . . . .2674
Table 525.Trigger memory element description . . . . .2674
Table 526.FDCAN register map and reset values . . . . .2713
Table 527.FDCAN TT register map and reset values . . . . .2735
Table 528.CCU register map and reset values . . . . .2741
Table 529.OTG_HS speeds supported . . . . .2744
Table 530.OTG_HS implementation . . . . .2746
Table 531.OTG_FS input/output pins . . . . .2748
Table 532.OTG_HS input/output pins . . . . .2748
Table 533.OTG_HS input/output signals . . . . .2748
Table 534.Compatibility of STM32 low power modes with the OTG . . . . .2761
Table 535.Core global control and status registers (CSRs). . . . .2769
Table 536.Host-mode control and status registers (CSRs) . . . . .2770
Table 537.Device-mode control and status registers . . . . .2772
Table 538.Data FIFO (DFIFO) access register map . . . . .2774
Table 539.Power and clock gating control and status registers . . . . .2774
Table 540.TRDT values . . . . .2783
Table 541.Minimum duration for soft disconnect . . . . .2828
Table 542.OTG_HS register map and reset values. . . . .2856
Table 543.Ethernet peripheral pins . . . . .2935
Table 544.Ethernet internal input/output signals . . . . .2936
Table 545.Priority scheme for Tx DMA and Rx DMA. . . . .2945
Table 546.Double VLAN processing features in Tx path. . . . .2951
Table 547.Double VLAN processing in Rx path . . . . .2952
Table 548.VLAN insertion or replacement based on VLTi bit . . . . .2953
Table 549.Destination address filtering . . . . .2956
Table 550.Source address filtering . . . . .2957
Table 551.VLAN match status . . . . .2958
Table 552.Ordinary clock: PTP messages for snapshot . . . . .2961
Table 553.End-to-end transparent clock: PTP messages for snapshot . . . . .2962
Table 554.Peer-to-peer transparent clock: PTP messages for snapshot. . . . .2963
Table 555.Egress and ingress latency for PHY interfaces . . . . .2966
Table 556.Minimum PTP clock frequency example. . . . .2967
Table 557.Message format defined in IEEE 1588-2008 . . . . .2968
Table 558.Message format defined in IEEE 1588-2008 . . . . .2968
Table 559.IPv6-UDP PTP packet fields required for control and status . . . . .2969
Table 560.Ethernet PTP packet fields required for control and status . . . . .2970
Table 561.Timestamp Snapshot Dependency on ETH_MACTSCR bits . . . . .2972
Table 562.PTP message generation criteria . . . . .2978
Table 563.Common PTP message header fields . . . . .2980
Table 564.MAC Transmit PTP mode and one-step timestamping operation. . . . .2983
Table 565.Transmit checksum offload engine functions for different packet types . . . . .2988
Table 566.Receive checksum offload engine functions for different packet types . . . . .2990
Table 567.TSO: TCP and IP header fields . . . . .2994
Table 568.Pause packet fields. . . . .2999
Table 569.Tx MAC flow control . . . . .3000
Table 570.Rx MAC flow control . . . . .3000
Table 571.Size of the maximum receive packet . . . . .3003
Table 572.MCD clock selection . . . . .3006
Table 573.MDIO Clause 45 frame structure . . . . .3007
Table 574.MDIO Clause 22 frame structure . . . . .3008
Table 575.Remote wakeup packet filter register . . . . .3019
Table 576.Description of the remote wakeup filter fields . . . . .3020
Table 577.Remote wakeup packet and PMT interrupt generation . . . . .3021
Table 578.Transfer complete interrupt behavior . . . . .3029
Table 579.TDES0 normal descriptor (read format) . . . . .3049
Table 580.TDES1 normal descriptor (read format) . . . . .3050
Table 581.TDES2 normal descriptor (read format) . . . . .3050
Table 582.TDES3 normal descriptor (read format) . . . . .3051
Table 583.TDES0 normal descriptor (write-back format). . . . .3054
Table 584.TDES1 normal descriptor (write-back format). . . . .3054
Table 585.TDES2 normal descriptor (write-back format). . . . .3055
Table 586.TDES3 normal descriptor (write-back format). . . . .3055
Table 587.TDES0 context descriptor. . . . .3058
Table 588.TDES1 context descriptor. . . . .3059
Table 589.TDES2 context descriptor. . . . .3059
Table 590.TDES3 context descriptor. . . . .3059
Table 591.RDES0 normal descriptor (read format) . . . . .3063
Table 592.RDES1 normal descriptor (read format) . . . . .3063
Table 593.RDES2 normal descriptor (read format) . . . . .3063
Table 594.RDES3 normal descriptor (read format) . . . . .3064
Table 595.RDES0 normal descriptor (write-back format) . . . . .3065
Table 596.RDES1 normal descriptor (write-back format) . . . . .3066
Table 597.RDES2 normal descriptor (write-back format) . . . . .3068
Table 598.RDES3 normal descriptor (write-back format) . . . . .3069
Table 599.RDES0 context descriptor . . . . .3072
Table 600.RDES1 context descriptor . . . . .3073
Table 601.RDES2 context descriptor . . . . .3073
Table 602.RDES3 context descriptor . . . . .3073
Table 603.ETH_DMA common register map and reset values . . . . .3097
Table 604.ETH_DMA_CH register map and reset values . . . . .3097
Table 605.ETH_MTL register map and reset values . . . . .3110
Table 606.Giant Packet Status based on S2KP and JE Bits . . . . .3116
Table 607.Packet Length based on the CST and ACS bits . . . . .3116
Table 608.Ethernet MAC register map and reset values . . . . .3197
Table 609.HDMI pin . . . . .3209
Table 610.HDMI-CEC internal input/output signals . . . . .3209
Table 611.Error handling timing parameters . . . . .3215
Table 612.TXERR timing parameters . . . . .3216
Table 613.HDMI-CEC interrupts . . . . .3217
Table 614.HDMI-CEC register map and reset values . . . . .3225
Table 615.JTAG/Serial-wire debug port pins . . . . .3228
Table 616.Trace port pins . . . . .3229
Table 617.Serial-wire trace port pins . . . . .3229
Table 618.Trigger pins . . . . .3229
Table 619.Packet request . . . . .3233
Table 620.ACK response . . . . .3233
Table 621.Data transfer . . . . .3234
Table 622.JTAG-DP data registers . . . . .3236
Table 623.Debug port registers . . . . .3238
Table 624.MEM-AP registers . . . . .3248
Table 625.System ROM table 1 . . . . .3252
Table 626.System ROM table 2 . . . . .3253
Table 627.System ROM table 1 register map and reset values . . . . .3259
Table 628.System ROM table 2 register map and reset values . . . . .3260
Table 629.TSG register map and reset values . . . . .3268
Table 630.System CTI inputs . . . . .3271
Table 631.System CTI outputs . . . . .3271
Table 632.Cortex-M7 CTI inputs . . . . .3271
Table 633.Cortex-M7 CTI outputs . . . . .3272
Table 634.Cortex-M4 CTI inputs . . . . .3272
Table 635.Cortex-M4 CTI outputs . . . . .3272
Table 636.CTI register map and reset values . . . . .3289
Table 637.CSTF register map and reset values . . . . .3300
Table 638.ETF register map and reset values . . . . .3321
Table 639.TPIU register map and reset values . . . . .3339
Table 640.SWO register map and reset values . . . . .3351
Table 641.SWTF register map and reset values . . . . .3362
Table 642.DBGMCU register map and reset values . . . . .3374
Table 643.Cortex-M7 processor ROM table . . . . .3376
Table 644.Cortex-M7 PPB ROM table . . . . .3376
Table 645.Cortex-M7 processor ROM table register map and reset values . . . . .3382
Table 646.Cortex-M7 PPB ROM table register map and reset values . . . . .3387
Table 647.Cortex-M7 DWT register map and reset values . . . . .3399
Table 648.Cortex-M7 ITM register map and reset values . . . . .3409
Table 649.Cortex-M7 FPB register map and reset values . . . . .3416
Table 650.Cortex-M7 ETM register map and reset values . . . . .3446
Table 651.Cortex-M4 ROM table . . . . .3451
Table 652.Cortex-M4 ROM table register map and reset values . . . . .3457
Table 653.Cortex-M4 DWT register map and reset values . . . . .3468
Table 654.Cortex-M4 ITM register map and reset values . . . . .3478
Table 655.Cortex-M4 FPB register map and reset values . . . . .3485
Table 656.Cortex-M4 ETM register map and reset values . . . . .3505
Table 657.Document revision history . . . . .3514

List of figures

Figure 1.System architecture for STM32H745/55/47/57xx devices . . . . .109
Figure 2.AXI interconnect . . . . .115
Figure 3.RAM ECC controller implementation schematic. . . . .147
Figure 4.Connection between RAM ECC controller and RAMECC monitoring unit . . . . .147
Figure 5.FLASH block diagram . . . . .155
Figure 6.Detailed FLASH architecture . . . . .157
Figure 7.Embedded flash memory organization . . . . .158
Figure 8.Embedded flash memory usage . . . . .161
Figure 9.FLASH protection mechanisms . . . . .162
Figure 10.FLASH read pipeline architecture . . . . .165
Figure 11.FLASH write pipeline architecture . . . . .168
Figure 12.Flash bank swapping sequence . . . . .177
Figure 13.RDP protection transition scheme . . . . .193
Figure 14.Example of protected region overlapping . . . . .195
Figure 15.Flash memory areas and services in Standard and Secure access modes . . . . .256
Figure 16.Bootloader state machine in Secure access mode . . . . .257
Figure 17.Core access to flash memory areas . . . . .260
Figure 18.ART accelerator - block schematic . . . . .263
Figure 19.Instruction fetch from cache . . . . .265
Figure 20.Power control block diagram . . . . .269
Figure 21.Power supply overview . . . . .273
Figure 22.System supply configurations . . . . .274
Figure 23.Device startup with V CORE supplied from voltage regulator . . . . .277
Figure 24.Device startup with V CORE supplied directly from
SMPS step-down converter . . . . .		278
Figure 25.Device startup with V CORE supplied in Bypass mode
from external regulator . . . . .		279
Figure 26.Backup domain . . . . .284
Figure 27.USB supply configurations . . . . .285
Figure 28.DSI supply configuration. . . . .286
Figure 29.Power-on reset/power-down reset waveform . . . . .287
Figure 30.BOR thresholds . . . . .288
Figure 31.PVD thresholds . . . . .289
Figure 32.AVD thresholds . . . . .290
Figure 33.VBAT thresholds . . . . .291
Figure 34.Temperature thresholds . . . . .292
Figure 35.V CORE overvoltage protection. . . . .293
Figure 36.Switching V CORE from VOS1 to VOS0 . . . . .298
Figure 37.V CORE voltage scaling versus system power modes . . . . .299
Figure 38.Power control modes detailed state diagram . . . . .301
Figure 39.Dynamic voltage scaling in Run mode . . . . .304
Figure 40.Dynamic voltage scaling behavior with D1,
D2 and system in Stop mode . . . . .		305
Figure 41.Dynamic Voltage Scaling D1, D2, system Standby mode . . . . .307
Figure 42.Dynamic voltage scaling behavior with D1 and D2 in DStandby mode and
D3 in autonomous mode. . . . .		309
Figure 43.Stop mode hold mechanism state diagram . . . . .318
Figure 44.EXTI, RCC and PWR interconnections . . . . .340
Figure 45.Timing diagram of SRAM4-to-LPUART1 transfer with BDMA and D3 domain in Autonomous mode . . . . .344
Figure 46.BDMA and DMAMUX2 interconnection . . . . .346
Figure 47.Timing diagram of LPUART1 transmission with D3 domain in Autonomous mode . . . . .349
Figure 48.RCC Block diagram . . . . .352
Figure 49.System reset circuit . . . . .356
Figure 50.Boot sequences versus system states . . . . .362
Figure 51.Top-level clock tree. . . . .365
Figure 52.HSE/LSE clock source . . . . .366
Figure 53.PLL block diagram . . . . .373
Figure 54.PLLs Initialization Flowchart . . . . .376
Figure 55.Core and bus clock generation . . . . .378
Figure 56.Kernel clock distribution for SAIs and DFSDM1 . . . . .385
Figure 57.Kernel clock distribution for SPIs and SPI/I2S . . . . .386
Figure 58.Kernel clock distribution for I2Cs . . . . .387
Figure 59.Kernel clock distribution for UARTs, USARTs and LPUART1 . . . . .387
Figure 60.Kernel clock distribution for DSI and LTDC . . . . .388
Figure 61.Kernel clock distribution for SDMMC, QUADSPI and FMC . . . . .388
Figure 62.Kernel clock distribution For USB (2) . . . . .389
Figure 63.Kernel clock distribution for Ethernet . . . . .390
Figure 64.Kernel clock distribution For ADCs, SWPMI, RNG and FDCAN (2) . . . . .391
Figure 65.Kernel clock distribution for LPTIMs and HDMI-CEC (2) . . . . .392
Figure 66.Peripheral allocation example. . . . .396
Figure 67.Kernel Clock switching . . . . .401
Figure 68.Peripheral kernel clock enable logic details . . . . .404
Figure 69.Bus clock enable logic . . . . .411
Figure 70.RCC mapping overview . . . . .414
Figure 71.CRS block diagram. . . . .543
Figure 72.CRS counter behavior . . . . .545
Figure 73.HSEM block diagram . . . . .555
Figure 74.Procedure state diagram . . . . .556
Figure 75.Interrupt state diagram . . . . .559
Figure 76.Basic structure of an I/O port bit . . . . .569
Figure 77.Basic structure of a 5-Volt tolerant I/O port bit . . . . .569
Figure 78.Input floating / pull up / pull down configurations . . . . .574
Figure 79.Output configuration . . . . .575
Figure 80.Alternate function configuration . . . . .576
Figure 81.High impedance-analog configuration . . . . .576
Figure 82.Analog inputs connected to ADC inputs . . . . .577
Figure 83.MDMA block diagram . . . . .651
Figure 84.DMA block diagram . . . . .676
Figure 85.Peripheral-to-memory mode . . . . .680
Figure 86.Memory-to-peripheral mode . . . . .681
Figure 87.Memory-to-memory mode . . . . .682
Figure 88.FIFO structure. . . . .687
Figure 89.BDMA block diagram . . . . .709
Figure 90.DMAMUX block diagram . . . . .738
Figure 91.Synchronization mode of the DMAMUX request line multiplexer channel . . . . .741
Figure 92.Event generation of the DMA request line multiplexer channel . . . . .741
Figure 93.DMA2D block diagram . . . . .756
Figure 94.Intel 8080 16-bit mode (RGB565). . . . .762
Figure 95.Intel 8080 18/24-bit mode (RGB888) . . . . .763
Figure 96.EXTI block diagram . . . . .798
Figure 97.Configurable event triggering logic CPU wakeup . . . . .800
Figure 98.Configurable event triggering logic Any wakeup . . . . .802
Figure 99.Direct event triggering logic CPU Wakeup . . . . .803
Figure 100.Direct event triggering logic Any Wakeup . . . . .804
Figure 101.D3 domain Pending request clear logic . . . . .805
Figure 102.CRC calculation unit block diagram . . . . .831
Figure 103.FMC block diagram. . . . .839
Figure 104.FMC memory banks (default mapping) . . . . .842
Figure 105.Mode 1 read access waveforms . . . . .853
Figure 106.Mode 1 write access waveforms. . . . .854
Figure 107.Mode A read access waveforms. . . . .856
Figure 108.Mode A write access waveforms . . . . .857
Figure 109.Mode 2 and mode B read access waveforms. . . . .859
Figure 110.Mode 2 write access waveforms. . . . .859
Figure 111.Mode B write access waveforms . . . . .860
Figure 112.Mode C read access waveforms . . . . .862
Figure 113.Mode C write access waveforms . . . . .862
Figure 114.Mode D read access waveforms . . . . .865
Figure 115.Mode D write access waveforms . . . . .865
Figure 116.Muxed read access waveforms . . . . .868
Figure 117.Muxed write access waveforms . . . . .868
Figure 118.Asynchronous wait during a read access waveforms. . . . .871
Figure 119.Asynchronous wait during a write access waveforms. . . . .871
Figure 120.Wait configuration waveforms. . . . .874
Figure 121.Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM). . . . .874
Figure 122.Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . .876
Figure 123.NAND flash controller waveforms for common memory access. . . . .890
Figure 124.Access to non 'CE don't care' NAND-flash. . . . .891
Figure 125.Burst write SDRAM access waveforms . . . . .901
Figure 126.Burst read SDRAM access . . . . .902
Figure 127.Logic diagram of Read access with RBURST bit set (CAS=2, RPIPE=0) . . . . .903
Figure 128.Read access crossing row boundary . . . . .905
Figure 129.Write access crossing row boundary . . . . .905
Figure 130.Self-refresh mode . . . . .908
Figure 131.Power-down mode . . . . .909
Figure 132.QUADSPI block diagram when dual-flash mode is disabled . . . . .919
Figure 133.QUADSPI block diagram when dual-flash mode is enabled. . . . .920
Figure 134.Example of read command in quad-SPI mode . . . . .921
Figure 135.Example of a DDR command in quad-SPI mode . . . . .924
Figure 136.NCS when CKMODE = 0 (T = CLK period) . . . . .932
Figure 137.NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .933
Figure 138.NCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . .933
Figure 139.NCS when CKMODE = 1 with an abort (T = CLK period). . . . .934
Figure 140.DLYB block diagram. . . . .947
Figure 141.ADC block diagram . . . . .955
Figure 142.ADC Clock scheme . . . . .958
Figure 143.ADC1 connectivity . . . . .959
Figure 144.ADC2 connectivity . . . . .960
Figure 145.ADC3 connectivity . . . . .961
Figure 146.ADC calibration . . . . .965
Figure 147.Updating the ADC offset calibration factor . . . . .965
Figure 148.Mixing single-ended and differential channels . . . . .966
Figure 149.Enabling / Disabling the ADC . . . . .969
Figure 150.Analog to digital conversion time . . . . .975
Figure 151.Stopping ongoing regular conversions . . . . .976
Figure 152.Stopping ongoing regular and injected conversions . . . . .976
Figure 153.Triggers are shared between ADC master and ADC slave . . . . .978
Figure 154.Injected conversion latency . . . . .981
Figure 155.Example of JSQR queue of context (sequence change) . . . . .984
Figure 156.Example of JSQR queue of context (trigger change) . . . . .985
Figure 157.Example of JSQR queue of context with overflow before conversion . . . . .985
Figure 158.Example of JSQR queue of context with overflow during conversion . . . . .986
Figure 159.Example of JSQR queue of context with empty queue (case JQM=0). . . . .986
Figure 160.Example of JSQR queue of context with empty queue (case JQM=1). . . . .987
Figure 161.Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion. . . . .		987
Figure 162.Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . .		988
Figure 163.Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs outside an ongoing conversion . . . . .		988
Figure 164.Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . .989
Figure 165.Flushing JSQR queue of context by setting ADDIS=1 (JQM=0). . . . .989
Figure 166.Flushing JSQR queue of context by setting ADDIS=1 (JQM=1). . . . .990
Figure 167.Single conversions of a sequence, software trigger . . . . .992
Figure 168.Continuous conversion of a sequence, software trigger. . . . .992
Figure 169.Single conversions of a sequence, hardware trigger . . . . .993
Figure 170.Continuous conversions of a sequence, hardware trigger . . . . .993
Figure 171.Right alignment (offset disabled, unsigned value) . . . . .995
Figure 172.Right alignment (offset enabled, signed value) . . . . .995
Figure 173.Left alignment (offset disabled, unsigned value) . . . . .996
Figure 174.Left alignment (offset enabled, signed value) . . . . .996
Figure 175.Example of overrun (OVRMOD = 0). . . . .999
Figure 176.Example of overrun (OVRMOD = 1). . . . .999
Figure 177.AUTDLY=1, regular conversion in continuous mode, software trigger . . . . .1003
Figure 178.AUTDLY=1, regular HW conversions interrupted by injected conversions
(DISCEN=0; JDISCEN=0) . . . . .		1003
Figure 179.AUTDLY=1, regular HW conversions interrupted by injected conversions.
(DISCEN=1, JDISCEN=1) . . . . .		1004
Figure 180.AUTDLY=1, regular continuous conversions interrupted by injected conversions . . . . .1005
Figure 181.AUTDLY=1 in auto- injected mode (JAUTO=1) . . . . .1005
Figure 182.Analog watchdog guarded area . . . . .1006
Figure 183.ADC y _AWD x _OUT signal generation (on all regular channels). . . . .1008
Figure 184.ADC y _AWD x _OUT signal generation (AWD x flag not cleared by SW) . . . . .1008
Figure 185.ADC y _AWD x _OUT signal generation (on a single regular channel) . . . . .1009
Figure 186.ADC y _AWD x _OUT signal generation (on all injected channels) . . . . .1009
Figure 187.16-bit result oversampling with 10-bits right shift and rounding . . . . .1010
Figure 188.Triggered regular oversampling mode (TROVS bit = 1). . . . .1011
Figure 189.Regular oversampling modes (4x ratio) . . . . .1012
Figure 190.Regular and injected oversampling modes used simultaneously . . . . .1013
Figure 191.Triggered regular oversampling with injection . . . . .1013
Figure 192.Oversampling in auto-injected mode . . . . .1014
Figure 193. Dual ADC block diagram (1) . . . . .1016
Figure 194. Injected simultaneous mode on 4 channels: dual ADC mode . . . . .1017
Figure 195. Regular simultaneous mode on 16 channels: dual ADC mode . . . . .1019
Figure 196. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode . . . . .1020
Figure 197. Interleaved mode on 1 channel in single conversion mode: dual ADC mode . . . . .1021
Figure 198. Interleaved conversion with injection . . . . .1021
Figure 199. Alternate trigger: injected group of each ADC . . . . .1022
Figure 200. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . .1023
Figure 201. Alternate + regular simultaneous . . . . .1024
Figure 202. Case of trigger occurring during injected conversion . . . . .1024
Figure 203. Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . .1025
Figure 204. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first . . . . .		1025
Figure 205. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . .		1025
Figure 206. DMA Requests in regular simultaneous mode when DAMDF=0b00 . . . . .1026
Figure 207. DMA requests in regular simultaneous mode when DAMDF=0b10 . . . . .1027
Figure 208. DMA requests in interleaved mode when DAMDF=0b10 . . . . .1027
Figure 209. Temperature sensor channel block diagram . . . . .1029
Figure 210. VBAT channel block diagram . . . . .1031
Figure 211. VREFINT channel block diagram . . . . .1031
Figure 212. Dual-channel DAC block diagram . . . . .1079
Figure 213. Data registers in single DAC channel mode . . . . .1082
Figure 214. Data registers in dual DAC channel mode . . . . .1082
Figure 215. Timing diagram for conversion with trigger disabled TEN = 0 . . . . .1083
Figure 216. DAC LFSR register calculation algorithm . . . . .1085
Figure 217. DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .1085
Figure 218. DAC triangle wave generation . . . . .1086
Figure 219. DAC conversion (SW trigger enabled) with triangle wave generation . . . . .1086
Figure 220. DAC Sample and hold mode phase diagram . . . . .1089
Figure 221. Comparator functional block diagram . . . . .1118
Figure 222. Comparator hysteresis . . . . .1121
Figure 223. Comparator output blanking . . . . .1121
Figure 224. Output redirection . . . . .1123
Figure 225. Scaler block diagram . . . . .1125
Figure 226. Standalone mode: external gain setting mode . . . . .1135
Figure 227. Follower configuration . . . . .1136
Figure 228. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . .1137
Figure 229. PGA mode, internal gain setting (x2/x4/x8/x16),
inverting input used for filtering . . . . .		1138
Figure 230. PGA mode, non-inverting gain setting (x2/x4/x8/x16)
or inverting gain setting (x-1/x-3/x-7/x-15) . . . . .		1139
Figure 231. Example configuration . . . . .1139
Figure 232. PGA mode, non-inverting gain setting (x2/x4/x8/x16) or inverting gain
setting (x-1/x-3/x-7/x-15) with filtering . . . . .		1140
Figure 233. Example configuration . . . . .1140
Figure 234. Single DFSDM block diagram . . . . .1154
Figure 235. Input channel pins redirection . . . . .1158
Figure 236. Channel transceiver timing diagrams . . . . .1161
Figure 237. Clock absence timing diagram for SPI . . . . .1162
Figure 238. Clock absence timing diagram for Manchester coding . . . . .1163
Figure 239. First conversion for Manchester coding (Manchester synchronization) . . . . .1165
Figure 240. DFSDM_CHyDATINR registers operation modes and assignment . . . . .1169
Figure 241. Example: Sinc3 filter response . . . . .1171
Figure 242. DCMI block diagram . . . . .1211
Figure 243. DCMI signal waveforms . . . . .1212
Figure 244. Timing diagram . . . . .1214
Figure 245. Frame capture waveforms in snapshot mode. . . . .1216
Figure 246. Frame capture waveforms in continuous grab mode . . . . .1217
Figure 247. Coordinates and size of the window after cropping . . . . .1217
Figure 248. Data capture waveforms. . . . .1218
Figure 249. Pixel raster scan order . . . . .1219
Figure 250. LTDC block diagram . . . . .1234
Figure 251. LTDC synchronous timings. . . . .1237
Figure 252. Layer window programmable parameters . . . . .1240
Figure 253. Blending two layers with background . . . . .1242
Figure 254. Interrupt events. . . . .1244
Figure 255. DSI block diagram . . . . .1266
Figure 256. DSI Host architecture . . . . .1268
Figure 257. Flow to update the LTDC interface configuration using shadow registers . . . . .1273
Figure 258. Immediate update procedure . . . . .1274
Figure 259. Configuration update during the transmission of a frame . . . . .1274
Figure 260. Adapted command mode usage flow . . . . .1276
Figure 261. 24 bpp APB pixel to byte organization . . . . .1280
Figure 262. 18 bpp APB pixel to byte organization . . . . .1281
Figure 263. 16 bpp APB pixel to byte organization . . . . .1281
Figure 264. 12 bpp APB pixel to byte organization . . . . .1282
Figure 265. 8 bpp APB pixel to byte organization . . . . .1282
Figure 266. Timing of PRESP_TO after a bus-turn-around. . . . .1285
Figure 267. Timing of PRESP_TO after a read request (HS or LP). . . . .1286
Figure 268. Timing of PRESP_TO after a write request (HS or LP) . . . . .1287
Figure 269. Effect of prep mode at 1 . . . . .1288
Figure 270. Command transmission periods within the image area . . . . .1289
Figure 271. Transmission of commands on the last line of a frame. . . . .1290
Figure 272. LPSIZE for non-burst with sync pulses. . . . .1291
Figure 273. LPSIZE for burst or non-burst with sync events . . . . .1291
Figure 274. VLPSIZE for non-burst with sync pulses . . . . .1293
Figure 275. VLPSIZE for non-burst with sync events . . . . .1293
Figure 276. VLPSIZE for burst mode. . . . .1293
Figure 277. Location of LPSIZE and VLPSIZE in the image area . . . . .1295
Figure 278. Clock lane and data lane in HS . . . . .1296
Figure 279. Clock lane in HS and data lanes in LP . . . . .1297
Figure 280. Clock lane and data lane in LP . . . . .1297
Figure 281. Command transmission by the generic interface . . . . .1298
Figure 282. Vertical color bar mode. . . . .1300
Figure 283. Horizontal color bar mode. . . . .1300
Figure 284. RGB888 BER testing pattern . . . . .1301
Figure 285. Vertical pattern (103x15) . . . . .1302
Figure 286. Horizontal pattern (103x15) . . . . .1302
Figure 287. PLL block diagram . . . . .1306
Figure 288. Error sources . . . . .1309
Figure 289. Video packet transmission configuration flow diagram. . . . .1320
Figure 290. Programming sequence to send a test pattern. . . . .1322
Figure 291. Frame configuration registers . . . . .1323
Figure 292. JPEG codec block diagram . . . . .1382
Figure 293. RNG block diagram . . . . .1402
Figure 294. Entropy source model . . . . .1403
Figure 295. RNG initialization overview . . . . .1406
Figure 296. CRYPT block diagram . . . . .1415
Figure 297. AES-ECB mode overview . . . . .1418
Figure 298. AES-CBC mode overview . . . . .1419
Figure 299. AES-CTR mode overview . . . . .1420
Figure 300. AES-GCM mode overview . . . . .1421
Figure 301. AES-GMAC mode overview . . . . .1421
Figure 302. AES-CCM mode overview . . . . .1422
Figure 303. Example of suspend mode management . . . . .1427
Figure 304. DES/TDES-ECB mode encryption . . . . .1428
Figure 305. DES/TDES-ECB mode decryption . . . . .1429
Figure 306. DES/TDES-CBC mode encryption . . . . .1430
Figure 307. DES/TDES-CBC mode decryption . . . . .1431
Figure 308. AES-ECB mode encryption . . . . .1433
Figure 309. AES-ECB mode decryption . . . . .1434
Figure 310. AES-CBC mode encryption . . . . .1435
Figure 311. AES-CBC mode decryption . . . . .1436
Figure 312. Message construction for the Counter mode . . . . .1438
Figure 313. AES-CTR mode encryption . . . . .1439
Figure 314. AES-CTR mode decryption . . . . .1440
Figure 315. Message construction for the Galois/counter mode . . . . .1442
Figure 316. Message construction for the Galois Message Authentication Code mode . . . . .1447
Figure 317. Message construction for the Counter with CBC-MAC mode . . . . .1448
Figure 318. 64-bit block construction according to the data type (IN FIFO) . . . . .1455
Figure 319. 128-bit block construction according to the data type . . . . .1457
Figure 320. HASH block diagram . . . . .1481
Figure 321. Message data swapping feature . . . . .1483
Figure 322. HASH suspend/resume mechanism . . . . .1489
Figure 323. High-resolution timer block diagram . . . . .1505
Figure 324. Timer A..E overview . . . . .1510
Figure 325. Continuous timer operation . . . . .1511
Figure 326. Single-shot timer operation . . . . .1512
Figure 327. Timer reset resynchronization (prescaling ratio above 32) . . . . .1513
Figure 328. Repetition rate vs HRTIM_REPxR content in continuous mode . . . . .1514
Figure 329. Repetition counter behavior in single-shot mode . . . . .1515
Figure 330. Compare events action on outputs: set on compare 1, reset on compare 2 . . . . .1516
Figure 331. Timing unit capture circuitry . . . . .1518
Figure 332. Auto-delayed overview (Compare 2 only) . . . . .1519
Figure 333. Auto-delayed compare . . . . .1520
Figure 334. Push-pull mode block diagram . . . . .1522
Figure 335. Push-pull mode example . . . . .1523
Figure 336. Complementary outputs with deadtime insertion . . . . .1523
Figure 337. Deadtime insertion vs deadtime sign (1 indicates negative deadtime) . . . . .1524
Figure 338. Complementary outputs for low pulse width (SDTRx = SDTFx = 0) . . . . .1525
Figure 339. Complementary outputs for low pulse width (SDTRx = SDTFx = 1) . . . . .1525
Figure 340. Complementary outputs for low pulse width (SDTRx = 0, SDTFx = 1) . . . . .1525
Figure 341. Complementary outputs for low pulse width (SDTRx = 1, SDTFx=0) . . . . .1526
Figure 342. Master timer overview . . . . .1527
Figure 343. External event conditioning overview (1 channel represented) . . . . .1530
Figure 344. Latency to external events falling edge (counter reset and output set) . . . . .1533
Figure 345. Latency to external events (output reset on external event). . . . .1533
Figure 346. Event blanking mode . . . . .1534
Figure 347. Event postpone mode. . . . .1534
Figure 348. External trigger blanking with edge-sensitive trigger . . . . .1536
Figure 349. External trigger blanking, level sensitive triggering. . . . .1536
Figure 350. Event windowing mode. . . . .1537
Figure 351. External trigger windowing with edge-sensitive trigger. . . . .1538
Figure 352. External trigger windowing, level sensitive triggering . . . . .1538
Figure 353. Delayed Idle mode entry. . . . .1540
Figure 354. Burst mode and delayed protection priorities (DIDL = 0) . . . . .1541
Figure 355. Burst mode and delayed protection priorities (DIDL = 1) . . . . .1542
Figure 356. Balanced Idle protection example. . . . .1543
Figure 357. Output management overview . . . . .1553
Figure 358. HRTIM output states and transitions . . . . .1553
Figure 359. Burst mode operation example. . . . .1555
Figure 360. Burst mode trigger on external event . . . . .1557
Figure 361. Delayed burst mode entry with deadtime enabled and IDLESx = 1 . . . . .1559
Figure 362. Delayed Burst mode entry during deadtime . . . . .1560
Figure 363. Burst mode exit when the deadtime generator is enabled . . . . .1561
Figure 364. Burst mode emulation example . . . . .1563
Figure 365. Carrier frequency signal insertion . . . . .1563
Figure 366. HRTIM outputs with Chopper mode enabled . . . . .1564
Figure 367. Fault protection circuitry (FAULT1 fully represented, FAULT2..5 partially). . . . .1565
Figure 368. Fault signal filtering (FLTxF[3:0]= 0010: \( f_{\text{SAMPLING}} = f_{\text{HRTIM}} \) , N = 4) . . . . .1566
Figure 369. Auxiliary outputs . . . . .1568
Figure 370. Auxiliary and main outputs during burst mode (DIDLx = 0) . . . . .1569
Figure 371. Deadtime distortion on auxiliary output when exiting burst mode. . . . .1569
Figure 372. Counter behavior in synchronized start mode . . . . .1573
Figure 373. ADC trigger selection overview . . . . .1574
Figure 374. Combining several updates on a single hrtim_dac_trgx output . . . . .1575
Figure 375. DMA burst overview . . . . .1579
Figure 376. Burst DMA operation flowchart . . . . .1580
Figure 377. Registers update following DMA burst transfer . . . . .1581
Figure 378. Buck converter topology . . . . .1583
Figure 379. Dual Buck converter management . . . . .1584
Figure 380. Synchronous rectification depending on output current . . . . .1584
Figure 381. Buck with synchronous rectification . . . . .1585
Figure 382. 3-phase interleaved buck converter . . . . .1586
Figure 383. 3-phase interleaved buck converter control . . . . .1587
Figure 384. Transition mode PFC . . . . .1587
Figure 385. Transition mode PFC waveforms . . . . .1588
Figure 386. Advanced-control timer block diagram . . . . .1678
Figure 387. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1680
Figure 388. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1680
Figure 389. Counter timing diagram, internal clock divided by 1 . . . . .1682
Figure 390. Counter timing diagram, internal clock divided by 2 . . . . .1682
Figure 391. Counter timing diagram, internal clock divided by 4 . . . . .1683
Figure 392. Counter timing diagram, internal clock divided by N. . . . .1683
Figure 393. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .1684
Figure 394. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .1684
Figure 395. Counter timing diagram, internal clock divided by 1 . . . . .1686
Figure 396. Counter timing diagram, internal clock divided by 2 . . . . .1686
Figure 397. Counter timing diagram, internal clock divided by 4 . . . . .1687
Figure 398. Counter timing diagram, internal clock divided by N . . . . .1687
Figure 399. Counter timing diagram, update event when repetition counter is not used. . . . .1688
Figure 400. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .1689
Figure 401. Counter timing diagram, internal clock divided by 2 . . . . .1690
Figure 402. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .1690
Figure 403. Counter timing diagram, internal clock divided by N . . . . .1691
Figure 404. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .1691
Figure 405. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .1692
Figure 406. Update rate examples depending on mode and TIMx_RCR register settings . . . . .1693
Figure 407. External trigger input block . . . . .1694
Figure 408. TIM1/TIM8 ETR input circuitry . . . . .1694
Figure 409. Control circuit in normal mode, internal clock divided by 1 . . . . .1695
Figure 410. TI2 external clock connection example. . . . .1696
Figure 411. Control circuit in external clock mode 1 . . . . .1697
Figure 412. External trigger input block . . . . .1697
Figure 413. Control circuit in external clock mode 2 . . . . .1698
Figure 414. Capture/compare channel (example: channel 1 input stage) . . . . .1699
Figure 415. Capture/compare channel 1 main circuit . . . . .1699
Figure 416. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .1700
Figure 417. Output stage of capture/compare channel (channel 4). . . . .1700
Figure 418. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .1701
Figure 419. PWM input mode timing . . . . .1703
Figure 420. Output compare mode, toggle on OC1 . . . . .1705
Figure 421. Edge-aligned PWM waveforms (ARR=8) . . . . .1706
Figure 422. Center-aligned PWM waveforms (ARR=8). . . . .1707
Figure 423. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1709
Figure 424. Combined PWM mode on channel 1 and 3 . . . . .1710
Figure 425. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .1711
Figure 426. Complementary output with dead-time insertion . . . . .1712
Figure 427. Dead-time waveforms with delay greater than the negative pulse . . . . .1712
Figure 428. Dead-time waveforms with delay greater than the positive pulse. . . . .1713
Figure 429. Break and Break2 circuitry overview . . . . .1715
Figure 430. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .1717
Figure 431. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .1718
Figure 432. PWM output state following BRK assertion (OSSI=0) . . . . .1719
Figure 433. Output redirection . . . . .1719
Figure 434. Clearing TIMx_OCxREF . . . . .1720
Figure 435. 6-step generation, COM example (OSSR=1) . . . . .1721
Figure 436. Example of one pulse mode. . . . .1722
Figure 437. Retriggerable one pulse mode . . . . .1724
Figure 438. Example of counter operation in encoder interface mode. . . . .1725
Figure 439. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .1726
Figure 440. Measuring time interval between edges on 3 signals . . . . .1727
Figure 441. Example of Hall sensor interface . . . . .1729
Figure 442. Control circuit in reset mode . . . . .1730
Figure 443. Control circuit in Gated mode . . . . .1731
Figure 444. Control circuit in trigger mode . . . . .1732
Figure 445. Control circuit in external clock mode 2 + trigger mode . . . . .1733
Figure 446. General-purpose timer block diagram . . . . .1782
Figure 447. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1784
Figure 448. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1784
Figure 449. Counter timing diagram, internal clock divided by 1 . . . . .1785
Figure 450. Counter timing diagram, internal clock divided by 2 . . . . .1786
Figure 451. Counter timing diagram, internal clock divided by 4 . . . . .1786
Figure 452. Counter timing diagram, internal clock divided by N . . . . .1787
Figure 453. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .1787
Figure 454. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .1788
Figure 455. Counter timing diagram, internal clock divided by 1 . . . . .1789
Figure 456. Counter timing diagram, internal clock divided by 2 . . . . .1789
Figure 457. Counter timing diagram, internal clock divided by 4 . . . . .1790
Figure 458. Counter timing diagram, internal clock divided by N . . . . .1790
Figure 459. Counter timing diagram, Update event . . . . .1791
Figure 460. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .1792
Figure 461. Counter timing diagram, internal clock divided by 2 . . . . .1793
Figure 462. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .1793
Figure 463. Counter timing diagram, internal clock divided by N . . . . .1794
Figure 464. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .1794
Figure 465. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .1795
Figure 466. Control circuit in normal mode, internal clock divided by 1 . . . . .1796
Figure 467. TI2 external clock connection example. . . . .1796
Figure 468. Control circuit in external clock mode 1 . . . . .1797
Figure 469. External trigger input block . . . . .1798
Figure 470. Control circuit in external clock mode 2 . . . . .1799
Figure 471. Capture/Compare channel (example: channel 1 input stage) . . . . .1799
Figure 472. Capture/Compare channel 1 main circuit . . . . .1800
Figure 473. Output stage of Capture/Compare channel (channel 1). . . . .1800
Figure 474. PWM input mode timing . . . . .1802
Figure 475. Output compare mode, toggle on OC1 . . . . .1804
Figure 476. Edge-aligned PWM waveforms (ARR=8). . . . .1805
Figure 477. Center-aligned PWM waveforms (ARR=8). . . . .1806
Figure 478. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1807
Figure 479. Combined PWM mode on channels 1 and 3 . . . . .1809
Figure 480. Clearing TIMx_OCxREF . . . . .1810
Figure 481. Example of one-pulse mode. . . . .1811
Figure 482. Retriggerable one-pulse mode. . . . .1813
Figure 483. Example of counter operation in encoder interface mode . . . . .1814
Figure 484. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .1815
Figure 485. Control circuit in reset mode . . . . .1816
Figure 486. Control circuit in gated mode . . . . .1817
Figure 487. Control circuit in trigger mode. . . . .1818
Figure 488. Control circuit in external clock mode 2 + trigger mode . . . . .1819
Figure 489. Master/Slave timer example . . . . .1819
Figure 490. Master/slave connection example with 1 channel only timers . . . . .1820
Figure 491. Gating TIM2 with OC1REF of TIM3 . . . . .1821
Figure 492. Gating TIM2 with Enable of TIM3 . . . . .1822
Figure 493. Triggering TIM2 with update of TIM3 . . . . .1822
Figure 494. Triggering TIM2 with Enable of TIM3 . . . . .1823
Figure 495. Triggering TIM3 and TIM2 with TIM3 TI1 input. . . . .1824
Figure 496. General-purpose timer block diagram (TIM12). . . . .1859
Figure 497. General-purpose timer block diagram (TIM13/TIM14) . . . . .1860
Figure 498. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1862
Figure 499. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1862
Figure 500.Counter timing diagram, internal clock divided by 1 . . . . .1863
Figure 501.Counter timing diagram, internal clock divided by 2 . . . . .1864
Figure 502.Counter timing diagram, internal clock divided by 4 . . . . .1864
Figure 503.Counter timing diagram, internal clock divided by N . . . . .1865
Figure 504.Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .1865
Figure 505.Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .1866
Figure 506.Control circuit in normal mode, internal clock divided by 1 . . . . .1867
Figure 507.TI2 external clock connection example. . . . .1867
Figure 508.Control circuit in external clock mode 1 . . . . .1868
Figure 509.Capture/compare channel (example: channel 1 input stage) . . . . .1869
Figure 510.Capture/compare channel 1 main circuit . . . . .1869
Figure 511.Output stage of capture/compare channel (channel 1). . . . .1870
Figure 512.PWM input mode timing . . . . .1872
Figure 513.Output compare mode, toggle on OC1. . . . .1874
Figure 514.Edge-aligned PWM waveforms (ARR=8) . . . . .1875
Figure 515.Combined PWM mode on channel 1 and 2 . . . . .1876
Figure 516.Example of one pulse mode. . . . .1877
Figure 517.Retriggerable one pulse mode . . . . .1878
Figure 518.Measuring time interval between edges on 2 signals . . . . .1879
Figure 519.Control circuit in reset mode . . . . .1880
Figure 520.Control circuit in gated mode . . . . .1881
Figure 521.Control circuit in trigger mode . . . . .1881
Figure 522.TIM15 block diagram . . . . .1913
Figure 523.TIM16/TIM17 block diagram . . . . .1914
Figure 524.Counter timing diagram with prescaler division change from 1 to 2 . . . . .1916
Figure 525.Counter timing diagram with prescaler division change from 1 to 4 . . . . .1916
Figure 526.Counter timing diagram, internal clock divided by 1 . . . . .1918
Figure 527.Counter timing diagram, internal clock divided by 2 . . . . .1918
Figure 528.Counter timing diagram, internal clock divided by 4 . . . . .1919
Figure 529.Counter timing diagram, internal clock divided by N . . . . .1919
Figure 530.Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .1920
Figure 531.Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .1920
Figure 532.Update rate examples depending on mode and TIMx_RCR register settings . . . . .1922
Figure 533.Control circuit in normal mode, internal clock divided by 1 . . . . .1923
Figure 534.TI2 external clock connection example. . . . .1923
Figure 535.Control circuit in external clock mode 1 . . . . .1924
Figure 536.Capture/compare channel (example: channel 1 input stage) . . . . .1925
Figure 537.Capture/compare channel 1 main circuit . . . . .1925
Figure 538.Output stage of capture/compare channel (channel 1). . . . .1926
Figure 539.Output stage of capture/compare channel (channel 2 for TIM15) . . . . .1926
Figure 540.PWM input mode timing . . . . .1928
Figure 541.Output compare mode, toggle on OC1. . . . .1930
Figure 542.Edge-aligned PWM waveforms (ARR=8) . . . . .1931
Figure 543.Combined PWM mode on channel 1 and 2 . . . . .1932
Figure 544.Complementary output with dead-time insertion. . . . .1933
Figure 545.Dead-time waveforms with delay greater than the negative pulse. . . . .1933
Figure 546.Dead-time waveforms with delay greater than the positive pulse. . . . .1934
Figure 547.Break circuitry overview . . . . .1936
Figure 548. Output behavior in response to a break . . . . .1938
Figure 549. 6-step generation, COM example (OSSR=1) . . . . .1939
Figure 550. Example of one pulse mode . . . . .1940
Figure 551. Retriggerable one pulse mode . . . . .1942
Figure 552. Measuring time interval between edges on 2 signals . . . . .1943
Figure 553. Control circuit in reset mode . . . . .1944
Figure 554. Control circuit in gated mode . . . . .1945
Figure 555. Control circuit in trigger mode . . . . .1946
Figure 556. Basic timer block diagram. . . . .1997
Figure 557. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1999
Figure 558. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1999
Figure 559. Counter timing diagram, internal clock divided by 1 . . . . .2000
Figure 560. Counter timing diagram, internal clock divided by 2 . . . . .2001
Figure 561. Counter timing diagram, internal clock divided by 4 . . . . .2001
Figure 562. Counter timing diagram, internal clock divided by N . . . . .2002
Figure 563. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .2002
Figure 564. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .2003
Figure 565. Control circuit in normal mode, internal clock divided by 1 . . . . .2004
Figure 566. Low-power timer block diagram (LPTIM1 and LPTIM2) . . . . .2011
Figure 567. Low-power timer block diagram (LPTIM3) . . . . .2012
Figure 568. Low-power timer block diagram (LPTIM4 and LPTIM5) . . . . .2012
Figure 569. Glitch filter timing diagram . . . . .2017
Figure 570. LPTIM output waveform, single counting mode configuration . . . . .2019
Figure 571. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set). . . . .2019
Figure 572. LPTIM output waveform, Continuous counting mode configuration . . . . .2020
Figure 573. Waveform generation . . . . .2021
Figure 574. Encoder mode counting sequence . . . . .2025
Figure 575. Watchdog high-level block diagram . . . . .2039
Figure 576. Watchdog block diagram . . . . .2042
Figure 577. Window watchdog timing diagram . . . . .2043
Figure 578. Independent watchdog block diagram . . . . .2047
Figure 579. RTC block overview . . . . .2057
Figure 580. Detailed RTC block diagram. . . . .2058
Figure 581. Tamper detection . . . . .2059
Figure 582. I2C block diagram . . . . .2104
Figure 583. I2C bus protocol . . . . .2106
Figure 584. Setup and hold timings . . . . .2108
Figure 585. I2C initialization flow . . . . .2111
Figure 586. Data reception . . . . .2112
Figure 587. Data transmission . . . . .2113
Figure 588. Slave initialization flow . . . . .2116
Figure 589. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0. . . . .2118
Figure 590. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1. . . . .2119
Figure 591. Transfer bus diagrams for I2C slave transmitter (mandatory events only). . . . .2120
Figure 592. Transfer sequence flow for slave receiver with NOSTRETCH = 0 . . . . .2121
Figure 593. Transfer sequence flow for slave receiver with NOSTRETCH = 1 . . . . .2122
Figure 594. Transfer bus diagrams for I2C slave receiver (mandatory events only). . . . .2122
Figure 595. Master clock generation . . . . .2124
Figure 596. Master initialization flow . . . . .2126
Figure 597. 10-bit address read access with HEAD10R = 0 . . . . .2126
Figure 598. 10-bit address read access with HEAD10R = 1 . . . . .2127
Figure 599. Transfer sequence flow for I2C master transmitter for N ≤ 255 bytes . . . . .2128
Figure 600. Transfer sequence flow for I2C master transmitter for N > 255 bytes . . . . .2129
Figure 601. Transfer bus diagrams for I2C master transmitter
(mandatory events only) . . . . .		2130
Figure 602. Transfer sequence flow for I2C master receiver for N ≤ 255 bytes . . . . .2132
Figure 603. Transfer sequence flow for I2C master receiver for N > 255 bytes . . . . .2133
Figure 604. Transfer bus diagrams for I2C master receiver
(mandatory events only) . . . . .		2134
Figure 605. Timeout intervals for t LOW:SEXT , t LOW:MEXT . . . . .2138
Figure 606. Transfer sequence flow for SMBus slave transmitter N bytes + PEC. . . . .2142
Figure 607. Transfer bus diagrams for SMBus slave transmitter (SBC = 1) . . . . .2142
Figure 608. Transfer sequence flow for SMBus slave receiver N bytes + PEC. . . . .2144
Figure 609. Bus transfer diagrams for SMBus slave receiver (SBC = 1). . . . .2145
Figure 610. Bus transfer diagrams for SMBus master transmitter . . . . .2146
Figure 611. Bus transfer diagrams for SMBus master receiver . . . . .2148
Figure 612. I2C interrupt mapping diagram . . . . .2154
Figure 613. USART block diagram . . . . .2173
Figure 614. Word length programming . . . . .2176
Figure 615. Configurable stop bits . . . . .2178
Figure 616. TC/TXE behavior when transmitting . . . . .2181
Figure 617. Start bit detection when oversampling by 16 or 8. . . . .2182
Figure 618. usart_ker_ck clock divider block diagram . . . . .2185
Figure 619. Data sampling when oversampling by 16 . . . . .2186
Figure 620. Data sampling when oversampling by 8 . . . . .2187
Figure 621. Mute mode using Idle line detection . . . . .2194
Figure 622. Mute mode using address mark detection . . . . .2195
Figure 623. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .2198
Figure 624. Break detection in LIN mode vs. Framing error detection. . . . .2199
Figure 625. USART example of synchronous master transmission. . . . .2200
Figure 626. USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . .		2200
Figure 627. USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . .		2201
Figure 628. USART data clock timing diagram in synchronous slave mode
(M bits = 00) . . . . .		2202
Figure 629. ISO 7816-3 asynchronous protocol . . . . .2204
Figure 630. Parity error detection using the 1.5 stop bits . . . . .2206
Figure 631. IrDA SIR ENDEC block diagram. . . . .2210
Figure 632. IrDA data modulation (3/16) - Normal mode. . . . .2210
Figure 633. Transmission using DMA . . . . .2212
Figure 634. Reception using DMA . . . . .2213
Figure 635. Hardware flow control between 2 USARTs . . . . .2213
Figure 636. RS232 RTS flow control . . . . .2214
Figure 637. RS232 CTS flow control . . . . .2215
Figure 638. Wake-up event verified (wake-up event = address match, FIFO disabled) . . . . .2218
Figure 639. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		2218
Figure 640. LPUART block diagram . . . . .2260
Figure 641. LPUART word length programming . . . . .2262
Figure 642. Configurable stop bits . . . . .2264
Figure 643. TC/TXE behavior when transmitting . . . . .2266
Figure 644. lpuart_ker_ck clock divider block diagram . . . . .2269
Figure 645. Mute mode using Idle line detection . . . . .2273
Figure 646. Mute mode using address mark detection . . . . .2274
Figure 647. Transmission using DMA . . . . .2276
Figure 648. Reception using DMA . . . . .2277
Figure 649. Hardware flow control between 2 LPUARTs . . . . .2278
Figure 650. RS232 RTS flow control . . . . .2278
Figure 651. RS232 CTS flow control . . . . .2279
Figure 652. Wake-up event verified (wake-up event = address match,
FIFO disabled) . . . . .		2282
Figure 653. Wake-up event not verified (wake-up event = address match,
FIFO disabled) . . . . .		2282
Figure 654. SPI2S block diagram . . . . .2312
Figure 655. Full-duplex single master/ single slave application . . . . .2314
Figure 656. Half-duplex single master/ single slave application . . . . .2315
Figure 657. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		2316
Figure 658. Master and three independent slaves at star topology . . . . .2317
Figure 659. Master and three slaves at circular (daisy chain) topology . . . . .2318
Figure 660. Multimaster application . . . . .2319
Figure 661. Scheme of SS control logic . . . . .2321
Figure 662. Data flow timing control (SSOE=1, SSOM=0, SSM=0) . . . . .2321
Figure 663. SS interleaving pulses between data (SSOE=1, SSOM=1,SSM=0). . . . .2322
Figure 664. Data clock timing diagram . . . . .2324
Figure 665. Data alignment when data size is not equal to 8-bit, 16-bit or 32-bit . . . . .2325
Figure 666. Packing data in FIFO for transmission and reception . . . . .2333
Figure 667. TI mode transfer . . . . .2335
Figure 668. Optional configurations of slave behavior at detection of underrun condition . . . . .2337
Figure 669. Low-power mode application example . . . . .2341
Figure 670. Waveform examples . . . . .2348
Figure 671. Master I2S Philips protocol waveforms (16/32-bit full accuracy) . . . . .2349
Figure 672. I2S Philips standard waveforms . . . . .2349
Figure 673. Master MSB Justified 16-bit or 32-bit full-accuracy length . . . . .2350
Figure 674. Master MSB justified 16 or 24-bit data length . . . . .2350
Figure 675. Slave MSB justified . . . . .2351
Figure 676. LSB justified 16 or 24-bit data length . . . . .2351
Figure 677. Master PCM when the frame length is equal the data length . . . . .2352
Figure 678. Master PCM standard waveforms (16 or 24-bit data length) . . . . .2352
Figure 679. Slave PCM waveforms . . . . .2353
Figure 680. Startup sequence, I2S Philips standard, master . . . . .2356
Figure 681. Startup sequence, I2S Philips standard, slave . . . . .2356
Figure 682. Stop sequence, I2S Philips standard, master . . . . .2357
Figure 683. I 2 S clock generator architecture . . . . .2358
Figure 684. Data Format . . . . .2360
Figure 685. Handling of underrun situation . . . . .2362
Figure 686. Handling of overrun situation . . . . .2363
Figure 687. Frame error detection, with FIXCH=0 . . . . .2364
Figure 688. Frame error detection, with FIXCH=1 . . . . .2364
Figure 689. SAI functional block diagram . . . . .2391
Figure 690. Audio frame . . . . .2395
Figure 691. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .2397
Figure 692. FS role is start of frame (FSDEF = 0) . . . . .2398
Figure 693. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .2399
Figure 694. First bit offset . . . . .2399
Figure 695. Audio block clock generator overview . . . . .2401
Figure 696. PDM typical connection and timing . . . . .2405
Figure 697. Detailed PDM interface block diagram . . . . .2406
Figure 698. Start-up sequence . . . . .2407
Figure 699. SAI_ADR format in TDM, 32-bit slot width . . . . .2408
Figure 700. SAI_ADR format in TDM, 16-bit slot width . . . . .2409
Figure 701. SAI_ADR format in TDM, 8-bit slot width . . . . .2410
Figure 702. AC'97 audio frame . . . . .2413
Figure 703. Example of typical AC'97 configuration on devices featuring at least
2 embedded SAIs (three external AC'97 decoders) . . . . .		2414
Figure 704. SPDIF format . . . . .2415
Figure 705. SAI_xDR register ordering . . . . .2416
Figure 706. Data companding hardware in an audio block in the SAI . . . . .2420
Figure 707. Tristate strategy on SD output line on an inactive slot . . . . .2421
Figure 708. Tristate on output data line in a protocol like I2S . . . . .2422
Figure 709. Overrun detection error . . . . .2423
Figure 710. FIFO underrun event . . . . .2423
Figure 711. SPDIFRX block diagram . . . . .2459
Figure 712. S/PDIF sub-frame format . . . . .2460
Figure 713. S/PDIF block format . . . . .2460
Figure 714. S/PDIF Preambles . . . . .2461
Figure 715. Channel coding example . . . . .2462
Figure 716. SPDIFRX decoder . . . . .2463
Figure 717. Noise filtering and edge detection . . . . .2463
Figure 718. Thresholds . . . . .2465
Figure 719. Synchronization flowchart . . . . .2467
Figure 720. Synchronization process scheduling . . . . .2468
Figure 721. SPDIFRX States . . . . .2469
Figure 722. SPDIFRX_FMTx_DR register format . . . . .2471
Figure 723. Channel/user data format . . . . .2472
Figure 724. S/PDIF overrun error when RXSTEO = 0 . . . . .2474
Figure 725. S/PDIF overrun error when RXSTEO = 1 . . . . .2475
Figure 726. SPDIFRX interface interrupt mapping diagram . . . . .2476
Figure 727. S1 signal coding . . . . .2490
Figure 728. S2 signal coding . . . . .2490
Figure 729. SWPMI block diagram . . . . .2492
Figure 730. SWP bus states . . . . .2495
Figure 731. SWP frame structure . . . . .2496
Figure 732. SWPMI No software buffer mode transmission . . . . .2497
Figure 733. SWPMI No software buffer mode transmission, consecutive frames . . . . .2498
Figure 734. SWPMI Multi software buffer mode transmission . . . . .2500
Figure 735. SWPMI No software buffer mode reception . . . . .2502
Figure 736. SWPMI single software buffer mode reception . . . . .2503
Figure 737. SWPMI Multi software buffer mode reception . . . . .2505
Figure 738. SWPMI single buffer mode reception with CRC error . . . . .2506
Figure 739. MDIOS block diagram . . . . .2519
Figure 740. MDIO protocol write frame waveform . . . . .2520
Figure 741. MDIO protocol read frame waveform . . . . .2520
Figure 742. SDMMC “no response” and “no data” operations . . . . .2532
Figure 743. SDMMC (multiple) block read operation . . . . .2532
Figure 744. SDMMC (multiple) block write operation . . . . .2533
Figure 745. SDMMC (sequential) stream read operation . . . . .2533
Figure 746. SDMMC (sequential) stream write operation . . . . .2533
Figure 747. SDMMC block diagram . . . . .2535
Figure 748. SDMMC Command and data phase relation . . . . .2537
Figure 749. Control unit . . . . .2539
Figure 750. Command/response path . . . . .2540
Figure 751. Command path state machine (CPSM) . . . . .2541
Figure 752. Data path . . . . .2547
Figure 753. DDR mode data packet clocking . . . . .2548
Figure 754. DDR mode CRC status / boot acknowledgment clocking . . . . .2548
Figure 755. Data path state machine (DPSM) . . . . .2549
Figure 756. CLKMUX unit . . . . .2560
Figure 757. Asynchronous interrupt generation . . . . .2565
Figure 758. Synchronous interrupt period data read . . . . .2565
Figure 759. Synchronous interrupt period data write . . . . .2566
Figure 760. Asynchronous interrupt period data read . . . . .2567
Figure 761. Asynchronous interrupt period data write . . . . .2567
Figure 762. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25 . . . . .2570
Figure 763. Clock stop with SDMMC_CK for DDR50, SDR50, SDR104 . . . . .2570
Figure 764. Read Wait with SDMMC_CK < 50 MHz . . . . .2571
Figure 765. Read Wait with SDMMC_CK > 50 MHz . . . . .2572
Figure 766. CMD12 stream timing . . . . .2574
Figure 767. CMD5 Sleep Awake procedure . . . . .2576
Figure 768. Normal boot mode operation . . . . .2578
Figure 769. Alternative boot mode operation . . . . .2579
Figure 770. Command response R1b busy signaling . . . . .2580
Figure 771. SDMMC state control . . . . .2581
Figure 772. Card cycle power / power up diagram . . . . .2582
Figure 773. CMD11 signal voltage switch sequence . . . . .2583
Figure 774. Voltage switch transceiver typical application . . . . .2585
Figure 775. CAN subsystem . . . . .2614
Figure 776. FDCAN block diagram . . . . .2616
Figure 777. Transceiver delay measurement . . . . .2621
Figure 778. Pin control in bus monitoring mode . . . . .2623
Figure 779. Pin control in loop back mode . . . . .2625
Figure 780. Message RAM configuration . . . . .2626
Figure 781. Standard message ID filter path . . . . .2629
Figure 782. Extended message ID filter path . . . . .2630
Figure 783. Example of mixed configuration dedicated Tx buffers / Tx FIFO . . . . .2636
Figure 784. Example of mixed configuration dedicated Tx buffers / Tx queue . . . . .2636
Figure 785. Bit timing . . . . .2638
Figure 786. Bypass operation . . . . .2640
Figure 787. FSM calibration . . . . .2641
Figure 788. Cycle time and global time synchronization . . . . .2656
Figure 789. TTCAN level 0 and level 2 drift compensation . . . . .2657
Figure 790. Level 0 schedule synchronization state machine . . . . .2664
Figure 791. Level 0 master to slave relation . . . . .2665
Figure 792. USB1 OTG_HS high-speed block diagram (OTG_HS1) . . . . .2747
Figure 793. USB2 OTG_HS high-speed block diagram (OTG_HS2) . . . . .2747
Figure 794. OTG_HS A-B device connection . . . . .2750
Figure 795. OTG_HS peripheral-only connection . . . . .2752
Figure 796. OTG_HS host-only connection . . . . .2756
Figure 797. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . .2760
Figure 798. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .2762
Figure 799. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .2763
Figure 800. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . .2764
Figure 801. Interrupt hierarchy . . . . .2768
Figure 802. Transmit FIFO write task . . . . .2873
Figure 803. Receive FIFO read task . . . . .2874
Figure 804. Normal bulk/control OUT/SETUP . . . . .2875
Figure 805. Bulk/control IN transactions . . . . .2879
Figure 806. Normal interrupt OUT . . . . .2882
Figure 807. Normal interrupt IN . . . . .2887
Figure 808. Isochronous OUT transactions . . . . .2889
Figure 809. Isochronous IN transactions . . . . .2892
Figure 810. Normal bulk/control OUT/SETUP transactions - DMA . . . . .2894
Figure 811. Normal bulk/control IN transaction - DMA . . . . .2896
Figure 812. Normal interrupt OUT transactions - DMA mode . . . . .2897
Figure 813. Normal interrupt IN transactions - DMA mode . . . . .2898
Figure 814. Normal isochronous OUT transaction - DMA mode . . . . .2899
Figure 815. Normal isochronous IN transactions - DMA mode . . . . .2900
Figure 816. Receive FIFO packet read . . . . .2906
Figure 817. Processing a SETUP packet . . . . .2908
Figure 818. Bulk OUT transaction . . . . .2915
Figure 819. TRDT max timing case . . . . .2924
Figure 820. A-device SRP . . . . .2925
Figure 821. B-device SRP . . . . .2926
Figure 822. A-device HNP . . . . .2927
Figure 823. B-device HNP . . . . .2929
Figure 824. Ethernet high-level block diagram . . . . .2937
Figure 825. DMA transmission flow (standard mode) . . . . .2940
Figure 826. DMA transmission flow (OSP mode) . . . . .2942
Figure 827. Receive DMA flow . . . . .2944
Figure 828. Overview of MAC transmission flow . . . . .2948
Figure 829. MAC reception flow . . . . .2950
Figure 830. Packet filtering sequence . . . . .2954
Figure 831. Networked time synchronization . . . . .2963
Figure 832. Propagation delay calculation in clocks supporting
peer-to-peer path correction . . . . .		2964
Figure 833. System time update using fine correction method . . . . .2974
Figure 834. TCP segmentation offload overview . . . . .2991
Figure 835. TCP segmentation offload flow . . . . .2992
Figure 836. Header and payload fields of segmented packets . . . . .2995
Figure 837. Supported PHY interfaces . . . . .3005
Figure 838. SMA Interface block . . . . .3005
Figure 839. MDIO packet structure (Clause 45) . . . . .3006
Figure 840. MDIO packet structure (Clause 22) . . . . .3007
Figure 841. SMA write operation flow . . . . .3009
Figure 842. Write data packet . . . . .3010
Figure 843. Read data packet . . . . .3010
Figure 844. Media independent interface (MII) signals . . . . .3012
Figure 845. RMII block diagram . . . . .3014
Figure 846. Transmission bit order . . . . .3015
Figure 847. Receive bit order. . . . .3016
Figure 848. LPI transitions (Transmit, 100 Mbds) . . . . .3024
Figure 849. LPI Tx clock gating (when LPITCSE = 1) . . . . .3025
Figure 850. LPI transitions (receive, 100 Mbps) . . . . .3026
Figure 851. Descriptor ring structure . . . . .3047
Figure 852. DMA descriptor ring . . . . .3048
Figure 853. Transmit descriptor (read format) . . . . .3049
Figure 854. Transmit descriptor write-back format. . . . .3054
Figure 855. Transmit context descriptor format . . . . .3058
Figure 856. Receive normal descriptor (read format) . . . . .3062
Figure 857. Receive normal descriptor (write-back format) . . . . .3065
Figure 858. Receive context descriptor . . . . .3072
Figure 859. Generation of ETH_DMAISR flags . . . . .3090
Figure 860. HDMI-CEC block diagram . . . . .3210
Figure 861. Message structure . . . . .3210
Figure 862. Blocks . . . . .3211
Figure 863. Bit timings . . . . .3211
Figure 864. Signal free time . . . . .3212
Figure 865. Arbitration phase. . . . .3212
Figure 866. SFT of three nominal bit periods. . . . .3212
Figure 867. Error bit timing . . . . .3213
Figure 868. Error handling . . . . .3215
Figure 869. TXERR detection . . . . .3216
Figure 870. Block diagram of debug infrastructure . . . . .3228
Figure 871. Power domains of debug infrastructure . . . . .3230
Figure 872. Clock domains of debug infrastructure . . . . .3231
Figure 873. SWD successful data transfer . . . . .3234
Figure 874. JTAG TAP state machine . . . . .3235
Figure 875. Debug and access port connections. . . . .3246
Figure 876. APB-D CoreSight component topology . . . . .3254
Figure 877. Global timestamp distribution . . . . .3262
Figure 878. Embedded cross trigger . . . . .3270
Figure 879. Mapping of trigger inputs to outputs . . . . .3273
Figure 880. Cross trigger configuration example. . . . .3274
Figure 881. ETF state transition diagram. . . . .3303
Figure 882. Cortex-M7 CoreSight topology . . . . .3377
Figure 883. Cortex-M4 CoreSight Topology . . . . .3452

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