50. Revision history

Added support for STM32L431xx.

FW:

Updated LENG bitfield in Section 4.4.6: Volatile data segment length (FW_VDSL) .

PWR:

Updated Section : Entering Stop 2 mode .

RCC:

Updated Section 6.2.11: Clock security system on LSE .

GPIO:

Updated reset values in Section 6.4.4: GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..G) .

DMA:

Updated Table 40: Programmable data width & endianness (when bits PINC = MINC = 1) .

Updated Section 11.5.2: DMA interrupt flag clear register (DMA_IFCR) .

Updated NDT bit description in Section 11.5.4: DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number) .

CRC:

Added Section 13.3.2: CRC internal signals .

Updated Section 13.4.2: Independent data register (CRC_IDR) .

ADC:

Updated Section 18.4.8: Calibration (ADCAL, ADCALDIF, ADCx_CALFACT) .

Updated Section 18.4.9: ADC on-off control (ADEN, ADDIS, ADRDY) .

TIM1:

Updated Section 21.3.28: DMA burst mode .

Updated Section 21.3.29: Debug mode .

Updated Table 207: Output control bits for complementary OCx and OCxN channels with break feature .

Updated Section 21.4.20: TIM1 DMA address for full transfer (TIM1_DMAR) .

Updated Section 26.4.25: TIM1 option register 2 (TIM1_OR2) .

Updated:
Document convention:
Section 1.1: General information , Table 1: Product specific features
Memory organization:
Section 2.2.2: Memory map and register boundary addresses , Section 2.4: Embedded SRAM , Table 2: STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx memory map and peripheral register boundary addresses , Table 3: SRAM2 organization
Added Table 4: SRAM2 organization (continuation for STM32L43x/44x/45x/46x devices only)
Embedded Flash memory:
Section 3.2: FLASH main features , Section 3.3.7: Flash main memory programming sequences , Section : Programming errors , Section : WRP Area B address option bytes , Section 3.7.8: Flash option register (FLASH_OPTR) , Section 3.7.9: Flash PCROP Start address register (FLASH_PCROP1SR) , Section 3.7.10: Flash PCROP End address register (FLASH_PCROP1ER) , Section 3.7.11: Flash WRP area A address register (FLASH_WRP1AR)
FIREWALL:
Section 4.3.2: Functional requirements , Table 16: Segment accesses according to the Firewall state
PWR:
Section 5.1: Power supplies , Section 5.1.1: Independent analog peripherals supply , Section 5.2.2: Programmable voltage detector (PVD) , Section 5.3.6: Stop 0 mode , Section 5.3.9: Standby mode , Section 5.3.10: Shutdown mode , Section 5.4.3: Power control register 3 (PWR_CR3) , Section 5.4.8: Power Port A pull-up control register (PWR_PUCRA) , Section 5.4.10: Power Port B pull-up control register (PWR_PUCRB) , Section 5.4.11: Power Port B pull-down control register (PWR_PDCRB) , Section 5.4.13: Power Port C pull-down control register (PWR_PDCRC) , Section 5.4.16: Power Port E pull-up control register (PWR_PUCRE) , Section 5.4.18: Power Port H pull-up control register (PWR_PUCRH)
Added notes (12,13 and 14) in Table 21: Functionalities depending on the working mode
RCC:
Section 6.1.2: System reset , Section 6.2: Clocks , Figure 13: Clock tree , Section 6.2.1: HSE clock , Table 31: Clock source frequency , Section 6.2.18: Peripheral clock enable register (RCC_AHBxENR, RCC_APBxENRy) , Figure 16: Frequency measurement with TIM16 in capture mode

CRS:
Section 7.7.1: CRS control register (CRS_CR)

DMA:
Updated Section 11.1: Introduction , Section 11.2: DMA main features , Section 11.4: DMA functional description , Figure 27: DMA block diagram , Section 11.4.3: DMA transfers , Section 11.4.4: DMA arbitration , Section 11.4.5: DMA channels , Section 11.4.6: DMA data width, alignment, and endianness , Section 11.4.7: DMA error management , Section 11.5: DMA interrupts , Section 11.6.1: DMA interrupt status register (DMA_ISR) , Section 11.6.2: DMA interrupt flag clear register (DMA_IFCR) , Section 11.6.3: DMA channel x configuration register (DMA_CCRx) , Section 11.6.4: DMA channel x number of data to transfer register (DMA_CNDTRx) , Section 11.6.5: DMA channel x peripheral address register (DMA_CPARx) , Section 11.6.6: DMA channel x memory address register (DMA_CMARx)
Added Section 11.3.1: DMA1 and DMA2 , Section 11.3.2: DMA request mapping
Removed Section 11.4.7: DMA request mapping , Section 11.6.8: DMA2 channel selection register (DMA2_CSELR) .

INTERRUPTS:
Updated Section 12.2: SysTick calibration value register
Added note 1 in Table 51 :
STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table , note 6 in Table 52: EXTI lines connections

ADC:
Updated Section 16.2: ADC main features , Figure 39: ADC block diagram , Table 60: ADC internal input/output signals , Table 61: ADC input/output pins , Section 16.4.3: ADC clocks , Figure 41: ADC1 connectivity , Section 16.4.7: Single-ended and differential input channels , Section 16.4.8: Calibration (ADCAL, ADCALDIF, ADC_CALFACT) , Section 16.4.11: Channel selection (SQRx, JSQRx) , Section 16.4.12: Channel-wise programmable sampling time (SMPR1, SMPR2) , Section 16.4.32: Temperature sensor , Figure 108: VREFINT channel block diagram , Section 16.7.17: ADC offset y register (ADC_OFry) , Section 16.7.18: ADC injected channel y data register (ADC_JDry) , Section 16.8.2: ADC common control register (ADC_CCR)

DAC:
Updated Section 17.2: DAC main features , Section 17.3: DAC implementation , Figure 109: Dual-channel DAC block diagram , Figure 117: DAC sample and hold mode phase diagram , Section 17.4.12: Dual DAC channel conversion modes (if dual channels are available) , Section 17.7.1: DAC control register (DAC_CR) , Section 17.7.17: DAC channel1 sample and hold sample time register (DAC_SHSR1) , Section 17.7.18: DAC channel2 sample and hold sample time register (DAC_SHSR2) , Table 86: DAC register map and reset values

VREFBUF:
Updated Section 18.2: VREFBUF functional description

DFSDM:
Updated Section 21.4.3: DFSDM reset and clocks , Section 21.8.1: DFSDM filter x control register 1 (DFSDM_FLTxCR1) , Section 21.8.5: DFSDM filter x injected channel group selection register (DFSDM_FLTxJCHGR) , Section 21.8.7: DFSDM filter x data register for injected group (DFSDM_FLTxJDATAR) , Section 21.8.8: DFSDM filter x data register for the regular channel (DFSDM_FLTxRDATAR) , Section 21.8.9: DFSDM filter x analog watchdog high threshold register (DFSDM_FLTxAWHTR) , Section 21.8.10: DFSDM filter x analog watchdog low threshold register (DFSDM_FLTxAWLTR) , Section 21.8.11: DFSDM filter x analog watchdog status register (DFSDM_FLTxAWSR) , Section 21.8.12: DFSDM filter x analog watchdog clear flag register (DFSDM_FLTxAWCFR) , Section 21.8.13: DFSDM filter x extremes detector maximum register (DFSDM_FLTxEXMAX) , Section 21.8.14: DFSDM filter x extremes detector minimum register (DFSDM_FLTxEXMIN) , Section 21.8.15: DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR)

RNG:
Updated Section 24.3.3: Random number generation , Section 24.7.1: RNG control register (RNG_CR) , Table 124: RNG register map and reset map

AES:
Updated Section 25.1: Introduction , Section 25.2: AES main features , Section 25.4: AES functional description , Figure 153: AES block diagram , Figure 154: ECB encryption and decryption principle , Figure 155: CBC encryption and decryption principle , Figure 156: CTR encryption and decryption principle , Figure 157: GCM encryption and authentication principle , Figure 158: GMAC authentication principle , Section 25.4.16: AES DMA interface , Section 25.5: AES interrupts , Section 25.7.2: AES status register (AES_SR) , Section 25.4.10: AES Galois/counter mode (GCM) , Section 25.7.4: AES data output register (AES_DOUTR) , Section 25.7.5: AES key register 0 (AES_KEYR0) , Section 25.7.9: AES initialization vector register 0 (AES_IVR0) , Section 25.7.10: AES initialization vector register 1 (AES_IVR1) , Section 25.7.11: AES initialization vector register 2 (AES_IVR2) , Section 25.7.12: AES initialization vector register 3 (AES_IVR3)

Added Figure 159: CCM encryption and authentication principle , Section 25.4.4: AES procedure to perform a cipher operation , Section 25.4.5: AES decryption key preparation , Section 25.4.6: AES ciphertext stealing and data padding , Section 25.4.7: AES task suspend and resume , Section 25.4.8: AES basic chaining modes (ECB, CBC) , Section 25.4.9: AES counter (CTR) mode , Section 25.4.10: AES Galois/counter mode (GCM) , Section 25.4.11: AES Galois message authentication code (GMAC) , Section 25.4.12: AES counter with CBC-MAC (CCM) , Section 25.4.13: .AES data registers and data swapping , Section 25.4.14: AES key registers , Section 25.4.15: AES initialization vector registers , Section 25.4.17: AES error management

ADVANCED CONTROL TIMER (TIM1):
Updated Figure 197: Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6

GENERAL PURPOSE TIMER(TIM2/TIM3):
Updated Section 27.1: TIM2/TIM3 introduction, Figure 248: Counter timing diagram, internal clock divided by 4

GENERAL PURPOSE TIMER(TIM15/TIM16):
Added Section 28.5.16: Retriggerable one pulse mode (TIM15 only), Section 28.6.12: TIM15 auto-reload register (TIM15_ARR), Section 28.7.4: TIM16 status register (TIM16_SR), Section 28.7.11: TIM16 auto-reload register (TIM16_ARR), Section 28.7.17: TIM16 option register 1 (TIM16_OR1)

LPTIMER:
Added Figure 498: Low-power timer block diagram for STM32L43xxx/44xxx/45xxx/46xxx, Section 30.4.3: LPTIM trigger mapping, Section 30.4.4: LPTIM reset and clocks, Figure 502: LPTIM output waveform, single counting mode configuration when repetition register content is different than zero (with PRELOAD = 1), Section 23.4.13: Timer counter reset, Section 43.4.15: Repetition Counter, Table 160: Interrupt events

Updated Section 30.4.8: Operating mode, Figure 339: LPTIM output waveform, single counting mode configuration, Figure 340: LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set), Figure 341: LPTIM output waveform, Continuous counting mode configuration, Section 43.4.10: Register update, Section 30.4.12: Counter mode, Section 30.5: LPTIM low-power modes, Section 43.7.1: LPTIM interrupt and status register (LPTIM_ISR), Section 30.7.2: LPTIM interrupt clear register (LPTIM_ICR), Section 30.7.3: LPTIM interrupt enable register (LPTIM_IER), Section 30.7.4: LPTIM configuration register (LPTIM_CFGR), Section 30.7.5: LPTIM control register (LPTIM_CR)

WWDG:
Updated Figure 354: Watchdog block diagram, Figure 355: Window watchdog timing diagram

RTC:
Added Section 35: Real-time clock (RTC) applied to STM32L41xxx and STM32L42xxx devices only and Section 36: Tamper and backup registers (TAMP) applied to STM32L41xxx and STM32L42xxx devices only

Updated Figure 358: RTC block diagram, Section 37.3.6: Periodic auto-wake-up, Section 37.3.7: RTC initialization and configuration, Section 37.3.11: RTC reference clock detection

I2C: Updated Figure 359: Block diagram, Section 38.6: I2C interrupts

SAI:
Updated Figure 442: SAI functional block diagram , Table 234: SAI internal input/output signals , Table 235: SAI input/output pins , Section 42.6.1: SAI configuration register 1 (SAI_ACR1) , Section 42.6.2: SAI configuration register 2 (SAI_ACR2) , Section 42.6.2: SAI configuration register 2 (SAI_ACR2) , Section 42.6.10: SAI configuration register 2 (SAI_BCR2) , Section 42.6.3: SAI frame configuration register (SAI_AFR) , Section 42.6.11: SAI frame configuration register (SAI_BFR) , Section 42.6.4: SAI slot register (SAI_ASLOTR) , Section 42.6.11: SAI frame configuration register (SAI_BFR) , Section 42.6.4: SAI slot register (SAI_ASLOTR) , Section 42.6.12: SAI slot register (SAI_BSLOTR) , Section 42.6.13: SAI interrupt mask register (SAI_BIM) , Section 42.6.13: SAI interrupt mask register (SAI_BIM) , Section 42.6.6: SAI status register (SAI_ASR) , Section 42.6.14: SAI status register (SAI_BSR) , Section 42.6.7: SAI clear flag register (SAI_ACLRFR) , Section 42.6.15: SAI clear flag register (SAI_BCLRFR) , Section 42.6.8: SAI data register (SAI_ADR) , Section 42.6.16: SAI data register (SAI_BDR) , Table 241: SAI register map and reset values

Replace “TDM mode” with ‘free protocol mode’.

SWPMI:
Added Section 43.1: Introduction , Section 43.2: SWPMI main features

BXCAN:
Added Figure 484: Single-CAN block diagram
Updated Figure 486: bxCAN in silent mode , Figure 487: bxCAN in Loop back mode , Figure 488: bxCAN in combined mode , Figure 489: Transmit mailbox states , Figure 490: Receive FIFO states , Figure 491: Filter bank scale configuration - Register organization , Figure 492: Example of filter numbering , Figure 493: Filtering mechanism example , Figure 495: Bit timing , Figure 496: CAN frames , Figure 497: Event flags and interrupt generation , Figure 498: CAN mailbox registers , Table 281: bxCAN register map and reset values

DEVICE SIGNATURE:
Updated Section 48.3: Package data register

Added Section 16.4.20: Discontinuous mode (DISCEN, DISCNUM, JDISCEN) .

Updated Table 66: TSAR timings depending on resolution .

Updated Section : Reading the temperature .

Updated Section 16.4.34: Monitoring the internal voltage reference .

Updated Section 16.7.4: ADC configuration register (ADC_CFGR) .

Updated Section 16.7.6: ADC sample time register 1 (ADC_SMPR1) .

Updated Section 16.7.11: ADC regular sequence register 1 (ADC_SQR1) .

Updated Section 16.7.12: ADC regular sequence register 2 (ADC_SQR2) .

Updated Section 16.7.13: ADC regular sequence register 3 (ADC_SQR3) .

Updated Section 16.7.14: ADC regular sequence register 4 (ADC_SQR4) .

Updated Section 16.7.16: ADC injected sequence register (ADC_JSQR) .

Updated Section 16.7.17: ADC offset y register (ADC_OFRy) .

Updated Section 16.7.19: ADC analog watchdog 2 configuration register (ADC_AWD2CR) .

Updated Section 16.7.20: ADC analog watchdog 3 configuration register (ADC_AWD3CR) .

Updated Section Table 76.: ADC global register map .

DAC:

Updated Section 17.4.6: DAC trigger selection .

Updated Section : Normal mode .

VREFBUF:

Section 18.3.2: VREFBUF calibration control register (VREFBUF_CCR) .

DFSDM:

Updated Section 21.2: DFSDM main features .

Updated Section 21.3: DFSDM implementation .

Updated Section : DFSDM clocks .

Updated Section 21.7: DFSDM channel y registers (y=0..3) introduction.

Updated Section 21.8: DFSDM filter x module registers (x=0..1) introduction.

RNG:

Updated Section : Normal operations .

Updated Section : Clock error detection .

Updated Table 122: RNG interrupt requests .

Updated Section 24.6: RNG entropy source validation .

Updated Section 24.7.2: RNG status register (RNG_SR) .

Updated Section 24.7.3: RNG data register (RNG_DR) .

AES:

Updated Section : Suspend/resume operations in GCM mode .

TIM1:

Updated Section 26.3.3: Repetition counter

Updated Section : External clock source mode 2

Updated Section 26.4: TIM1 registers introduction .

Updated Section 26.4.1: TIM1 control register 1 (TIM1_CR1) .

Updated Table 139: TIM1 internal trigger connection .

Updated Section 26.4.27: TIM1 option register 2 (TIM1_OR2) .

Updated Section 26.4.28: TIM1 option register 3 (TIM1_OR3) .

TIM2/TIM3:

Updated Section : External clock source mode 2 .

Updated Section 27.3.19: Timer synchronization .

Updated Section 27.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 3) .

Updated Section 27.4.9: TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 3) .

Updated Section 27.4.10: TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2) (x = 2 to 3) .

Updated Section 27.4.11: TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 3) .

Updated Table 144: Output control bit for standard OCx channels

Updated Section 27.4.12: TIMx counter (TIMx_CNT)(x = 2 to 3) .

Updated Section 27.4.13: TIMx counter [alternate] (TIMx_CNT)(x = 2 to 3) .

Updated Section 27.4.15: TIMx auto-reload register (TIMx_ARR)(x = 2 to 3) .

Updated Section 27.4.16: TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 3) .

Updated Section 27.4.16: TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 3) .

Updated Section 27.4.17: TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 3) .

Updated Section 27.4.18: TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 3) .

Updated Section 27.4.19: TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 3) .

Updated Section 27.4.22: TIM2 option register 1 (TIM2_OR1) .

LPTIM section Split:

For STM32L43xxx, STM32L44xxx, STM32L45xxx and STM32L46xxx microcontrollers: Section 30: Low-power timer (LPTIM) .

For STM32L41xxx and STM32L42xxx microcontrollers: Section 31: Low-power timer (LPTIM) .

I2C:

Added Section 38.4.2: I2C pins and internal signals .

Updated Table 210: Effect of low-power modes to I2C .