12. Nested vectored interrupt controller (NVIC)

12.1 NVIC main features

• 67 maskable interrupt channels (not including the sixteen Cortex®-M4 with FPU interrupt lines)
• 16 programmable priority levels (4 bits of interrupt priority are used)
• Low-latency exception and interrupt handling
• Power management control
• Implementation of System Control Registers

The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts.

All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to the PM0214 programming manual for Cortex™-M4 products.

12.2 SysTick calibration value register

The SysTick calibration value is set to 0x4000270F, which gives a reference time base of 1 ms with the SysTick clock set to 10 MHz (max $f_{HCLK}/8$ ).

12.3 Interrupt and exception vectors

The grey rows in Table 51 describe the vectors without specific position.

Refer to device datasheet for availability of each peripheral.

Table 51. STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table

Position	Priority	Type of priority	Acronym	Description	Address
-	-	-	-	Reserved	0x0000 0000
-	-3	fixed	Reset	Reset	0x0000 0004
-	-2	fixed	NMI	Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector.	0x0000 0008
-	-1	fixed	HardFault	All classes of fault	0x0000 000C
-	0	settable	MemManage	Memory management	0x0000 0010
-	1	settable	BusFault	Pre-fetch fault, memory access fault	0x0000 0014
-	2	settable	UsageFault	Undefined instruction or illegal state	0x0000 0018
-	-	-	-	Reserved	0x0000 001C - 0x0000 0028
-	3	settable	SVCall	System service call via SWI instruction	0x0000 002C
-	4	settable	Debug	Monitor	0x0000 0030
-	-	-	-	Reserved	0x0000 0034
-	5	settable	PendSV	Pendable request for system service	0x0000 0038
-	6	settable	SysTick	System tick timer	0x0000 003C
0	7	settable	WWDG	Window Watchdog interrupt	0x0000 0040
1	8	settable	PVD_PVM	PVD/PVM1/PVM2 ⁽¹⁾/PVM3/PVM4 through EXTI lines 16/35/36/37/38 interrupts	0x0000 0044
2	9	settable	RTC_TAMP_STAMP /CSS_LSE	RTC Tamper or TimeStamp /CSS on LSE through EXTI line 19 interrupts	0x0000 0048
3	10	settable	RTC_WKUP	RTC Wakeup timer through EXTI line 20 interrupt	0x0000 004C
4	11	settable	FLASH	Flash global interrupt	0x0000 0050
5	12	settable	RCC	RCC global interrupt	0x0000 0054
6	13	settable	EXTI0	EXTI Line0 interrupt	0x0000 0058
7	14	settable	EXTI1	EXTI Line1 interrupt	0x0000 005C
8	15	settable	EXTI2	EXTI Line2 interrupt	0x0000 0060
9	16	settable	EXTI3	EXTI Line3 interrupt	0x0000 0064
10	17	settable	EXTI4	EXTI Line4 interrupt	0x0000 0068

Table 51. STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table (continued)

Position	Priority	Type of priority	Acronym	Description	Address
11	18	settable	DMA1_CH1	DMA1 channel 1 interrupt	0x0000 006C
12	19	settable	DMA1_CH2	DMA1 channel 2 interrupt	0x0000 0070
13	20	settable	DMA1_CH3	DMA1 channel 3 interrupt	0x0000 0074
14	21	settable	DMA1_CH4	DMA1 channel 4 interrupt	0x0000 0078
15	22	settable	DMA1_CH5	DMA1 channel 5 interrupt	0x0000 007C
16	23	settable	DMA1_CH6	DMA1 channel 6 interrupt	0x0000 0080
17	24	settable	DMA1_CH7	DMA1 channel 7 interrupt	0x0000 0084
18	25	settable	ADC1_2	ADC1 and ADC2 ⁽²⁾global interrupt	0x0000 0088
19	26	settable	CAN1_TX ⁽¹⁾	CAN1_TX interrupts	0x0000 008C
20	27	settable	CAN1_RX0 ⁽¹⁾	CAN1_RX0 interrupts	0x0000 0090
21	28	settable	CAN1_RX1 ⁽¹⁾	CAN1_RX1 interrupt	0x0000 0094
22	29	settable	CAN1_SCE ⁽¹⁾	CAN1_SCE interrupt	0x0000 0098
23	30	settable	EXTI9_5	EXTI Line[9:5] interrupts	0x0000 009C
24	31	settable	TIM1_BRK/TIM15	TIM1 Break/TIM15 global interrupts	0x0000 00A0
25	32	settable	TIM1_UP/TIM16	TIM1 Update/TIM16 global interrupts	0x0000 00A4
26	33	settable	TIM1_TRG_COM	TIM1 trigger and commutation interrupt	0x0000 00A8
27	34	settable	TIM1_CC	TIM1 capture compare interrupt	0x0000 00AC
28	35	settable	TIM2	TIM2 global interrupt	0x0000 00B0
29	36	settable	TIM3 ⁽³⁾	TIM3 global interrupt	0x0000 00B4
30	37	settable	-	Reserved	0x0000 00B8
31	38	settable	I2C1_EV	I2C1 event interrupt	0x0000 00BC
32	39	settable	I2C1_ER	I2C1 error interrupt	0x0000 00C0
33	40	settable	I2C2_EV ⁽⁴⁾	I2C2 event interrupt	0x0000 00C4
34	41	settable	I2C2_ER ⁽⁴⁾	I2C2 error interrupt	0x0000 00C8
35	42	settable	SPI1	SPI1 global interrupt	0x0000 00CC
36	43	settable	SPI2 ⁽⁴⁾	SPI2 global interrupt	0x0000 00D0
37	44	settable	USART1	USART1 global interrupt	0x0000 00D4
38	45	settable	USART2	USART2 global interrupt	0x0000 00D8
39	46	settable	USART3 ⁽⁴⁾	USART3 global interrupt	0x0000 00DC
40	47	settable	EXTI15_10	EXTI Line[15:10] interrupts	0x0000 00E0
41	48	settable	RTC_ALARM	RTC alarms through EXTI line 18 interrupts	0x0000 00E4
42	49	settable	-	Reserved	0x0000 00E8
43	50	settable	-	Reserved	0x0000 00EC

Table 51. STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table (continued)

Position	Priority	Type of priority	Acronym	Description	Address
44	51	settable	-	Reserved	0x0000 00F0
45	52	settable	-	Reserved	0x0000 00F4
46	53	settable	-	Reserved	0x0000 00F8
47	54	settable	-	Reserved	0x0000 00FC
48	55	settable	-	Reserved	0x0000 0100
49	56	settable	SDMMC1 ⁽⁴⁾⁽¹⁾	SDMMC1 global interrupt	0x0000 0104
50	57	settable	-	Reserved	0x0000 0108
51	58	settable	SPI3	SPI3 global interrupt	0x0000 010C
52	59	settable	UART4 ⁽³⁾	UART4 global interrupt	0x0000 0110
53	60	settable	-	Reserved	0x0000 0114
54	61	settable	TIM6_DACUNDER	TIM6 global and DAC1 ⁽¹⁾underrun interrupts	0x0000 0118
55	62	settable	TIM7 ⁽⁵⁾	TIM7 global interrupt	0x0000 011C
56	63	settable	DMA2_CH1	DMA2 channel 1 interrupt	0x0000 0120
57	64	settable	DMA2_CH2	DMA2 channel 2 interrupt	0x0000 0124
58	65	settable	DMA2_CH3	DMA2 channel 3 interrupt	0x0000 0128
59	66	settable	DMA2_CH4	DMA2 channel 4 interrupt	0x0000 012C
60	67	settable	DMA2_CH5	DMA2 channel 5 interrupt	0x0000 0130
61	68	settable	DFSDM1_FLT0 ⁽³⁾	DFSDM1_FLT0 global interrupt	0x0000 0134
62	69	settable	DFSDM1_FLT1 ⁽³⁾	DFSDM1_FLT1 global interrupt	0x0000 0138
63	70	settable	-	Reserved	0x0000 013C
64	71	settable	COMP	COMP1/COMP2 ⁽¹⁾through EXTI lines 21/22 interrupts	0x0000 0140
65	72	settable	LPTIM1	LPTIM1 global interrupt	0x0000 0144
66	73	settable	LPTIM2	LPTIM2 global interrupt	0x0000 0148
67	74	settable	USB_FS ⁽⁶⁾	USB event interrupt through EXTI line 17	0x0000 014C
68	75	settable	DMA2_CH6	DMA2 channel 6 interrupt	0x0000 0150
69	76	settable	DMA2_CH7	DMA2 channel 7 interrupt	0x0000 0154
70	77	settable	LPUART1	LPUART1 global interrupt	0x0000 0158
71	78	settable	QUADSPI	QUADSPI global interrupt	0x0000 015C
72	79	settable	I2C3_EV	I2C3 event interrupt	0x0000 0160
73	80	settable	I2C3_ER	I2C3 error interrupt	0x0000 0164
74	81	settable	SAI1 ⁽¹⁾	SAI1 global interrupt	0x0000 0168
75	82	settable	-	Reserved	0x0000 016C

Table 51. STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table (continued)

Position	Priority	Type of priority	Acronym	Description	Address
76	83	settable	SWPMI1 ⁽⁵⁾	SWPMI1 global interrupt	0x0000 0170
77	84	settable	TSC	TSC global interrupt	0x0000 0174
78	85	settable	LCD ⁽⁷⁾	LCD global interrupt	0x0000 0178
79	86	settable	AES ⁽⁸⁾	AES global interrupt	0x0000 017C
80	87	settable	RNG	RNG global interrupt	0x0000 0180
81	88	settable	FPU	Floating point interrupt	0x0000 0184
82	89	settable	CRS	CRS interrupt	0x0000 0188
83	90	settable	I2C4_EV ⁽³⁾	I2C4 event interrupt, wakeup through EXTI line 40	0x0000 018C
84	91	settable	I2C4_ER ⁽³⁾	I2C4 error interrupt	0x0000 0190

1. Not available on STM32L41xxx and STM32L42xxx devices.
2. Available on STM32L41xxx and STM32L42xxx devices only.
3. Available on STM32L45xxx and STM32L46xxx devices only.
4. Not available on STM32L432xx and STM32L442xx devices.
5. Available on STM32L43xxx and STM32L44xxx devices only.
6. Available on STM32L4x2xx and STM32L4x3xx devices only.
7. Available on STM32L4x3xx devices only.
8. Available on STM32L42xx, STM32L44xxx and STM32L46xxx devices only.