10. Peripherals interconnect matrix

10.1 Introduction

Several peripherals have direct connections between them.

This allows autonomous communication and or synchronization between peripherals, saving CPU resources thus power supply consumption.

In addition, these hardware connections remove software latency and allow design of predictable system.

Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes.

10.2 Connection summary

Table 43. STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx peripherals interconnect matrix ^{(1) (2)}

-		Destination
-		TIM1	TIM2	TIM6	TIM7	TIM15	TIM16	LPTIM1	LPTIM2	ADC1	ADC2	OPAMP1	DAC1	DAC2	COMP1	COMP2	IRTIM
Source	TIM1	-	1	-	-	1	-	-	-	2	2	-	-	-	7	-	-
	TIM2	1	-	-	-	-	-	-	-	2	2	-	4	4	7	-	-
	TIM6	-	-	-	-	-	-	-	-	2	2	-	4	4	-	-	-
	TIM7	-	-	-	-	-	-	-	-	-	-	-	4	4	-	-	-
	TIM15	1	-	-	-	-	-	-	-	2	2	-	4	4	-	7	12
	TIM16	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	12
	LPTIM1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
	LPTIM2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
	ADC1	3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
	T. Sensor	-	-	-	-	-	-	-	-	9	-	-	-	-	-	-	-
	VBAT	-	-	-	-	-	-	-	-	9	-	-	-	-	-	-	-
	VREFINT	-	-	-	-	-	-	-	-	9	-	-	-	-	-	-	-
	OPAMP1	-	-	-	-	-	-	-	-	9	9	-	-	-	-	-	-
	DAC1	-	-	-	-	-	-	-	-	9	-	9	-	-	-	-	-
	DAC2	-	-	-	-	-	-	-	-	9	-	-	-	-	-	-	-
	HSE	-	-	-	-	-	5	-	-	-	-	-	-	-	-	-	-
	LSE	-	5	-	-	5	5	-	-	-	-	-	-	-	-	-	-
	MSI	-	-	-	-	-	5	-	-	-	-	-	-	-	-	-	-
	LSI	-	-	-	-	-	5	-	-	-	-	-	-	-	-	-	-

Table 43. STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx peripherals interconnect matrix ^{(1) (2)}

-		Destination
-		TIM1	TIM2	TIM6	TIM7	TIM15	TIM16	LPTIM1	LPTIM2	ADC1	ADC2	OPAMP1	DAC1	DAC2	COMP1	COMP2	IRTIM
Source	MCO	-	-	-	-	-	5	-	-	-	-	-	-	-	-	-	-
	EXTI	-	-	-	-	-	-	-	-	2	2	-	4	4	-	-	-
	RTC	-	-	-	-	-	5	6	6	-	-	-	-	-	-	-	-
	COMP1	10	10	-	-	10	10	6	6	-	-	-	-	-	-	-	-
	COMP2	10	10	-	-	10	10	6	6	-	-	-	-	-	-	-	-
	SYST ERR	11	-	-	-	11	11	-	-	-	-	-	-	-	-	-	-
	USB ⁽³⁾	-	8	-	-	-	-	-	-	-	-	-	-	-	-	-	-

1. Numbers in table are links to corresponding detailed sub-section in Section 10.3: Interconnection details .
2. The “-” symbol in grayed cells means no interconnect.
3. Not available for STM32L431xx devices.

10.3 Interconnection details

10.3.1 From timer (TIM1/TIM2/TIM15/TIM16) to timer (TIM1/TIM2/TIM15/TIM16)

Purpose

Some of the TIMx timers are linked together internally for timer synchronization or chaining. When one timer is configured in Master Mode, it can reset, start, stop or clock the counter of another timer configured in Slave Mode.

A description of the feature is provided in: Section 27.3.19: Timer synchronization .

The modes of synchronization are detailed in:

• Section 27.3.19: Timer synchronization for advanced-control timers (TIM1)
• Section 27.3.18: Timers and external trigger synchronization for general-purpose timers (TIM2)
• Section 28.5.19: External trigger synchronization (TIM15 only) for general-purpose timer (TIM15)

Triggering signals

The output (from Master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1) following a configurable timer event.

The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3

The input and output signals for TIM1 are shown in Figure 183: Advanced-control timer block diagram .

The possible master/slave connections are given in:

• Table 139: TIM1 internal trigger connection

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.2 From timer (TIM1/TIM2/TIM6/TIM15) and EXTI to ADC (ADC1)

Purpose

General-purpose timers (TIM2), basic timer (TIM6), advanced-control timer (TIM1), general-purpose timer (TIM15) and EXTI can be used to generate an ADC triggering event.

TIMx synchronization is described in: Section 26.3.5: Clock selection (TIM1).

ADC synchronization is described in: Section 16.4.18: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) .

Triggering signals

The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event.

The input (to ADC) is on signal EXT[15:0], JEXT[15:0].

The connection between timers and ADC is provided in:

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.3 From ADC (ADC1) to timer (TIM1)

Purpose

ADC1 can provide trigger event through watchdog signals to advanced-control timers (TIM1).

A description of the ADC analog watchdog setting is provided in: Section 16.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) .

Trigger settings on the timer are provided in: Section 26.3.4: External trigger input .

Triggering signals

The output (from ADC) is on signals ADCn_AWDx_OUT n = 1, 2, 3 (for ADC1) x = 1, 2, 3 (3 watchdog per ADC) and the input (to timer) on signal TIMx_ETR (external trigger).

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.4 From timer (TIM2/TIM6/TIM7) and EXTI to DAC (DAC1/DAC2)

Purpose

General-purpose timer (TIM2), basic timers (TIM6, TIM7), and EXTI can be used as triggering event to start a DAC conversion.

Triggering signals

The output (from timer) is on signal TIMx_TRGO directly connected to corresponding DAC inputs.

Selection of input triggers on DAC is provided in Section 17.4.6: DAC trigger selection (single and dual mode).

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.5 From HSE, LSE, LSI, MSI, MCO, RTC to timer (TIM2/TIM15/TIM16)

Purpose

External clocks (HSE, LSE), internal clocks (LSI, MSI), microcontroller output clock (MCO), GPIO and RTC wakeup interrupt can be used as input to general-purpose timer (TIM15/16) channel 1.

This allows to calibrate the HSI16/MSI system clocks (with TIM15/TIM16 and LSE) or LSI (with TIM16 and HSE). This is also used to precisely measure LSI (with TIM16 and HSI16) or MSI (with and HSI16) oscillator frequency.

When Low Speed External (LSE) oscillator is used, no additional hardware connections are required.

This feature is described in Section 6.2.17: Internal/external clock measurement with TIM15/TIM16 .

External clock LSE can be used as input to general-purpose timers (TIM2) on TIM2_ETR pin, see Section 27.4.22: TIM2 option register 1 (TIM2_OR1) .

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.6 From RTC, COMP1, COMP2 to low-power timer (LPTIM1/LPTIM2)

Purpose

RTC alarm A/B, RTC_TAMP1/2/3 input detection, COMP1/2_OUT can be used as trigger to start LPTIM counters (LPTIM1/2).

Triggering signals

This trigger feature is described in Section 30.4.7: Trigger multiplexer (and following sections).

The input selection is described in Table 155: LPTIM1 external trigger connection .

Active power mode

Run, Sleep, Low-power run, Low-power sleep, Stop 0, Stop 1, Stop 2 (LPTIM1 only).

10.3.7 From timer (TIM1/TIM2/TIM15) to comparators (COMP1/COMP2)

Purpose

Advanced-control timer (TIM1), general-purpose timer (TIM2) and general-purpose timer (TIM15) can be used as blanking window input to COMP1/COMP2

The blanking function is described in Section 19.3.7: Comparator output blanking function .

The blanking sources are given in:

• Section 19.6.1: Comparator 1 control and status register (COMP1_CSR) bits 20:18 BLANKING[2:0]
• Section 19.6.2: Comparator 2 control and status register (COMP2_CSR) bits 20:18 BLANKING[2:0]

Triggering signals

Timer output signal TIMx_Ocx are the inputs to blanking source of COMP1/COMP2.

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.8 From ADC (ADC1) to ADC (ADC2)

Purpose

ADC1 can be used as a “master” to trigger ADC2 “slave” start of conversion.

In dual ADC mode, the converted data of the master and slave ADCs can be read in parallel.

A description of dual ADC mode is provided in: Section 16.4.31: Dual ADC modes .

Triggering signals

Internal to the ADCs.

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.9 From USB to timer (TIM2)

Purpose

USB (FS SOF) can generate a trigger to general-purpose timer (TIM2).

Connection of USB to TIM2 is described in .

Triggering signals

Internal signal generated by USB FS Start Of Frame.

Active power mode

Run, Sleep.

10.3.10 From internal analog source to ADC (ADC1) and OPAMP (OPAMP1)

Purpose

Internal temperature sensor ( $V_{TS}$ ) and $V_{BAT}$ monitoring channel are connected to ADC1 input channels.

Internal reference voltage ( $V_{REFINT}$ ) is connected to ADC1 input channels.

OPAMP1 output can be connected to ADC1 input channel through the GPIO.

DAC1_OUT1 and DAC1_OUT2 outputs can be connected to input channel.

DAC1_OUT1 can be connected to OPAMP1_VINP.

This is according:

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.11 From comparators (COMP1/COMP2) to timers (TIM1/TIM2/TIM15/TIM16)

Purpose

Comparators (COMP1/COMP2) output values can be connected to timers (TIM1/TIM2/TIM15/TIM16) input captures or TIMx_ETR signals.

The connection to ETR is described in Section 26.3.4: External trigger input .

Comparators (COMP1/COMP2) output values can also generate break input signals for timers (TIM1) on input pins TIMx_BKIN or TIMx_BKIN2 through GPIO alternate function selection using open drain connection of IO, see Section 26.3.17: Bidirectional break inputs .

The possible connections are given in:

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.12 From system errors to timers (TIM1/TIM15/TIM16)

Purpose

CSS, CPU hardfault, RAM parity error, FLASH ECC double error detection, PVD can generate system errors in the form of timer break toward timers (TIM1/TIM15/TIM16).

The purpose of the break function is to protect power switches driven by PWM signals generated by the timers.

List of possible source of break are described in:

• Section 26.3.16: Using the break function (TIM1)
• Section 28.5.13: Using the break function (TIM15/TIM16)
• Figure 293: TIM15 block diagram
• Figure 294: TIM16 block diagram

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.13 From timers (TIM16) to IRTIM

Purpose

General-purpose timer (TIM16) output channel TIMx_OC1 are used to generate the waveform of infrared signal output.

The functionality is described in Section 32: Infrared interface (IRTIM) .

Active power mode

Run, Sleep, Low-power run, Low-power sleep.