RM0394-STM32L41-42-43-44-45-46

Introduction

This reference manual targets application developers. It provides complete information on how to use the STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx microcontroller memory and peripherals.

The STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx is a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the corresponding datasheets.

For information on the Arm ® Cortex ® -M4 core, please refer to the Cortex ® -M4 Technical Reference Manual.

The STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx microprocessors include ST state-of-the-art patented technology.

Contents

3.3.4Adaptive real-time memory accelerator (ART Accelerator™)84
3.3.5Flash program and erase operations86
3.3.6Flash main memory erase sequences87
3.3.7Flash main memory programming sequences88
3.4FLASH option bytes92
3.4.1Option bytes description92
3.4.2Option bytes programming96
3.5FLASH memory protection98
3.5.1Read protection (RDP)98
3.5.2Proprietary code readout protection (PCROP)101
3.5.3Write protection (WRP)102
3.6FLASH interrupts103
3.7FLASH registers104
3.7.1Flash access control register (FLASH_ACR)104
3.7.2Flash Power-down key register (FLASH_PDKEYR)105
3.7.3Flash key register (FLASH_KEYR)105
3.7.4Flash option key register (FLASH_OPTKEYR)106
3.7.5Flash status register (FLASH_SR)106
3.7.6Flash control register (FLASH_CR)108
3.7.7Flash ECC register (FLASH_ECCR)110
3.7.8Flash option register (FLASH_OPTR)111
3.7.9Flash PCROP Start address register (FLASH_PCROP1SR)113
3.7.10Flash PCROP End address register (FLASH_PCROP1ER)113
3.7.11Flash WRP area A address register (FLASH_WRP1AR)114
3.7.12Flash WRP area B address register (FLASH_WRP1BR)114
3.7.13FLASH register map116
4Firewall (FW)118
4.1Introduction118
4.2Firewall main features118
4.3Firewall functional description119
4.3.1Firewall AMBA bus snoop119
4.3.2Functional requirements119
4.3.3Firewall segments120
4.3.4Segment accesses and properties121
4.3.5Firewall initialization122
5.4PWR registers . . . . .162
5.4.1Power control register 1 (PWR_CR1) . . . . .162
5.4.2Power control register 2 (PWR_CR2) . . . . .163
5.4.3Power control register 3 (PWR_CR3) . . . . .164
5.4.4Power control register 4 (PWR_CR4) . . . . .165
5.4.5Power status register 1 (PWR_SR1) . . . . .167
5.4.6Power status register 2 (PWR_SR2) . . . . .168
5.4.7Power status clear register (PWR_SCR) . . . . .169
5.4.8Power Port A pull-up control register (PWR_PUCRA) . . . . .170
5.4.9Power Port A pull-down control register (PWR_PDCRA) . . . . .170
5.4.10Power Port B pull-up control register (PWR_PUCRB) . . . . .171
5.4.11Power Port B pull-down control register (PWR_PDCRB) . . . . .171
5.4.12Power Port C pull-up control register (PWR_PUCRC) . . . . .172
5.4.13Power Port C pull-down control register (PWR_PDCRC) . . . . .172
5.4.14Power Port D pull-up control register (PWR_PUCRD) . . . . .173
5.4.15Power Port D pull-down control register (PWR_PDCRD) . . . . .173
5.4.16Power Port E pull-up control register (PWR_PUCRE) . . . . .174
5.4.17Power Port E pull-down control register (PWR_PDCRE) . . . . .174
5.4.18Power Port H pull-up control register (PWR_PUCRH) . . . . .175
5.4.19Power Port H pull-down control register (PWR_PDCRH) . . . . .175
5.4.20PWR register map and reset value table . . . . .177
6Reset and clock control (RCC) . . . . .179
6.1Reset . . . . .179
6.1.1Power reset . . . . .179
6.1.2System reset . . . . .179
6.1.3Backup domain reset . . . . .180
6.2Clocks . . . . .181
6.2.1HSE clock . . . . .185
6.2.2HSI16 clock . . . . .186
6.2.3MSI clock . . . . .187
6.2.4HSI48 clock . . . . .187
6.2.5PLL . . . . .188
6.2.6LSE clock . . . . .189
6.2.7LSI clock . . . . .189
6.2.8System clock (SYSCLK) selection . . . . .190
6.2.9Clock source frequency versus voltage scaling . . . . .190
6.4.24APB1 peripheral clocks enable in Sleep and Stop modes register 1 (RCC_APB1SMENR1) .....232
6.4.25APB1 peripheral clocks enable in Sleep and Stop modes register 2 (RCC_APB1SMENR2) .....235
6.4.26APB2 peripheral clocks enable in Sleep and Stop modes register (RCC_APB2SMENR) .....237
6.4.27Peripherals independent clock configuration register (RCC_CCIPR) .....238
6.4.28Backup domain control register (RCC_BDCR) .....241
6.4.29Control/status register (RCC_CSR) .....243
6.4.30Clock recovery RC register (RCC_CRRRCR) .....245
6.4.31Peripherals independent clock configuration register (RCC_CCIPR2) .....246
6.4.32RCC register map .....246
7Clock recovery system (CRS) .....251
7.1CRS introduction .....251
7.2CRS main features .....251
7.3CRS implementation .....251
7.4CRS functional description .....252
7.4.1CRS block diagram .....252
7.4.2CRS internal signals .....252
7.4.3Synchronization input .....253
7.4.4Frequency error measurement .....253
7.4.5Frequency error evaluation and automatic trimming .....254
7.4.6CRS initialization and configuration .....255
7.5CRS in low-power modes .....256
7.6CRS interrupts .....256
7.7CRS registers .....256
7.7.1CRS control register (CRS_CR) .....256
7.7.2CRS configuration register (CRS_CFGR) .....258
7.7.3CRS interrupt and status register (CRS_ISR) .....259
7.7.4CRS interrupt flag clear register (CRS_ICR) .....261
7.7.5CRS register map .....261
8General-purpose I/Os (GPIO) .....263
8.1Introduction .....263
8.2GPIO main features .....263
8.3GPIO functional description .....263
8.3.1General-purpose I/O (GPIO) .....266
8.3.2I/O pin alternate function multiplexer and mapping .....266
8.3.3I/O port control registers .....267
8.3.4I/O port state in Low-power modes .....267
8.3.5I/O port data registers .....267
8.3.6I/O data bitwise handling .....267
8.3.7GPIO locking mechanism .....268
8.3.8I/O alternate function input/output .....268
8.3.9External interrupt/wakeup lines .....269
8.3.10Input configuration .....269
8.3.11Output configuration .....270
8.3.12Alternate function configuration .....270
8.3.13Analog configuration .....271
8.3.14Using the HSE or LSE oscillator pins as GPIOs .....272
8.3.15Using the GPIO pins in the RTC supply domain .....272
8.3.16Using PH3 as GPIO .....272
8.4GPIO in low-power modes .....272
8.5..... GPIO registers273
8.5.1GPIO port mode register (GPIOx_MODER) (x = A to E, H) .....273
8.5.2GPIO port output type register (GPIOx_OTYPER) (x = A to E, H) .....273
8.5.3GPIO port output speed register (GPIOx_OSPEEDR) (x = A to E, H) .....274
8.5.4GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to E, H) .....274
8.5.5GPIO port input data register (GPIOx_IDR) (x = A to E, H) .....275
8.5.6GPIO port output data register (GPIOx_ODR) (x = A to E, H) .....275
8.5.7GPIO port bit set/reset register (GPIOx_BSRR) (x = A to E, H) .....275
8.5.8GPIO port configuration lock register (GPIOx_LCKR) (x = A to E, H) .....276
8.5.9GPIO alternate function low register (GPIOx_AFRL) (x = A to E, H) .....277
8.5.10GPIO alternate function high register (GPIOx_AFRH) (x = A to E, H) .....278
8.5.11GPIO port bit reset register (GPIOx_BRR) (x = A to E, H) .....279
8.5.12GPIO register map .....279
9System configuration controller (SYSCFG) .....281
9.1SYSCFG main features .....281
9.2SYSCFG registers .....281
9.2.1SYSCFG memory remap register (SYSCFG_MEMRMP) .....281
9.2.2SYSCFG configuration register 1 (SYSCFG_CFGR1) .....282
9.2.3SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) .....283
9.2.4SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) .....285
9.2.5SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) .....286
9.2.6SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) .....288
9.2.7SYSCFG SRAM2 control and status register (SYSCFG_SCSR) .....289
9.2.8SYSCFG configuration register 2 (SYSCFG_CFGR2) .....290
9.2.9SYSCFG SRAM2 write protection register (SYSCFG_SWPR) .....291
9.2.10SYSCFG SRAM2 key register (SYSCFG_SKR) .....291
9.2.11SYSCFG register map .....292
10Peripherals interconnect matrix .....293
10.1Introduction .....293
10.2Connection summary .....293
10.3Interconnection details .....294
10.3.1From timer (TIM1/TIM2/TIM15/TIM16) to timer (TIM1/TIM2/TIM15/TIM16) .....294
10.3.2From timer (TIM1/TIM2/TIM6/TIM15) and EXTI to ADC (ADC1) .....295
10.3.3From ADC (ADC1) to timer (TIM1) .....295
10.3.4From timer (TIM2/TIM6/TIM7) and EXTI to DAC (DAC1/DAC2) .....295
10.3.5From HSE, LSE, LSI, MSI, MCO, RTC to timer (TIM2/TIM15/TIM16) .....296
10.3.6From RTC, COMP1, COMP2 to low-power timer (LPTIM1/LPTIM2) .....296
10.3.7From timer (TIM1/TIM2/TIM15) to comparators (COMP1/COMP2) .....297
10.3.8From ADC (ADC1) to ADC (ADC2) .....297
10.3.9From USB to timer (TIM2) .....297
10.3.10From internal analog source to ADC (ADC1) and OPAMP (OPAMP1) .....298
10.3.11From comparators (COMP1/COMP2) to timers (TIM1/TIM2/TIM15/TIM16) .....298
10.3.12From system errors to timers (TIM1/TIM15/TIM16) .....299
10.3.13From timers (TIM16) to IRTIM .....299
11Direct memory access controller (DMA) .....300
11.1Introduction .....300
11.2DMA main features .....300
13.3.6Software interrupt/event selection . . . . .332
13.4EXTI interrupt/event line mapping . . . . .332
13.5EXTI registers . . . . .335
13.5.1Interrupt mask register 1 (EXTI_IMR1) . . . . .335
13.5.2Event mask register 1 (EXTI_EMR1) . . . . .335
13.5.3Rising trigger selection register 1 (EXTI_RTSR1) . . . . .336
13.5.4Falling trigger selection register 1 (EXTI_FTSR1) . . . . .336
13.5.5Software interrupt event register 1 (EXTI_SWIER1) . . . . .337
13.5.6Pending register 1 (EXTI_PR1) . . . . .338
13.5.7Interrupt mask register 2 (EXTI_IMR2) . . . . .338
13.5.8Event mask register 2 (EXTI_EMR2) . . . . .339
13.5.9Rising trigger selection register 2 (EXTI_RTSR2) . . . . .339
13.5.10Falling trigger selection register 2 (EXTI_FTSR2) . . . . .340
13.5.11Software interrupt event register 2 (EXTI_SWIER2) . . . . .340
13.5.12Pending register 2 (EXTI_PR2) . . . . .341
13.5.13EXTI register map . . . . .342
14Cyclic redundancy check calculation unit (CRC) . . . . .343
14.1Introduction . . . . .343
14.2CRC main features . . . . .343
14.3CRC functional description . . . . .344
14.3.1CRC block diagram . . . . .344
14.3.2CRC internal signals . . . . .344
14.3.3CRC operation . . . . .344
14.4CRC registers . . . . .346
14.4.1CRC data register (CRC_DR) . . . . .346
14.4.2CRC independent data register (CRC_IDR) . . . . .346
14.4.3CRC control register (CRC_CR) . . . . .347
14.4.4CRC initial value (CRC_INIT) . . . . .348
14.4.5CRC polynomial (CRC_POL) . . . . .348
14.4.6CRC register map . . . . .349
15Quad-SPI interface (QUADSPI) . . . . .350
15.1Introduction . . . . .350
15.2QUADSPI main features . . . . .350
15.3QUADSPI functional description . . . . .350

16        Analog-to-digital converters (ADC) . . . . . 378

16.4ADC functional description . . . . .381
16.4.1ADC block diagram . . . . .381
16.4.2ADC pins and internal signals . . . . .382
16.4.3ADC clocks . . . . .383
16.4.4ADC1/2 connectivity . . . . .385
16.4.5Slave AHB interface . . . . .387
16.4.6ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) . . . . .387
16.4.7Single-ended and differential input channels . . . . .388
16.4.8Calibration (ADCAL, ADCALDIF, ADC_CALFACT) . . . . .388
16.4.9ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .391
16.4.10Constraints when writing the ADC control bits . . . . .392
16.4.11Channel selection (SQRx, JSQRx) . . . . .393
16.4.12Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . .394
16.4.13Single conversion mode (CONT = 0) . . . . .395
16.4.14Continuous conversion mode (CONT = 1) . . . . .395
16.4.15Starting conversions (ADSTART, JADSTART) . . . . .396
16.4.16ADC timing . . . . .397
16.4.17Stopping an ongoing conversion (ADSTP, JADSTP) . . . . .397
16.4.18Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . .399
16.4.19Injected channel management . . . . .401
16.4.20Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . .403
16.4.21Queue of context for injected conversions . . . . .404
16.4.22Programmable resolution (RES) - Fast conversion mode . . . . .412
16.4.23End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . . . .413
16.4.24End of conversion sequence (EOS, JEOS) . . . . .413
16.4.25Timing diagrams example (single/continuous modes, hardware/software triggers) . . . . .414
16.4.26Data management . . . . .416
16.4.27Managing conversions using the DFSDM . . . . .421
16.4.28Dynamic low-power features . . . . .422
16.4.29Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . .427
16.4.30Oversampler . . . . .431
16.4.31Dual ADC modes . . . . .437
16.4.32Temperature sensor . . . . .450
16.4.33VBAT supply monitoring . . . . .452
16.4.34Monitoring the internal voltage reference . . . . .453
16.5ADC in low-power mode . . . . .455
16.6ADC interrupts . . . . .455
16.7ADC registers (for each ADC) . . . . .457
16.7.1ADC interrupt and status register (ADC_ISR) . . . . .457
16.7.2ADC interrupt enable register (ADC_IER) . . . . .459
16.7.3ADC control register (ADC_CR) . . . . .461
16.7.4ADC configuration register (ADC_CFGR) . . . . .464
16.7.5ADC configuration register 2 (ADC_CFGR2) . . . . .468
16.7.6ADC sample time register 1 (ADC_SMPR1) . . . . .470
16.7.7ADC sample time register 2 (ADC_SMPR2) . . . . .471
16.7.8ADC watchdog threshold register 1 (ADC_TR1) . . . . .472
16.7.9ADC watchdog threshold register 2 (ADC_TR2) . . . . .473
16.7.10ADC watchdog threshold register 3 (ADC_TR3) . . . . .473
16.7.11ADC regular sequence register 1 (ADC_SQR1) . . . . .474
16.7.12ADC regular sequence register 2 (ADC_SQR2) . . . . .475
16.7.13ADC regular sequence register 3 (ADC_SQR3) . . . . .476
16.7.14ADC regular sequence register 4 (ADC_SQR4) . . . . .477
16.7.15ADC regular data register (ADC_DR) . . . . .478
16.7.16ADC injected sequence register (ADC_JSQR) . . . . .478
16.7.17ADC offset y register (ADC_OF Ry) . . . . .480
16.7.18ADC injected channel y data register (ADC_JDRy) . . . . .481
16.7.19ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . .481
16.7.20ADC analog watchdog 3 configuration register (ADC_AWD3CR) . . . . .482
16.7.21ADC differential mode selection register (ADC_DIFSEL) . . . . .482
16.7.22ADC calibration factors (ADC_CALFACT) . . . . .483
16.8ADC common registers . . . . .483
16.8.1ADC common status register (ADC_CSR) . . . . .483
16.8.2ADC common control register (ADC_CCR) . . . . .485
16.8.3ADC common regular data register for dual mode (ADC_CDR) . . . . .488
16.9ADC register map . . . . .488
17Digital-to-analog converter (DAC) . . . . .492
17.1Introduction . . . . .492
17.2DAC main features . . . . .492
17.3DAC implementation . . . . .493
17.4DAC functional description . . . . .494
17.4.1DAC block diagram . . . . .494
17.4.2DAC channel enable . . . . .495
17.4.3DAC data format . . . . .495
17.4.4DAC conversion . . . . .497
17.4.5DAC output voltage . . . . .497
17.4.6DAC trigger selection . . . . .497
17.4.7DMA requests . . . . .498
17.4.8Noise generation . . . . .499
17.4.9Triangle-wave generation . . . . .500
17.4.10DAC channel modes . . . . .501
17.4.11DAC channel buffer calibration . . . . .504
17.4.12Dual DAC channel conversion modes (if dual channels are available) . . . . .505
17.5DAC in low-power modes . . . . .509
17.6DAC interrupts . . . . .510
17.7DAC registers . . . . .510
17.7.1DAC control register (DAC_CR) . . . . .510
17.7.2DAC software trigger register (DAC_SWTRGR) . . . . .513
17.7.3DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . .514
17.7.4DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) . . . . .514
17.7.5DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) . . . . .515
17.7.6DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) . . . . .515
17.7.7DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) . . . . .516
17.7.8DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . .516
17.7.9Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . .517
17.7.10Dual DAC 12-bit left aligned data holding register (DAC_DHR12LD) . . . . .517
17.7.11Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD) . . . . .518
17.7.12DAC channel1 data output register (DAC_DOR1) . . . . .518
17.7.13DAC channel2 data output register (DAC_DOR2) . . . . .519
17.7.14DAC status register (DAC_SR) . . . . .519
17.7.15DAC calibration control register (DAC_CCR) . . . . .521
17.7.16DAC mode control register (DAC_MCR) . . . . .521
17.7.17DAC channel1 sample and hold sample time register
(DAC_SHSR1) . . . . .		523
17.7.18DAC channel2 sample and hold sample time register
(DAC_SHSR2) . . . . .		523
17.7.19DAC sample and hold time register (DAC_SHHR) . . . . .523
17.7.20DAC sample and hold refresh time register (DAC_SHRR) . . . . .524
17.7.21DAC register map . . . . .525
18Voltage reference buffer (VREFBUF) . . . . .528
18.1Introduction . . . . .528
18.2VREFBUF functional description . . . . .528
18.3VREFBUF registers . . . . .529
18.3.1VREFBUF control and status register (VREFBUF_CSR) . . . . .529
18.3.2VREFBUF calibration control register (VREFBUF_CCR) . . . . .530
18.3.3VREFBUF register map . . . . .530
19Comparator (COMP) . . . . .531
19.1Introduction . . . . .531
19.2COMP main features . . . . .531
19.3COMP functional description . . . . .532
19.3.1COMP block diagram . . . . .532
19.3.2COMP pins and internal signals . . . . .532
19.3.3COMP reset and clocks . . . . .534
19.3.4Comparator LOCK mechanism . . . . .534
19.3.5Window comparator . . . . .534
19.3.6Hysteresis . . . . .535
19.3.7Comparator output blanking function . . . . .536
19.3.8COMP power and speed modes . . . . .536
19.4COMP low-power modes . . . . .537
19.5COMP interrupts . . . . .537
19.6COMP registers . . . . .538
19.6.1Comparator 1 control and status register (COMP1_CSR) . . . . .538
19.6.2Comparator 2 control and status register (COMP2_CSR) . . . . .540
19.6.3COMP register map . . . . .543
20Operational amplifiers (OPAMP) . . . . .544
20.1Introduction . . . . .544
20.2OPAMP main features . . . . .544
20.3OPAMP functional description . . . . .544
20.3.1OPAMP reset and clocks . . . . .544
20.3.2Initial configuration . . . . .545
20.3.3Signal routing . . . . .545
20.3.4OPAMP modes . . . . .545
20.3.5Calibration . . . . .549
20.4OPAMP low-power modes . . . . .551
20.5OPAMP registers . . . . .552
20.5.1OPAMP1 control/status register (OPAMP1_CSR) . . . . .552
20.5.2OPAMP1 offset trimming register in normal mode (OPAMP1_OTR) . . . . .553
20.5.3OPAMP1 offset trimming register in low-power mode
(OPAMP1_LPOTR) . . . . .		553
20.5.4OPAMP register map . . . . .554
21Digital filter for sigma delta modulators (DFSDM) . . . . .555
21.1Introduction . . . . .555
21.2DFSDM main features . . . . .556
21.3DFSDM implementation . . . . .557
21.4DFSDM functional description . . . . .558
21.4.1DFSDM block diagram . . . . .558
21.4.2DFSDM pins and internal signals . . . . .559
21.4.3DFSDM reset and clocks . . . . .560
21.4.4Serial channel transceivers . . . . .561
21.4.5Configuring the input serial interface . . . . .570
21.4.6Parallel data inputs . . . . .570
21.4.7Channel selection . . . . .572
21.4.8Digital filter configuration . . . . .572
21.4.9Integrator unit . . . . .574
21.4.10Analog watchdog . . . . .574
21.4.11Short-circuit detector . . . . .577
21.4.12Extreme detector . . . . .577
21.4.13Data unit block . . . . .578
21.4.14Signed data format . . . . .579
21.4.15Launching conversions . . . . .579
21.4.16Continuous and fast continuous modes . . . . .580
21.4.17Request precedence . . . . .580
21.4.18Power optimization in run mode . . . . .581
21.5DFSDM interrupts . . . . .581
21.6DFSDM DMA transfer . . . . .583
21.7DFSDM channel y registers (y=0..3) . . . . .583
21.7.1DFSDM channel y configuration register (DFSDM_CHyCFGGR1) . . . . .583
21.7.2DFSDM channel y configuration register (DFSDM_CHyCFGGR2) . . . . .586
21.7.3DFSDM channel y analog watchdog and short-circuit detector register (DFSDM_CHyAWSCDR) . . . . .586
21.7.4DFSDM channel y watchdog filter data register (DFSDM_CHyWDATR) . . . . .587
21.7.5DFSDM channel y data input register (DFSDM_CHyDATINR) . . . . .588
21.8DFSDM filter x module registers (x=0..1) . . . . .589
21.8.1DFSDM filter x control register 1 (DFSDM_FLTxCR1) . . . . .589
21.8.2DFSDM filter x control register 2 (DFSDM_FLTxCR2) . . . . .591
21.8.3DFSDM filter x interrupt and status register (DFSDM_FLTxISR) . . . . .593
21.8.4DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) . . . . .594
21.8.5DFSDM filter x injected channel group selection register (DFSDM_FLTxJCHGR) . . . . .595
21.8.6DFSDM filter x control register (DFSDM_FLTxFCR) . . . . .596
21.8.7DFSDM filter x data register for injected group (DFSDM_FLTxJDATAR) . . . . .597
21.8.8DFSDM filter x data register for the regular channel (DFSDM_FLTxRDATAR) . . . . .598
21.8.9DFSDM filter x analog watchdog high threshold register (DFSDM_FLTxAWHTR) . . . . .598
21.8.10DFSDM filter x analog watchdog low threshold register (DFSDM_FLTxAWLTR) . . . . .599
21.8.11DFSDM filter x analog watchdog status register (DFSDM_FLTxAWSR) . . . . .600
21.8.12DFSDM filter x analog watchdog clear flag register (DFSDM_FLTxAWCFR) . . . . .600
21.8.13DFSDM filter x extremes detector maximum register (DFSDM_FLTxEXMAX) . . . . .601
21.8.14DFSDM filter x extremes detector minimum register (DFSDM_FLTxEXMIN) . . . . .601
21.8.15DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR) . . . . .602
21.8.16DFSDM register map . . . . .603
22Liquid crystal display controller (LCD) . . . . .608
22.1LCD introduction . . . . .608
22.2LCD main features . . . . .608
22.3LCD functional description . . . . .610
22.3.1General description . . . . .610
22.3.2Frequency generator . . . . .611
22.3.3Common driver . . . . .612
22.3.4Segment driver . . . . .615
22.3.5Voltage generator and contrast control . . . . .619
22.3.6Double-buffer memory . . . . .622
22.3.7COM and SEG multiplexing . . . . .622
22.3.8Flowchart . . . . .628
22.4LCD low-power modes . . . . .629
22.5LCD interrupts . . . . .629
22.6LCD registers . . . . .630
22.6.1LCD control register (LCD_CR) . . . . .630
22.6.2LCD frame control register (LCD_FCR) . . . . .631
22.6.3LCD status register (LCD_SR) . . . . .633
22.6.4LCD clear register (LCD_CLR) . . . . .635
22.6.5LCD display memory (LCD_RAMx) . . . . .635
22.6.6LCD display memory (LCD_RAMx) . . . . .636
22.6.7LCD display memory (LCD_RAMx) . . . . .636
22.6.8LCD register map . . . . .636
23Touch sensing controller (TSC) . . . . .639
23.1Introduction . . . . .639
23.2TSC main features . . . . .639
23.3TSC functional description . . . . .640
23.3.1TSC block diagram . . . . .640
23.3.2Surface charge transfer acquisition overview . . . . .640
23.3.3Reset and clocks . . . . .643
23.3.4Charge transfer acquisition sequence . . . . .643
23.3.5Spread spectrum feature . . . . .644
23.3.6Max count error . . . . .645
23.3.7Sampling capacitor I/O and channel I/O mode selection . . . . .645
23.3.8Acquisition mode . . . . .646
24.7.1RNG control register (RNG_CR) . . . . .664
24.7.2RNG status register (RNG_SR) . . . . .665
24.7.3RNG data register (RNG_DR) . . . . .666
24.7.4RNG register map . . . . .667
25AES hardware accelerator (AES) . . . . .668
25.1Introduction . . . . .668
25.2AES main features . . . . .668
25.3AES implementation . . . . .669
25.4AES functional description . . . . .669
25.4.1AES block diagram . . . . .669
25.4.2AES internal signals . . . . .669
25.4.3AES cryptographic core . . . . .670
25.4.4AES procedure to perform a cipher operation . . . . .675
25.4.5AES decryption key preparation . . . . .679
25.4.6AES ciphertext stealing and data padding . . . . .680
25.4.7AES task suspend and resume . . . . .681
25.4.8AES basic chaining modes (ECB, CBC) . . . . .682
25.4.9AES counter (CTR) mode . . . . .687
25.4.10AES Galois/counter mode (GCM) . . . . .689
25.4.11AES Galois message authentication code (GMAC) . . . . .694
25.4.12AES counter with CBC-MAC (CCM) . . . . .696
25.4.13AES data registers and data swapping . . . . .701
25.4.14AES key registers . . . . .703
25.4.15AES initialization vector registers . . . . .703
25.4.16AES DMA interface . . . . .703
25.4.17AES error management . . . . .706
25.5AES interrupts . . . . .706
25.6AES processing latency . . . . .707
25.7AES registers . . . . .708
25.7.1AES control register (AES_CR) . . . . .708
25.7.2AES status register (AES_SR) . . . . .711
25.7.3AES data input register (AES_DINR) . . . . .712
25.7.4AES data output register (AES_DOUTR) . . . . .713
25.7.5AES key register 0 (AES_KEYR0) . . . . .713
25.7.6AES key register 1 (AES_KEYR1) . . . . .714
25.7.7AES key register 2 (AES_KEYR2) . . . . .714
25.7.8AES key register 3 (AES_KEYR3) . . . . .715
25.7.9AES initialization vector register 0 (AES_IVR0) . . . . .715
25.7.10AES initialization vector register 1 (AES_IVR1) . . . . .715
25.7.11AES initialization vector register 2 (AES_IVR2) . . . . .716
25.7.12AES initialization vector register 3 (AES_IVR3) . . . . .716
25.7.13AES key register 4 (AES_KEYR4) . . . . .717
25.7.14AES key register 5 (AES_KEYR5) . . . . .717
25.7.15AES key register 6 (AES_KEYR6) . . . . .717
25.7.16AES key register 7 (AES_KEYR7) . . . . .718
25.7.17AES suspend registers (AES_SUSPxR) . . . . .718
25.7.18AES register map . . . . .719
26Advanced-control timer (TIM1) . . . . .721
26.1TIM1 introduction . . . . .721
26.2TIM1 main features . . . . .722
26.3TIM1 functional description . . . . .724
26.3.1Time-base unit . . . . .724
26.3.2Counter modes . . . . .726
26.3.3Repetition counter . . . . .737
26.3.4External trigger input . . . . .739
26.3.5Clock selection . . . . .740
26.3.6Capture/compare channels . . . . .744
26.3.7Input capture mode . . . . .747
26.3.8PWM input mode . . . . .748
26.3.9Forced output mode . . . . .748
26.3.10Output compare mode . . . . .749
26.3.11PWM mode . . . . .750
26.3.12Asymmetric PWM mode . . . . .753
26.3.13Combined PWM mode . . . . .754
26.3.14Combined 3-phase PWM mode . . . . .755
26.3.15Complementary outputs and dead-time insertion . . . . .756
26.3.16Using the break function . . . . .758
26.3.17Bidirectional break inputs . . . . .764
26.3.18Clearing the OCxREF signal on an external event . . . . .765
26.3.196-step PWM generation . . . . .766
26.3.20One-pulse mode . . . . .767
26.3.21Retriggerable one pulse mode . . . . .768
26.3.22Encoder interface mode . . . . .769
26.3.23UIF bit remapping . . . . .771
26.3.24Timer input XOR function . . . . .772
26.3.25Interfacing with Hall sensors . . . . .772
26.3.26Timer synchronization . . . . .775
26.3.27ADC synchronization . . . . .779
26.3.28DMA burst mode . . . . .779
26.3.29Debug mode . . . . .780
26.4TIM1 registers . . . . .781
26.4.1TIM1 control register 1 (TIM1_CR1) . . . . .781
26.4.2TIM1 control register 2 (TIM1_CR2) . . . . .782
26.4.3TIM1 slave mode control register
(TIM1_SMCR) . . . . .		785
26.4.4TIM1 DMA/interrupt enable register
(TIM1_DIER) . . . . .		787
26.4.5TIM1 status register (TIM1_SR) . . . . .789
26.4.6TIM1 event generation register (TIM1_EGR) . . . . .791
26.4.7TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . .792
26.4.8TIM1 capture/compare mode register 1 [alternate]
(TIM1_CCMR1) . . . . .		793
26.4.9TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . .796
26.4.10TIM1 capture/compare mode register 2 [alternate]
(TIM1_CCMR2) . . . . .		797
26.4.11TIM1 capture/compare enable register
(TIM1_CCER) . . . . .		799
26.4.12TIM1 counter (TIM1_CNT) . . . . .802
26.4.13TIM1 prescaler (TIM1_PSC) . . . . .802
26.4.14TIM1 auto-reload register (TIM1_ARR) . . . . .802
26.4.15TIM1 repetition counter register (TIM1_RCR) . . . . .803
26.4.16TIM1 capture/compare register 1
(TIM1_CCR1) . . . . .		803
26.4.17TIM1 capture/compare register 2
(TIM1_CCR2) . . . . .		804
26.4.18TIM1 capture/compare register 3
(TIM1_CCR3) . . . . .		804
26.4.19TIM1 capture/compare register 4
(TIM1_CCR4) . . . . .		805
26.4.20TIM1 break and dead-time register
(TIM1_BDTR) . . . . .		805
27.3.20DMA burst mode .....863
27.3.21Debug mode .....864
27.4TIM2/TIM3 registers .....865
27.4.1TIMx control register 1 (TIMx_CR1)(x = 2 to 3) .....865
27.4.2TIMx control register 2 (TIMx_CR2)(x = 2 to 3) .....866
27.4.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 3) .....868
27.4.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 3) .....871
27.4.5TIMx status register (TIMx_SR)(x = 2 to 3) .....872
27.4.6TIMx event generation register (TIMx_EGR)(x = 2 to 3) .....873
27.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 3) ..874
27.4.8TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 3) .....		876
27.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 3) ..878
27.4.10TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 3) .....		879
27.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 3) .....		880
27.4.12TIMx counter (TIMx_CNT)(x = 2 to 3) .....881
27.4.13TIMx counter [alternate] (TIMx_CNT)(x = 2 to 3) .....882
27.4.14TIMx prescaler (TIMx_PSC)(x = 2 to 3) .....882
27.4.15TIMx auto-reload register (TIMx_ARR)(x = 2 to 3) .....883
27.4.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 3) .....883
27.4.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 3) .....884
27.4.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 3) .....884
27.4.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 3) .....885
27.4.20TIMx DMA control register (TIMx_DCR)(x = 2 to 3) .....886
27.4.21TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 3) .....886
27.4.22TIM2 option register 1 (TIM2_OR1) .....886
27.4.23TIM2 option register 2 (TIM2_OR2) .....887
27.4.24TIMx register map .....888
28General-purpose timers (TIM15/TIM16) .....891
28.1TIM15/TIM16 introduction .....891
28.2TIM15 main features .....891
28.3TIM16 main features .....892
28.4Implementation .....894
28.5TIM15/TIM16 functional description .....895
28.5.1Time-base unit . . . . .895
28.5.2Counter modes . . . . .897
28.5.3Repetition counter . . . . .901
28.5.4Clock selection . . . . .902
28.5.5Capture/compare channels . . . . .904
28.5.6Input capture mode . . . . .906
28.5.7PWM input mode (only for TIM15) . . . . .907
28.5.8Forced output mode . . . . .908
28.5.9Output compare mode . . . . .909
28.5.10PWM mode . . . . .910
28.5.11Combined PWM mode (TIM15 only) . . . . .911
28.5.12Complementary outputs and dead-time insertion . . . . .912
28.5.13Using the break function . . . . .914
28.5.146-step PWM generation . . . . .919
28.5.15One-pulse mode . . . . .920
28.5.16Retriggerable one pulse mode (TIM15 only) . . . . .921
28.5.17UIF bit remapping . . . . .922
28.5.18Timer input XOR function (TIM15 only) . . . . .923
28.5.19External trigger synchronization (TIM15 only) . . . . .924
28.5.20Slave mode – combined reset + trigger mode . . . . .926
28.5.21DMA burst mode . . . . .926
28.5.22Timer synchronization (TIM15) . . . . .928
28.5.23Using timer output as trigger for other timers (TIM16) . . . . .928
28.5.24Debug mode . . . . .928
28.6TIM15 registers . . . . .929
28.6.1TIM15 control register 1 (TIM15_CR1) . . . . .929
28.6.2TIM15 control register 2 (TIM15_CR2) . . . . .930
28.6.3TIM15 slave mode control register (TIM15_SMCR) . . . . .932
28.6.4TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .933
28.6.5TIM15 status register (TIM15_SR) . . . . .934
28.6.6TIM15 event generation register (TIM15_EGR) . . . . .936
28.6.7TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . .937
28.6.8TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		938
28.6.9TIM15 capture/compare enable register (TIM15_CCER) . . . . .941
28.6.10TIM15 counter (TIM15_CNT) . . . . .944
28.6.11TIM15 prescaler (TIM15_PSC) . . . . .944
28.6.12TIM15 auto-reload register (TIM15_ARR) . . . . .944
28.6.13TIM15 repetition counter register (TIM15_RCR) . . . . .945
28.6.14TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .945
28.6.15TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .946
28.6.16TIM15 break and dead-time register (TIM15_BDTR) . . . . .946
28.6.17TIM15 DMA control register (TIM15_DCR) . . . . .948
28.6.18TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .949
28.6.19TIM15 option register 1 (TIM15_OR1) . . . . .949
28.6.20TIM15 option register 2 (TIM15_OR2) . . . . .950
28.6.21TIM15 register map . . . . .951
28.7TIM16 registers . . . . .954
28.7.1TIM16 control register 1 (TIM16_CR1) . . . . .954
28.7.2TIM16 control register 2 (TIM16_CR2) . . . . .955
28.7.3TIM16 DMA/interrupt enable register (TIM16_DIER) . . . . .956
28.7.4TIM16 status register (TIM16_SR) . . . . .957
28.7.5TIM16 event generation register (TIM16_EGR) . . . . .958
28.7.6TIM16 capture/compare mode register 1 (TIM16_CCMR1) . . . . .959
28.7.7TIM16 capture/compare mode register 1 [alternate] (TIM16_CCMR1) . . . . .960
28.7.8TIM16 capture/compare enable register (TIM16_CCER) . . . . .962
28.7.9TIM16 counter (TIM16_CNT) . . . . .964
28.7.10TIM16 prescaler (TIM16_PSC) . . . . .965
28.7.11TIM16 auto-reload register (TIM16_ARR) . . . . .965
28.7.12TIM16 repetition counter register (TIM16_RCR) . . . . .966
28.7.13TIM16 capture/compare register 1 (TIM16_CCR1) . . . . .966
28.7.14TIM16 break and dead-time register (TIM16_BDTR) . . . . .967
28.7.15TIM16 DMA control register (TIM16_DCR) . . . . .969
28.7.16TIM16 DMA address for full transfer (TIM16_DMAR) . . . . .969
28.7.17TIM16 option register 1 (TIM16_OR1) . . . . .970
28.7.18TIM16 option register 2 (TIM16_OR2) . . . . .970
28.7.19TIM16 register map . . . . .972
29Basic timers (TIM6/TIM7) . . . . .974
29.1TIM6/TIM7 introduction . . . . .974
29.2TIM6/TIM7 main features . . . . .974
29.3TIM6/TIM7 functional description . . . . .975
29.3.1Time-base unit . . . . .975
29.3.2Counting mode . . . . .977
30.7LPTIM registers . . . . .999
30.7.1LPTIM interrupt and status register (LPTIM_ISR) . . . . .1000
30.7.2LPTIM interrupt clear register (LPTIM_ICR) . . . . .1001
30.7.3LPTIM interrupt enable register (LPTIM_IER) . . . . .1001
30.7.4LPTIM configuration register (LPTIM_CFGR) . . . . .1002
30.7.5LPTIM control register (LPTIM_CR) . . . . .1005
30.7.6LPTIM compare register (LPTIM_CMP) . . . . .1006
30.7.7LPTIM autoreload register (LPTIM_ARR) . . . . .1007
30.7.8LPTIM counter register (LPTIM_CNT) . . . . .1007
30.7.9LPTIM1 option register (LPTIM1_OR) . . . . .1008
30.7.10LPTIM2 option register (LPTIM2_OR) . . . . .1008
30.7.11LPTIM register map . . . . .1009
31Low-power timer (LPTIM) . . . . .1010
31.1Introduction . . . . .1010
31.2LPTIM main features . . . . .1010
31.3LPTIM implementation . . . . .1010
31.4LPTIM functional description . . . . .1011
31.4.1LPTIM block diagram . . . . .1011
31.4.2LPTIM pins and internal signals . . . . .1011
31.4.3LPTIM input and trigger mapping . . . . .1012
31.4.4LPTIM reset and clocks . . . . .1013
31.4.5Glitch filter . . . . .1013
31.4.6Prescaler . . . . .1014
31.4.7Trigger multiplexer . . . . .1014
31.4.8Operating mode . . . . .1015
31.4.9Timeout function . . . . .1017
31.4.10Waveform generation . . . . .1017
31.4.11Register update . . . . .1018
31.4.12Counter mode . . . . .1019
31.4.13Timer enable . . . . .1020
31.4.14Timer counter reset . . . . .1020
31.4.15Encoder mode . . . . .1021
31.4.16Repetition counter . . . . .1022
31.4.17Debug mode . . . . .1023
31.5LPTIM low-power modes . . . . .1024
31.6LPTIM interrupts . . . . .1024
31.7LPTIM registers . . . . .1025
31.7.1LPTIM interrupt and status register (LPTIM_ISR) . . . . .1025
31.7.2LPTIM interrupt clear register (LPTIM_ICR) . . . . .1026
31.7.3LPTIM interrupt enable register (LPTIM_IER) . . . . .1027
31.7.4LPTIM configuration register (LPTIM_CFGR) . . . . .1028
31.7.5LPTIM control register (LPTIM_CR) . . . . .1031
31.7.6LPTIM compare register (LPTIM_CMP) . . . . .1032
31.7.7LPTIM autoreload register (LPTIM_ARR) . . . . .1032
31.7.8LPTIM counter register (LPTIM_CNT) . . . . .1033
31.7.9LPTIM configuration register 2 (LPTIM_CFGR2) . . . . .1033
31.7.10LPTIM repetition register (LPTIM_RCR) . . . . .1034
31.7.11LPTIM register map . . . . .1034
32Infrared interface (IRTIM) . . . . .1036
33Independent watchdog (IWDG) . . . . .1037
33.1Introduction . . . . .1037
33.2IWDG main features . . . . .1037
33.3IWDG functional description . . . . .1037
33.3.1IWDG block diagram . . . . .1037
33.3.2Window option . . . . .1038
33.3.3Hardware watchdog . . . . .1039
33.3.4Low-power freeze . . . . .1039
33.3.5Register access protection . . . . .1039
33.3.6Debug mode . . . . .1039
33.4IWDG registers . . . . .1040
33.4.1IWDG key register (IWDG_KR) . . . . .1040
33.4.2IWDG prescaler register (IWDG_PR) . . . . .1041
33.4.3IWDG reload register (IWDG_RLR) . . . . .1042
33.4.4IWDG status register (IWDG_SR) . . . . .1043
33.4.5IWDG window register (IWDG_WINR) . . . . .1044
33.4.6IWDG register map . . . . .1045
34System window watchdog (WWDG) . . . . .1046
34.1Introduction . . . . .1046
34.2WWDG main features . . . . .1046
34.3WWDG functional description . . . . .1046
34.3.1WWDG block diagram . . . . .1047
34.3.2Enabling the watchdog . . . . .1047
34.3.3Controlling the down-counter . . . . .1047
34.3.4How to program the watchdog timeout . . . . .1047
34.3.5Debug mode . . . . .1048
34.4WWDG interrupts . . . . .1049
34.5WWDG registers . . . . .1049
34.5.1WWDG control register (WWDG_CR) . . . . .1049
34.5.2WWDG configuration register (WWDG_CFR) . . . . .1050
34.5.3WWDG status register (WWDG_SR) . . . . .1050
34.5.4WWDG register map . . . . .1051
35Real-time clock (RTC) applied to
STM32L41xxx and STM32L42xxx devices only . . . . .		1052
35.1Introduction . . . . .1052
35.2RTC main features . . . . .1052
35.3RTC functional description . . . . .1053
35.3.1RTC block diagram . . . . .1053
35.3.2RTC pins and internal signals . . . . .1055
35.3.3GPIOs controlled by the RTC and TAMP . . . . .1056
35.3.4Clock and prescalers . . . . .1058
35.3.5Real-time clock and calendar . . . . .1059
35.3.6Calendar ultra-low power mode . . . . .1059
35.3.7Programmable alarms . . . . .1059
35.3.8Periodic auto-wake-up . . . . .1060
35.3.9RTC initialization and configuration . . . . .1061
35.3.10Reading the calendar . . . . .1063
35.3.11Resetting the RTC . . . . .1064
35.3.12RTC synchronization . . . . .1064
35.3.13RTC reference clock detection . . . . .1064
35.3.14RTC smooth digital calibration . . . . .1065
35.3.15Timestamp function . . . . .1067
35.3.16Calibration clock output . . . . .1068
35.3.17Tamper and alarm output . . . . .1069
35.4RTC low-power modes . . . . .1069
35.5RTC interrupts . . . . .1070
35.6RTC registers . . . . .1071
35.6.1RTC time register (RTC_TR) . . . . .1071
35.6.2RTC date register (RTC_DR) . . . . .1072
35.6.3RTC sub second register (RTC_SSR) . . . . .1073
35.6.4RTC initialization control and status register (RTC_ICSR) . . . . .1073
35.6.5RTC prescaler register (RTC_PRER) . . . . .1075
35.6.6RTC wake-up timer register (RTC_WUTR) . . . . .1075
35.6.7RTC control register (RTC_CR) . . . . .1076
35.6.8RTC write protection register (RTC_WPR) . . . . .1079
35.6.9RTC calibration register (RTC_CALR) . . . . .1080
35.6.10RTC shift control register (RTC_SHIFTR) . . . . .1081
35.6.11RTC timestamp time register (RTC_TSTR) . . . . .1082
35.6.12RTC timestamp date register (RTC_TSDR) . . . . .1082
35.6.13RTC timestamp sub second register (RTC_TSSSR) . . . . .1083
35.6.14RTC alarm A register (RTC_ALRMAR) . . . . .1083
35.6.15RTC alarm A sub second register (RTC_ALRMASSR) . . . . .1084
35.6.16RTC alarm B register (RTC_ALRMBR) . . . . .1085
35.6.17RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .1086
35.6.18RTC status register (RTC_SR) . . . . .1087
35.6.19RTC masked interrupt status register (RTC_MISR) . . . . .1088
35.6.20RTC status clear register (RTC_SCR) . . . . .1089
35.6.21RTC register map . . . . .1090
36Tamper and backup registers (TAMP) applied to
STM32L41xxx and STM32L42xxx devices only . . . . .		1092
36.1Introduction . . . . .1092
36.2TAMP main features . . . . .1092
36.3TAMP functional description . . . . .1093
36.3.1TAMP block diagram . . . . .1093
36.3.2TAMP pins and internal signals . . . . .1093
36.3.3TAMP register write protection . . . . .1094
36.3.4Tamper detection . . . . .1094
36.4TAMP low-power modes . . . . .1097
36.5TAMP interrupts . . . . .1097
36.6TAMP registers . . . . .1097
36.6.1TAMP control register 1 (TAMP_CR1) . . . . .1098
36.6.2TAMP control register 2 (TAMP_CR2) . . . . .1099
36.6.3TAMP filter control register (TAMP_FLTCR) . . . . .1100
36.6.4TAMP interrupt enable register (TAMP_IER) . . . . .1101
36.6.5TAMP status register (TAMP_SR) . . . . .1102
36.6.6TAMP masked interrupt status register (TAMP_MISR) . . . . .1103
36.6.7TAMP status clear register (TAMP_SCR) . . . . .1103
36.6.8TAMP backup x register (TAMP_BKPxR) . . . . .1104
36.6.9TAMP register map . . . . .1105
37Real-time clock (RTC) applied to
STM32L43x/44x/45x/46x devices only . . . . .		1106
37.1Introduction . . . . .1106
37.2RTC main features . . . . .1107
37.3RTC functional description . . . . .1108
37.3.1RTC block diagram . . . . .1108
37.3.2GPIOs controlled by the RTC . . . . .1109
37.3.3Clock and prescalers . . . . .1111
37.3.4Real-time clock and calendar . . . . .1112
37.3.5Programmable alarms . . . . .1112
37.3.6Periodic auto-wake-up . . . . .1112
37.3.7RTC initialization and configuration . . . . .1113
37.3.8Reading the calendar . . . . .1115
37.3.9Resetting the RTC . . . . .1116
37.3.10RTC synchronization . . . . .1116
37.3.11RTC reference clock detection . . . . .1117
37.3.12RTC smooth digital calibration . . . . .1117
37.3.13Time-stamp function . . . . .1119
37.3.14Tamper detection . . . . .1120
37.3.15Calibration clock output . . . . .1122
37.3.16Alarm output . . . . .1123
37.4RTC low-power modes . . . . .1123
37.5RTC interrupts . . . . .1123
37.6RTC registers . . . . .1124
37.6.1RTC time register (RTC_TR) . . . . .1124
37.6.2RTC date register (RTC_DR) . . . . .1125
37.6.3RTC control register (RTC_CR) . . . . .1127
37.6.4RTC initialization and status register (RTC_ISR) . . . . .1130
37.6.5RTC prescaler register (RTC_PRER) . . . . .1133
37.6.6RTC wake-up timer register (RTC_WUTR) . . . . .1134
37.6.7RTC alarm A register (RTC_ALRMAR) . . . . .1135
37.6.8RTC alarm B register (RTC_ALRMBR) . . . . .1136
37.6.9RTC write protection register (RTC_WPR) . . . . .1137
37.6.10RTC sub second register (RTC_SSR) . . . . .1137
37.6.11RTC shift control register (RTC_SHIFTR) . . . . .1138
37.6.12RTC timestamp time register (RTC_TSTR) . . . . .1139
37.6.13RTC timestamp date register (RTC_TSDR) . . . . .1140
37.6.14RTC time-stamp sub second register (RTC_TSSSR) . . . . .1141
37.6.15RTC calibration register (RTC_CALR) . . . . .1142
37.6.16RTC tamper configuration register (RTC_TAMPCR) . . . . .1143
37.6.17RTC alarm A sub second register (RTC_ALRMASSR) . . . . .1146
37.6.18RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .1147
37.6.19RTC option register (RTC_OR) . . . . .1148
37.6.20RTC backup registers (RTC_BKPxR) . . . . .1148
37.6.21RTC register map . . . . .1149
38Inter-integrated circuit interface (I2C) . . . . .1151
38.1Introduction . . . . .1151
38.2I2C main features . . . . .1151
38.3I2C implementation . . . . .1152
38.4I2C functional description . . . . .1152
38.4.1I2C block diagram . . . . .1153
38.4.2I2C pins and internal signals . . . . .1153
38.4.3I2C clock requirements . . . . .1154
38.4.4I2C mode selection . . . . .1154
38.4.5I2C initialization . . . . .1155
38.4.6I2C reset . . . . .1159
38.4.7I2C data transfer . . . . .1160
38.4.8I2C target mode . . . . .1162
38.4.9I2C controller mode . . . . .1171
38.4.10I2C_TIMINGR register configuration examples . . . . .1182
38.4.11SMBus specific features . . . . .1184
38.4.12SMBus initialization . . . . .1187
38.4.13SMBus I2C_TIMEOUTR register configuration examples . . . . .1189
38.4.14SMBus target mode . . . . .1189
38.4.15SMBus controller mode . . . . .1193
38.4.16Wake-up from Stop mode on address match . . . . .1196
38.4.17Error conditions . . . . .1197
38.5I2C in low-power modes . . . . .1199
38.6I2C interrupts . . . . .1199
38.7I2C DMA requests . . . . .1200
38.7.1Transmission using DMA . . . . .1200
38.7.2Reception using DMA . . . . .1200
38.8I2C debug modes . . . . .1201
38.9I2C registers . . . . .1201
38.9.1I2C control register 1 (I2C_CR1) . . . . .1201
38.9.2I2C control register 2 (I2C_CR2) . . . . .1203
38.9.3I2C own address 1 register (I2C_OAR1) . . . . .1205
38.9.4I2C own address 2 register (I2C_OAR2) . . . . .1206
38.9.5I2C timing register (I2C_TIMINGR) . . . . .1207
38.9.6I2C timeout register (I2C_TIMEOUTR) . . . . .1208
38.9.7I2C interrupt and status register (I2C_ISR) . . . . .1209
38.9.8I2C interrupt clear register (I2C_ICR) . . . . .1211
38.9.9I2C PEC register (I2C_PECR) . . . . .1212
38.9.10I2C receive data register (I2C_RXDR) . . . . .1212
38.9.11I2C transmit data register (I2C_TXDR) . . . . .1213
38.9.12I2C register map . . . . .1214
39Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .1215
39.1Introduction . . . . .1215
39.2USART main features . . . . .1215
39.3USART extended features . . . . .1216
39.4USART implementation . . . . .1217
39.5USART functional description . . . . .1217
39.5.1USART character description . . . . .1220
39.5.2USART transmitter . . . . .1222
39.5.3USART receiver . . . . .1224
39.5.4USART baud rate generation . . . . .1231

40 Low-power universal asynchronous receiver
transmitter (LPUART) . . . . . 1284

40.4.2LPUART transmitter . . . . .1290
40.4.3LPUART receiver . . . . .1292
40.4.4LPUART baud rate generation . . . . .1295
40.4.5Tolerance of the LPUART receiver to clock deviation . . . . .1297
40.4.6Multiprocessor communication using LPUART . . . . .1298
40.4.7LPUART parity control . . . . .1300
40.4.8Single-wire half-duplex communication using LPUART . . . . .1301
40.4.9Continuous communication in DMA mode using LPUART . . . . .1301
40.4.10RS232 hardware flow control and RS485 Driver Enable
using LPUART . . . . .		1304
40.4.11Wake-up from Stop mode using LPUART . . . . .1307
40.5LPUART in low-power mode . . . . .1308
40.6LPUART interrupts . . . . .1309
40.7LPUART registers . . . . .1311
40.7.1Control register 1 (LPUART_CR1) . . . . .1311
40.7.2Control register 2 (LPUART_CR2) . . . . .1314
40.7.3Control register 3 (LPUART_CR3) . . . . .1316
40.7.4Baud rate register (LPUART_BRR) . . . . .1318
40.7.5Request register (LPUART_RQR) . . . . .1318
40.7.6Interrupt & status register (LPUART_ISR) . . . . .1319
40.7.7Interrupt flag clear register (LPUART_ICR) . . . . .1322
40.7.8Receive data register (LPUART_RDR) . . . . .1323
40.7.9Transmit data register (LPUART_TDR) . . . . .1323
40.7.10LPUART register map . . . . .1325
41Serial peripheral interface (SPI) . . . . .1326
41.1Introduction . . . . .1326
41.2SPI main features . . . . .1326
41.3SPI implementation . . . . .1327
41.4SPI functional description . . . . .1327
41.4.1General description . . . . .1327
41.4.2Communications between one master and one slave . . . . .1328
41.4.3Standard multislave communication . . . . .1330
41.4.4Multimaster communication . . . . .1331
41.4.5Slave select (NSS) pin management . . . . .1332
41.4.6Communication formats . . . . .1333
41.4.7Configuration of SPI . . . . .1335

42 Serial audio interface (SAI) . . . . . 1361

42.4.14Disabling the SAI .....1386
42.4.15SAI DMA interface .....1386
42.5SAI interrupts .....1387
42.6SAI registers .....1389
42.6.1SAI configuration register 1 (SAI_ACR1) .....1389
42.6.2SAI configuration register 2 (SAI_ACR2) .....1391
42.6.3SAI frame configuration register (SAI_AFRCR) .....1393
42.6.4SAI slot register (SAI_ASLOTR) .....1394
42.6.5SAI interrupt mask register (SAI_AIM) .....1395
42.6.6SAI status register (SAI_ASR) .....1396
42.6.7SAI clear flag register (SAI_ACLRFR) .....1398
42.6.8SAI data register (SAI_ADR) .....1399
42.6.9SAI configuration register 1 (SAI_BCR1) .....1400
42.6.10SAI configuration register 2 (SAI_BCR2) .....1402
42.6.11SAI frame configuration register (SAI_BFRCR) .....1404
42.6.12SAI slot register (SAI_BSLOTR) .....1405
42.6.13SAI interrupt mask register (SAI_BIM) .....1406
42.6.14SAI status register (SAI_BSR) .....1407
42.6.15SAI clear flag register (SAI_BCLRFR) .....1409
42.6.16SAI data register (SAI_BDR) .....1410
42.6.17SAI register map .....1411
43Single wire protocol master interface (SWPMI) .....1412
43.1Introduction .....1412
43.2SWPMI main features .....1413
43.3SWPMI functional description .....1414
43.3.1SWPMI block diagram .....1414
43.3.2SWP initialization and activation .....1414
43.3.3SWP bus states .....1415
43.3.4SWPMI_IO (internal transceiver) bypass .....1416
43.3.5SWPMI bit rate .....1416
43.3.6SWPMI frame handling .....1417
43.3.7Transmission procedure .....1417
43.3.8Reception procedure .....1422
43.3.9Error management .....1426
43.3.10Loopback mode .....1428
44.5.1R1 (normal response command) .....1476
44.5.2R1b .....1476
44.5.3R2 (CID, CSD register) .....1476
44.5.4R3 (OCR register) .....1477
44.5.5R4 (Fast I/O) .....1477
44.5.6R4b .....1477
44.5.7R5 (interrupt request) .....1478
44.5.8R6 .....1478
44.6SDIO I/O card-specific operations .....1479
44.6.1SDIO I/O read wait operation by SDMMC_D2 signalling .....1479
44.6.2SDIO read wait operation by stopping SDMMC_CK .....1480
44.6.3SDIO suspend/resume operation .....1480
44.6.4SDIO interrupts .....1480
44.7HW flow control .....1480
44.8SDMMC registers .....1481
44.8.1SDMMC power control register (SDMMC_POWER) .....1481
44.8.2SDMMC clock control register (SDMMC_CLKCR) .....1481
44.8.3SDMMC argument register (SDMMC_ARG) .....1484
44.8.4SDMMC command register (SDMMC_CMD) .....1484
44.8.5SDMMC command response register (SDMMC_RESPCMD) .....1485
44.8.6SDMMC response 1..4 register (SDMMC_RESPx) .....1485
44.8.7SDMMC data timer register (SDMMC_DTIMER) .....1486
44.8.8SDMMC data length register (SDMMC_DLEN) .....1487
44.8.9SDMMC data control register (SDMMC_DCTRL) .....1487
44.8.10SDMMC data counter register (SDMMC_DCOUNT) .....1490
44.8.11SDMMC status register (SDMMC_STA) .....1490
44.8.12SDMMC interrupt clear register (SDMMC_ICR) .....1491
44.8.13SDMMC mask register (SDMMC_MASK) .....1493
44.8.14SDMMC FIFO counter register (SDMMC_FIFOCNT) .....1495
44.8.15SDMMC data FIFO register (SDMMC_FIFO) .....1496
44.8.16SDMMC register map .....1497
45Controller area network (bxCAN) .....1499
45.1Introduction .....1499
45.2bxCAN main features .....1499
45.3bxCAN general description .....1500
46.5.1Generic USB device programming . . . . .1545
46.5.2System and power-on reset . . . . .1546
46.5.3Double-buffered endpoints . . . . .1551
46.5.4Isochronous transfers . . . . .1553
46.5.5Suspend/Resume events . . . . .1554
46.6USB and USB SRAM registers . . . . .1557
46.6.1Common registers . . . . .1557
46.6.2Buffer descriptor table . . . . .1570
46.6.3USB register map . . . . .1573
47Debug support (DBG) . . . . .1575
47.1Overview . . . . .1575
47.2Reference Arm® documentation . . . . .1576
47.3SWJ debug port (serial wire and JTAG) . . . . .1576
47.3.1Mechanism to select the JTAG-DP or the SW-DP . . . . .1577
47.4Pinout and debug port pins . . . . .1577
47.4.1SWJ debug port pins . . . . .1578
47.4.2Flexible SWJ-DP pin assignment . . . . .1578
47.4.3Internal pull-up and pull-down on JTAG pins . . . . .1578
47.4.4Using serial wire and releasing the unused debug pins as GPIOs . . . . .1580
47.5STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx JTAG TAP connection . . . . .1580
47.6ID codes and locking mechanism . . . . .1581
47.6.1MCU device ID code . . . . .1582
47.6.2Boundary scan TAP . . . . .1582
47.6.3Cortex®-M4 TAP . . . . .1582
47.6.4Cortex®-M4 JEDEC-106 ID code . . . . .1583
47.7JTAG debug port . . . . .1583
47.8SW debug port . . . . .1585
47.8.1SW protocol introduction . . . . .1585
47.8.2SW protocol sequence . . . . .1585
47.8.3SW-DP state machine (reset, idle states, ID code) . . . . .1586
47.8.4DP and AP read/write accesses . . . . .1586
47.8.5SW-DP registers . . . . .1587
47.8.6SW-AP registers . . . . .1588
47.9AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP . . . . .		1588
47.10Core debug . . . . .1589
47.11Capability of the debugger host to connect under system reset . . . . .1589
47.12FPB (Flash patch breakpoint) . . . . .1590
47.13DWT (data watchpoint trigger) . . . . .1590
47.14ITM (instrumentation trace macrocell) . . . . .1591
47.14.1General description . . . . .1591
47.14.2Time stamp packets, synchronization and overflow packets . . . . .1591
47.15ETM (Embedded trace macrocell) . . . . .1593
47.15.1General description . . . . .1593
47.15.2Signal protocol, packet types . . . . .1593
47.15.3Main ETM registers . . . . .1593
47.15.4Configuration example . . . . .1594
47.16MCU debug component (DBGMCU) . . . . .1594
47.16.1Debug support for low-power modes . . . . .1594
47.16.2Debug support for timers, RTC, watchdog, bxCAN and I 2 C . . . . .1595
47.16.3Debug MCU configuration register (DBGMCU_CR) . . . . .1595
47.16.4Debug MCU APB1 freeze register1(DBGMCU_APB1FZR1) . . . . .1596
47.16.5Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2) . . . . .1597
47.16.6Debug MCU APB2 freeze register (DBGMCU_APB2FZR) . . . . .1598
47.17TPIU (trace port interface unit) . . . . .1599
47.17.1Introduction . . . . .1599
47.17.2TRACE pin assignment . . . . .1599
47.17.3TPUI formatter . . . . .1601
47.17.4TPUI frame synchronization packets . . . . .1602
47.17.5Transmission of the synchronization frame packet . . . . .1602
47.17.6Synchronous mode . . . . .1602
47.17.7Asynchronous mode . . . . .1603
47.17.8TRACECLKIN connection inside the
STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx . . . . .		1603
47.17.9TPIU registers . . . . .1604
47.17.10Example of configuration . . . . .1605
47.18DBG register map . . . . .1606
48Device electronic signature . . . . .1607
48.1Unique device ID register (96 bits) . . . . .1607
48.2Flash size data register . . . . .1608
48.3Package data register . . . . .1609
49Important security notice . . . . .1610
50Revision history . . . . .1611

List of tables

Table 1.Product specific features . . . . .65
Table 2.STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx memory map and peripheral register boundary addresses . . . . .72
Table 3.SRAM2 organization. . . . .76
Table 4.SRAM2 organization (continuation for STM32L43x/44x/45x/46x devices only) . . . . .76
Table 5.SRAM2 organization (continuation for STM32L45x and STM32L46x devices only) . . . . .77
Table 6.Boot modes. . . . .78
Table 7.Memory mapping vs. Boot mode/Physical remap. . . . .80
Table 8.Flash module - single bank organization . . . . .82
Table 9.Number of wait states according to CPU clock (HCLK) frequency. . . . .83
Table 10.Option byte format . . . . .92
Table 11.Option byte organization. . . . .92
Table 12.Flash memory read protection status . . . . .98
Table 13.Access status versus protection level and execution modes . . . . .100
Table 14.Flash interrupt request . . . . .103
Table 15.Flash interface - register map and reset values . . . . .116
Table 16.Segment accesses according to the Firewall state. . . . .121
Table 17.Segment granularity and area ranges . . . . .122
Table 18.Firewall register map and reset values . . . . .129
Table 19.PVM features . . . . .140
Table 20.Low-power mode summary . . . . .144
Table 21.Functionalities depending on the working mode. . . . .145
Table 22.Low-power run . . . . .149
Table 23.Sleep. . . . .150
Table 24.Low-power sleep. . . . .152
Table 25.Stop 0 mode . . . . .154
Table 26.Stop 1 mode . . . . .155
Table 27.Stop 2 mode . . . . .157
Table 28.Standby mode. . . . .159
Table 29.Shutdown mode . . . . .161
Table 30.PWR register map and reset values . . . . .177
Table 31.Clock source frequency . . . . .190
Table 32.RCC register map and reset values . . . . .247
Table 33.CRS features . . . . .251
Table 34.CRS internal input/output signals . . . . .252
Table 35.CRS interconnection. . . . .253
Table 36.Effect of low-power modes on CRS . . . . .256
Table 37.Interrupt control bits . . . . .256
Table 38.CRS register map and reset values . . . . .261
Table 39.Port bit configuration table . . . . .265
Table 40.Status of GPIO in low-power modes. . . . .272
Table 41.GPIO register map and reset values . . . . .279
Table 42.SYSCFG register map and reset values. . . . .292
Table 43.STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx peripherals interconnect matrix . . . . .293
Table 44.DMA1 and DMA2 implementation . . . . .301
Table 45.DMA1 requests for each channel . . . . .303
Table 46.DMA2 requests for each channel . . . . .304
Table 47.DMA internal input/output signals . . . . .306
Table 48.Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .311
Table 49.DMA interrupt requests . . . . .313
Table 50.DMA register map and reset values . . . . .322
Table 51.STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx vector table . . . . .326
Table 52.EXTI lines connections . . . . .333
Table 53.Extended interrupt/event controller register map and reset values. . . . .342
Table 54.CRC internal input/output signals . . . . .344
Table 55.CRC register map and reset values . . . . .349
Table 56.QUADSPI pins . . . . .351
Table 57.QUADSPI interrupt requests. . . . .365
Table 58.QUADSPI register map and reset values . . . . .376
Table 59.ADC features . . . . .380
Table 60.ADC internal input/output signals . . . . .382
Table 61.ADC input/output pins . . . . .382
Table 62.Configuring the trigger polarity for regular external triggers . . . . .399
Table 63.Configuring the trigger polarity for injected external triggers . . . . .399
Table 64.ADC1 and ADC2 - External triggers for regular channels. . . . .400
Table 65.ADC1 and ADC2 - External trigger for injected channels . . . . .401
Table 66.TSAR timings depending on resolution . . . . .413
Table 67.Offset computation versus data resolution . . . . .416
Table 68.Analog watchdog channel selection . . . . .427
Table 69.Analog watchdog 1 comparison . . . . .428
Table 70.Analog watchdog 2 and 3 comparison . . . . .428
Table 71.Maximum output results versus N and M (gray cells indicate truncation). . . . .432
Table 72.Oversampler operating modes summary . . . . .436
Table 73.Effect of low-power modes on the ADC . . . . .455
Table 74.ADC interrupts per each ADC. . . . .455
Table 75.DELAY bits versus ADC resolution. . . . .487
Table 76.ADC global register map. . . . .488
Table 77.ADC register map and reset values for each ADC (offset = 0x000
for master ADC, 0x100 for slave ADC). . . . .		488
Table 78.ADC register map and reset values (master and slave ADC
common registers) offset = 0x300 . . . . .		491
Table 79.DAC features . . . . .493
Table 80.DAC input/output pins. . . . .495
Table 81.DAC trigger selection . . . . .498
Table 82.Sample and refresh timings . . . . .502
Table 83.Channel output modes summary . . . . .503
Table 84.Effect of low-power modes on DAC . . . . .509
Table 85.DAC interrupts . . . . .510
Table 86.DAC register map and reset values . . . . .525
Table 87.VREF buffer modes . . . . .528
Table 88.VREFBUF register map and reset values. . . . .530
Table 89.COMP1 input plus assignment . . . . .532
Table 90.COMP1 input minus assignment . . . . .533
Table 91.COMP2 input plus assignment . . . . .533
Table 92.COMP2 input minus assignment . . . . .533
Table 93.Comparator behavior in the low power modes . . . . .537
Table 94.Interrupt control bits . . . . .537
Table 95.COMP register map and reset values. . . . .543
Table 96.Operational amplifier possible connections . . . . .545
Table 97.Operating modes and calibration . . . . .550
Table 98.Effect of low-power modes on the OPAMP . . . . .551
Table 99.OPAMP register map and reset values . . . . .554
Table 100.DFSDM1 implementation . . . . .557
Table 101.DFSDM external pins . . . . .559
Table 102.DFSDM internal signals . . . . .559
Table 103.DFSDM triggers connection . . . . .559
Table 104.DFSDM break connection. . . . .560
Table 105.Filter maximum output resolution (peak data values from filter output) for some FOSR values . . . . .574
Table 106.Integrator maximum output resolution (peak data values from integrator output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . . .574
Table 107.DFSDM interrupt requests . . . . .582
Table 108.DFSDM register map and reset values. . . . .603
Table 109.Example of frame rate calculation . . . . .611
Table 110.Blink frequency . . . . .619
Table 111.Remapping capability . . . . .623
Table 112.LCD behavior in low-power modes. . . . .629
Table 113.LCD interrupt requests . . . . .629
Table 114.LCD register map and reset values . . . . .636
Table 115.Acquisition sequence summary . . . . .642
Table 116.Spread spectrum deviation versus AHB clock frequency . . . . .644
Table 117.I/O state depending on its mode and IODEF bit value . . . . .645
Table 118.Effect of low-power modes on TSC . . . . .647
Table 119.Interrupt control bits . . . . .647
Table 120.TSC register map and reset values . . . . .655
Table 121.RNG internal input/output signals . . . . .658
Table 122.RNG interrupt requests. . . . .663
Table 123.RNG configurations . . . . .664
Table 124.RNG register map and reset map. . . . .667
Table 125.AES internal input/output signals . . . . .669
Table 126.CTR mode initialization vector definition. . . . .688
Table 127.GCM last block definition . . . . .690
Table 128.GCM mode IVI bitfield initialization . . . . .691
Table 129.Initialization of AES_IVRx registers in CCM mode . . . . .698
Table 130.Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . .703
Table 131.DMA channel configuration for memory-to-AES data transfer . . . . .704
Table 132.DMA channel configuration for AES-to-memory data transfer . . . . .705
Table 133.AES interrupt requests . . . . .707
Table 134.Processing latency (in clock cycle) for ECB, CBC and CTR. . . . .707
Table 135.Processing latency for GCM and CCM (in clock cycle) . . . . .707
Table 136.AES register map and reset values . . . . .719
Table 137.Behavior of timer outputs versus BRK/BRK2 inputs. . . . .763
Table 138.Counting direction versus encoder signals. . . . .770
Table 139.TIM1 internal trigger connection . . . . .787
Table 140.Output control bits for complementary OCx and OCxN channels with break feature. . . . .801
Table 141.TIM1 register map and reset values . . . . .816
Table 142.Counting direction versus encoder signals. . . . .853
Table 143.TIMx internal trigger connection . . . . .870
Table 144.Output control bit for standard OCx channels. . . . .881
Table 145.TIM2/TIM3 register map and reset values . . . . .888
Table 146.TIMx Internal trigger connection . . . . .933
Table 147.Output control bits for complementary OCx and OCxN channels with break feature (TIM15) . . . . .943
Table 148.TIM15 register map and reset values . . . . .951
Table 149.Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) . . . . .964
Table 150.TIM16 register map and reset values . . . . .972
Table 151.TIMx register map and reset values . . . . .986
Table 152.STM32L43xxx/44xxx/45xxx/46xxx LPTIM features . . . . .988
Table 153.LPTIM input/output pins . . . . .989
Table 154.LPTIM internal signals . . . . .989
Table 155.LPTIM1 external trigger connection . . . . .989
Table 156.LPTIM2 external trigger connection . . . . .990
Table 157.Prescaler division ratios . . . . .991
Table 158.Encoder counting scenarios . . . . .997
Table 159.Effect of low-power modes on the LPTIM . . . . .998
Table 160.Interrupt events . . . . .999
Table 161.LPTIM register map and reset values . . . . .1009
Table 162.STM32L41xxx/42xxx LPTIM features . . . . .1010
Table 163.LPTIM input/output pins . . . . .1011
Table 164.LPTIM1/2/3 internal signals . . . . .1012
Table 165.LPTIM1 external trigger connections . . . . .1012
Table 166.LPTIM2 external trigger connections . . . . .1013
Table 167.Prescaler division ratios . . . . .1014
Table 168.Encoder counting scenarios . . . . .1021
Table 169.Effect of low-power modes on the LPTIM . . . . .1024
Table 170.Interrupt events . . . . .1024
Table 171.LPTIM register map and reset values . . . . .1034
Table 172.IWDG register map and reset values . . . . .1045
Table 173.WWDG register map and reset values . . . . .1051
Table 174.RTC input/output pins . . . . .1055
Table 175.RTC internal input/output signals . . . . .1055
Table 176.RTC interconnection . . . . .1055
Table 177.PC13 configuration . . . . .1056
Table 178.RTC_OUT mapping . . . . .1058
Table 179.Effect of low-power modes on RTC . . . . .1069
Table 180.RTC pins functionality over modes . . . . .1070
Table 181.Interrupt requests . . . . .1070
Table 182.RTC register map and reset values . . . . .1090
Table 183.TAMP input/output pins . . . . .1093
Table 184.TAMP internal input/output signals . . . . .1094
Table 185.TAMP interconnection . . . . .1094
Table 186.Effect of low-power modes on TAMP . . . . .1097
Table 187.Interrupt requests . . . . .1097
Table 188.TAMP register map and reset values . . . . .1105
Table 189.RTC pin PC13 configuration . . . . .1109
Table 190.RTC_OUT mapping . . . . .1110
Table 191.RTC functions over modes . . . . .1111
Table 192.Effect of low-power modes on RTC . . . . .1123
Table 193.Interrupt control bits . . . . .1124
Table 194.RTC register map and reset values . . . . .1149
Table 195.I2C implementation . . . . .1152
Table 196.I2C input/output pins . . . . .1153
Table 197.I2C internal input/output signals . . . . .1154
Table 198.Comparison of analog and digital filters . . . . .1156
Table 199.I 2 C-bus and SMBus specification data setup and hold times . . . . .1158
Table 200.I2C configuration. . . . .1162
Table 201.I 2 C-bus and SMBus specification clock timings . . . . .1173
Table 202.Timing settings for f I2CCLK of 8 MHz. . . . .1183
Table 203.Timing settings for f I2CCLK of 16 MHz. . . . .1183
Table 204.Timing settings for f I2CCLK of 48 MHz. . . . .1184
Table 205.SMBus timeout specifications . . . . .1186
Table 206.SMBus with PEC configuration . . . . .1188
Table 207.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms. . . . .1189
Table 208.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .1189
Table 209.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .1189
Table 210.Effect of low-power modes to I2C. . . . .1199
Table 211.I2C interrupt requests . . . . .1199
Table 212.I2C register map and reset values . . . . .1214
Table 213.USART/LPUART features . . . . .1217
Table 214.Noise detection from sampled data . . . . .1229
Table 215.Error calculation for programmed baud rates at f CK = 72MHz in both cases of oversampling by 16 or by 8. . . . .1232
Table 216.Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .1234
Table 217.Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . .1234
Table 218.Frame formats . . . . .1238
Table 219.Effect of low-power modes on the USART . . . . .1257
Table 220.USART interrupt requests. . . . .1257
Table 221.USART register map and reset values . . . . .1282
Table 222.USART/LPUART implementation . . . . .1286
Table 223.Error calculation for programmed baud rates at f ck = 32.768 kHz. . . . .1296
Table 224.Error calculation for programmed baud rates at f ck = 80 MHz. . . . .1296
Table 225.Tolerance of the LPUART receiver. . . . .1297
Table 226.Frame formats . . . . .1300
Table 227.Effect of low-power modes on the LPUART . . . . .1308
Table 228.LPUART interrupt requests. . . . .1309
Table 229.LPUART register map and reset values . . . . .1325
Table 230.SPI implementation . . . . .1327
Table 231.SPI interrupt requests . . . . .1351
Table 232.SPI register map and reset values . . . . .1360
Table 233.STM32L43xxx/44xxx/45xxx/46xxx SAI features . . . . .1362
Table 234.SAI internal input/output signals . . . . .1364
Table 235.SAI input/output pins. . . . .1364
Table 236.Example of possible audio frequency sampling range . . . . .1372
Table 237.SOPD pattern . . . . .1377
Table 238.Parity bit calculation . . . . .1377
Table 239.Audio sampling frequency versus symbol rates . . . . .1378
Table 240.SAI interrupt sources . . . . .1387
Table 241.SAI register map and reset values . . . . .1411
Table 242.Effect of low-power modes on SWPMI . . . . .1428
Table 243.Interrupt control bits . . . . .1429
Table 244.Buffer modes selection for transmission/reception . . . . .1431
Table 245.SWPMI register map and reset values . . . . .1438
Table 246.SDMMC I/O definitions . . . . .1442
Table 247.Command format . . . . .1447
Table 248.Short response format . . . . .1448
Table 249.Long response format. . . . .1448
Table 250.Command path status flags . . . . .1448
Table 251.Data token format . . . . .1451
Table 252.DPSM flags . . . . .1452
Table 253.Transmit FIFO status flags . . . . .1453
Table 254.Receive FIFO status flags . . . . .1453
Table 255.Card status . . . . .1464
Table 256.SD status . . . . .1467
Table 257.Speed class code field . . . . .1468
Table 258.Performance move field . . . . .1469
Table 259.AU_SIZE field . . . . .1469
Table 260.Maximum AU size . . . . .1469
Table 261.Erase size field . . . . .1470
Table 262.Erase timeout field . . . . .1470
Table 263.Erase offset field . . . . .1470
Table 264.Block-oriented write commands . . . . .1473
Table 265.Block-oriented write protection commands. . . . .1474
Table 266.Erase commands . . . . .1474
Table 267.I/O mode commands . . . . .1474
Table 268.Lock card . . . . .1475
Table 269.Application-specific commands . . . . .1475
Table 270.R1 response . . . . .1476
Table 271.R2 response . . . . .1476
Table 272.R3 response . . . . .1477
Table 273.R4 response . . . . .1477
Table 274.R4b response . . . . .1477
Table 275.R5 response . . . . .1478
Table 276.R6 response . . . . .1479
Table 277.Response type and SDMMC_RESPx registers . . . . .1486
Table 278.SDMMC register map . . . . .1497
Table 279.Transmit mailbox mapping . . . . .1513
Table 280.Receive mailbox mapping. . . . .1513
Table 281.bxCAN register map and reset values . . . . .1538
Table 282.STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx USB implementation . . . . .1542
Table 283.Double-buffering buffer flag definition. . . . .1552
Table 284.Bulk double-buffering memory buffers usage . . . . .1552
Table 285.Isochronous memory buffers usage . . . . .1554
Table 286.Resume event detection . . . . .1555
Table 287.Reception status encoding . . . . .1568
Table 288.Endpoint type encoding . . . . .1568
Table 289.Endpoint kind meaning . . . . .1568
Table 290.Transmission status encoding . . . . .1569
Table 291.Definition of allocated buffer memory . . . . .1572
Table 292.USB register map and reset values . . . . .1573
Table 293.SWJ debug port pins . . . . .1578
Table 294.Flexible SWJ-DP pin assignment . . . . .1578
Table 295.JTAG debug port data registers . . . . .1583
Table 296.32-bit debug port registers addressed through the shifted value A[3:2] . . . . .1584
Table 297.Packet request (8-bits) . . . . .1585
Table 298.ACK response (3 bits). . . . .1586
Table 299.DATA transfer (33 bits) . . . . .1586
Table 300.SW-DP registers . . . . .1587
Table 301.Cortex®-M4 AHB-AP registers . . . . .1588
Table 302.Core debug registers . . . . .1589
Table 303.Main ITM registers . . . . .1591
Table 304.Main ETM registers . . . . .1593
Table 305.Asynchronous TRACE pin assignment . . . . .1599
Table 306.Synchronous TRACE pin assignment . . . . .1600
Table 307.Flexible TRACE pin assignment . . . . .1600
Table 308.Important TPIU registers . . . . .1604
Table 309.DBG register map and reset values . . . . .1606
Table 310.Document revision history . . . . .1611

List of figures

Figure 1.System architecture . . . . .68
Figure 2.Memory map . . . . .71
Figure 3.Sequential 16-bit instructions execution . . . . .85
Figure 4.Changing the Read protection (RDP) level. . . . .100
Figure 5.STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx firewall connection schematics . . . . .119
Figure 6.Firewall functional states . . . . .123
Figure 7.Power supply overview . . . . .132
Figure 8.Internal main regulator overview. . . . .136
Figure 9.Brown-out reset waveform . . . . .139
Figure 10.PVD thresholds . . . . .140
Figure 11.Low-power modes possible transitions. . . . .143
Figure 12.Simplified diagram of the reset circuit. . . . .180
Figure 13.Clock tree . . . . .184
Figure 14.HSE/ LSE clock sources. . . . .185
Figure 15.Frequency measurement with TIM15 in capture mode. . . . .193
Figure 16.Frequency measurement with TIM16 in capture mode. . . . .194
Figure 17.CRS block diagram. . . . .252
Figure 18.CRS counter behavior . . . . .254
Figure 19.Basic structure of an I/O port bit . . . . .264
Figure 20.Basic structure of a 5-Volt tolerant I/O port bit . . . . .264
Figure 21.Input floating/pull up/pull down configurations . . . . .269
Figure 22.Output configuration . . . . .270
Figure 23.Alternate function configuration . . . . .271
Figure 24.High impedance-analog configuration . . . . .271
Figure 25.DMA1 request mapping . . . . .302
Figure 26.DMA2 request mapping . . . . .303
Figure 27.DMA block diagram . . . . .305
Figure 28.Configurable interrupt/event block diagram . . . . .331
Figure 29.External interrupt/event GPIO mapping . . . . .333
Figure 30.CRC calculation unit block diagram . . . . .344
Figure 31.QUADSPI block diagram when dual-flash mode is disabled . . . . .350
Figure 32.QUADSPI block diagram when dual-flash mode is enabled . . . . .351
Figure 33.Example of read command in quad-SPI mode . . . . .352
Figure 34.Example of a DDR command in quad-SPI mode . . . . .355
Figure 35.NCS when CKMODE = 0 (T = CLK period) . . . . .363
Figure 36.NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .363
Figure 37.NCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . .364
Figure 38.NCS when CKMODE = 1 with an abort (T = CLK period). . . . .364
Figure 39.ADC block diagram . . . . .381
Figure 40.ADC clock scheme . . . . .384
Figure 41.ADC1 connectivity . . . . .385
Figure 42.ADC2 connectivity . . . . .386
Figure 43.ADC calibration. . . . .389
Figure 44.Updating the ADC calibration factor . . . . .390
Figure 45.Mixing single-ended and differential channels . . . . .391
Figure 46.Enabling / disabling the ADC . . . . .392
Figure 47.Analog-to-digital conversion time . . . . .397
Figure 48.Stopping ongoing regular conversions . . . . .398
Figure 49.Stopping ongoing regular and injected conversions . . . . .398
Figure 50.Triggers sharing between ADC master and ADC slave . . . . .400
Figure 51.Injected conversion latency . . . . .402
Figure 52.Example of JSQR queue of context (sequence change) . . . . .406
Figure 53.Example of JSQR queue of context (trigger change) . . . . .406
Figure 54.Example of JSQR queue of context with overflow before conversion . . . . .407
Figure 55.Example of JSQR queue of context with overflow during conversion . . . . .407
Figure 56.Example of JSQR queue of context with empty queue (case JQM = 0). . . . .408
Figure 57.Example of JSQR queue of context with empty queue (case JQM = 1). . . . .409
Figure 58.Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs during an ongoing conversion . . . . .		409
Figure 59.Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . .		410
Figure 60.Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs outside an ongoing conversion . . . . .		410
Figure 61.Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 1) . . . . .411
Figure 62.Flushing JSQR queue of context by setting ADDIS = 1 (JQM = 0). . . . .411
Figure 63.Flushing JSQR queue of context by setting ADDIS = 1 (JQM = 1). . . . .412
Figure 64.Single conversions of a sequence, software trigger . . . . .414
Figure 65.Continuous conversion of a sequence, software trigger. . . . .414
Figure 66.Single conversions of a sequence, hardware trigger . . . . .415
Figure 67.Continuous conversions of a sequence, hardware trigger . . . . .415
Figure 68.Right alignment (offset disabled, unsigned value) . . . . .417
Figure 69.Right alignment (offset enabled, signed value). . . . .418
Figure 70.Left alignment (offset disabled, unsigned value) . . . . .418
Figure 71.Left alignment (offset enabled, signed value). . . . .419
Figure 72.Example of overrun (OVR) . . . . .420
Figure 73.AUTODLY = 1, regular conversion in continuous mode, software trigger . . . . .423
Figure 74.AUTODLY = 1, regular HW conversions interrupted by injected conversions
(DISCEN = 0; JDISCEN = 0) . . . . .		424
Figure 75.AUTODLY = 1, regular HW conversions interrupted by injected conversions
(DISCEN = 1, JDISCEN = 1) . . . . .		425
Figure 76.AUTODLY = 1, regular continuous conversions interrupted by injected conversions . . . . .426
Figure 77.AUTODLY = 1 in auto- injected mode (JAUTO = 1) . . . . .426
Figure 78.Analog watchdog guarded area . . . . .427
Figure 79.ADC y _AWD x _OUT signal generation (on all regular channels). . . . .429
Figure 80.ADC y _AWD x _OUT signal generation (AWD x flag not cleared by software) . . . . .430
Figure 81.ADC y _AWD x _OUT signal generation (on a single regular channel) . . . . .430
Figure 82.ADC y _AWD x _OUT signal generation (on all injected channels) . . . . .430
Figure 83.20-bit to 16-bit result truncation . . . . .431
Figure 84.Numerical example with 5-bit shift and rounding . . . . .431
Figure 85.Triggered regular oversampling mode (TROVS bit = 1). . . . .433
Figure 86.Regular oversampling modes (4x ratio) . . . . .434
Figure 87.Regular and injected oversampling modes used simultaneously . . . . .435
Figure 88.Triggered regular oversampling with injection . . . . .435
Figure 89.Oversampling in auto-injected mode . . . . .436
Figure 90.Dual ADC block diagram (1) . . . . .438
Figure 91.Injected simultaneous mode on 4 channels: dual ADC mode . . . . .439
Figure 92.Regular simultaneous mode on 16 channels: dual ADC mode . . . . .441
Figure 93.Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode. . . . .442
Figure 94.Interleaved mode on 1 channel in single conversion mode: dual ADC mode. . . . .443
Figure 95.Interleaved conversion with injection . . . . .443
Figure 96.Alternate trigger: injected group of each ADC . . . . .444
Figure 97.Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . .445
Figure 98.Alternate + regular simultaneous . . . . .446
Figure 99.Case of trigger occurring during injected conversion . . . . .446
Figure 100.Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . .447
Figure 101.Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first . . . . .		447
Figure 102.Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . .		447
Figure 103.DMA Requests in regular simultaneous mode when MDMA = 00 . . . . .448
Figure 104.DMA requests in regular simultaneous mode when MDMA = 10 . . . . .449
Figure 105.DMA requests in interleaved mode when MDMA = 10 . . . . .449
Figure 106.Temperature sensor channel block diagram . . . . .451
Figure 107.VBAT channel block diagram . . . . .453
Figure 108.VREFINT channel block diagram . . . . .453
Figure 109.Dual-channel DAC block diagram . . . . .494
Figure 110.Data registers in single DAC channel mode . . . . .496
Figure 111.Data registers in dual DAC channel mode . . . . .496
Figure 112.Timing diagram for conversion with trigger disabled TEN = 0 . . . . .497
Figure 113.DAC LFSR register calculation algorithm . . . . .499
Figure 114.DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .499
Figure 115.DAC triangle wave generation . . . . .500
Figure 116.DAC conversion (SW trigger enabled) with triangle wave generation . . . . .500
Figure 117.DAC sample and hold mode phase diagram . . . . .503
Figure 118.Comparator block diagram . . . . .532
Figure 119.Window mode . . . . .535
Figure 120.Comparator hysteresis . . . . .535
Figure 121.Comparator output blanking . . . . .536
Figure 122.Standalone mode: external gain setting mode . . . . .546
Figure 123.Follower configuration . . . . .547
Figure 124.PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . .548
Figure 125.PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for
filtering . . . . .		549
Figure 126.Single DFSDM block diagram . . . . .558
Figure 127.Input channel pins redirection . . . . .562
Figure 128.Channel transceiver timing diagrams . . . . .564
Figure 129.Clock absence timing diagram for SPI . . . . .565
Figure 130.Clock absence timing diagram for Manchester coding . . . . .566
Figure 131.First conversion for Manchester coding (Manchester synchronization) . . . . .568
Figure 132.DFSDM_CHyDATINR registers operation modes and assignment . . . . .571
Figure 133.Example: Sinc3 filter response . . . . .573
Figure 134.LCD controller block diagram . . . . .610
Figure 135.1/3 bias, 1/4 duty . . . . .612
Figure 136.Static duty case 1 . . . . .613
Figure 137.Static duty case 2 . . . . .614
Figure 138.1/2 duty, 1/2 bias . . . . .615
Figure 139.1/3 duty, 1/3 bias . . . . .616
Figure 140.1/4 duty, 1/3 bias . . . . .617
Figure 141.1/8 duty, 1/4 bias . . . . .618
Figure 142.LCD voltage control . . . . .621
Figure 143.Deadtime . . . . .622
Figure 144. SEG/COM mux feature example . . . . .627
Figure 145. Flowchart example . . . . .628
Figure 146. TSC block diagram . . . . .640
Figure 147. Surface charge transfer analog I/O group structure . . . . .641
Figure 148. Sampling capacitor voltage variation . . . . .642
Figure 149. Charge transfer acquisition sequence . . . . .643
Figure 150. Spread spectrum variation principle . . . . .644
Figure 151. RNG block diagram . . . . .658
Figure 152. Entropy source model . . . . .659
Figure 153. AES block diagram . . . . .669
Figure 154. ECB encryption and decryption principle . . . . .671
Figure 155. CBC encryption and decryption principle . . . . .672
Figure 156. CTR encryption and decryption principle . . . . .673
Figure 157. GCM encryption and authentication principle . . . . .674
Figure 158. GMAC authentication principle . . . . .674
Figure 159. CCM encryption and authentication principle . . . . .675
Figure 160. STM32 cryptolib AES flowchart examples . . . . .676
Figure 161. STM32 cryptolib AES flowchart examples (continued) . . . . .677
Figure 162. Encryption key derivation for ECB/CBC decryption (Mode 2) . . . . .680
Figure 163. Example of suspend mode management . . . . .681
Figure 164. ECB encryption . . . . .682
Figure 165. ECB decryption . . . . .682
Figure 166. CBC encryption . . . . .683
Figure 167. CBC decryption . . . . .683
Figure 168. ECB/CBC encryption (Mode 1) . . . . .684
Figure 169. ECB/CBC decryption (Mode 3) . . . . .685
Figure 170. Message construction in CTR mode . . . . .687
Figure 171. CTR encryption . . . . .688
Figure 172. CTR decryption . . . . .688
Figure 173. Message construction in GCM . . . . .690
Figure 174. GCM authenticated encryption . . . . .691
Figure 175. Message construction in GMAC mode . . . . .695
Figure 176. GMAC authentication mode . . . . .695
Figure 177. Message construction in CCM mode . . . . .696
Figure 178. CCM mode authenticated decryption . . . . .698
Figure 179. 128-bit block construction with respect to data swap . . . . .702
Figure 180. DMA transfer of a 128-bit data block during input phase . . . . .704
Figure 181. DMA transfer of a 128-bit data block during output phase . . . . .705
Figure 182. AES interrupt signal generation . . . . .706
Figure 183. Advanced-control timer block diagram . . . . .723
Figure 184. Counter timing diagram with prescaler division change from 1 to 2 . . . . .725
Figure 185. Counter timing diagram with prescaler division change from 1 to 4 . . . . .725
Figure 186. Counter timing diagram, internal clock divided by 1 . . . . .727
Figure 187. Counter timing diagram, internal clock divided by 2 . . . . .727
Figure 188. Counter timing diagram, internal clock divided by 4 . . . . .728
Figure 189. Counter timing diagram, internal clock divided by N . . . . .728
Figure 190. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .729
Figure 191. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .729
Figure 192. Counter timing diagram, internal clock divided by 1 . . . . .731
Figure 193. Counter timing diagram, internal clock divided by 2 . . . . .731
Figure 194. Counter timing diagram, internal clock divided by 4 . . . . .732
Figure 195. Counter timing diagram, internal clock divided by N . . . . .732
Figure 196. Counter timing diagram, update event when repetition counter is not used . . . . .733
Figure 197. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .734
Figure 198. Counter timing diagram, internal clock divided by 2 . . . . .735
Figure 199. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .735
Figure 200. Counter timing diagram, internal clock divided by N . . . . .736
Figure 201. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .736
Figure 202. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .737
Figure 203. Update rate examples depending on mode and TIMx_RCR register settings . . . . .738
Figure 204. External trigger input block . . . . .739
Figure 205. TIM1 ETR input circuitry . . . . .739
Figure 206. Control circuit in normal mode, internal clock divided by 1 . . . . .740
Figure 207. TI2 external clock connection example . . . . .741
Figure 208. Control circuit in external clock mode 1 . . . . .742
Figure 209. External trigger input block . . . . .742
Figure 210. Control circuit in external clock mode 2 . . . . .743
Figure 211. Capture/compare channel (example: channel 1 input stage) . . . . .744
Figure 212. Capture/compare channel 1 main circuit . . . . .745
Figure 213. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .745
Figure 214. Output stage of capture/compare channel (channel 4) . . . . .746
Figure 215. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .746
Figure 216. PWM input mode timing . . . . .748
Figure 217. Output compare mode, toggle on OC1 . . . . .750
Figure 218. Edge-aligned PWM waveforms (ARR=8) . . . . .751
Figure 219. Center-aligned PWM waveforms (ARR=8) . . . . .752
Figure 220. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .754
Figure 221. Combined PWM mode on channel 1 and 3 . . . . .755
Figure 222. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .756
Figure 223. Complementary output with dead-time insertion . . . . .757
Figure 224. Dead-time waveforms with delay greater than the negative pulse . . . . .757
Figure 225. Dead-time waveforms with delay greater than the positive pulse . . . . .758
Figure 226. Break and Break2 circuitry overview . . . . .760
Figure 227. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .762
Figure 228. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .763
Figure 229. PWM output state following BRK assertion (OSSI=0) . . . . .764
Figure 230. Output redirection . . . . .764
Figure 231. Clearing TIMx_OCxREF . . . . .765
Figure 232. 6-step generation, COM example (OSSR=1) . . . . .766
Figure 233. Example of one pulse mode . . . . .767
Figure 234. Retriggerable one pulse mode . . . . .769
Figure 235. Example of counter operation in encoder interface mode . . . . .770
Figure 236. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .771
Figure 237. Measuring time interval between edges on 3 signals . . . . .772
Figure 238. Example of Hall sensor interface . . . . .774
Figure 239. Control circuit in reset mode . . . . .775
Figure 240. Control circuit in Gated mode . . . . .776
Figure 241. Control circuit in trigger mode . . . . .777
Figure 242. Control circuit in external clock mode 2 + trigger mode . . . . .778
Figure 243. General-purpose timer block diagram . . . . .820
Figure 244. Counter timing diagram with prescaler division change from 1 to 2 . . . . .822
Figure 245. Counter timing diagram with prescaler division change from 1 to 4 . . . . .822
Figure 246. Counter timing diagram, internal clock divided by 1 . . . . .823
Figure 247. Counter timing diagram, internal clock divided by 2 . . . . .824
Figure 248. Counter timing diagram, internal clock divided by 4 . . . . .824
Figure 249. Counter timing diagram, internal clock divided by N . . . . .825
Figure 250. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .825
Figure 251. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .826
Figure 252. Counter timing diagram, internal clock divided by 1 . . . . .827
Figure 253. Counter timing diagram, internal clock divided by 2 . . . . .827
Figure 254. Counter timing diagram, internal clock divided by 4 . . . . .828
Figure 255. Counter timing diagram, internal clock divided by N . . . . .828
Figure 256. Counter timing diagram, Update event . . . . .829
Figure 257. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .830
Figure 258. Counter timing diagram, internal clock divided by 2 . . . . .831
Figure 259. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .831
Figure 260. Counter timing diagram, internal clock divided by N . . . . .832
Figure 261. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .832
Figure 262. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .833
Figure 263. Control circuit in normal mode, internal clock divided by 1 . . . . .834
Figure 264. TI2 external clock connection example. . . . .834
Figure 265. Control circuit in external clock mode 1 . . . . .835
Figure 266. External trigger input block . . . . .836
Figure 267. Control circuit in external clock mode 2 . . . . .837
Figure 268. Capture/Compare channel (example: channel 1 input stage) . . . . .838
Figure 269. Capture/Compare channel 1 main circuit . . . . .838
Figure 270. Output stage of Capture/Compare channel (channel 1). . . . .839
Figure 271. PWM input mode timing . . . . .841
Figure 272. Output compare mode, toggle on OC1 . . . . .843
Figure 273. Edge-aligned PWM waveforms (ARR=8). . . . .844
Figure 274. Center-aligned PWM waveforms (ARR=8). . . . .845
Figure 275. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .846
Figure 276. Combined PWM mode on channels 1 and 3 . . . . .848
Figure 277. Clearing TIMx_OCxREF . . . . .849
Figure 278. Example of one-pulse mode. . . . .850
Figure 279. Retriggerable one-pulse mode . . . . .852
Figure 280. Example of counter operation in encoder interface mode . . . . .853
Figure 281. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .854
Figure 282. Control circuit in reset mode . . . . .855
Figure 283. Control circuit in gated mode . . . . .856
Figure 284. Control circuit in trigger mode . . . . .857
Figure 285. Control circuit in external clock mode 2 + trigger mode . . . . .858
Figure 286. Master/Slave timer example . . . . .859
Figure 287. Master/slave connection example with 1 channel only timers . . . . .859
Figure 288. Gating TIMz with OC1REF of TIMy . . . . .860
Figure 289. Gating TIMz with Enable of TIMy . . . . .861
Figure 290. Triggering TIMz with update of TIMy . . . . .862
Figure 291. Triggering TIMz with Enable of TIMy . . . . .862
Figure 292. Triggering TIMy3 and TIMz2 with TIMy3 TI1 input . . . . .863
Figure 293. TIM15 block diagram . . . . .893
Figure 294. TIM16 block diagram . . . . .894
Figure 295. Counter timing diagram with prescaler division change from 1 to 2 . . . . .896
Figure 296. Counter timing diagram with prescaler division change from 1 to 4 . . . . .896
Figure 297. Counter timing diagram, internal clock divided by 1 . . . . .898
Figure 298. Counter timing diagram, internal clock divided by 2 . . . . .898
Figure 299. Counter timing diagram, internal clock divided by 4 . . . . .899
Figure 300. Counter timing diagram, internal clock divided by N . . . . .899
Figure 301. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .900
Figure 302. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .900
Figure 303. Update rate examples depending on mode and TIMx_RCR register settings . . . . .902
Figure 304. Control circuit in normal mode, internal clock divided by 1 . . . . .903
Figure 305. TI2 external clock connection example. . . . .903
Figure 306. Control circuit in external clock mode 1 . . . . .904
Figure 307. Capture/compare channel (example: channel 1 input stage). . . . .905
Figure 308. Capture/compare channel 1 main circuit . . . . .905
Figure 309. Output stage of capture/compare channel (channel 1). . . . .906
Figure 310. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .906
Figure 311. PWM input mode timing . . . . .908
Figure 312. Output compare mode, toggle on OC1 . . . . .910
Figure 313. Edge-aligned PWM waveforms (ARR=8) . . . . .911
Figure 314. Combined PWM mode on channel 1 and 2 . . . . .912
Figure 315. Complementary output with dead-time insertion. . . . .913
Figure 316. Dead-time waveforms with delay greater than the negative pulse. . . . .913
Figure 317. Dead-time waveforms with delay greater than the positive pulse. . . . .914
Figure 318. Break circuitry overview . . . . .916
Figure 319. Output behavior in response to a break . . . . .918
Figure 320. 6-step generation, COM example (OSSR=1) . . . . .919
Figure 321. Example of one pulse mode . . . . .920
Figure 322. Retriggerable one pulse mode . . . . .922
Figure 323. Measuring time interval between edges on 2 signals . . . . .923
Figure 324. Control circuit in reset mode . . . . .924
Figure 325. Control circuit in gated mode . . . . .925
Figure 326. Control circuit in trigger mode . . . . .926
Figure 327. Basic timer block diagram. . . . .974
Figure 328. Counter timing diagram with prescaler division change from 1 to 2 . . . . .976
Figure 329. Counter timing diagram with prescaler division change from 1 to 4 . . . . .976
Figure 330. Counter timing diagram, internal clock divided by 1 . . . . .977
Figure 331. Counter timing diagram, internal clock divided by 2 . . . . .978
Figure 332. Counter timing diagram, internal clock divided by 4 . . . . .978
Figure 333. Counter timing diagram, internal clock divided by N . . . . .979
Figure 334. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .979
Figure 335. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .980
Figure 336. Control circuit in normal mode, internal clock divided by 1 . . . . .981
Figure 337. Low-power timer block diagram . . . . .988
Figure 338. Glitch filter timing diagram . . . . .991
Figure 339. LPTIM output waveform, single counting mode configuration . . . . .993
Figure 340. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set). . . . .993
Figure 341. LPTIM output waveform, Continuous counting mode configuration . . . . .994
Figure 342. Waveform generation . . . . .995
Figure 343. Encoder mode counting sequence . . . . .998
Figure 344. Low-power timer block diagram . . . . .1011
Figure 345. Glitch filter timing diagram . . . . .1014
Figure 346. LPTIM output waveform, single-counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . .1016
Figure 347. LPTIM output waveform, single-counting mode configuration and Set-once mode activated (WAVE bit is set). . . . .1016
Figure 348. LPTIM output waveform, Continuous counting mode configuration . . . . .1017
Figure 349. Waveform generation . . . . .1018
Figure 350. Encoder mode counting sequence . . . . .1022
Figure 351. Continuous counting mode when repetition register LPTIM_RCR different from zero (with PRELOAD = 1). . . . .1023
Figure 352. IRTIM internal hardware connections with TIM15 and TIM16 and TIM17 . . . . .1036
Figure 353. Independent watchdog block diagram . . . . .1037
Figure 354. Watchdog block diagram . . . . .1047
Figure 355. Window watchdog timing diagram . . . . .1048
Figure 356. RTC block diagram . . . . .1054
Figure 357. TAMP block diagram . . . . .1093
Figure 358. RTC block diagram . . . . .1108
Figure 359. Block diagram . . . . .1153
Figure 360. I 2 C-bus protocol . . . . .1155
Figure 361. Setup and hold timings . . . . .1157
Figure 362. I2C initialization flow . . . . .1159
Figure 363. Data reception . . . . .1160
Figure 364. Data transmission . . . . .1161
Figure 365. Target initialization flow . . . . .1164
Figure 366. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .1166
Figure 367. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .1167
Figure 368. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .1168
Figure 369. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .1169
Figure 370. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .1170
Figure 371. Transfer bus diagrams for I2C target receiver (mandatory events only) . . . . .1170
Figure 372. Controller clock generation . . . . .1172
Figure 373. Controller initialization flow . . . . .1174
Figure 374. 10-bit address read access with HEAD10R = 0 . . . . .1174
Figure 375. 10-bit address read access with HEAD10R = 1 . . . . .1175
Figure 376. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .1176
Figure 377. Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .1177
Figure 378. Transfer bus diagrams for I2C controller transmitter (mandatory events only) . . . . .1178
Figure 379. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .1180
Figure 380. Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .1181
Figure 381. Transfer bus diagrams for I2C controller receiver (mandatory events only) . . . . .1182
Figure 382. Timeout intervals for t LOW:SEXT , t LOW:MEXT . . . . .1186
Figure 383. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .1190
Figure 384. Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . .1190
Figure 385. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .1192
Figure 386. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .1193
Figure 387. Bus transfer diagrams for SMBus controller transmitter . . . . .1194
Figure 388. Bus transfer diagrams for SMBus controller receiver . . . . .1196
Figure 389. USART block diagram . . . . .1219
Figure 390. Word length programming . . . . .1221
Figure 391. Configurable stop bits . . . . .1223
Figure 392. TC/TXE behavior when transmitting . . . . .1224
Figure 393. Start bit detection when oversampling by 16 or 8 . . . . .1225
Figure 394. Data sampling when oversampling by 16 . . . . .1229
Figure 395. Data sampling when oversampling by 8 . . . . .1229
Figure 396. Mute mode using Idle line detection . . . . .1236
Figure 397. Mute mode using address mark detection . . . . .1237
Figure 398. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .1240
Figure 399. Break detection in LIN mode vs. Framing error detection. . . . .1241
Figure 400. USART example of synchronous transmission. . . . .1242
Figure 401. USART data clock timing diagram (M bits = 00) . . . . .1242
Figure 402. USART data clock timing diagram (M bits = 01) . . . . .1243
Figure 403. RX data setup/hold time . . . . .1243
Figure 404. ISO 7816-3 asynchronous protocol . . . . .1245
Figure 405. Parity error detection using the 1.5 stop bits . . . . .1246
Figure 406. IrDA SIR ENDEC- block diagram . . . . .1250
Figure 407. IrDA data modulation (3/16) - normal mode . . . . .1250
Figure 408. Transmission using DMA . . . . .1252
Figure 409. Reception using DMA . . . . .1253
Figure 410. Hardware flow control between 2 USARTs . . . . .1253
Figure 411. RS232 RTS flow control . . . . .1254
Figure 412. RS232 CTS flow control . . . . .1255
Figure 413. USART interrupt mapping diagram . . . . .1259
Figure 414. LPUART block diagram . . . . .1287
Figure 415. Word length programming . . . . .1289
Figure 416. Configurable stop bits . . . . .1290
Figure 417. TC/TXE behavior when transmitting . . . . .1292
Figure 418. Mute mode using Idle line detection . . . . .1299
Figure 419. Mute mode using address mark detection . . . . .1300
Figure 420. Transmission using DMA . . . . .1303
Figure 421. Reception using DMA . . . . .1304
Figure 422. Hardware flow control between 2 LPUARTs . . . . .1304
Figure 423. RS232 RTS flow control . . . . .1305
Figure 424. RS232 CTS flow control . . . . .1306
Figure 425. LPUART interrupt mapping diagram . . . . .1310
Figure 426. SPI block diagram. . . . .1327
Figure 427. Full-duplex single master/ single slave application. . . . .1328
Figure 428. Half-duplex single master/ single slave application . . . . .1329
Figure 429. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		1330
Figure 430. Master and three independent slaves. . . . .1331
Figure 431. Multimaster application . . . . .1332
Figure 432. Hardware/software slave select management . . . . .1333
Figure 433. Data clock timing diagram . . . . .1334
Figure 434. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .1335
Figure 435. Packing data in FIFO for transmission and reception. . . . .1339
Figure 436. Master full-duplex communication . . . . .1342
Figure 437. Slave full-duplex communication . . . . .1343
Figure 438. Master full-duplex communication with CRC . . . . .1344
Figure 439. Master full-duplex communication in packed mode . . . . .1345
Figure 440. NSSP pulse generation in Motorola SPI master mode. . . . .1348
Figure 441. TI mode transfer . . . . .1349
Figure 442. SAI functional block diagram . . . . .1363
Figure 443. Audio frame . . . . .1366
Figure 444. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .1368
Figure 445. FS role is start of frame (FSDEF = 0) . . . . .1369
Figure 446. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .1370
Figure 447. First bit offset . . . . .1370
Figure 448. Audio block clock generator overview . . . . .1371
Figure 449. AC'97 audio frame . . . . .1375
Figure 450. SPDIF format . . . . .1376
Figure 451. SAI_xDR register ordering . . . . .1377
Figure 452. Data companding hardware in an audio block in the SAI . . . . .1380
Figure 453. Tristate strategy on SD output line on an inactive slot . . . . .1382
Figure 454. Tristate on output data line in a protocol like I2S . . . . .1383
Figure 455. Overrun detection error . . . . .1384
Figure 456. FIFO underrun event . . . . .1384
Figure 457. S1 signal coding . . . . .1412
Figure 458. S2 signal coding . . . . .1413
Figure 459. SWPMI block diagram . . . . .1414
Figure 460. SWP bus states . . . . .1416
Figure 461. SWP frame structure . . . . .1417
Figure 462. SWPMI No software buffer mode transmission . . . . .1418
Figure 463. SWPMI No software buffer mode transmission, consecutive frames . . . . .1419
Figure 464. SWPMI Multi software buffer mode transmission . . . . .1421
Figure 465. SWPMI No software buffer mode reception . . . . .1423
Figure 466. SWPMI single software buffer mode reception . . . . .1424
Figure 467. SWPMI Multi software buffer mode reception . . . . .1426
Figure 468. SWPMI single buffer mode reception with CRC error . . . . .1427
Figure 469. "No response" and "no data" operations . . . . .1440
Figure 470. (Multiple) block read operation . . . . .1440
Figure 471. (Multiple) block write operation . . . . .1440
Figure 472. Sequential read operation . . . . .1441
Figure 473. Sequential write operation . . . . .1441
Figure 474. SDMMC block diagram . . . . .1441
Figure 475. SDMMC adapter . . . . .1443
Figure 476. Control unit . . . . .1444
Figure 477. SDMMC_CK clock dephasing (BYPASS = 0) . . . . .1445
Figure 478. SDMMC adapter command path . . . . .1445
Figure 479. Command path state machine (SDMMC) . . . . .1446
Figure 480. SDMMC command transfer . . . . .1447
Figure 481. Data path . . . . .1449
Figure 482. Data path state machine (DPSM) . . . . .1450
Figure 483. CAN network topology . . . . .1500
Figure 484. Single-CAN block diagram . . . . .1501
Figure 485. bxCAN operating modes . . . . .1503
Figure 486. bxCAN in silent mode . . . . .1504
Figure 487. bxCAN in Loop back mode . . . . .1504
Figure 488. bxCAN in combined mode . . . . .1505
Figure 489. Transmit mailbox states . . . . .1506
Figure 490. Receive FIFO states . . . . .1507
Figure 491. Filter bank scale configuration - Register organization . . . . .1510
Figure 492. Example of filter numbering . . . . .1511
Figure 493. Filtering mechanism example . . . . .1512
Figure 494. CAN error state diagram . . . . .1513
Figure 495. Bit timing . . . . .1515
Figure 496. CAN frames . . . . .1516
Figure 497. Event flags and interrupt generation. . . . .1517
Figure 498. CAN mailbox registers . . . . .1529
Figure 499. USB peripheral block diagram . . . . .1543
Figure 500. Packet buffer areas with examples of buffer description table locations . . . . .1547
Figure 501. Block diagram of STM32 MCU and Cortex®-M4-level debug support . . . . .1575
Figure 502. SWJ debug port . . . . .1577
Figure 503. JTAG TAP connections . . . . .1581
Figure 504. TPIU block diagram . . . . .1599

Chapters