36. Revision history

Table 258. Document revision history

Date	Revision	Changes
17-Mar-2015	1	Initial release.
12-Jan-2016	2	Updated Section 5.1.2: Battery backup domain (also known as RTC domain) . Updated Table 19: Standby mode entry and exit . Updated Section 6.3.2: RCC PLL configuration register (RCC_PLLCFGGR) , Section 6.3.23: RCC PLLI2S configuration register (RCC_PLLI2SCFGGR) and Section 6.3.24: RCC PLL configuration register (RCC_PLLSAICFGGR) . Updated Section 11.4: AHB interface , Section 11.5.3: SDRAM address mapping , Section 11.6.4: NOR flash/PSRAM controller asynchronous transactions , Section 11.6.6: NOR/PSRAM controller registers , SRAM/NOR-flash write timing registers x (FMC_BWTRx) , FIFO status and interrupt register (FMC_SR) , Common memory space timing register (FMC_PMEM) and Attribute memory space timing register (FMC_PATT) , SDRAM initialization . Updated Table 74: Programmable NAND flash access parameters . Updated figures 32, 43, 44, 45 and 46 in Section 11 . Updated footnote 5 of Figure 53 , and added footnote 2 to Figure 52 and footnote 1 to Figure 91 . Updated Section 12.5.7: QUADSPI address register (QUADSPI_AR) . Updated Section 13.2: ADC main features and Section 13.13.2: ADC control register 1 (ADC_CR1) . Updated figures 110, 139, 153 and Input capture mode in Section 16 . Updated Figure 183 , Section 17.4.3: TIMx slave mode control register (TIMx_SMCR) and Input capture mode in Section 17 . Updated Table 115: TIMx internal trigger connections and Input capture mode in Section 18 . Updated Figure 238: Watchdog block diagram and Section 21.4: How to program the watchdog timeout . Updated Section 22.6.4: RTC initialization and status register (RTC_ISR) . Updated Section 23.7.5: Timing register (FMPI2C_TIMINGR) . Updated Section 24.6.2: I ²C control register 2 (I2C_CR2) . Added Section 25.3: USART implementation . Updated tables in Section 25.4.4: Fractional baud rate generation . Updated figures 304, 305, 306 and 307, and their footnotes in Section 26.3: SPI functional description . Updated Section 29.1: SDIO main features , Section 29.3: SDIO functional description , Section 29.8.1: SDIO power control register (SDIO_POWER) , Section 29.8.2: SDIO clock control register (SDIO_CLKCR) , Section 29.8.4: SDIO command register (SDIO_CMD) , Section 30.7.4: Identifier filtering , CAN filter mode register (CAN_FM1R) , CAN filter scale register (CAN_FS1R) , CAN filter FIFO assignment register (CAN_FFA1R) , CAN filter activation register (CAN_FA1R) , and Section 30.9.5: bxCAN register map . Updated Section 31.15.5: OTG reset register (OTG_GRSTCTL) . Updated Section 33.6.1: MCU device ID code and Section 33.6.3: Cortex ^®-M4 with FPU TAP .

Table 258. Document revision history (continued)

Date	Revision	Changes
04-Jul-2017	3	Updated Section 1.2: List of abbreviations for registers . Updated Section 5.4.2: PWR power control/status register (PWR_CSR) . Replaced former Section 9.3.1: General description with Section 9.3.1: DMA block diagram and Section 9.3.1: DMA block diagram . Updated Section 11.2: FMC main features, SRAM/NOR-flash chip-select timing register for bank x (FMC_BTRx), Common memory space timing register (FMC_PMEM), Attribute memory space timing register (FMC_PATT) and SDRAM control register x (FMC_SDCRx) . Updated Table 54: FMC_BCRx bitfields (mode 1) and Table 72: FMC_BCRx bitfields (Synchronous multiplexed write mode) . Updated Figure 39: Mode 2 write access waveforms and Figure 52: NAND flash controller waveforms for common memory access . Added Section 12.3.2: QUADSPI pins . Updated Section 12.3.7: QUADSPI memory-mapped mode , Section 12.3.13: QUADSPI error management and Section 12.5.1: QUADSPI control register (QUADSPI_CR) . Updated notes in Section 13.13.7: ADC watchdog higher threshold register (ADC_HTR) and Section 13.13.8: ADC watchdog lower threshold register (ADC_LTR) . Removed former Section 15.3: DCMI pins and added Section 15.4.1: DCMI block diagram . Updated Table 96: DCMI external signals . Changed D, PIXCLK, HSYNC and VSYNC with, respectively, DCMI_D, DCMI_HSYNC, DCMI_VSYNC and DCMI_VSYNC in Section 15: Digital camera interface (DCMI) . Updated I2C master initialization , Section 23.7.2: Control register 2 (FMPI2C_CR2) , Section 23.7.3: Own address 1 register (FMPI2C_OAR1) , Section 23.7.4: Own address 2 register (FMPI2C_OAR2) and Section 23.7.5: Timing register (FMPI2C_TIMINGR) . Updated Figure 247: Target initialization flow . Updated Section 25.6.1: Status register (USART_SR) . Updated Section 26.1: Introduction , Section 26.3.7: SPI configuration and notes in Resetting the SPIx_TXCRC and SPIx_RXCRC values and in Section 26.7.1: SPI control register 1 (SPI_CR1) (not used in I ²S mode) . Added Section 26.6.2: I2S full-duplex . Updated Section 27.2: SPDIFRX main features , Section 27.3: SPDIFRX functional description , Section 27.5.1: Control register (SPDIFRX_CR) and Section 27.5.3: Status register (SPDIFRX_SR) . Added Section 27.3.11: Symbol clock generation , Section 27.3.10: DMA interface , Section 27.5.10: SPDIFRX version register (SPDIFRX_VERR) , Section 27.5.11: SPDIFRX identification register (SPDIFRX_PIDR) and Section 27.5.12: SPDIFRX size identification register (SPDIFRX_SIDR) . Updated Table 173: SPDIFRX interface register map and reset values .

Date

Revision

Changes

04-Jul-2017

Updated Section 1.2: List of abbreviations for registers .

Updated Section 5.4.2: PWR power control/status register (PWR_CSR) .

Replaced former Section 9.3.1: General description with Section 9.3.1: DMA block diagram and Section 9.3.1: DMA block diagram .

Updated Section 11.2: FMC main features, SRAM/NOR-flash chip-select timing register for bank x (FMC_BTRx), Common memory space timing register (FMC_PMEM), Attribute memory space timing register (FMC_PATT) and SDRAM control register x (FMC_SDCRx) .

Updated Table 54: FMC_BCRx bitfields (mode 1) and Table 72: FMC_BCRx bitfields (Synchronous multiplexed write mode) .

Updated Figure 39: Mode 2 write access waveforms and Figure 52: NAND flash controller waveforms for common memory access .

Added Section 12.3.2: QUADSPI pins .

Updated Section 12.3.7: QUADSPI memory-mapped mode , Section 12.3.13: QUADSPI error management and Section 12.5.1: QUADSPI control register (QUADSPI_CR) .

Updated notes in Section 13.13.7: ADC watchdog higher threshold register (ADC_HTR) and Section 13.13.8: ADC watchdog lower threshold register (ADC_LTR) .

Removed former Section 15.3: DCMI pins and added Section 15.4.1: DCMI block diagram .

Updated Table 96: DCMI external signals .

Changed D, PIXCLK, HSYNC and VSYNC with, respectively, DCMI_D, DCMI_HSYNC, DCMI_VSYNC and DCMI_VSYNC in Section 15: Digital camera interface (DCMI) .

Updated I2C master initialization , Section 23.7.2: Control register 2 (FMPI2C_CR2) , Section 23.7.3: Own address 1 register (FMPI2C_OAR1) , Section 23.7.4: Own address 2 register (FMPI2C_OAR2) and Section 23.7.5: Timing register (FMPI2C_TIMINGR) .

Updated Figure 247: Target initialization flow .

Updated Section 25.6.1: Status register (USART_SR) .

Updated Section 26.1: Introduction , Section 26.3.7: SPI configuration and notes in Resetting the SPIx_TXCRC and SPIx_RXCRC values and in Section 26.7.1: SPI control register 1 (SPI_CR1) (not used in I ²S mode) .

Added Section 26.6.2: I2S full-duplex .

Updated Section 27.2: SPDIFRX main features , Section 27.3: SPDIFRX functional description , Section 27.5.1: Control register (SPDIFRX_CR) and Section 27.5.3: Status register (SPDIFRX_SR) .

Added Section 27.3.11: Symbol clock generation , Section 27.3.10: DMA interface , Section 27.5.10: SPDIFRX version register (SPDIFRX_VERR) , Section 27.5.11: SPDIFRX identification register (SPDIFRX_PIDR) and Section 27.5.12: SPDIFRX size identification register (SPDIFRX_SIDR) .

Updated Table 173: SPDIFRX interface register map and reset values .

Table 258. Document revision history (continued)

Date	Revision	Changes
04-Jul-2017	3 (cont'd)	Added Section 28.3.2: SAI pins and internal signals and updated Section 28.3.8: SAI clock generator , Section 28.3.9: Internal FIFOs , Section 28.5.1: SAI global configuration register (SAI_GCR) , Section 28.5.2: SAI configuration register 1 (SAI_ACR1) . Updated Figure 353: SAI functional block diagram and Figure 359: Audio block clock generator overview . Updated Table 177: Example of possible audio frequency sampling range and Table 181: SAI interrupt sources . Updated Section 31.1: Introduction , Section 31.2.3: Peripheral-mode features , Section 31.9: OTG_FS/OTG_HS low-power modes , Section 31.11.4: FIFO RAM allocation , Section 31.15.1: OTG control and status register (OTG_GOTGCTL) , Section 31.15.3: OTG AHB configuration register (OTG_GAHBCFG) , Section 31.15.4: OTG USB configuration register (OTG_GUSBCFG) , Section 31.15.5: OTG reset register (OTG_GRSTCTL) , Section 31.15.6: OTG core interrupt register (OTG_GINTSTS) , Section 31.15.12: OTG receive FIFO size register (OTG_GRXFSIZ) , Section 31.15.14: OTG nonperiodic transmit FIFO/queue status register (OTG_HNPTXSTS) , Section 31.15.15: OTG general core configuration register (OTG_GCCFG) , Section 31.15.20: OTG device IN endpoint transmit FIFO x size register (OTG_DIEPTXFx) , Section 31.15.40: OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) , Section 31.15.52: OTG device IN endpoint x control register (OTG_DIEPCTLx) , Section 31.15.62: OTG device OUT endpoint x control register (OTG_DOEPCTLx) , Section 31.15.53: OTG device IN endpoint x interrupt register (OTG_DIEPINTx) , Section 31.15.59: OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) , Section 31.15.57: OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) , Section 31.15.56: OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) , Section 31.15.63: OTG device OUT endpoint x transfer size register (OTG_DOEPTSIZx) , Section 31.16.3: Device initialization , Section 31.16.4: DMA mode , Section 31.16.5: Host programming model and Section 31.16.6: Device programming model . Added Section 31.15.17: OTG core LPM configuration register (OTG_GLPMCFG) and Section 31.15.55: OTG device IN endpoint x DMA address register (OTG_DIEPDMAX) . Added Table 219: OTG_HS speeds supported and Table 220: OTG_FS speeds supported . Updated Table 227: Core global control and status registers (CSRs) , Table 229: Device-mode control and status registers and Table 235: OTG_FS/OTG_HS register map and reset values . Updated Section 32.1: HDMI-CEC introduction . Added Section 32.3.2: HDMI-CEC block diagram .

Date

Revision

Changes

04-Jul-2017

3
(cont'd)

Added Section 28.3.2: SAI pins and internal signals and updated Section 28.3.8: SAI clock generator , Section 28.3.9: Internal FIFOs , Section 28.5.1: SAI global configuration register (SAI_GCR) , Section 28.5.2: SAI configuration register 1 (SAI_ACR1) .

Updated Figure 353: SAI functional block diagram and Figure 359: Audio block clock generator overview .

Updated Table 177: Example of possible audio frequency sampling range and Table 181: SAI interrupt sources .

Updated Section 31.1: Introduction , Section 31.2.3: Peripheral-mode features , Section 31.9: OTG_FS/OTG_HS low-power modes , Section 31.11.4: FIFO RAM allocation , Section 31.15.1: OTG control and status register (OTG_GOTGCTL) , Section 31.15.3: OTG AHB configuration register (OTG_GAHBCFG) , Section 31.15.4: OTG USB configuration register (OTG_GUSBCFG) , Section 31.15.5: OTG reset register (OTG_GRSTCTL) , Section 31.15.6: OTG core interrupt register (OTG_GINTSTS) , Section 31.15.12: OTG receive FIFO size register (OTG_GRXFSIZ) , Section 31.15.14: OTG nonperiodic transmit FIFO/queue status register (OTG_HNPTXSTS) , Section 31.15.15: OTG general core configuration register (OTG_GCCFG) , Section 31.15.20: OTG device IN endpoint transmit FIFO x size register (OTG_DIEPTXFx) , Section 31.15.40: OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) , Section 31.15.52: OTG device IN endpoint x control register (OTG_DIEPCTLx) , Section 31.15.62: OTG device OUT endpoint x control register (OTG_DOEPCTLx) , Section 31.15.53: OTG device IN endpoint x interrupt register (OTG_DIEPINTx) , Section 31.15.59: OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) , Section 31.15.57: OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) , Section 31.15.56: OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) , Section 31.15.63: OTG device OUT endpoint x transfer size register (OTG_DOEPTSIZx) , Section 31.16.3: Device initialization , Section 31.16.4: DMA mode , Section 31.16.5: Host programming model and Section 31.16.6: Device programming model .

Added Section 31.15.17: OTG core LPM configuration register (OTG_GLPMCFG) and Section 31.15.55: OTG device IN endpoint x DMA address register (OTG_DIEPDMAX) .

Added Table 219: OTG_HS speeds supported and Table 220: OTG_FS speeds supported .

Updated Table 227: Core global control and status registers (CSRs) , Table 229: Device-mode control and status registers and Table 235: OTG_FS/OTG_HS register map and reset values .

Updated Section 32.1: HDMI-CEC introduction .

Added Section 32.3.2: HDMI-CEC block diagram .

Table 258. Document revision history (continued)

Date	Revision	Changes
12-Feb-2018	4	Updated Introduction and Section 1.2: List of abbreviations for registers . Updated Section 2.2.1: Introduction and Section 2.2.2: Memory map and register boundary addresses , and added Figure 2: Memory map . Updated Section 5.4.2: PWR power control/status register (PWR_CSR) . Updated Section 9.1: DMA introduction , Section 9.2: DMA main features . Updated Section 12.5.4: QUADSPI flag clear register (QUADSPI_FCR) . Updated Section 15.7.6: DCMI interrupt clear register (DCMI_ICR) . Updated Section 48.2: I2C main features , Section 48.4.1: I2C block diagram , Section 23.4.11: SMBus specific features , Section 23.6: FMPI2C interrupts and Section 23.7.9: PEC register (FMPI2C_PECR) . Updated Table 127: FMPI2C implementation and Figure 241: Block diagram . Added Table 135: Timing settings for f _I2CCLKof 16 MHz and Table 134: Timing settings for f _I2CCLKof 8 MHz . Updated Section 26.1: Introduction and Section 26.1: Introduction . Updated Section 27.3: SPDIFRX functional description , Section 27.3.6: Data reception management and Section 27.5.1: Control register (SPDIFRX_CR) . Removed former Section 27.3.10: Symbol clock generation , Section 27.5.10: SPDIFRX version register (SPDIFRX_VERR) , Section 27.5.11: SPDIFRX identification register (SPDIFRX_IPIDR) and Section 27.5.12: SPDIFRX size identification register (SPDIFRX_SIDR) . Updated Table 173: SPDIFRX interface register map and reset values . Updated Frame synchronization polarity , Clock generator programming in SPDIF generator mode , Anticipated frame synchronization detection (AFSDET) , Wrong clock configuration in master mode (with NODIV = 0) , Section 28.3.14: Disabling the SAI and Section 28.5.2: SAI configuration register 1 (SAI_ACR1) . Updated Table 174: SAI internal input/output signals , Table 175: SAI input/output pins and Table 182: SAI register map and reset values . Updated Section 30.2: bxCAN main features , Section 30.3.4: Acceptance filters , Section 30.6: Behavior in debug mode and Section 30.9.4: CAN filter registers . Updated Figure 393: Filtering mechanism example , Figure 395: Bit timing and Figure 397: Event flags and interrupt generation . Updated Figure 399: OTG_FS full-speed block diagram , Figure 400: OTG_HS high-speed block diagram , Figure 405: Updating OTG_HFIR dynamically (RLDCTRL = 1) , Figure 410: Interrupt hierarchy and its footnote. Updated Table 227: Core global control and status registers (CSRs) , Table 228: Host-mode control and status registers (CSRs) , Table 229: Device-mode control and status registers , Table 231: Power and clock gating control and status registers , Table 235: OTG_FS/OTG_HS register map and reset values . Removed former Section 31.4.6: External Full-speed OTG PHY using the I2C interface , Section 31.15.12: OTG I2C access register (OTG_GI2CCTL) and former footnote 1 from Figure 403 . Added Table 221: OTG_FS/OTG_HS implementation , Table 222: OTG_FS input/output pins and Table 223: OTG_HS input/output pins .

Date

Revision

Changes

12-Feb-2018

Updated Introduction and Section 1.2: List of abbreviations for registers .

Updated Section 2.2.1: Introduction and Section 2.2.2: Memory map and register boundary addresses , and added Figure 2: Memory map .

Updated Section 5.4.2: PWR power control/status register (PWR_CSR) .

Updated Section 9.1: DMA introduction , Section 9.2: DMA main features .

Updated Section 12.5.4: QUADSPI flag clear register (QUADSPI_FCR) .

Updated Section 15.7.6: DCMI interrupt clear register (DCMI_ICR) .

Updated Section 48.2: I2C main features , Section 48.4.1: I2C block diagram , Section 23.4.11: SMBus specific features , Section 23.6: FMPI2C interrupts and Section 23.7.9: PEC register (FMPI2C_PECR) .

Updated Table 127: FMPI2C implementation and Figure 241: Block diagram .

Added Table 135: Timing settings for f _I2CCLKof 16 MHz and Table 134: Timing settings for f _I2CCLKof 8 MHz .

Updated Section 26.1: Introduction and Section 26.1: Introduction .

Updated Section 27.3: SPDIFRX functional description , Section 27.3.6: Data reception management and Section 27.5.1: Control register (SPDIFRX_CR) .

Removed former Section 27.3.10: Symbol clock generation , Section 27.5.10: SPDIFRX version register (SPDIFRX_VERR) , Section 27.5.11: SPDIFRX identification register (SPDIFRX_IPIDR) and Section 27.5.12: SPDIFRX size identification register (SPDIFRX_SIDR) .

Updated Table 173: SPDIFRX interface register map and reset values .

Updated Frame synchronization polarity , Clock generator programming in SPDIF generator mode , Anticipated frame synchronization detection (AFSDET) , Wrong clock configuration in master mode (with NODIV = 0) , Section 28.3.14: Disabling the SAI and Section 28.5.2: SAI configuration register 1 (SAI_ACR1) .

Updated Table 174: SAI internal input/output signals , Table 175: SAI input/output pins and Table 182: SAI register map and reset values .

Updated Section 30.2: bxCAN main features , Section 30.3.4: Acceptance filters , Section 30.6: Behavior in debug mode and Section 30.9.4: CAN filter registers .

Updated Figure 393: Filtering mechanism example , Figure 395: Bit timing and Figure 397: Event flags and interrupt generation .

Updated Figure 399: OTG_FS full-speed block diagram , Figure 400: OTG_HS high-speed block diagram , Figure 405: Updating OTG_HFIR dynamically (RLDCTRL = 1) , Figure 410: Interrupt hierarchy and its footnote.

Updated Table 227: Core global control and status registers (CSRs) , Table 228: Host-mode control and status registers (CSRs) , Table 229: Device-mode control and status registers , Table 231: Power and clock gating control and status registers , Table 235: OTG_FS/OTG_HS register map and reset values .

Removed former Section 31.4.6: External Full-speed OTG PHY using the I2C interface , Section 31.15.12: OTG I2C access register (OTG_GI2CCTL) and former footnote 1 from Figure 403 .

Added Table 221: OTG_FS/OTG_HS implementation , Table 222: OTG_FS input/output pins and Table 223: OTG_HS input/output pins .

Table 258. Document revision history (continued)

Date	Revision	Changes
12-Feb-2018	4 (cont'd)	Updated Section 31.1: Introduction , Section 31.2.1: General features , Section 31.3: OTG_FS/OTG_HS implementation , Section 31.4.3: OTG_FS/OTG_HS core , Section 31.4.4: Embedded full-speed OTG PHY connected to OTG_FS , Section 31.7: OTG_FS/OTG_HS as a USB host , Section 31.2.2: Host-mode features , Section 31.9: OTG_FS/OTG_HS low-power modes , Section 31.15.1: OTG control and status register (OTG_GOTGCTL) , Section 31.15.3: OTG AHB configuration register (OTG_GAHBCFG) , Section 31.15.4: OTG USB configuration register (OTG_GUSBCFG) , Section 31.15.7: OTG interrupt mask register (OTG_GINTMSK) , Section 31.15.9: OTG receive status debug read [alternate] (OTG_GRXSTSR) , Section 31.15.15: OTG general core configuration register (OTG_GCCFG) , Section 31.15.16: OTG core ID register (OTG_CID) , Section 31.15.20: OTG device IN endpoint transmit FIFO x size register (OTG_DIEPTXFx) , Section 31.15.23: OTG host frame interval register (OTG_HFIR) , Section 31.15.36: OTG device configuration register (OTG_DCFG) , Section 31.15.39: OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK) , Section 31.15.40: OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) and Section 31.15.56: OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) . Added Section 31.4.2: OTG_FS/OTG_HS pin and internal signals , Section 31.4.2: OTG_FS/OTG_HS pin and internal signals , Section 31.15.46: OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK) , Section 31.15.49: OTG device each IN endpoint-1 interrupt mask register (OTG_HS_DIEPEACHMSK1) and Section 31.15.50: OTG device each OUT endpoint-1 interrupt mask register (OTG_HS_DOEPEACHMSK1) . Updated Section 34.1: Unique device ID register (96 bits) and Section 34.2: Flash memory size register .

Date

Revision

Changes

12-Feb-2018

4
(cont'd)

Updated Section 31.1: Introduction , Section 31.2.1: General features , Section 31.3: OTG_FS/OTG_HS implementation , Section 31.4.3: OTG_FS/OTG_HS core , Section 31.4.4: Embedded full-speed OTG PHY connected to OTG_FS , Section 31.7: OTG_FS/OTG_HS as a USB host , Section 31.2.2: Host-mode features , Section 31.9: OTG_FS/OTG_HS low-power modes , Section 31.15.1: OTG control and status register (OTG_GOTGCTL) , Section 31.15.3: OTG AHB configuration register (OTG_GAHBCFG) , Section 31.15.4: OTG USB configuration register (OTG_GUSBCFG) , Section 31.15.7: OTG interrupt mask register (OTG_GINTMSK) , Section 31.15.9: OTG receive status debug read [alternate] (OTG_GRXSTSR) , Section 31.15.15: OTG general core configuration register (OTG_GCCFG) , Section 31.15.16: OTG core ID register (OTG_CID) , Section 31.15.20: OTG device IN endpoint transmit FIFO x size register (OTG_DIEPTXFx) , Section 31.15.23: OTG host frame interval register (OTG_HFIR) , Section 31.15.36: OTG device configuration register (OTG_DCFG) , Section 31.15.39: OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK) , Section 31.15.40: OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) and Section 31.15.56: OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) .

Added Section 31.4.2: OTG_FS/OTG_HS pin and internal signals , Section 31.4.2: OTG_FS/OTG_HS pin and internal signals , Section 31.15.46: OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK) , Section 31.15.49: OTG device each IN endpoint-1 interrupt mask register (OTG_HS_DIEPEACHMSK1) and Section 31.15.50: OTG device each OUT endpoint-1 interrupt mask register (OTG_HS_DOEPEACHMSK1) .

Updated Section 34.1: Unique device ID register (96 bits) and Section 34.2: Flash memory size register .

Table 258. Document revision history (continued)

Date	Revision	Changes
18-Dec-2020	5	Updated Section 1.2: List of abbreviations for registers , Section 6.3.10: RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) , Section 6.3.19: RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) , Section 6.3.24: RCC PLL configuration register (RCC_PLLSAICFGR) , Section 9.3.4: Channel selection , Section 11.6.6: NOR/PSRAM controller registers , Section 12.3.10: QUADSPI configuration , Section 12.5.1: QUADSPI control register (QUADSPI_CR) , Section 12.5.6: QUADSPI communication configuration register (QUADSPI_CCR) , Section 15.1: DCMI introduction , Section 15.3.5: DCMI physical interface , Section 15.3.11: DCMI data format description , Section 15.5: DCMI registers , Section 48.4.1: I2C block diagram , Section 23.6: FMPI2C interrupts , Section 23.9.1: FMPI2C control register 1 (FMPI2C_CR1) , Section 23.9.3: FMPI2C own address 1 register (FMPI2C_OAR1) , Section 24.6.2: I ²C control register 2 (I2C_CR2) , Section 25: Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmitter (UART) , Section 25.6.1: Status register (USART_SR) , Section 25.6.6: Control register 3 (USART_CR3) , Section 26.7: SPI and I ²S registers , Section 27.2: SPDIFRX main features , Section 27.3.6: Data reception management , Section 29.8.8: SDIO data length register (SDIO_DLEN) , Section 31.4.3: OTG_FS/OTG_HS core , Section 31.6: OTG_FS/OTG_HS as a USB peripheral , Section 31.15.8: OTG receive status debug read register (OTG_GRXSTSR) , Section 33.6.1: MCU device ID code and Section 34.1: Unique device ID register (96 bits) . Made two different sections for each register in Section 28: Serial audio interface (SAI) . Added Section 1.1: General information , Section 11.1: FMC introduction and Section 23.4.2: FMPI2C pins and internal signals . Removed former Section 15.3: DCMI clocks . Updated Table 21: RCC register map and reset values , Table 105: DCMI interrupts , Table 142: FMPI2C interrupt requests and Table 182: SAI register map and reset values . Updated Figure 33: FMC memory banks , Figure 107: Coordinates and size of the window after cropping , Figure 110: Advanced-control timer block diagram and Figure 337: SPDIFRX block diagram . Minor text edits across the whole document.
02-Mar-2021	6	Updated Introduction , Section 3.5.2: Program/erase parallelism , Section 13.9: Multi ADC mode , Section 13.10: Temperature sensor , Section 29.8.2: SDIO clock control register (SDIO_CLKCR) and Section 33.4.3: Internal pull-up and pull-down on JTAG pins . Updated Table 6: Program/erase parallelism and Table 28: DMA1 request mapping . Updated Figure 396: CAN frames . Minor text edits across the whole document.

Date

Revision

Changes

18-Dec-2020

Updated Section 1.2: List of abbreviations for registers , Section 6.3.10: RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) , Section 6.3.19: RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) , Section 6.3.24: RCC PLL configuration register (RCC_PLLSAICFGR) , Section 9.3.4: Channel selection , Section 11.6.6: NOR/PSRAM controller registers , Section 12.3.10: QUADSPI configuration , Section 12.5.1: QUADSPI control register (QUADSPI_CR) , Section 12.5.6: QUADSPI communication configuration register (QUADSPI_CCR) , Section 15.1: DCMI introduction , Section 15.3.5: DCMI physical interface , Section 15.3.11: DCMI data format description , Section 15.5: DCMI registers , Section 48.4.1: I2C block diagram , Section 23.6: FMPI2C interrupts , Section 23.9.1: FMPI2C control register 1 (FMPI2C_CR1) , Section 23.9.3: FMPI2C own address 1 register (FMPI2C_OAR1) , Section 24.6.2: I ²C control register 2 (I2C_CR2) , Section 25: Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmitter (UART) , Section 25.6.1: Status register (USART_SR) , Section 25.6.6: Control register 3 (USART_CR3) , Section 26.7: SPI and I ²S registers , Section 27.2: SPDIFRX main features , Section 27.3.6: Data reception management , Section 29.8.8: SDIO data length register (SDIO_DLEN) , Section 31.4.3: OTG_FS/OTG_HS core , Section 31.6: OTG_FS/OTG_HS as a USB peripheral , Section 31.15.8: OTG receive status debug read register (OTG_GRXSTSR) , Section 33.6.1: MCU device ID code and Section 34.1: Unique device ID register (96 bits) .

Made two different sections for each register in Section 28: Serial audio interface (SAI) .

Added Section 1.1: General information , Section 11.1: FMC introduction and Section 23.4.2: FMPI2C pins and internal signals .

Removed former Section 15.3: DCMI clocks .

Updated Table 21: RCC register map and reset values , Table 105: DCMI interrupts , Table 142: FMPI2C interrupt requests and Table 182: SAI register map and reset values .

Updated Figure 33: FMC memory banks , Figure 107: Coordinates and size of the window after cropping , Figure 110: Advanced-control timer block diagram and Figure 337: SPDIFRX block diagram .

Minor text edits across the whole document.

02-Mar-2021

Updated Introduction , Section 3.5.2: Program/erase parallelism , Section 13.9: Multi ADC mode , Section 13.10: Temperature sensor , Section 29.8.2: SDIO clock control register (SDIO_CLKCR) and Section 33.4.3: Internal pull-up and pull-down on JTAG pins .

Updated Table 6: Program/erase parallelism and Table 28: DMA1 request mapping .

Updated Figure 396: CAN frames .

Minor text edits across the whole document.

Table 258. Document revision history (continued)

Date	Revision	Changes
09-Jun-2025	7	Updated Related documents , Section 3.8.5: Flash control register (FLASH_CR) , Backup domain description , Section 5.4.1: PWR power control register (PWR_CR) , Section 5.4.2: PWR power control/status register (PWR_CSR) , Section 6.1.1: System reset , Section 6.1.3: Backup domain reset , Section 6.2: Clocks , Section 7.3.2: I/O pin multiplexer and mapping , Section 6.3.4: RCC clock interrupt register (RCC_CIR) , Section 10.3.6: Pending register (EXTI_PR) , Section 13.2: ADC main features , Temperature sensor , V _REFINTand V _BATinternal channels , Section 13.13.1: ADC status register (ADC_SR) , Section 15.2: DCMI main features , Section 16.3.16: Encoder interface mode , Section 22.6.14: RTC time stamp date register (RTC_TSDR) , Section 24.6.8: I ²C clock control register (I2C_CCR) , Section 26.6.4: Clock generator , Section 23.2: FMPI2C main features , Section 23.4.1: FMPI2C block diagram , Section 23.5: FMPI2C in low-power modes , Section 23.6: FMPI2C interrupts , Section 27.2: SPDIFRX main features , CAN mailbox data length control and time stamp register (CAN_TDTxR) (x = 0..2), and Section 31.7: OTG_FS/OTG_HS as a USB host . Added Section 1.3: Register reset value and note to Section 3.6.3: Read protection (RDP) . Updated Figure 69: Single ADC block diagram and Figure 109: Pixel raster scan order . Updated Table 21: RCC register map and reset values , Table 84: ADC pins , Table 126: RTC register map and reset values , and Table 182: SAI register map and reset values . Changed master/slave into controller/target in Section 23: Fast-mode Plus Inter-integrated circuit interface (FMPI2C) and in Section 24: Inter-integrated circuit (I ²C) interface . Replaced ITEVFEN with ITEVTEN in Section 24: Inter-integrated circuit (I ²C) interface . Rearranged sequence of registers in Section 28: Serial audio interface (SAI) . Minor text edits across the whole document.

Date

Revision

Changes

09-Jun-2025

Updated Related documents , Section 3.8.5: Flash control register (FLASH_CR) , Backup domain description , Section 5.4.1: PWR power control register (PWR_CR) , Section 5.4.2: PWR power control/status register (PWR_CSR) , Section 6.1.1: System reset , Section 6.1.3: Backup domain reset , Section 6.2: Clocks , Section 7.3.2: I/O pin multiplexer and mapping , Section 6.3.4: RCC clock interrupt register (RCC_CIR) , Section 10.3.6: Pending register (EXTI_PR) , Section 13.2: ADC main features , Temperature sensor , V _REFINTand V _BATinternal channels , Section 13.13.1: ADC status register (ADC_SR) , Section 15.2: DCMI main features , Section 16.3.16: Encoder interface mode , Section 22.6.14: RTC time stamp date register (RTC_TSDR) , Section 24.6.8: I ²C clock control register (I2C_CCR) , Section 26.6.4: Clock generator , Section 23.2: FMPI2C main features , Section 23.4.1: FMPI2C block diagram , Section 23.5: FMPI2C in low-power modes , Section 23.6: FMPI2C interrupts , Section 27.2: SPDIFRX main features , CAN mailbox data length control and time stamp register (CAN_TDTxR) (x = 0..2), and Section 31.7: OTG_FS/OTG_HS as a USB host .

Added Section 1.3: Register reset value and note to Section 3.6.3: Read protection (RDP) .

Updated Figure 69: Single ADC block diagram and Figure 109: Pixel raster scan order .

Updated Table 21: RCC register map and reset values , Table 84: ADC pins , Table 126: RTC register map and reset values , and Table 182: SAI register map and reset values .

Changed master/slave into controller/target in Section 23: Fast-mode Plus Inter-integrated circuit interface (FMPI2C) and in Section 24: Inter-integrated circuit (I ²C) interface .

Replaced ITEVFEN with ITEVTEN in Section 24: Inter-integrated circuit (I ²C) interface .

Rearranged sequence of registers in Section 28: Serial audio interface (SAI) .

Minor text edits across the whole document.

Table 258. Document revision history (continued)

Date	Revision	Changes
22-Jan-2026	8	Updated Section 1.1: General information . Updated Figure 14: Clock tree . Updated Exiting low power mode , Section 6.3.4: RCC clock interrupt register (RCC_CIR) , Section 7.4.3: GPIO port output speed register (GPIOx_OSPEEDR) (x = A..H) , SDRAM timing register x (FMC_SDTRx) , Section : SDRAM control register x (FMC_SDCRx) , Section 12.5.1: QUADSPI control register (QUADSPI_CR) , Section 12.5.5: QUADSPI data length register (QUADSPI_DLR) , Section 31.11.4: FIFO RAM allocation , and Simplex communications . Added Section 31.11.1: FIFO allocation for DMA address register storage . Updated Figure 406: Device-mode FIFO address mapping and AHB FIFO access mapping (for OTG_FS) and Figure 407: Device-mode FIFO address mapping and AHB FIFO access mapping (for OTG_HS) . Updated reset values of OTG control and status register (OTG_GOTGCTL) , OTG interrupt register (OTG_GOTGINT) , OTG USB configuration register (OTG_GUSBCFG) , and OTG reset register (OTG_GRSTCTL) . Updated Table 227: Core global control and status registers (CSRs) . Updated Section 32.3.1: HDMI-CEC pin and Figure 433: HDMI-CEC block diagram . Minor text edits across the whole document.
03-Feb-2026	9	Updated Section 1.1: General information .

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