23. Fast-mode Plus Inter-integrated circuit interface (FMPI2C)

23.1 FMPI2C introduction

The FMPI2C peripheral handles the interface between the device and the serial I ² C (inter-integrated circuit) bus. It provides multicontroller capability, and controls all I ² C-bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).

The FMPI2C peripheral is also SMBus (system management bus) and PMBus ^® (power management bus) compatible.

It can use DMA to reduce the CPU load.

23.2 FMPI2C main features

• • I ² C-bus specification rev03 compatibility:
  • – Target and controller modes
  • – Multicontroller capability
  • – Standard-mode (up to 100 kHz)
  • – Fast-mode (up to 400 kHz)
  • – Fast-mode Plus (up to 1 MHz)
  • – 7-bit and 10-bit addressing mode
  • – Multiple 7-bit target addresses (2 addresses, 1 with configurable mask)
  • – All 7-bit-addresses acknowledge mode
  • – General call
  • – Programmable setup and hold times
  • – Easy-to-use event management
  • – Clock stretching (optional)
• • 1-byte buffer with DMA capability
• • Programmable analog and digital noise filters
• • SMBus specification rev 3.0 compatibility ^(a) :
  • – Hardware PEC (packet error checking) generation and verification with ACK control
  • – Command and data acknowledge control
  • – Address resolution protocol (ARP) support
  • – Host and device support
  • – SMBus alert
  • – Timeouts and idle condition detection
• • PMBus rev 1.3 standard compatibility

a. To check the compliance of the GPIOs selected for SMBus with the specified logical levels, refer to the product datasheet.

• • Independent clock

For information on FMPI2C instantiation, refer to Section 23.3: FMPI2C implementation .

23.3 FMPI2C implementation

This section provides an implementation overview with respect to the FMPI2C instantiation.

Table 127. FMPI2C implementation

1. X = supported.

23.4 FMPI2C functional description

In addition to receiving and transmitting data, the peripheral converts them from serial to parallel format and vice versa. The interrupts are enabled or disabled by software. The peripheral is connected to the I ² C-bus through a data pin (SDA) and a clock pin (SCL). It supports Standard-mode (up to 100 kHz), Fast-mode (up to 400 kHz), and Fast-mode Plus (up to 1 MHz) I ² C-bus.

The peripheral can also be connected to an SMBus, through the data pin (SDA), the clock pin (SCL), and an optional SMBus alert pin (SMBA).

The independent clock function allows the FMPI2C communication speed to be independent of the PCLK1 frequency.

For I2C I/Os supporting 20 mA output current drive for Fast-mode Plus operation, the driving capability is enabled through control bits in the system configuration block (SYSCFG).

23.4.1 FMPI2C block diagram

Figure 241. Block diagram

23.4.2 FMPI2C pins and internal signals

Table 128. FMPI2C input/output pins

Table 129. FMPI2C internal input/output signals

Table 129. FMPI2C internal input/output signals (continued)

23.4.3 FMPI2C clock requirements

The FMPI2C kernel is clocked by FMPI2CCLK.

The FMPI2CCLK period \( t_{I2CCLK} \) must respect the following conditions:

where \( t_{LOW} \) is the SCL low time, \( t_{HIGH} \) is the SCL high time, and \( t_{filters} \) is the sum of the analog and digital filter delays (when enabled).

The digital filter delay is \( DNF[3:0] \times t_{I2CCLK} \) .

The PCLK1 clock period \( t_{PCLK} \) must respect the condition \( t_{PCLK} < 4/3 t_{SCL} \) , where \( t_{SCL} \) is the SCL period.

Caution: When the FMPI2C kernel is clocked by PCLK1, this clock must respect the conditions for \( t_{I2CCLK} \) .

23.4.4 FMPI2C mode selection

The peripheral can operate as:

• • Target transmitter
• • Target receiver
• • Controller transmitter
• • Controller receiver

By default, the peripheral operates in target mode. It automatically switches from target to controller mode upon generating START condition, and from controller to target mode upon arbitration loss or upon generating STOP condition. This allows the use of the FMPI2C peripheral in a multicontroller I ² C-bus environment.

Communication flow

In controller mode, the FMPI2C peripheral initiates a data transfer and generates the clock signal. Serial data transfers always begin with a START condition and end with a STOP condition. Both START and STOP conditions are generated in controller mode by software.

In target mode, the peripheral recognizes its own 7-bit or 10-bit address, and the general call address. The general call address detection can be enabled or disabled by software. The reserved SMBus addresses can also be enabled by software.

Data and addresses are transferred as 8-bit bytes, MSB first. The address is contained in the first byte (7-bit addressing) or in the first two bytes (10-bit addressing) following the START condition. The address is always transmitted in controller mode.

The following figure shows the transmission of a single byte. The controller generates nine SCL pulses. The transmitter sends the eight data bits to the receiver with the SCL pulses 1 to 8. Then the receiver sends the acknowledge bit to the transmitter with the ninth SCL pulse.

Figure 242. I ² C-bus protocol

The acknowledge can be enabled or disabled by software. The own addresses of the FMI2C peripheral can be selected by software.

23.4.5 FMI2C initialization

Enabling and disabling the peripheral

Before enabling the FMI2C peripheral, configure and enable its clock through the RCC, and initialize its control registers.

The FMI2C peripheral can then be enabled by setting the PE bit of the FMI2C_CR1 register.

Disabling the FMI2C peripheral by clearing the PE bit resets the FMI2C peripheral. Refer to Section 23.4.6 for more details.

Noise filters

Before enabling the FMI2C peripheral by setting the PE bit of the FMI2C_CR1 register, the user must configure the analog and/or digital noise filters, as required.

The analog noise filter on the SDA and SCL inputs complies with the I ² C-bus specification which requires, in Fast-mode and Fast-mode Plus, the suppression of spikes shorter than 50 ns. Enabled by default, it can be disabled by setting the ANFOFF bit.

The digital filter is controlled through the DNF[3:0] bitfield of the FMI2C_CR1 register. When it is enabled, the internal SCL and SDA signals only take the level of their corresponding I ² C-bus line when remaining stable for more than DNF[3:0] periods of FMI2CCLK. This allows suppressing spikes shorter than the filtering capacity period programmable from one to fifteen FMI2CCLK periods.

The following table compares the two filters.

Table 130. Comparison of analog and digital filters

1. Maximum duration of spikes that the filter can suppress

Caution: The filter configuration cannot be changed when the FMPI2C peripheral is enabled.

FMPI2C timings

To ensure correct data hold and setup times, the corresponding timings must be configured through the PRESC[3:0], SCLDEL[3:0], and SDADEL[3:0] bitfields of the FMPI2C_TIMINGR register.

The STM32CubeMX tool calculates and provides the FMPI2C_TIMINGR content in the I2C configuration window.

Figure 243. Setup and hold timings

When the SCL falling edge is internally detected, the delay \( t_{SDADEL} \) (impacting the hold time \( t_{HD;DAT} \) ) is inserted before sending SDA output:

The total SDA output delay is:

The \( t_{SYNC1} \) duration depends upon:

• • SCL falling slope
• • input delay \( t_{AF(min)} < t_{AF} < t_{AF(max)} \) introduced by the analog filter (if enabled)
• • input delay \( t_{DNF} = DNF \times t_{I2CCLK} \) introduced by the digital filter (if enabled)
• • delay due to SCL synchronization to FMPI2CCLK clock (two to three FMPI2CCLK periods)

To bridge the undefined region of the SCL falling edge, the user must set SDADEL[3:0] so as to fulfill the following condition:

Note: \( t_{AF(min)} \) and \( t_{AF(max)} \) are only part of the condition when the analog filter is enabled. Refer to the device datasheet for \( t_{AF} \) values.

The \( t_{HD;DAT} \) time can at maximum be 3.45 µs for Standard-mode, 0.9 µs for Fast-mode, and 0.45 µs for Fast-mode Plus. It must be lower than the maximum of \( t_{VD;DAT} \) by a transition time. This maximum must only be met if the device does not stretch the LOW period ( \( t_{LOW} \) ) of the SCL signal. When it stretches SCL, the data must be valid by the set-up time before it releases the clock.

The SDA rising edge is usually the worst case. The previous condition then becomes:

Note: This condition can be violated when NOSTRETCH = 0, because the device stretches SCL low to guarantee the set-up time, according to the SCLDEL[3:0] value.

After \( t_{SDADEL} \) , or after sending SDA output when the target had to stretch the clock because the data was not yet written in FMPI2C_TXDR register, the SCL line is kept at low level during the setup time. This setup time is \( t_{SCLDEL} = (SCLDEL + 1) \times t_{PRESC} \) , where \( t_{PRESC} = (PRESC + 1) \times t_{I2CCLK} \) . \( t_{SCLDEL} \) impacts the setup time \( t_{SU;DAT} \) .

To bridge the undefined region of the SDA transition (rising edge usually worst case), the user must program SCLDEL[3:0] so as to fulfill the following condition:

Refer to the following table for \( t_f \) , \( t_r \) , \( t_{HD;DAT} \) , \( t_{VD;DAT} \) , and \( t_{SU;DAT} \) standard values.

Use the SDA and SCL real transition time values measured in the application to widen the scope of allowed SDADEL[3:0] and SCLDEL[3:0] values. Use the maximum SDA and SCL transition time values defined in the standard to make the device work reliably regardless of the application.

Note: At every clock pulse, after SCL falling edge detection, FMPI2C operating as controller or target stretches SCL low during at least \( [(SDADEL + SCLDEL + 1) \times (PRESC + 1) + 1] \times t_{I2CCLK} \) , in both transmission and reception modes. In transmission mode, if the data is not yet written in I2C_TXDR when SDA delay elapses, the I2C peripheral keeps stretching SCL low

until the next data is written. Then new data MSB is sent on SDA output, and SCLDEL counter starts, continuing stretching SCL low to guarantee the data setup time.

When the NOSTRETCH bit is set in target mode, the SCL is not stretched. The SDADEL[3:0] must then be programmed so that it ensures a sufficient setup time.

Table 131. I ² C-bus and SMBus specification data setup and hold times

Additionally, in controller mode, the SCL clock high and low levels must be configured by programming the PRESC[3:0], SCLH[7:0], and SCLL[7:0] bitfields of the FMPI2C_TIMINGR register.

When the SCL falling edge is internally detected, the FMPI2C peripheral releasing the SCL output after the delay \( t_{SCLL} = (SCLL + 1) \times t_{PRESC} \) , where \( t_{PRESC} = (PRESC + 1) \times t_{I2CCLK} \) . The \( t_{SCLL} \) delay impacts the SCL low time \( t_{LOW} \) .

When the SCL rising edge is internally detected, the FMPI2C peripheral forces the SCL output to low level after the delay \( t_{SCLH} = (SCLH + 1) \times t_{PRESC} \) , where \( t_{PRESC} = (PRESC + 1) \times t_{I2CCLK} \) . The \( t_{SCLH} \) impacts the SCL high time \( t_{HIGH} \) .

Refer to FMPI2C controller initialization for more details.

Caution: Changing the timing configuration and the NOSTRETCH configuration is not allowed when the FMPI2C peripheral is enabled. Like the timing settings, the target NOSTRETCH settings must also be done before enabling the peripheral. Refer to FMPI2C target initialization for more details.

Figure 244. FMPI2C initialization flow

graph TD; A([Initial settings]) --> B[Clear PE bit in FMPI2C_CR1]; B --> C["Configure ANFOFF and DNF[3:0] in FMPI2C_CR1"]; C --> D["Configure PRESC[3:0], SDADEL[3:0], SCLDEL[3:0], SCLH[7:0], SCLL[7:0] in FMPI2C_TIMINGR"]; D --> E[Configure NOSTRETCH in FMPI2C_CR1]; E --> F[Set PE bit in FMPI2C_CR1]; F --> G([End]);

23.4.6 FMPI2C reset

The reset of the FMPI2C peripheral is performed by clearing the PE bit of the FMPI2C_CR1 register. It has the effect of releasing the SCL and SDA lines. Internal state machines are reset and the communication control bits and the status bits revert to their reset values. This reset does not impact the configuration registers.

The impacted register bits are:

1. 1. FMPI2C_CR2 register: START, STOP, PECBYTE, and NACK
2. 2. FMPI2C_ISR register: BUSY, TXE, TXIS, RXNE, ADDR, NACKF, TCR, TC, STOPF, BERR, ARLO, PECERR, TIMEOUT, ALERT, and OVR

PE must be kept low during at least three APB clock cycles to perform the FMPI2C reset. To ensure this, perform the following software sequence:

1. 1. Write PE = 0
2. 2. Check PE = 0
3. 3. Write PE = 1

23.4.7 FMPI2C data transfer

The data transfer is managed through transmit and receive data registers and a shift register.

Reception

The SDA input fills the shift register. After the eighth SCL pulse (when the complete data byte is received), the shift register is copied into the FMPI2C_RXDR register if it is empty (RXNE = 0). If RXNE = 1, which means that the previous received data byte has not yet been read, the SCL line is stretched low until FMPI2C_RXDR is read. The stretch occurs between the eighth and the ninth SCL pulse (before the acknowledge pulse).

Figure 245. Data reception

MSv35976V1

Transmission

If the FMI2C_TXDR register is not empty (TXE = 0), its content is copied into the shift register after the ninth SCL pulse (the acknowledge pulse). Then the shift register content is shifted out on the SDA line. If TXE = 1, which means that no data is written yet in FMI2C_TXDR, the SCL line is stretched low until FMI2C_TXDR is written. The stretch starts after the ninth SCL pulse.

Figure 246. Data transmission

Hardware transfer management

The FMI2C features an embedded byte counter to manage byte transfer and to close the communication in various modes, such as:

• – NACK, STOP and ReSTART generation in controller mode
• – ACK control in target receiver mode
• – PEC generation/checking

In controller mode, the byte counter is always used. By default, it is disabled in target mode. It can be enabled by software, by setting the SBC (target byte control) bit of the FMI2C_CR1 register.

The number of bytes to transfer is programmed in the NBBYTES[7:0] bitfield of the FMI2C_CR2 register. If this number is greater than 255, or if a receiver wants to control the acknowledge value of a received data byte, the reload mode must be selected, by setting the RELOAD bit of the FMI2C_CR2 register. In this mode, the TCR flag is set when the number of bytes programmed in NBBYTES[7:0] is transferred (when the associated counter reaches zero), and an interrupt is generated if TCIE is set. SCL is stretched as long as the TCR flag is set. TCR is cleared by software when NBBYTES[7:0] is written to a non-zero value.

When NBBYTES[7:0] is reloaded with the last number of bytes to transfer, the RELOAD bit must be cleared.

When RELOAD = 0 in controller mode, the counter can be used in two modes:

• • Automatic end (AUTOEND = 1 in the FMPI2C_CR2 register). In this mode, the controller automatically sends a STOP condition once the number of bytes programmed in the NBBYTES[7:0] bitfield is transferred.
• • Software end (AUTOEND = 0 in the FMPI2C_CR2 register). In this mode, a software action is expected once the number of bytes programmed in the NBBYTES[7:0] bitfield is transferred; the TC flag is set and an interrupt is generated if the TCIE bit is set. The SCL signal is stretched as long as the TC flag is set. The TC flag is cleared by software when the START or STOP bit of the FMPI2C_CR2 register is set. This mode must be used when the controller wants to send a RESTART condition.

Caution: The AUTOEND bit has no effect when the RELOAD bit is set.

Table 132. FMPI2C configuration

23.4.8 FMPI2C target mode

FMPI2C target initialization

To work in target mode, the user must enable at least one target address. The FMPI2C_OAR1 and FMPI2C_OAR2 registers are available to program the target own addresses OA1 and OA2, respectively.

OA1 can be configured either in 7-bit (default) or in 10-bit addressing mode, by setting the OA1MODE bit of the FMPI2C_OAR1 register.

OA1 is enabled by setting the OA1EN bit of the FMPI2C_OAR1 register.

If an additional target addresses are required, the second target address OA2 can be configured. Up to seven OA2 LSBs can be masked, by configuring the OA2MSK[2:0] bitfield of the FMPI2C_OAR2 register. Therefore, for OA2MSK[2:0] configured from 1 to 6, only OA2[7:2], OA2[7:3], OA2[7:4], OA2[7:5], OA2[7:6], or OA2[7] are compared with the received address. When OA2MSK[2:0] is other than 0, the address comparator for OA2 excludes the FMPI2C reserved addresses (0000 XXX and 1111 XXX) and they are not acknowledged. If OA2MSK[2:0] = 7, all received 7-bit addresses are acknowledged (except reserved addresses). OA2 is always a 7-bit address.

When enabled through the specific bit, the reserved addresses can be acknowledged if they are programmed in the FMPI2C_OAR1 or FMPI2C_OAR2 register with OA2MSK[2:0] = 0.

OA2 is enabled by setting the OA2EN bit of the FMPI2C_OAR2 register.

The general call address is enabled by setting the GCEN bit of the FMPI2C_CR1 register.

When the FMPI2C peripheral is selected by one of its enabled addresses, the ADDR interrupt status flag is set, and an interrupt is generated if the ADDRIE bit is set.

By default, the target uses its clock stretching capability, which means that it stretches the SCL signal at low level when required, to perform software actions. If the controller does not

support clock stretching, FMPI2C must be configured with NOSTRETCH = 1 in the FMPI2C_CR1 register.

After receiving an ADDR interrupt, if several addresses are enabled, the user must read the ADDCODE[6:0] bitfield of the FMPI2C_ISR register to check which address matched. The DIR flag must also be checked to know the transfer direction.

Target with clock stretching

As long as the NOSTRETCH bit of the FMPI2C_CR1 register is zero (default), the FMPI2C peripheral operating as an I ² C-bus target stretches the SCL signal in the following situations:

• • The ADDR flag is set and the received address matches with one of the enabled target addresses.
  The stretch is released when the software clears the ADDR flag by setting the ADDRCF bit.
• • In transmission, the previous data transmission is completed and no new data is written in FMPI2C_TXDR register, or the first data byte is not written when the ADDR flag is cleared (TXE = 1).
  The stretch is released when the data is written to the FMPI2C_TXDR register.
• • In reception, the FMPI2C_RXDR register is not read yet and a new data reception is completed.
  The stretch is released when FMPI2C_RXDR is read.
• • In target byte control mode (SBC bit set) with reload (RELOAD bit set), the last data byte transfer is finished (TCR bit set).
  The stretch is released when the TCR is cleared by writing a non-zero value in the NBBYTES[7:0] bitfield.
• • After SCL falling edge detection.
  The stretch is released after \( [(\text{SDADEL} + \text{SCLDEL} + 1) \times (\text{PRESC} + 1) + 1] \times t_{i2\text{CCLK}} \) period.

Target without clock stretching

As long as the NOSTRETCH bit of the FMPI2C_CR1 register is set, the FMPI2C peripheral operating as an I ² C-bus target does not stretch the SCL signal.

The SCL clock is not stretched while the ADDR flag is set.

In transmission, the data must be written in the FMPI2C_TXDR register before the first SCL pulse corresponding to its transfer occurs. If not, an underrun occurs, the OVR flag is set in the FMPI2C_ISR register and an interrupt is generated if the ERRIE bit of the FMPI2C_CR1 register is set. The OVR flag is also set when the first data transmission starts and the STOPF bit is still set (has not been cleared). Therefore, if the user clears the STOPF flag of the previous transfer only after writing the first data to be transmitted in the next transfer, it ensures that the OVR status is provided, even for the first data to be transmitted.

In reception, the data must be read from the FMPI2C_RXDR register before the ninth SCL pulse (ACK pulse) of the next data byte occurs. If not, an overrun occurs, the OVR flag is set in the FMPI2C_ISR register, and an interrupt is generated if the ERRIE bit of the FMPI2C_CR1 register is set.

Target byte control mode

To allow byte ACK control in target reception mode, the target byte control mode must be enabled, by setting the SBC bit of the FMP12C_CR1 register. This is required to comply with SMBus standards.

The reload mode must be selected to allow byte ACK control in target reception mode (RELOAD = 1). To get control of each byte, NBBYTES[7:0] must be initialized to 0x1 in the ADDR interrupt subroutine, and reloaded to 0x1 after each received byte. When the byte is received, the TCR bit is set, stretching the SCL signal low between the eighth and the ninth SCL pulse. The user can read the data from the FMP12C_RXDR register, and then decide to acknowledge it or not by configuring the ACK bit of the FMP12C_CR2 register. The SCL stretch is released by programming NBBYTES to a non-zero value: the acknowledge or not-acknowledge is sent and the next byte can be received.

NBYTES[7:0] can be loaded with a value greater than 0x1. Receiving then continues until the corresponding number of bytes are received.

Note: The SBC bit must be configured when the FMP12C peripheral is disabled, when the target is not addressed, or when ADDR = 1.

The RELOAD bit value can be changed when ADDR = 1, or when TCR = 1.

Caution: The target byte control mode is not compatible with NOSTRETCH mode. Setting SBC when NOSTRETCH = 1 is not allowed.

Figure 247. Target initialization flow

graph TD; A([Target initialization]) --> B[Initial settings]; B --> C[Clear OA1EN, OA2EN in FMP12C_OAR1/FMP12C_OAR2]; C --> D["Configure OA1[9:0], OA1MODE, OA1EN, OA2[6:0], OA2MSK[2:0], OA2EN, and GCEN"]; D --> E[Optional: Configure SBC in FMP12C_CR1(1)]; E --> F[Enable interrupts and/or DMA in FMP12C_CR1]; F --> G([End]);

1. 1. SBC must be set to support SMBus features.

Target transmitter

A transmit interrupt status (TXIS) flag is generated when the FMPI2C_TXDR register becomes empty. An interrupt is generated if the TXIE bit of the FMPI2C_CR1 register is set.

The TXIS flag is cleared when the FMPI2C_TXDR register is written with the next data byte to transmit.

When NACK is received, the NACKF flag is set in the FMPI2C_ISR register and an interrupt is generated if the NACKIE bit of the FMPI2C_CR1 register is set. The target automatically releases the SCL and SDA lines to let the controller perform a STOP or a RESTART condition. The TXIS bit is not set when a NACK is received.

When STOP is received and the STOPIE bit of the FMPI2C_CR1 register is set, the STOPF flag of the FMPI2C_ISR register is set and an interrupt is generated. In most applications, the SBC bit is usually programmed to 0. In this case, if TXE = 0 when the target address is received (ADDR = 1), the user can choose either to send the content of the FMPI2C_TXDR register as the first data byte, or to flush the FMPI2C_TXDR register, by setting the TXE bit in order to program a new data byte.

In target byte control mode (SBC = 1), the number of bytes to transmit must be programmed in NBBYTES[7:0] in the address match interrupt subroutine (ADDR = 1). In this case, the number of TXIS events during the transfer corresponds to the value programmed in NBBYTES[7:0].

Caution: When NOSTRETCH = 1, the SCL clock is not stretched while the ADDR flag is set, so the user cannot flush the FMPI2C_TXDR register content in the ADDR subroutine to program the first data byte. The first data byte to send must be previously programmed in the FMPI2C_TXDR register:

• • This data can be the one written in the last TXIS event of the previous transmission message.
• • If this data byte is not the one to send, the FMPI2C_TXDR register can be flushed, by setting the TXE bit, to program a new data byte. The STOPF bit must be cleared only after these actions. This guarantees that they are executed before the first data transmission starts, following the address acknowledge.

If STOPF is still set when the first data transmission starts, an underrun error is generated (the OVR flag is set).

If a TXIS event (transmit interrupt or transmit DMA request) is required, the user must set the TXIS bit in addition to the TXE bit, to generate the event.

Figure 248. Transfer sequence flow for FMPI2C target transmitter, NOSTRETCH = 0

graph TD; Start([Target transmission]) --> Init[Target initialization]; Init --> ADDR{FMPI2C_ISR.ADDR = 1?}; ADDR -- No --> Init; ADDR -- Yes --> Read[Read ADDCODE and DIR in FMPI2C_ISR<br/>Optional: Set FMPI2C_ISR.TXE = 1<br/>Set FMPI2C_ICR.ADDRCF]; Read --> TXIS{FMPI2C_ISR.TXIS = 1?}; TXIS -- No --> Read; TXIS -- Yes --> Write[Write FMPI2C_TXDR.TXDATA]; Write --> Read

Figure 249. Transfer sequence flow for FMPI2C target transmitter, NOSTRETCH = 1

graph TD; A([Target transmission]) --> B[Target initialization]; B --> C{FMPI2C_ISR.TXIS = 1?}; C -- Yes --> D[Write FMPI2C_TXDR.TXDATA]; D --> C; C -- No --> E{FMPI2C_ISR.STOPE = 1?}; E -- Yes --> F[Optional: Set FMPI2C_ISR.TXE = 1 and FMPI2C_ISR.TXIS=1]; F --> G[Set FMPI2C_ICR.STOPCF]; G --> C; E -- No --> C;

Figure 250. Transfer bus diagrams for FMI2C target transmitter (mandatory events only)

Example FMI2C target transmitter 3 bytes with 1st data flushed
NOSTRETCH=0:

legend:

• transmission
• reception
• — SCL stretch

• EV1: ADDR ISR: check ADDCODE and DIR, set TXE, set ADDRCF
• EV2: TXIS ISR: wr data1
• EV3: TXIS ISR: wr data2
• EV4: TXIS ISR: wr data3
• EV5: TXIS ISR: wr data4 (not sent)

Example FMI2C target transmitter 3 bytes without 1st data flush,
NOSTRETCH=0:

legend :

• transmission
• reception
• — SCL stretch

• EV1: ADDR ISR: check ADDCODE and DIR, set ADDRCF
• EV2: TXIS ISR: wr data2
• EV3: TXIS ISR: wr data3
• EV4: TXIS ISR: wr data4 (not sent)

Example FMI2C target transmitter 3 bytes, NOSTRETCH=1:

legend:

• transmission
• reception
• — SCL stretch

• EV1: wr data1
• EV2: TXIS ISR: wr data2
• EV3: TXIS ISR: wr data3
• EV4: TXIS ISR: wr data4 (not sent)
• EV5: STOPF ISR: (optional: set TXE and TXIS), set STOPCF

MSV35975V2

Target receiver

The RXNE bit of the FMPI2C_ISR register is set when the FMPI2C_RXDR is full, which generates an interrupt if the RXIE bit of the FMPI2C_CR1 register is set. RXNE is cleared when FMPI2C_RXDR is read.

When STOP condition is received and the STOPIE bit of the FMPI2C_CR1 register is set, the STOPF flag in the FMPI2C_ISR register is set and an interrupt is generated.

Figure 251. Transfer sequence flow for FMPI2C target receiver, NOSTRETCH = 0

graph TD; A([Target reception]) --> B[Target initialization]; B --> C{FMPI2C_ISR.ADDR = 1?}; C -- No --> B; C -- Yes --> D[Read ADDCODE and DIR in FMPI2C_ISR<br/>Set FMPI2C_ICR.ADDRCF]; D --> E{FMPI2C_ISR.RXNE = 1?}; E -- No --> D; E -- Yes --> F[Write FMPI2C_RXDR.RXDATA]; F --> E;

Figure 252. Transfer sequence flow for FMPI2C target receiver, NOSTRETCH = 1

graph TD
    Start([Target reception]) --> Init[Target initialization]
    Init --> RXNE{FMPI2C_ISR.RXNE = 1?}
    RXNE -- Yes --> Read[Read FMPI2C_RXDR.RXDATA]
    Read --> RXNE
    RXNE -- No --> STOPF{FMPI2C_ISR.STOPF = 1?}
    STOPF -- Yes --> Stop[Set FMPI2C_ICR.STOPCF]
    Stop --> RXNE
    STOPF -- No --> RXNE
    

Figure 253. Transfer bus diagrams for FMPI2C target receiver (mandatory events only)

23.4.9 FMPI2C controller mode

FMPI2C controller initialization

Before enabling the peripheral, the FMPI2C controller clock must be configured, by setting the SCLH and SCLL bits in the FMPI2C_TIMINGR register.

The STM32CubeMX tool calculates and provides the FMPI2C_TIMINGR content in the I2C Configuration window.

A clock synchronization mechanism is implemented in order to support multicontroller environment and target clock stretching.

In order to allow clock synchronization:

• • The low level of the clock is counted using the SCLL counter, starting from the SCL low level internal detection.
• • The high level of the clock is counted using the SCLH counter, starting from the SCL high level internal detection.

FMPI2C detects its own SCL low level after a \( t_{\text{SYNC1}} \) delay depending on the SCL falling edge, SCL input noise filters (analog and digital), and SCL synchronization to the FMPI2CxCLK clock. FMPI2C releases SCL to high level once the SCLL counter reaches the value programmed in the SCLL[7:0] bitfield of the FMPI2C_TIMINGR register.

FMPI2C detects its own SCL high level after a \( t_{\text{SYNC2}} \) delay depending on the SCL rising edge, SCL input noise filters (analog and digital), and SCL synchronization to the FMPI2CxCLK clock. FMPI2C ties SCL to low level once the SCLH counter reaches the value programmed in the SCLH[7:0] bitfield of the FMPI2C_TIMINGR register.

Consequently the controller clock period is:

The duration of \( t_{\text{SYNC1}} \) depends upon:

• • SCL falling slope
• • input delay induced by the analog filter (when enabled)
• • input delay induced by the digital filter (when enabled): \( \text{DNF}[3:0] \times t_{\text{I2CCLK}} \)
• • delay due to SCL synchronization with the FMPI2CCLK clock (two to three FMPI2CCLK periods)

The duration of \( t_{\text{SYNC2}} \) depends upon:

• • SCL rising slope
• • input delay induced by the analog filter (when enabled)
• • input delay induced by the digital filter (when enabled): \( \text{DNF}[3:0] \times t_{\text{I2CCLK}} \)
• • delay due to SCL synchronization with the FMPI2CCLK clock (two to three FMPI2CCLK periods)

Figure 254. Controller clock generation

Caution: For compliance with the I ² C-bus or SMBus specification, the controller clock must respect the timings in the following table.

Table 133. I ² C-bus and SMBus specification clock timings

Note: The SCLL[7:0] bitfield also determines the t _BUF and t _SU:STA timings and SCLH[7:0] the t _HD:STA and t _SU:STO timings.

Refer to Section 23.4.10 for examples of FMPI2C_TIMINGR settings versus the FMPI2CCLK frequency.

Controller communication initialization (address phase)

To initiate the communication with a target to address, set the following bitfields of the FMPI2C_CR2 register:

• • ADD10: addressing mode (7-bit or 10-bit)
• • SADD[9:0]: target address to send
• • RD_WRN: transfer direction
• • HEAD10R: in case of 10-bit address read, this bit determines whether the header only (for direction change) or the complete address sequence is sent.
• • NBYTES[7:0]: the number of bytes to transfer; if equal to or greater than 255 bytes, the bitfield must initially be set to 0xFF.

Note: Changing these bitfields is not allowed as long as the START bit is set.

Before launching the communication, make sure that the I ² C-bus is idle. This can be checked using the bus idle detection function or by verifying that the IDR bits of the GPIOs selected as SDA and SCL are set. Any low-level incident on the I ² C-bus lines that coincides with the START condition asserted by the FMPI2C peripheral may cause its deadlock if not filtered out by the input filters. If such incidents cannot be prevented, design the software so that it restores the normal operation of the FMPI2C peripheral in case of a deadlock, by toggling the PE bit of the FMPI2C_CR1 register.

To launch the communication, set the START bit of the FMPI2C_CR2 register. The controller then automatically sends a START condition followed by the target address, either immediately if the BUSY flag is low, or \( t_{BUF} \) time after the BUSY flag transits from high to low state. The BUSY flag is set upon sending the START condition.

In case of an arbitration loss, the controller automatically switches back to target mode and can acknowledge its own address if it is addressed as a target.

Note: The START bit is reset by hardware when the target address is sent on the bus, whatever the received acknowledge value. The START bit is also reset by hardware upon arbitration loss.

In 10-bit addressing mode, the controller automatically keeps resending the target address in a loop until the first address byte (first seven address bits) is acknowledged by the target. Setting the ADDRCF bit makes FMPI2C quit that loop.

If the FMPI2C peripheral is addressed as a target (ADDR = 1) while the START bit is set, the FMPI2C peripheral switches to target mode and the START bit is cleared when the ADDRCF bit is set.

Note: The same procedure is applied for a repeated START condition. In this case, BUSY = 1.

Figure 255. Controller initialization flow

graph TD
    A([Controller initialization]) --> B[Initial settings]
    B --> C[Enable interrupts and/or DMA in FMPI2C_CR1]
    C --> D([End])

Initialization of a controller receiver addressing a 10-bit address target

If the target address is in 10-bit format, the user can choose to send the complete read sequence, by clearing the HEAD10R bit of the FMPI2C_CR2 register. In this case, the controller automatically sends the following complete sequence after the START bit is set:

(RE)START + Target address 10-bit header Write + Target address second byte + (RE)START + Target address 10-bit header Read.

Figure 256. 10-bit address read access with HEAD10R = 0

If the controller addresses a 10-bit address target, transmits data to this target and then reads data from the same target, a controller transmission flow must be done first. Then a repeated START is set with the 10-bit target address configured with HEAD10R = 1. In this case, the controller sends this sequence:

RESTART + Target address 10-bit header Read.

Figure 257. 10-bit address read access with HEAD10R = 1

Controller transmitter

In the case of a write transfer, the TXIS flag is set after each byte transmission, after the ninth SCL pulse when an ACK is received.

A TXIS event generates an interrupt if the TXIE bit of the FMI2C_CR1 register is set. The flag is cleared when the FMI2C_TXDR register is written with the next data byte to transmit.

The number of TXIS events during the transfer corresponds to the value programmed in NBBYTES[7:0]. If the total number of data bytes to transmit is greater than 255, the reload mode must be selected by setting the RELOAD bit in the FMI2C_CR2 register. In this case, when the NBBYTES[7:0] number of data bytes is transferred, the TCR flag is set and the SCL line is stretched low until NBBYTES[7:0] is written with a non-zero value.

When RELOAD = 0 and the number of data bytes defined in NBBYTES[7:0] is transferred:

• • In automatic end mode (AUTOEND = 1), a STOP condition is automatically sent.
• • In software end mode (AUTOEND = 0), the TC flag is set and the SCL line is stretched low, to perform software actions:
  • – A RESTART condition can be requested by setting the START bit of the FMI2C_CR2 register with the proper target address configuration and the number of bytes to transfer. Setting the START bit clears the TC flag and sends the START condition on the bus.
  • – A STOP condition can be requested by setting the STOP bit of the FMI2C_CR2 register. This clears the TC flag and sends a STOP condition on the bus.

When a NACK is received, the TXIS flag is not set and a STOP condition is automatically sent. The NACKF flag of the FMI2C_ISR register is set. An interrupt is generated if the NACKIE bit is set.

Figure 258. Transfer sequence flow for FMI2C controller transmitter, N ≤ 255 bytes

graph TD; A([Controller transmission]) --> B[Controller initialization]; B --> C["NBYTES = N<br/>AUTOEND = 0 for RESTART; 1 for STOP<br/>Configure target address<br/>Set FMI2C_CR2.START"]; C --> D{FMI2C_ISR.TXIS = 1?}; D -- No --> E{FMI2C_ISR.NACKF = 1?}; D -- Yes --> F[Write FMI2C_TXDR]; F --> G{NBYTES transmitted?}; G -- No --> D; G -- Yes --> H{FMI2C_ISR.TC = 1?}; H -- Yes --> I["Set FMI2C_CR2.START<br/>with target address NBYTES<br/>..."]; H -- No --> J([End]); I --> J; E -- Yes --> J; E -- No --> D;

MSV35969V2

Figure 259. Transfer sequence flow for FMPI2C controller transmitter, N > 255 bytes

graph TD
    Start([Controller
transmission]) --> Init[Controller initialization]
    Init --> Setup[NBYTES = 0xFF; N=N-255
RELOAD = 1
Configure target address
Set FMPI2C_CR2.START]
    Setup --> NACKF{FMPI2C_ISR.NACKF
= 1?}
    NACKF -- No --> TXIS{FMPI2C_ISR.TXIS
= 1?}
    NACKF -- Yes --> End1([End])
    TXIS -- No --> NACKF
    TXIS -- Yes --> Write[Write FMPI2C_TXDR]
    Write --> Transmitted{NBYTES
transmitted?}
    Transmitted -- No --> TXIS
    Transmitted -- Yes --> TC{FMPI2C_ISR.TC
= 1?}
    TC -- Yes --> SetStart[Set FMPI2C_CR2.START
with target address
NBYTES ...]
    SetStart --> End2([End])
    TC -- No --> TCR{FMPI2C_ISR.TCR
= 1?}
    TCR -- No --> TC
    TCR -- Yes --> Logic[IF N < 256
NBYTES = N; N = 0; RELOAD = 0
AUTOEND = 0 for RESTART; 1 for STOP
ELSE
NBYTES = 0xFF; N = N-255
RELOAD = 1]
    Logic --> NACKF
    
    style End1 fill:#fff,stroke:#000
    style End2 fill:#fff,stroke:#000
    style Start fill:#fff,stroke:#000
  

Figure 260. Transfer bus diagrams for FMPI2C controller transmitter (mandatory events only)

Controller receiver

In the case of a read transfer, the RXNE flag is set after each byte reception, after the eighth SCL pulse. An RXNE event generates an interrupt if the RXIE bit of the FMP12C_CR1 register is set. The flag is cleared when FMP12C_RXDR is read.

If the total number of data bytes to receive is greater than 255, select the reload mode, by setting the RELOAD bit of the FMP12C_CR2 register. In this case, when the NBBYTES[7:0] number of data bytes is transferred, the TCR flag is set and the SCL line is stretched low until NBBYTES[7:0] is written with a non-zero value.

When RELOAD = 0 and the number of data bytes defined in NBBYTES[7:0] is transferred:

• • In automatic end mode (AUTOEND = 1), a NACK and a STOP are automatically sent after the last received byte.
• • In software end mode (AUTOEND = 0), a NACK is automatically sent after the last received byte. The TC flag is set and the SCL line is stretched low in order to allow software actions:
  • – A RESTART condition can be requested by setting the START bit of the FMP12C_CR2 register, with the proper target address configuration and the number of bytes to transfer. Setting the START bit clears the TC flag and sends the START condition and the target address on the bus.
  • – A STOP condition can be requested by setting the STOP bit of the FMP12C_CR2 register. This clears the TC flag and sends a STOP condition on the bus.

Figure 261. Transfer sequence flow for FMPI2C controller receiver, N ≤ 255 bytes

graph TD; A([Controller reception]) --> B[Controller initialization]; B --> C["NBYTES = N<br/>AUTOEND = 0 for RESTART; 1 for STOP<br/>Configure target address<br/>Set FMPI2C_CR2.START"]; C --> D{FMPI2C_ISR.RX.NE = 1?}; D -- No --> C; D -- Yes --> E[Read FMPI2C_RXDR]; E --> F{NBYTES received?}; F -- No --> C; F -- Yes --> G{FMPI2C_ISR.TC = 1?}; G -- No --> H([End]); G -- Yes --> I["Set FMPI2C_CR2.START<br/>with target address<br/>NBYTES ..."]; I -.-> J[...];

MSv35971V2

Figure 262. Transfer sequence flow for FMPI2C controller receiver, N &gt; 255 bytes

graph TD; Start([Controller reception]) --> Init[Controller initialization]; Init --> Config["NBYTES = 0xFF; N = N-255<br/>RELOAD = 1<br/>Configure target address<br/>Set FMPI2C_CR2.START"]; Config --> RXNE{FMPI2C_ISR.RXNE = 1?}; RXNE -- No --> RXNE; RXNE -- Yes --> Read[Read FMPI2C_RXDR]; Read --> Received{NBYTES received?}; Received -- No --> RXNE; Received -- Yes --> TC{FMPI2C_ISR.TC = 1?}; TC -- Yes --> SetStart["Set FMPI2C_CR2.START<br/>with target address<br/>NBYTES ..."]; SetStart -.-> Dots[...]; TC -- No --> TCR{FMPI2C_ISR.TCR = 1?}; TCR -- Yes --> EndCondition["IF N < 256<br/>NBYTES = N; N = 0; RELOAD = 0<br/>AUTOEND = 0 for RESTART; 1 for STOP<br/>ELSE<br/>NBYTES = 0xFF; N = N - 255<br/>RELOAD = 1"]; TCR -- No --> End([End]); EndCondition --> End; EndCondition --> RXNE;

MSv35972V2

Figure 263. Transfer bus diagrams for FMPI2C controller receiver (mandatory events only)

23.4.10 FMPI2C_TIMINGR register configuration examples

The following tables provide examples of how to program the FMPI2C_TIMINGR register to obtain timings compliant with the I ² C-bus specification. To get more accurate configuration values, use the STM32CubeMX tool ( I ² C Configuration window).

1. 1. \( t_{SCL} \) is greater than \( t_{SCLL} + t_{SCLH} \) due to SCL internal detection delay. Values provided for \( t_{SCL} \) are examples only.
2. 2. \( t_{SYNC1} + t_{SYNC2} \) minimum value is \( 4 \times f_{I2CCLK} = 500 \) ns. Example with \( t_{SYNC1} + t_{SYNC2} = 1000 \) ns.
3. 3. \( t_{SYNC1} + t_{SYNC2} \) minimum value is \( 4 \times f_{I2CCLK} = 500 \) ns. Example with \( t_{SYNC1} + t_{SYNC2} = 750 \) ns.
4. 4. \( t_{SYNC1} + t_{SYNC2} \) minimum value is \( 4 \times f_{I2CCLK} = 500 \) ns. Example with \( t_{SYNC1} + t_{SYNC2} = 655 \) ns.

1. 1. \( t_{SCL} \) is greater than \( t_{SCLL} + t_{SCLH} \) due to SCL internal detection delay. Values provided for \( t_{SCL} \) are examples only.
2. 2. \( t_{SYNC1} + t_{SYNC2} \) minimum value is \( 4 \times f_{I2CCLK} = 250 \) ns. Example with \( t_{SYNC1} + t_{SYNC2} = 1000 \) ns.
3. 3. \( t_{SYNC1} + t_{SYNC2} \) minimum value is \( 4 \times f_{I2CCLK} = 250 \) ns. Example with \( t_{SYNC1} + t_{SYNC2} = 750 \) ns.
4. 4. \( t_{SYNC1} + t_{SYNC2} \) minimum value is \( 4 \times f_{I2CCLK} = 250 \) ns. Example with \( t_{SYNC1} + t_{SYNC2} = 500 \) ns.

23.4.11 SMBus specific features

Introduction

The system management bus (SMBus) is a two-wire interface through which various devices can communicate with each other and with the rest of the system. It is based on operation principles of the I ² C-bus. The SMBus provides a control bus for system and power management related tasks.

The FMI2C peripheral is compatible with the SMBus specification ( http://smbus.org ).

The system management bus specification refers to three types of devices:

• • Target is a device that receives or responds to a command.
• • Controller is a device that issues commands, generates clocks, and terminates the transfer.
• • Host is a specialized controller that provides the main interface to the system CPU. A host must be a controller-target and must support the SMBus host notify protocol. Only one host is allowed in a system.

The FMI2C peripheral can be configured as a controller or a target device, and also as a host.

Bus protocols

There are eleven possible command protocols for any given device. The device can use any or all of them to communicate. These are: Quick Command , Send Byte , Receive Byte , Write Byte , Write Word , Read Byte , Read Word , Process Call , Block Read , Block Write , and Block Write-Block Read Process Call . The protocols must be implemented by the user software.

For more details on these protocols, refer to the SMBus specification ( http://smbus.org ).

STM32CubeMX implements an SMBus stack thanks to X-CUBE-SMBUS, a downloadable software pack that allows basic SMBus configuration per FMI2C instance.

Address resolution protocol (ARP)

SMBus target address conflicts can be resolved by dynamically assigning a new unique address to each target device. To provide a mechanism to isolate each device for the purpose of address assignment, each device must implement a unique 128-bit device identifier (UDID). In the FMI2C peripheral, it is implemented by software.

The FMI2C peripheral supports the Address resolution protocol (ARP). The SMBus device default address (0b1100 001) is enabled by setting the SMBDEN bit of the FMI2C_CR1 register. The ARP commands must be implemented by the user software.

Arbitration is also performed in target mode for ARP support.

For more details on the SMBus address resolution protocol, refer to the SMBus specification ( http://smbus.org ).

Received command and data acknowledge control

An SMBus receiver must be able to NACK each received command or data. In order to allow the ACK control in target mode, the target byte control mode must be enabled, by setting the SBC bit of the FMI2C_CR1 register. Refer to Target byte control mode for more details.

Host notify protocol

To enable the host notify protocol, set the SMBHEN bit of the FMI2C_CR1 register. The FMI2C peripheral then acknowledges the SMBus host address (0b0001 000).

When this protocol is used, the device acts as a controller and the host as a target.

SMBus alert

The FMI2C peripheral supports the SMBALERT# optional signal through the SMBA pin. With the SMBALERT# signal, an SMBus target device can signal to the SMBus host that it wants to talk. The host processes the interrupt and simultaneously accesses all SMBALERT# devices through the alert response address (0b0001 100). Only the device/devices which pulled SMBALERT# low acknowledges/acknowledge the alert response address.

When the FMI2C peripheral is configured as an SMBus target device (SMBHEN = 0), the SMBA pin is pulled low by setting the ALERTEN bit of the FMI2C_CR1 register. The alert response address is enabled at the same time.

When the FMI2C peripheral is configured as an SMBus host (SMBHEN = 1), the ALERT flag of the FMI2C_ISR register is set when a falling edge is detected on the SMBA pin and ALERTEN = 1. An interrupt is generated if the ERRRIE bit of the FMI2C_CR1 register is set. When ALERTEN = 0, the alert line is considered high even if the external SMBA pin is low.

Note: If the SMBus alert pin is not required, keep the ALERTEN bit cleared. The SMBA pin can then be used as a standard GPIO.

Packet error checking

A packet error checking mechanism introduced in the SMBus specification improves reliability and communication robustness. The packet error checking is implemented by appending a packet error code (PEC) at the end of each message transfer. The PEC is calculated by using the \( C(x) = x^8 + x^2 + x + 1 \) CRC-8 polynomial on all the message bytes (including addresses and read/write bits).

The FMI2C peripheral embeds a hardware PEC calculator and allows a not acknowledge to be sent automatically when the received byte does not match the hardware calculated PEC.

Timeouts

To comply with the SMBus timeout specifications, the FMI2C peripheral embeds hardware timers.

Table 136. SMBus timeout specifications

1. 1. \( t_{LOW:SEXT} \) is the cumulative time a given target device is allowed to extend the clock cycles in one message from the initial START to the STOP. It is possible that another target device or the controller also extends the clock causing the combined clock low extend time to be greater than \( t_{LOW:SEXT} \) . The value provided applies to a single target device connected to a full-target controller.
2. 2. \( t_{LOW:MEXT} \) is the cumulative time a controller device is allowed to extend its clock cycles within each byte of a message as defined from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is possible that a target device or another controller also extends the clock, causing the combined clock low time to be greater than \( t_{LOW:MEXT} \) on a given byte. The value provided applies to a single target device connected to a full-target controller.

Bus idle detection

A controller can assume that the bus is free if it detects that the clock and data signals have been high for \( t_{IDLE} > t_{HIGH(max)} \) (refer to the table in Section 23.4.9 ).

This timing parameter covers the condition where a controller is dynamically added to the bus, and may not have detected a state transition on the SMBCLK or SMBDAT lines. In this case, the controller must wait long enough to ensure that a transfer is not currently in progress. The FMPI2C peripheral supports a hardware bus idle detection.

23.4.12 SMBus initialization

In addition to the FMPI2C initialization for the I ² C-bus, the use of the peripheral for the SMBus communication requires some extra initialization steps.

Received command and data acknowledge control (target mode)

An SMBus receiver must be able to NACK each received command or data. To allow ACK control in target mode, the target byte control mode must be enabled, by setting the SBC bit of the FMPI2C_CR1 register. Refer to Target byte control mode for more details.

Specific addresses (target mode)

The specific SMBus addresses must be enabled if required. Refer to Bus idle detection for more details.

The SMBus device default address (0b1100 001) is enabled by setting the SMBDEN bit of the FMPI2C_CR1 register.

The SMBus host address (0b0001 000) is enabled by setting the SMBHEN bit of the FMPI2C_CR1 register.

The alert response address (0b0001100) is enabled by setting the ALERTEN bit of the FMPI2C_CR1 register.

Packet error checking

PEC calculation is enabled by setting the PECEN bit of the FMPI2C_CR1 register. Then the PEC transfer is managed with the help of the hardware byte counter associated with the NBYTES[7:0] bitfield of the FMPI2C_CR2 register. The PECEN bit must be configured before enabling the FMPI2C.

The PEC transfer is managed with the hardware byte counter, so the SBC bit must be set when interfacing the SMBus in target mode. The PEC is transferred after transferring NBYTES[7:0] - 1 data bytes, if the PECBYTE bit is set and the RELOAD bit is cleared. If RELOAD is set, PECBYTE has no effect.

Caution: Changing the PECEN configuration is not allowed when the FMPI2C peripheral is enabled.

Table 137. SMBus with PEC configuration

Timeout detection

The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits of the FMPI2C_TIMEOUTR register. The timers must be programmed in such a way that they detect a timeout before the maximum time given in the SMBus specification.

\( t_{\text{TIMEOUT}} \) check

To check the \( t_{\text{TIMEOUT}} \) parameter, load the 12-bit TIMEOUTA[11:0] bitfield with the timer reload value. Keep the TIDLE bit at 0 to detect the SCL low level timeout.

Then set the TIMOUTEN bit of the FMPI2C_TIMEOUTR register, to enable the timer.

If SCL is tied low for longer than the \( (\text{TIMEOUTA} + 1) \times 2048 \times t_{\text{I2CCLK}} \) period, the TIMEOUT flag of the FMPI2C_ISR register is set.

Refer to Table 138 .

Caution: Changing the TIMEOUTA[11:0] bitfield and the TIDLE bit values is not allowed when the TIMOUTEN bit is set.

t _LOW:SEXT and t _LOW:MEXT check

A 12-bit timer associated with the TIMEOUTB[11:0] bitfield allows checking \( t_{LOW:SEXT} \) for the FMI2C peripheral operating as a target, or \( t_{LOW:MEXT} \) when it operates as a controller. As the standard only specifies a maximum, the user can choose the same value for both. The timer is then enabled by setting the TEXTEN bit in the FMI2C_TIMEOUTR register.

If the SMBus peripheral performs a cumulative SCL stretch for longer than the \( (TIMEOUTB + 1) \times 2048 \times t_{I2CCLK} \) period, and within the timeout interval described in Bus idle detection section, the TIMEOUT flag of the FMI2C_ISR register is set.

Refer to Table 139 .

Caution: Changing the TIMEOUTB[11:0] bitfield value is not allowed when the TEXTEN bit is set.

Bus idle detection

To check the \( t_{IDLE} \) period, the TIMEOUTA[11:0] bitfield associated with 12-bit timer must be loaded with the timer reload value. Keep the TIDLE bit at 1 to detect both SCL and SDA high level timeout. Then set the TIMOUTEN bit of the FMI2C_TIMEOUTR register to enable the timer.

If both the SCL and SDA lines remain high for longer than the \( (TIMEOUTA + 1) \times 4 \times t_{I2CCLK} \) period, the TIMEOUT flag of the FMI2C_ISR register is set.

Refer to Table 140 .

Caution: Changing the TIMEOUTA[11:0] bitfield and the TIDLE bit values is not allowed when the TIMOUTEN bit is set.

23.4.13 SMBus FMI2C_TIMEOUTR register configuration examples

The following tables provide examples of settings to reach desired \( t_{TIMEOUT} \) , \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) , and \( t_{IDLE} \) timings at different \( f_{I2CCLK} \) frequencies.

Table 138. TIMEOUTA[11:0] for maximum \( t_{TIMEOUT} \) of 25 ms

Table 139. TIMEOUTB[11:0] for maximum \( t_{LOW:SEXT} \) and \( t_{LOW:MEXT} \) of 8 ms

Table 140. TIMEOUTA[11:0] for maximum \( t_{IDLE} \) of 50 \( \mu\text{s} \)

23.4.14 SMBus target mode

In addition to FMPI2C target transfer management (refer to Section 23.4.8: FMPI2C target mode ), this section provides extra software flowcharts to support SMBus.

SMBus target transmitter

When using the FMPI2C peripheral in SMBus mode, set the SBC bit to enable the PEC transmission at the end of the programmed number of data bytes. When the PECBYTE bit is set, the number of bytes programmed in NBBYTES[7:0] includes the PEC transmission. In that case, the total number of TXIS interrupts is NBBYTES[7:0] - 1, and the content of the FMPI2C_PECR register is automatically transmitted if the controller requests an extra byte after the transfer of the NBBYTES[7:0] - 1 data bytes.

Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

Figure 265. Transfer sequence flow for SMBus target transmitter N bytes + PEC

graph TD; Start([SMBus target transmission]) --> Init[Target initialization]; Init --> Addr{FMPI2C_ISR.ADDR = 1?}; Addr -- No --> Init; Addr -- Yes --> Read[Read ADDCODE and DIR in FMPI2C_ISR<br/>FMPI2C_CR2.NBYTES = N + 1<br/>PECBYTE = 1<br/>Set FMPI2C_ICR.ADDRCF]; Read --> TxIs{FMPI2C_ISR.TXIS = 1?}; TxIs -- No --> Read; TxIs -- Yes --> Write[Write FMPI2C_TXDR.TXDATA]; Write --> Read; SCL[SCL stretched]

Figure 266. Transfer bus diagram for SMBus target transmitter (SBC = 1)

SMBus target receiver

When using the FMI2C peripheral in SMBus mode, set the SBC bit to enable the PEC checking at the end of the programmed number of data bytes. To allow the ACK control of each byte, the reload mode must be selected (RELOAD = 1). Refer to Target byte control mode for more details.

To check the PEC byte, the RELOAD bit must be cleared and the PECBYTE bit must be set. In this case, after the receipt of NBYTES[7:0] - 1 data bytes, the next received byte is compared with the internal FMI2C_PECR register content. A NACK is automatically generated if the comparison does not match, and an ACK is automatically generated if the comparison matches, whatever the ACK bit value. Once the PEC byte is received, it is copied into the FMI2C_RXDR register like any other data, and the RXNE flag is set.

Upon a PEC mismatch, the PECERR flag is set and an interrupt is generated if the ERRIE bit of the FMI2C_CR1 register is set.

If no ACK software control is required, the user can set the PECBYTE bit and, in the same write operation, load NBYTES[7:0] with the number of bytes to receive in a continuous flow. After the receipt of NBYTES[7:0] - 1 bytes, the next received byte is checked as being the PEC.

Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

Figure 267. Transfer sequence flow for SMBus target receiver N bytes + PEC

graph TD; Start([SMBus target reception]) --> Init[Target initialization]; Init --> ADDR{FMPI2C_ISR.ADDR = 1?}; ADDR -- No --> ADDR; ADDR -- Yes --> Config["Read ADDCODE and DIR in FMPI2C_ISR
FMPI2C_CR2.NBYTES = 1, RELOAD = 1
PECBYTE = 1
Set FMPI2C_ICR.ADDRCF"]; Config --> RXNE1{FMPI2C_ISR.RXNE = FMPI2C_ISR.TCR = 1?}; RXNE1 -- No --> RXNE1; RXNE1 -- Yes --> ReadData1["Read FMPI2C_RXDR.RXDATA
Program FMPI2C_CR2.NACK = 0
FMPI2C_CR2.NBYTES = 1
N = N - 1"]; ReadData1 --> N1{N = 1?}; N1 -- No --> RXNE1; N1 -- Yes --> ConfigEnd["Read FMPI2C_RXDR.RXDATA
Program RELOAD = 0
NACK = 0 and NBBYTES = 1"]; ConfigEnd --> RXNE2{FMPI2C_ISR.RXNE = 1?}; RXNE2 -- No --> RXNE2; RXNE2 -- Yes --> ReadData2[Read FMPI2C_RXDR.RXDATA]; ReadData2 --> End([End]);

Figure 268. Bus transfer diagrams for SMBus target receiver (SBC = 1)

23.4.15 SMBus controller mode

In addition to FMI2C controller transfer management (refer to Section 23.4.9: FMI2C controller mode ), this section provides extra software flowcharts to support SMBus.

SMBus controller transmitter

When the SMBus controller wants to transmit the PEC, the PECBYTE bit must be set and the number of bytes must be loaded in the NBYTES[7:0] bitfield, before setting the START bit. In this case, the total number of TXIS interrupts is NBYTES[7:0] - 1. So if the PECBYTE bit is set when NBYTES[7:0] = 0x1, the content of the FMI2C_PECR register is automatically transmitted.

If the SMBus controller wants to send a STOP condition after the PEC, the automatic end mode must be selected (AUTOEND = 1). In this case, the STOP condition automatically follows the PEC transmission.

When the SMBus controller wants to send a RESTART condition after the PEC, the software mode must be selected (AUTOEND = 0). In this case, once NBYTES[7:0] - 1 are transmitted, the FMPI2C_PECR register content is transmitted. The TC flag is set after the PEC transmission, stretching the SCL line low. The RESTART condition must be programmed in the TC interrupt subroutine.

Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

Figure 269. Bus transfer diagrams for SMBus controller transmitter

SMBus controller receiver

When the SMBus controller wants to receive, at the end of the transfer, the PEC followed by a STOP condition, the automatic end mode can be selected (AUTOEND = 1). The PECBYTE bit must be set and the target address programmed before setting the START bit. In this case, after the receipt of NBBYTES[7:0] - 1 data bytes, the next received byte is automatically checked versus the FMI2C_PECR register content. A NACK response is given to the PEC byte, followed by a STOP condition.

When the SMBus controller receiver wants to receive, at the end of the transfer, the PEC byte followed by a RESTART condition, the software mode must be selected (AUTOEND = 0). The PECBYTE bit must be set and the target address programmed before setting the START bit. In this case, after the receipt of NBBYTES[7:0] - 1 data bytes, the next received byte is automatically checked versus the FMI2C_PECR register content. The TC flag is set after the PEC byte reception, stretching the SCL line low. The RESTART condition can be programmed in the TC interrupt subroutine.

Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

Figure 270. Bus transfer diagrams for SMBus controller receiver

23.4.16 Error conditions

The following errors are the conditions that can cause the communication to fail.

Bus error (BERR)

A bus error is detected when a START or a STOP condition is detected and is not located after a multiple of nine SCL clock pulses. START or STOP condition is detected when an SDA edge occurs while SCL is high.

The bus error flag is set only if the FMPI2C peripheral is involved in the transfer as controller or addressed target (that is, not during the address phase in target mode).

In case of a misplaced START or RESTART detection in target mode, the FMPI2C peripheral enters address recognition state like for a correct START condition.

When a bus error is detected, the BERR flag of the FMI2C_ISR register is set, and an interrupt is generated if the ERRIE bit of the FMI2C_CR1 register is set.

Arbitration loss (ARLO)

An arbitration loss is detected when a high level is sent on the SDA line, but a low level is sampled on the SCL rising edge.

In controller mode, arbitration loss is detected during the address phase, data phase and data acknowledge phase. In this case, the SDA and SCL lines are released, the START control bit is cleared by hardware and the controller switches automatically to target mode.

In target mode, arbitration loss is detected during data phase and data acknowledge phase. In this case, the transfer is stopped and the SCL and SDA lines are released.

When an arbitration loss is detected, the ARLO flag of the FMI2C_ISR register is set and an interrupt is generated if the ERRIE bit of the FMI2C_CR1 register is set.

Overrun/underrun error (OVR)

An overrun or underrun error is detected in target mode when NOSTRETCH = 1 and:

• • In reception when a new byte is received and the RXDR register has not been read yet. The new received byte is lost, and a NACK is automatically sent as a response to the new byte.
• • In transmission:
  • – When STOPF = 1 and the first data byte must be sent. The content of the FMI2C_TXDR register is sent if TXE = 0, 0xFF if not.
  • – When a new byte must be sent and the FMI2C_TXDR register has not been written yet, 0xFF is sent.

When an overrun or underrun error is detected, the OVR flag of the FMI2C_ISR register is set and an interrupt is generated if the ERRIE bit of the FMI2C_CR1 register is set.

Packet error checking error (PECERR)

A PEC error is detected when the received PEC byte does not match the FMI2C_PECR register content. A NACK is automatically sent after the wrong PEC reception.

When a PEC error is detected, the PECERR flag of the FMI2C_ISR register is set and an interrupt is generated if the ERRIE bit of the FMI2C_CR1 register is set.

Timeout error (TIMEOUT)

A timeout error occurs for any of these conditions:

• • TIDLE = 0 and SCL remains low for the time defined in the TIMEOUTA[11:0] bitfield: this is used to detect an SMBus timeout.
• • TIDLE = 1 and both SDA and SCL remains high for the time defined in the TIMEOUTA[11:0] bitfield: this is used to detect a bus idle condition.
• • Controller cumulative clock low extend time reaches the time defined in the TIMEOUTB[11:0] bitfield (SMBus \( t_{LOW:MEXT} \) parameter).
• • Target cumulative clock low extend time reaches the time defined in the TIMEOUTB[11:0] bitfield (SMBus \( t_{LOW:SEXT} \) parameter).

When a timeout violation is detected in controller mode, a STOP condition is automatically sent.

When a timeout violation is detected in target mode, the SDA and SCL lines are automatically released.

When a timeout error is detected, the TIMEOUT flag is set in the FMPI2C_ISR register and an interrupt is generated if the ERRIE bit of the FMPI2C_CR1 register is set.

Alert (ALERT)

The ALERT flag is set when the FMPI2C peripheral is configured as a host (SMBHEN = 1), the SMBALERT# signal detection is enabled (ALERTEN = 1), and a falling edge is detected on the SMBA pin. An interrupt is generated if the ERRIE bit of the FMPI2C_CR1 register is set.

23.5 FMPI2C in low-power modes

Table 141. Effect of low-power modes to FMPI2C

23.6 FMPI2C interrupts

The following table gives the list of FMPI2C interrupt requests.

Table 142. FMPI2C interrupt requests

Table 142. FMI2C interrupt requests (continued)

23.7 FMI2C DMA requests

23.7.1 Transmission using DMA

DMA (direct memory access) can be enabled for transmission by setting the TXDMAEN bit of the FMI2C_CR1 register. Data is loaded from an SRAM area configured through the DMA peripheral (see Section 9: Direct memory access controller (DMA) ) to the FMI2C_TXDR register whenever the TXIS bit is set.

Only the data are transferred with DMA.

In controller mode, the initialization, the target address, direction, number of bytes and START bit are programmed by software (the transmitted target address cannot be transferred with DMA). When all data are transferred using DMA, DMA must be initialized before setting the START bit. The end of transfer is managed with the NBBYTES counter. Refer to Controller transmitter .

In target mode:

• • With NOSTRETCH = 0, when all data are transferred using DMA, DMA must be initialized before the address match event, or in ADDR interrupt subroutine, before clearing ADDR.
• • With NOSTRETCH = 1, the DMA must be initialized before the address match event.

The PEC transfer is managed with the counter associated to the NBBYTES[7:0] bitfield. Refer to SMBus target transmitter and SMBus controller transmitter .

Note: If DMA is used for transmission, it is not required to set the TXIE bit.

23.7.2 Reception using DMA

DMA (direct memory access) can be enabled for reception by setting the RXDMAEN bit of the FMI2C_CR1 register. Data is loaded from the FMI2C_RXDR register to an SRAM area configured through the DMA peripheral (refer to Section 9: Direct memory access controller (DMA) ) whenever the RXNE bit is set. Only the data (including PEC) are transferred with DMA.

In controller mode, the initialization, the target address, direction, number of bytes and START bit are programmed by software. When all data are transferred using DMA, DMA

must be initialized before setting the START bit. The end of transfer is managed with the NBYTES counter.

In target mode with NOSTRETCH = 0, when all data are transferred using DMA, DMA must be initialized before the address match event, or in the ADDR interrupt subroutine, before clearing the ADDR flag.

The PEC transfer is managed with the counter associated to the NBYTES[7:0] bitfield. Refer to SMBus target receiver and SMBus controller receiver .

Note: If DMA is used for reception, it is not required to set the RXIE bit.

23.8 FMPI2C debug modes

When the device enters debug mode (core halted), the SMBus timeout either continues working normally or stops, depending on the DBG_I2CFMP_SMBUS_TIMEOUT bit in the DBG block.

23.9 FMPI2C registers

Refer to Section 1.2 for the list of abbreviations used in register descriptions.

The registers are accessed by words (32-bit).

23.9.1 FMPI2C control register 1 (FMPI2C_CR1)

Address offset: 0x00

Reset value: 0x0000 0000

Access: no wait states, except if a write access occurs while a write access is ongoing. In this case, wait states are inserted in the second write access, until the previous one is completed. The latency of the second write access can be up to \( 2 \times PCLK1 + 6 \times FMPI2CCLK \) .

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 PECEN : PEC enable

0: PEC calculation disabled

1: PEC calculation enabled

0: The SMBALERT# signal on SMBA pin is not supported in host mode (SMBHEN = 1). In device mode (SMBHEN = 0), the SMBA pin is released and the alert response address header is disabled (0001100x followed by NACK).

1: The SMBALERT# signal on SMBA pin is supported in host mode (SMBHEN = 1). In device mode (SMBHEN = 0), the SMBA pin is driven low and the alert response address header is enabled (0001100x followed by ACK).

Note: When ALERTEN = 0, the SMBA pin can be used as a standard GPIO.

0: Device default address disabled. Address 0b1100001x is NACKed.

1: Device default address enabled. Address 0b1100001x is ACKed.

0: Host address disabled. Address 0b0001000x is NACKed.

1: Host address enabled. Address 0b0001000x is ACKed.

0: General call disabled. Address 0b00000000 is NACKed.

1: General call enabled. Address 0b00000000 is ACKed.

Bit 18 Reserved, must be kept at reset value.

This bit is used to disable clock stretching in target mode. It must be kept cleared in controller mode.

0: Clock stretching enabled

1: Clock stretching disabled

Note: This bit can be programmed only when the FMPPI2C peripheral is disabled (PE = 0).

This bit is used to enable hardware byte control in target mode.

0: Target byte control disabled

1: Target byte control enabled

0: DMA mode disabled for reception

1: DMA mode enabled for reception

0: DMA mode disabled for transmission

1: DMA mode enabled for transmission

Bit 13 Reserved, must be kept at reset value.

0: Analog noise filter enabled

1: Analog noise filter disabled

Note: This bit can be programmed only when the FMPPI2C peripheral is disabled (PE = 0).

These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter, filters spikes with a length of up to \( \text{DNF}[3:0] * t_{\text{I2CCLK}} \)
0000: Digital filter disabled
0001: Digital filter enabled and filtering capability up to one \( t_{\text{I2CCLK}} \)

...

1111: digital filter enabled and filtering capability up to fifteen \( t_{\text{I2CCLK}} \)

Note: If the analog filter is enabled, the digital filter is added to it. This filter can be programmed only when the FMPI2C peripheral is disabled (PE = 0).

0: Error detection interrupts disabled
1: Error detection interrupts enabled

Note: Any of these errors generates an interrupt:

• - arbitration loss (ARLO)
• - bus error detection (BERR)
• - overrun/underrun (OVR)
• - timeout detection (TIMEOUT)
• - PEC error detection (PECERR)
• - alert pin event detection (ALERT)

0: Transfer complete interrupt disabled
1: Transfer complete interrupt enabled

Note: Any of these events generates an interrupt:

• Transfer complete (TC)
• Transfer complete reload (TCR)

0: STOP detection (STOPF) interrupt disabled
1: STOP detection (STOPF) interrupt enabled

0: Not acknowledge (NACKF) received interrupts disabled
1: Not acknowledge (NACKF) received interrupts enabled

0: Address match (ADDR) interrupts disabled
1: Address match (ADDR) interrupts enabled

0: Receive (RXNE) interrupt disabled
1: Receive (RXNE) interrupt enabled

0: Transmit (TXIS) interrupt disabled
1: Transmit (TXIS) interrupt enabled

0: Peripheral disabled
1: Peripheral enabled

Note: When PE = 0, the FMPI2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least three APB clock cycles.

23.9.2 FMPI2C control register 2 (FMPI2C_CR2)

Address offset: 0x04

Reset value: 0x0000 0000

Access: no wait states, except if a write access occurs while a write access is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x FMPI2CCLK.

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 PECBYTE : Packet error checking byte

This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE = 0.

0: No PEC transfer

1: PEC transmission/reception is requested

Note: Writing 0 to this bit has no effect.

This bit has no effect when RELOAD is set, and in target mode when SBC = 0.

Bit 25 AUTOEND : Automatic end mode (controller mode)

This bit is set and cleared by software.

0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low.

1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are transferred.

Note: This bit has no effect in target mode or when the RELOAD bit is set.

Bit 24 RELOAD : NBYTES reload mode

This bit is set and cleared by software.

0: The transfer is completed after the NBYTES data transfer (STOP or RESTART follows).

1: The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR flag is set when NBYTES data are transferred, stretching SCL low.

Bits 23:16 NBYTES[7:0] : Number of bytes

The number of bytes to be transmitted/received is programmed there. This field is don't care in target mode with SBC = 0.

Note: Changing these bits when the START bit is set is not allowed.

The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE = 0.

0: an ACK is sent after current received byte.

1: a NACK is sent after current received byte.

Note: Writing 0 to this bit has no effect.

This bit is used only in target mode: in controller receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value.

When an overrun occurs in target receiver NOSTRETCH mode, a NACK is automatically generated, whatever the NACK bit value.

When hardware PEC checking is enabled (PECBYTE = 1), the PEC acknowledge value does not depend on the NACK value.

This bit only pertains to controller mode. It is set by software and cleared by hardware when a STOP condition is detected or when PE = 0.

0: No STOP generation

1: STOP generation after current byte transfer

Note: Writing 0 to this bit has no effect.

This bit is set by software. It is cleared by hardware after the START condition followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software, by setting the ADDRCF bit of the FMPI2C_ICR register.

0: No START generation

1: RESTART/START generation:

If the FMPI2C is already in controller mode with AUTOEND = 0, setting this bit generates a repeated START condition when RELOAD = 0, after the end of the NBBYTES transfer.

Otherwise, setting this bit generates a START condition once the bus is free.

Note: Writing 0 to this bit has no effect.

The START bit can be set even if the bus is BUSY or FMPI2C is in target mode.

This bit has no effect when RELOAD is set.

0: The controller sends the complete 10-bit target address read sequence: START + 2 bytes 10-bit address in write direction + RESTART + first seven bits of the 10-bit address in read direction.

1: The controller sends only the first seven bits of the 10-bit address, followed by read direction.

Note: Changing this bit when the START bit is set is not allowed.

0: The controller operates in 7-bit addressing mode

1: The controller operates in 10-bit addressing mode

Note: Changing this bit when the START bit is set is not allowed.

0: Controller requests a write transfer

1: Controller requests a read transfer

Note: Changing this bit when the START bit is set is not allowed.

Bits 9:0 SADD[9:0] : Target address (controller mode)

Condition: In 7-bit addressing mode (ADD10 = 0):

SADD[7:1] must be written with the 7-bit target address to be sent. Bits SADD[9], SADD[8] and SADD[0] are don't care.

Condition: In 10-bit addressing mode (ADD10 = 1):

SADD[9:0] must be written with the 10-bit target address to be sent.

Note: Changing these bits when the START bit is set is not allowed.

23.9.3 FMI2C own address 1 register (FMI2C_OAR1)

Address offset: 0x08

Reset value: 0x0000 0000

Access: no wait states, except if a write access occurs while a write access is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x FMI2CCLK.

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 OA1EN : Own address 1 enable

0: Own address 1 disabled. The received target address OA1 is NACKed.

1: Own address 1 enabled. The received target address OA1 is ACKed.

Bits 14:11 Reserved, must be kept at reset value.

Bit 10 OA1MODE : Own address 1 10-bit mode

0: Own address 1 is a 7-bit address.

1: Own address 1 is a 10-bit address.

Note: This bit can be written only when OA1EN = 0.

Bits 9:0 OA1[9:0] : Interface own target address

7-bit addressing mode: OA1[7:1] contains the 7-bit own target address. Bits OA1[9], OA1[8] and OA1[0] are don't care.

10-bit addressing mode: OA1[9:0] contains the 10-bit own target address.

Note: These bits can be written only when OA1EN = 0.

23.9.4 FMI2C own address 2 register (FMI2C_OAR2)

Address offset: 0x0C

Reset value: 0x0000 0000

Access: no wait states, except if a write access occurs while a write access is ongoing. In this case, wait states are inserted in the second write access, until the previous one is completed. The latency of the second write access can be up to \( 2 \times PCLK1 + 6 \times FMPI2CCLK \) .

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 OA2EN : Own address 2 enable

0: Own address 2 disabled. The received target address OA2 is NACKed.

1: Own address 2 enabled. The received target address OA2 is ACKed.

Bits 14:11 Reserved, must be kept at reset value.

Bits 10:8 OA2MSK[2:0] : Own address 2 masks

• 000: No mask
• 001: OA2[1] is masked and don't care. Only OA2[7:2] are compared.
• 010: OA2[2:1] are masked and don't care. Only OA2[7:3] are compared.
• 011: OA2[3:1] are masked and don't care. Only OA2[7:4] are compared.
• 100: OA2[4:1] are masked and don't care. Only OA2[7:5] are compared.
• 101: OA2[5:1] are masked and don't care. Only OA2[7:6] are compared.
• 110: OA2[6:1] are masked and don't care. Only OA2[7] is compared.
• 111: OA2[7:1] are masked and don't care. No comparison is done, and all (except reserved) 7-bit received addresses are acknowledged.

Note: These bits can be written only when OA2EN = 0.

As soon as OA2MSK ≠ 0, the reserved FMPI2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged, even if the comparison matches.

Bits 7:1 OA2[7:1] : Interface address

7-bit addressing mode: 7-bit address

Note: These bits can be written only when OA2EN = 0.

Bit 0 Reserved, must be kept at reset value.

23.9.5 FMPI2C timing register (FMPI2C_TIMINGR)

Address offset: 0x10

Reset value: 0x0000 0000

Access: no wait states

Bits 31:28 PRESC[3:0] : Timing prescaler

This field is used to prescale FMPI2CCLK to generate the clock period \( t_{PRESC} \) used for data setup and hold counters (refer to section FMPI2C timings ), and for SCL high and low level counters (refer to section FMPI2C controller initialization ).

Bits 27:24 Reserved, must be kept at reset value.

Bits 23:20 SCLDEL[3:0] : Data setup time

This field is used to generate a delay \( t_{SCLDEL} = (SCLDEL + 1) \times t_{PRESC} \) between SDA edge and SCL rising edge. In controller and in target modes with NOSTRETCH = 0, the SCL line is stretched low during \( t_{SCLDEL} \) .

Note: \( t_{SCLDEL} \) is used to generate \( t_{SU:DAT} \) timing.

Bits 19:16 SDADEL[3:0] : Data hold time

This field is used to generate the delay \( t_{SDADEL} \) between SCL falling edge and SDA edge. In controller and in target modes with NOSTRETCH = 0, the SCL line is stretched low during \( t_{SDADEL} \) .

Note: \( t_{SDADEL} \) is used to generate \( t_{HD:DAT} \) timing.

Bits 15:8 SCLH[7:0] : SCL high period (controller mode)

This field is used to generate the SCL high period in controller mode.

Note: \( t_{SCLH} \) is also used to generate \( t_{SU:STO} \) and \( t_{HD:STA} \) timing.

Bits 7:0 SCLL[7:0] : SCL low period (controller mode)

This field is used to generate the SCL low period in controller mode.

Note: \( t_{SCLL} \) is also used to generate \( t_{BUF} \) and \( t_{SU:STA} \) timings.

Note: This register must be configured when the FMPI2C peripheral is disabled (PE = 0).

Note: The STM32CubeMX tool calculates and provides the FMPI2C_TIMINGR content in the I2C Configuration window.

23.9.6 FMPI2C timeout register (FMPI2C_TIMEOUTR)

Address offset: 0x14

Reset value: 0x0000 0000

Access: no wait states, except if a write access occurs while a write access is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to \( 2 \times PCLK1 + 6 \times FMPI2CCLK \) .

Bit 31 TEXTEN : Extended clock timeout enable

0: Extended clock timeout detection is disabled

1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more than \( t_{LOW:EXT} \) is done by the FMPI2C interface, a timeout error is detected (TIMEOUT = 1).

Bits 30:28 Reserved, must be kept at reset value.

Bits 27:16 TIMEOUTB[11:0] : Bus timeout B

This field is used to configure the cumulative clock extension timeout:

• – Controller mode: the controller cumulative clock low extend time ( \( t_{LOW:MEXT} \) ) is detected
• – Target mode: the target cumulative clock low extend time ( \( t_{LOW:SEXT} \) ) is detected

Note: These bits can be written only when TEXTEN = 0.

Bit 15 TIMOUTEN : Clock timeout enable

0: SCL timeout detection is disabled

1: SCL timeout detection is enabled. When SCL is low for more than \( t_{TIMEOUT} \) (TIDLE = 0) or high for more than \( t_{IDLE} \) (TIDLE = 1), a timeout error is detected (TIMEOUT = 1).

Bits 14:13 Reserved, must be kept at reset value.

Bit 12 TIDLE : Idle clock timeout detection

0: TIMEOUTA is used to detect SCL low timeout

1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)

Note: This bit can be written only when TIMOUTEN = 0.

Bits 11:0 TIMEOUTA[11:0] : Bus timeout A

This field is used to configure:

The SCL low timeout condition \( t_{TIMEOUT} \) when TIDLE = 0

The bus idle condition (both SCL and SDA high) when TIDLE = 1

Note: These bits can be written only when TIMOUTEN = 0.

23.9.7 FMPI2C interrupt and status register (FMPI2C_ISR)

Address offset: 0x18

Reset value: 0x0000 0001

Access: no wait states

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:17 ADDCODE[6:0] : Address match code (target mode)

These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the two MSBs of the address.

Bit 16 DIR : Transfer direction (target mode)

This flag is updated when an address match event occurs (ADDR = 1).

0: Write transfer, target enters receiver mode.

1: Read transfer, target enters transmitter mode.

Bit 15 BUSY : Bus busy

This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected, and cleared by hardware when a STOP condition is detected, or when PE = 0.

Bit 14 Reserved, must be kept at reset value.

Bit 13 ALERT : SMBus alert

This flag is set by hardware when SMBHEN = 1 (SMBus host configuration), ALERTEN = 1 and an SMBALERT# event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit.

Note: This bit is cleared by hardware when PE = 0.

Bit 12 TIMEOUT : Timeout or \( t_{LOW} \) detection flag

This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit.

Note: This bit is cleared by hardware when PE = 0.

Bit 11 PECERR : PEC error in reception

This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit.

Note: This bit is cleared by hardware when PE = 0.

Bit 10 OVR : Overrun/underrun (target mode)

This flag is set by hardware in target mode with NOSTRETCH = 1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit.

Note: This bit is cleared by hardware when PE = 0.

Bit 9 ARLO : Arbitration lost

This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit.

Note: This bit is cleared by hardware when PE = 0.

Bit 8 BERR : Bus error

This flag is set by hardware when a misplaced START or STOP condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in target mode. It is cleared by software by setting the BERRCF bit.

Note: This bit is cleared by hardware when PE = 0.

Bit 7 TCR : Transfer complete reload

This flag is set by hardware when RELOAD = 1 and NBBYTES data have been transferred. It is cleared by software when NBBYTES is written to a non-zero value.

Note: This bit is cleared by hardware when PE = 0.

This flag is only for controller mode, or for target mode when the SBC bit is set.

This flag is set by hardware when RELOAD = 0, AUTOEND = 0 and NBBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set.

Note: This bit is cleared by hardware when PE = 0.

This flag is set by hardware when a STOP condition is detected on the bus and the peripheral is involved in this transfer:

• – as a controller, provided that the STOP condition is generated by the peripheral.
• – as a target, provided that the peripheral has been addressed previously during this transfer.

It is cleared by software by setting the STOPCF bit.

Note: This bit is cleared by hardware when PE = 0.

This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit.

Note: This bit is cleared by hardware when PE = 0.

This bit is set by hardware as soon as the received target address matched with one of the enabled target addresses. It is cleared by software by setting ADDRCF bit.

Note: This bit is cleared by hardware when PE = 0.

This bit is set by hardware when the received data is copied into the FMPI2C_RXDR register, and is ready to be read. It is cleared when FMPI2C_RXDR is read.

Note: This bit is cleared by hardware when PE = 0.

This bit is set by hardware when the FMPI2C_TXDR register is empty and the data to be transmitted must be written in the FMPI2C_TXDR register. It is cleared when the next data to be sent is written in the FMPI2C_TXDR register.

This bit can be written to 1 by software only when NOSTRETCH = 1, to generate a TXIS event (interrupt if TXIE = 1 or DMA request if TXDMAEN = 1).

Note: This bit is cleared by hardware when PE = 0.

This bit is set by hardware when the FMPI2C_TXDR register is empty. It is cleared when the next data to be sent is written in the FMPI2C_TXDR register.

This bit can be written to 1 by software in order to flush the transmit data register FMPI2C_TXDR.

Note: This bit is set by hardware when PE = 0.

23.9.8 FMPI2C interrupt clear register (FMPI2C_ICR)

Address offset: 0x1C

Reset value: 0x0000 0000

Access: no wait states

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 ALERTCF : Alert flag clear

Writing 1 to this bit clears the ALERT flag in the FMPI2C_ISR register.

Bit 12 TIMOUTCF : Timeout detection flag clear

Writing 1 to this bit clears the TIMEOUT flag in the FMPI2C_ISR register.

Bit 11 PECCF : PEC error flag clear

Writing 1 to this bit clears the PECERR flag in the FMPI2C_ISR register.

Bit 10 OVR : Overrun/underrun flag clear

Writing 1 to this bit clears the OVR flag in the FMPI2C_ISR register.

Bit 9 ARLOCF : Arbitration lost flag clear

Writing 1 to this bit clears the ARLO flag in the FMPI2C_ISR register.

Bit 8 BERRCF : Bus error flag clear

Writing 1 to this bit clears the BERRF flag in the FMPI2C_ISR register.

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 STOPCF : STOP detection flag clear

Writing 1 to this bit clears the STOPF flag in the FMPI2C_ISR register.

Bit 4 NACKCF : Not acknowledge flag clear

Writing 1 to this bit clears the NACKF flag in FMPI2C_ISR register.

Bit 3 ADDRCF : Address matched flag clear

Writing 1 to this bit clears the ADDR flag in the FMPI2C_ISR register. Writing 1 to this bit also clears the START bit in the FMPI2C_CR2 register.

Bits 2:0 Reserved, must be kept at reset value.

23.9.9 FMPI2C PEC register (FMPI2C_PECR)

Address offset: 0x20

Reset value: 0x0000 0000

Access: no wait states

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PEC[7:0] : Packet error checking register

This field contains the internal PEC when PECEN=1.

The PEC is cleared by hardware when PE = 0.

23.9.10 FMPI2C receive data register (FMPI2C_RXDR)

Address offset: 0x24

Reset value: 0x0000 0000

Access: no wait states

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 RXDATA[7:0] : 8-bit receive data

Data byte received from the I ² C-bus.

Address offset: 0x28

Reset value: 0x0000 0000

Access: no wait states

Bits 31:8 Reserved, must be kept at reset value.

23.9.12 FMPI2C register map

The table below provides the FMPI2C register map and the reset values.

Table 143. FMPI2C register map and reset values

Refer to Section 2.2: Memory organization for the register boundary addresses.