5. Power controller (PWR)

5.1 Power supplies

The device requires a 1.8 to 3.6 V operating voltage supply ( \( V_{DD} \) ). An embedded linear voltage regulator is used to supply the internal 1.2 V digital power.

The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM) can be powered from the \( V_{BAT} \) voltage when the main \( V_{DD} \) supply is powered off.

Note: Depending on the operating power supply range, some peripheral may be used with limited functionality and performance. For more details refer to section “General operating conditions” in STM32F446xx datasheet.

Figure 8. Power supply overview for STM32F446xx

1. 1. \( V_{DDA} \) and \( V_{SSA} \) must be connected to \( V_{DD} \) and \( V_{SS} \) , respectively.

5.1.1 Independent A/D converter supply and reference voltage

To improve conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB.

• • The ADC voltage supply input is available on a separate \( V_{DDA} \) pin.
• • An isolated supply ground connection is provided on pin \( V_{SSA} \) .

To ensure a better accuracy of low voltage inputs, the user can connect a separate external reference voltage ADC input on \( V_{REF} \) . The voltage on \( V_{REF} \) ranges from 1.8 V to \( V_{DDA} \) .

5.1.2 Battery backup domain (also known as RTC domain)

Backup domain description

To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when \( V_{DD} \) is turned off, \( V_{BAT} \) pin can be connected to an optional standby voltage supplied by a battery or by another source.

To allow the RTC to operate even when the main digital supply ( \( V_{DD} \) ) is turned off, the \( V_{BAT} \) pin powers the following blocks:

• • The RTC
• • The LSE oscillator
• • The backup SRAM when the low-power backup regulator is enabled
• • PC13 to PC15 I/Os

The switch to the \( V_{BAT} \) supply is controlled by the power-down reset embedded in the Reset block.

Warning: During \( t_{RSTTEMPO} \) (temporization at \( V_{DD} \) startup) or after a PDR is detected, the power switch between \( V_{BAT} \) and \( V_{DD} \) remains connected to \( V_{BAT} \) .
During the startup phase, if \( V_{DD} \) is established in less than \( t_{RSTTEMPO} \) (refer to the datasheet for the value of \( t_{RSTTEMPO} \) ) and \( V_{DD} > V_{BAT} + 0.6 \) V, a current may be injected into \( V_{BAT} \) through an internal diode connected between \( V_{DD} \) and the power switch ( \( V_{BAT} \) ).
If the power supply/battery connected to the \( V_{BAT} \) pin cannot support this current injection, it is strongly recommended to connect an external low-drop diode between this power supply and the \( V_{BAT} \) pin.

If no external battery is used in the application, it is recommended to connect the \( V_{BAT} \) pin to \( V_{DD} \) supply, and add a 100 nF ceramic decoupling capacitor on \( V_{BAT} \) pin.

When the backup domain is supplied by \( V_{DD} \) (analog switch connected to \( V_{DD} \) ), the following functions are available:

• • PC14 and PC15 can be used as either GPIO or LSE pins
• • PC13 can be used as a GPIO as the \( RTC\_AF1 \) pin (refer to Table 24: \( RTC\_AF1 \) pin for more details about this pin configuration)

Note: Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is restricted: the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED).

When the backup domain is supplied by \( V_{BAT} \) (analog switch connected to \( V_{BAT} \) because \( V_{DD} \) is not present), the following functions are available:

• • PC14 and PC15 can be used as LSE pins only
• • PC13 can be used as the RTC_AF1 pin (refer to Table 24: RTC_AF1 pin for more details about this pin configuration).

Backup domain access

After reset, the backup domain (RTC registers, RTC backup register and backup SRAM) is protected against possible unwanted write accesses. To enable access to the backup domain, proceed as follows:

• • Access to the RTC and RTC backup registers
  1. 1. Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR register (see Section 6.3.13: RCC APB1 peripheral clock enable register (RCC_APB1ENR) )
  2. 2. Set the DBP bit in the Section 5.4.1: PWR power control register (PWR_CR) and PWR power control register (PWR_CR) to enable access to the backup domain
  3. 3. Select the RTC clock source: see Section 6.2.8: RTC/AWU clock
  4. 4. Enable the RTC clock by programming the RTCEN [15] bit in the Section 6.3.20: RCC Backup domain control register (RCC_BDCR)
• • Access to the backup SRAM
  1. 1. Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR register (see Section 6.3.13 ).
  2. 2. Set the DBP bit in the PWR power control register (PWR_CR) to enable access to the backup domain
  3. 3. Enable the backup SRAM clock by setting BKPSRAMEN bit in the RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) .

RTC and RTC backup registers

The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability. The RTC contains 20 backup data registers (80 bytes) which are reset when a tamper detection event occurs. For more details refer to .

Backup SRAM

The backup domain includes 4 Kbytes of backup SRAM addressed in 32-bit, 16-bit or 8-bit mode. Its content is retained even in Standby or \( V_{BAT} \) mode when the low-power backup regulator is enabled. It can be considered as an internal EEPROM when \( V_{BAT} \) is always present.

When the backup domain is supplied by \( V_{DD} \) (analog switch connected to \( V_{DD} \) ), the backup SRAM is powered from \( V_{DD} \) which replaces the \( V_{BAT} \) power supply to save battery life.

When the backup domain is supplied by \( V_{BAT} \) (analog switch connected to \( V_{BAT} \) because \( V_{DD} \) is not present), the backup SRAM is powered by a dedicated low-power regulator. This

regulator can be ON or OFF depending whether the application needs the backup SRAM function in Standby and \( V_{BAT} \) modes or not. The power-down of this regulator is controlled by a dedicated bit, the BRE control bit of the PWR_CSR register.

The backup SRAM is not mass erased by a tamper event.

When the Flash is read out protected, the backup SRAM is also read protected to prevent confidential data (such as cryptographic private key) from being accessed. When the protection level change from level 1 to level 0 is requested, the backup SRAM content is erased. Refer to the description of Read protection (RDP) option byte.

Figure 9. Backup domain

5.1.3 Voltage regulator

An embedded linear voltage regulator supplies all the digital circuitries except for the backup domain and the Standby circuitry. The regulator output voltage is around 1.2 V.

This voltage regulator requires two external capacitors to be connected to two dedicated pins, \( V_{CAP\_1} \) and \( V_{CAP\_2} \) available in all packages. Specific pins must be connected either to \( V_{SS} \) or \( V_{DD} \) to activate or deactivate the voltage regulator. These pins depend on the package.

When activated by software, the voltage regulator is always enabled after Reset. It works in three different modes depending on the application modes (Run, Stop, or Standby mode).

• • In Run mode , the main regulator supplies full power to the 1.2 V domain (core, memories and digital peripherals). In this mode, the regulator output voltage (around 1.2 V) can be scaled by software to different voltage values (scale 1, scale 2, and scale 3 can be configured through VOS[1:0] bits of the PWR_CR register). The scale can be modified only when the PLL is OFF and the HSI or HSE clock source is selected as system clock source. The new value programmed is active only when the PLL is ON. When the PLL is OFF, the voltage scale 3 is automatically selected.

The voltage scaling allows optimizing the power consumption when the device is clocked below the maximum system frequency. After exit from Stop mode, the voltage scale 3 is automatically selected. (see Section 5.4.1 ).

Two operating modes are available:

• – Normal mode: the CPU and core logic operate at maximum frequency at a given voltage scaling (scale 1, scale 2 or scale 3)
• – Over-drive mode: the CPU and the core logic can operate at a higher frequency than the normal mode for the voltage scaling scale 1 and scale 2.
• • In Stop mode: the main regulator or low-power regulator supplies a low-power voltage to the 1.2V domain, thus preserving the content of registers and internal SRAM.
  The voltage regulator can be put either in main regulator mode (MR) or in low-power mode (LPR). Both modes can be configured by software as follows:
  • – Normal mode: the 1.2 V domain is preserved in nominal leakage mode. It is the default mode when the main regulator (MR) or the low-power regulator (LPR) is enabled.
  • – Low voltage mode.
  • – Under-drive mode: the 1.2 V domain is preserved in reduced leakage mode. This mode is only available when the main regulator or the low-power regulator is in low voltage mode (see Table 14 ).
• • In Standby mode: the regulator is powered down. The content of the registers and SRAM are lost except for the Standby circuitry and the backup domain.

Note: Over-drive and under-drive mode are not available when the regulator is bypassed.
For more details, refer to the voltage regulator section in the STM32F446xx datasheet .

Table 14. Voltage regulator configuration mode versus device operating mode ⁽¹⁾

1. 1. '-' means that the corresponding configuration is not available.
2. 2. The over-drive mode is not available when \( V_{DD} = 1.8 \) to \( 2.1 \) V.

Entering Over-drive mode

It is recommended to enter Over-drive mode when the application is not running critical tasks and when the system clock source is either HSI or HSE. To optimize the configuration time, enable the Over-drive mode during the PLL lock phase.

To enter Over-drive mode, follow the sequence below:

1. 1. Select HSI or HSE as system clock.
2. 2. Configure RCC_PLLCFGR register and set PLLON bit of RCC_CR register.
3. 3. Set ODEN bit of PWR_CR register to enable the Over-drive mode and wait for the ODRDY flag to be set in the PWR_CSR register.
4. 4. Set the ODSW bit in the PWR_CR register to switch the voltage regulator from Normal mode to Over-drive mode. The System will be stalled during the switch but the PLL clock system will be still running during locking phase.
5. 5. Wait for the ODSWRDY flag in the PWR_CSR to be set.

1. 6. Select the required Flash latency as well as AHB and APB prescalers.
2. 7. Wait for PLL lock.
3. 8. Switch the system clock to the PLL.
4. 9. Enable the peripherals that are not generated by the System PLL (I2S clock, SAI1 and SAI2 clocks, USB_48MHz clock....).

Note: The PLLI2S and PLLSAI can be configured at the same time as the system PLL.

During the Over-drive switch activation, no peripheral clocks should be enabled. The peripheral clocks must be enabled once the Over-drive mode is activated.

Entering Stop mode disables the Over-drive mode, as well as the PLL. The application software has to configure again the Over-drive mode and the PLL after exiting from Stop mode.

Exiting from Over-drive mode

It is recommended to exit from Over-drive mode when the application is not running critical tasks and when the system clock source is either HSI or HSE. There are two sequences that allow exiting from over-drive mode:

• • By resetting simultaneously the ODEN and ODSW bits in the PWR_CR register (sequence 1)
• • By resetting first the ODSW bit to switch the voltage regulator to Normal mode and then resetting the ODEN bit to disable the Over-drive mode (sequence 2).

Example of sequence 1:

1. 1. Select HSI or HSE as system clock source.
2. 2. Disable the peripheral clocks that are not generated by the System PLL (I2S clock, SAI1 and SAI2 clocks, USB_48MHz clock,...)
3. 3. Reset simultaneously the ODEN and the ODSW bits in the PWR_CR register to switch back the voltage regulator to Normal mode and disable the Over-drive mode.
4. 4. Wait for the ODWRRDY flag of PWR_CSR to be reset.

Example of sequence 2:

1. 1. Select HSI or HSE as system clock source.
2. 2. Disable the peripheral clocks that are not generated by the System PLL (I2S clock, SAI1 and SAI2 clocks, USB_48MHz clock,...).
3. 3. Reset the ODSW bit in the PWR_CR register to switch back the voltage regulator to Normal mode. The system clock is stalled during voltage switching.
4. 4. Wait for the ODWRRDY flag of PWR_CSR to be reset.
5. 5. Reset the ODEN bit in the PWR_CR register to disable the Over-drive mode.

Note: During step 3, the ODEN bit remains set and the Over-drive mode is still enabled but not active (ODSW bit is reset). If the ODEN bit is reset instead, the Over-drive mode is disabled and the voltage regulator is switched back to the initial voltage.

5.2 Power supply supervisor

5.2.1 Power-on reset (POR) / power-down reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting from 1.8 V.

The device remains in Reset mode when \( V_{DD}/V_{DDA} \) is below a specified threshold, \( V_{POR/PDR} \) , without the need for an external reset circuit. For more details concerning the power on/power-down reset threshold, refer to the electrical characteristics of the datasheet.

Figure 10. Power-on reset/power-down reset waveform

5.2.2 Brownout reset (BOR)

During power on, the Brownout reset (BOR) keeps the device under reset until the supply voltage reaches the specified \( V_{BOR} \) threshold.

\( V_{BOR} \) is configured through device option bytes. By default, BOR is off. 3 programmable \( V_{BOR} \) threshold levels can be selected:

• • BOR Level 3 ( \( V_{BOR3} \) ). Brownout threshold level 3.
• • BOR Level 2 ( \( V_{BOR2} \) ). Brownout threshold level 2.
• • BOR Level 1 ( \( V_{BOR1} \) ). Brownout threshold level 1.

Note: For full details about BOR characteristics, refer to the "Electrical characteristics" section in the device datasheet.

When the supply voltage ( \( V_{DD} \) ) drops below the selected \( V_{BOR} \) threshold, a device reset is generated.

The BOR can be disabled by programming the device option bytes. In this case, the power-on and power-down is then monitored by the POR/ PDR (see Section 5.2.1 ).

The BOR threshold hysteresis is ~100 mV (between the rising and the falling edge of the supply voltage).

Figure 11. BOR thresholds

5.2.3 Programmable voltage detector (PVD)

You can use the PVD to monitor the \( V_{DD} \) power supply by comparing it to a threshold selected by the PLS[2:0] bits in the Section 5.4.1 .

The PVD is enabled by setting the PVDE bit.

A PVDO flag is available (see Section 5.4.2 ), to indicate if \( V_{DD} \) is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when \( V_{DD} \) drops below the PVD threshold and/or when \( V_{DD} \) rises above the PVD threshold, depending on EXTI line16 rising/falling edge configuration. As an example, the service routine can perform emergency shutdown tasks.

Figure 12. PVD thresholds

5.3 Low-power modes

By default, the MCU is in Run mode after a system or a power-on reset. In Run mode the CPU is clocked by HCLK and the program code is executed. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, short startup time, and available wake-up sources.

The devices feature three low-power modes:

• • Sleep mode (Cortex ^® -M4 with FPU core stopped, peripherals kept running)
• • Stop mode (all clocks are stopped)
• • Standby mode (1.2 V domain powered off)

In addition, the power consumption in Run mode can be reduced by one of the following means:

• • Slowing down the system clocks
• • Gating the clocks to the APBx and AHBx peripherals when they are unused.

Table 15. Low-power mode summary

5.3.1 Slowing down system clocks

In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode.

For more details refer to Section 6.3.3: RCC clock configuration register (RCC_CFGR) .

5.3.2 Peripheral clock gating

In Run mode, the HCLKx and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption.

To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.

Peripheral clock gating for STM32F446xx is controlled by the AHB1 peripheral clock enable register (RCC_AHB1ENR), AHB2 peripheral by the clock enable register (RCC_AHB2ENR), AHB3 by the peripheral clock enable register (RCC_AHB3ENR) (see Section 6.3.10: RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) , Section 6.3.11: RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) and Section 6.3.12: RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) , respectively).

Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers.

5.3.3 Low power mode

Entering low power mode

Low power modes are entered by the MCU executing the WFI (Wait For Interrupt), or WFE (Wait For Event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M4 System Control register is set on Return from ISR.

Exiting low power mode

From Sleep and Stop modes the MCU exits low power mode depending on the way the mode was entered:

• • If the WFI instruction or Return from ISR was used to enter the low power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device
• • If the WFE instruction was used to enter the low power mode, the MCU exits the mode as soon as an event occurs. The wakeup event can be generated either by:
  • – NVIC IRQ interrupt
    • - When SEVEONPEND=0 in the Cortex®-M4 System Control register.

By enabling an interrupt in the peripheral control register and in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.

• - When SEVEONPEND=1 in the Cortex®-M4 System Control register.

By enabling an interrupt in the peripheral control register and optionally in the NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and (when enabled) the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.

All NVIC interrupts wake up the MCU, even the disabled ones.

• - Event

Configuring a EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bits corresponding to the event line is not set. It may be necessary to clear the interrupt flag in the peripheral.

From Standby and Shutdown modes the MCU exits Low power mode through an external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event (see Figure 240: RTC block diagram ).

5.3.4 Sleep mode

Entering Sleep mode

The Sleep mode is entered according to Entering low power mode , when the SLEEPDEEP bit in the Cortex®-M4 System Control register is cleared.

Refer to Table 16 for details on how to enter the Sleep mode.

Exiting Sleep mode

The Sleep mode is exited according to Exiting low power mode .

Refer to Table 16 for details on how to exit the Sleep mode.

Table 16. Sleep-now entry and exit

5.3.5 Stop mode

The Stop mode is based on the Cortex®-M4 with FPU deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI and the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.

In Stop mode, the power consumption can be further reduced by using additional settings in the PWR_CR register. However this will induce an additional startup delay when waking up from Stop mode (see Table 17 ).

Table 17. Stop operating modes

Entering Stop mode

The Stop mode is entered according to Entering low power mode , when the SLEEPDEEP bit in Cortex ^® -M4 System Control register is set.

Refer to Table 18 for details on how to enter the Stop mode.

When the microcontroller enters in Stop mode, the voltage scale 3 is automatically selected. To further reduce power consumption in Stop mode, the internal voltage regulator can be put in low-power or low voltage mode. This is configured by the LPDS, MRUDS, LPUDS and UDEN bits of the PWR power control register (PWR_CR) .

Stop mode can be entered from Run mode and Low power run mode.

If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory access is finished.

If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB access is finished.

If the Over-drive mode was enabled before entering Stop mode, it is automatically disabled during when the Stop mode is activated.

In Stop mode, the following features can be selected by programming individual control bits:

• • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See Section 20.3: IWDG functional description .
• • Real-time clock (RTC): this is configured by the RTCEN bit in the RCC Backup domain control register (RCC_BDCR) .
• • Internal RC oscillator (LSI RC): this is configured by the LSION bit in the RCC clock control and status register (RCC_CSR) .
• • External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the RCC Backup domain control register (RCC_BDCR) .

The ADC or DAC can also consume power during the Stop mode, unless they are disabled before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit in the DAC_CR register must both be written to 0.

Note: Before entering Stop mode, it is recommended to enable the clock security system (CSS) feature to prevent external oscillator (HSE) failure from impacting the internal MCU behavior.

Exiting Stop mode

The Stop mode is exited according to Exiting low power mode .

Refer to Table 18 for more details on how to exit Stop mode.

When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is selected as system clock.

If the Under-drive mode was enabled, it is automatically disabled after exiting Stop mode.

When the voltage regulator operates in low-power or low voltage mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.

When the voltage regulator operates in Under-drive mode, an additional startup delay is induced when waking up from Stop mode.

Table 18. Stop mode entry and exit for STM32F446xx

5.3.6 Standby mode

The Standby mode allows to achieve the lowest power consumption. It is based on the Cortex ^® -M4 with FPU deepsleep mode, with the voltage regulator disabled. The 1.2 V domain is consequently powered off. The PLLs, the HSI oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for registers in the backup domain (RTC registers, RTC backup register and backup SRAM), and Standby circuitry (see Figure 8 ).

Entering Standby mode

The Standby mode is entered according to Entering low power mode , when the SLEEPDEEP bit in the Cortex ^® -M4 with FPU System Control register is set.

Refer to Table 19 for more details on how to enter Standby mode.

In Standby mode, the following features can be selected by programming individual control bits:

• • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. See Section 20.3: IWDG functional description .
• • Real-time clock (RTC): this is configured by the RTCEN bit in the backup domain control register (RCC_BDCR)
• • Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR).
• • External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the backup domain control register (RCC_BDCR)

Exiting Standby mode

The microcontroller exits Standby mode according to Exiting low power mode . The SBF status flag in the PWR power control/status register (PWR_CSR) indicates that the MCU was in Standby mode. All registers are reset after wakeup from standby except for PWR power control/status register (PWR_CSR) .

Refer to Table 19 for more details on how to exit Standby mode.

Table 19. Standby mode entry and exit

I/O states in Standby mode

In Standby mode, all I/O pins are high impedance except for:

• • Reset pad (still available)
• • RTC_AF1 pin (PC13) if configured for tamper, time stamp, RTC Alarm out, or RTC clock calibration out
• • WKUP pin (PA0), if enabled

Debug mode

By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex ^® -M4 with FPU core is no longer clocked.

However, by setting some configuration bits in the DBGMCU_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to Section 33.16.1: Debug support for low-power modes .

5.3.7 Programming the RTC alternate functions to wake up the device from the Stop and Standby modes

The MCU can be woken up from a low-power mode by an RTC alternate function.

The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), RTC wakeup, RTC tamper event detection and RTC time stamp event detection.

These RTC alternate functions can wake up the system from the Stop and Standby low-power modes.

The system can also wake up from low-power modes without depending on an external interrupt (Auto-wakeup mode), by using the RTC alarm or the RTC wakeup events.

The RTC provides a programmable time base for waking up from the Stop or Standby mode at regular intervals.

For this purpose, two of the three alternate RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the RCC Backup domain control register (RCC_BDCR) :

• • Low-power 32.768 kHz external crystal oscillator (LSE OSC)
  This clock source provides a precise time base with a very low-power consumption (additional consumption of less than 1 µA under typical conditions)
• • Low-power internal RC oscillator (LSI RC)
  This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC oscillator is designed to use minimum power.

RTC alternate functions to wake up the device from the Stop mode

• • To wake up the device from the Stop mode with an RTC alarm event, it is necessary to:
  1. a) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event modes)
  2. b) Enable the RTC Alarm Interrupt in the RTC_CR register
  3. c) Configure the RTC to generate the RTC alarm
• • To wake up the device from the Stop mode with an RTC tamper or time stamp event, it is necessary to:

• a) Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt or Event modes)
• b) Enable the RTC time stamp Interrupt in the RTC_CR register or the RTC tamper interrupt in the RTC_TAFCR register
• c) Configure the RTC to detect the tamper or time stamp event
• • To wake up the device from the Stop mode with an RTC wakeup event, it is necessary to:
  • a) Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt or Event modes)
  • b) Enable the RTC wakeup interrupt in the RTC_CR register
  • c) Configure the RTC to generate the RTC Wakeup event

RTC alternate functions to wake up the device from the Standby mode

• • To wake up the device from the Standby mode with an RTC alarm event, it is necessary to:
  • a) Enable the RTC alarm interrupt in the RTC_CR register
  • b) Configure the RTC to generate the RTC alarm
• • To wake up the device from the Standby mode with an RTC tamper or time stamp event, it is necessary to:
  • a) Enable the RTC time stamp interrupt in the RTC_CR register or the RTC tamper interrupt in the RTC_TAFCR register
  • b) Configure the RTC to detect the tamper or time stamp event
• • To wake up the device from the Standby mode with an RTC wakeup event, it is necessary to:
  • a) Enable the RTC wakeup interrupt in the RTC_CR register
  • b) Configure the RTC to generate the RTC wakeup event

Safe RTC alternate function wakeup flag clearing sequence

If the selected RTC alternate function is set before the PWR wakeup flag (WUTF) is cleared, it will not be detected on the next event as detection is made once on the rising edge.

To avoid bouncing on the pins onto which the RTC alternate functions are mapped, and exit correctly from the Stop and Standby modes, it is recommended to follow the sequence below before entering the Standby mode:

• • When using RTC alarm to wake up the device from the low-power modes:
  • a) Disable the RTC alarm interrupt (ALRAIE or ALRBIE bits in the RTC_CR register)
  • b) Clear the RTC alarm (ALRAF/ALRBF) flag
  • c) Clear the PWR Wakeup (WUF) flag
  • d) Enable the RTC alarm interrupt
  • e) Re-enter the low-power mode
• • When using RTC wakeup to wake up the device from the low-power modes:
  • a) Disable the RTC Wakeup interrupt (WUTIE bit in the RTC_CR register)
  • b) Clear the RTC Wakeup (WUTF) flag
  • c) Clear the PWR Wakeup (WUF) flag
  • d) Enable the RTC Wakeup interrupt

• • e) Re-enter the low-power mode
• • When using RTC tamper to wake up the device from the low-power modes:
  • a) Disable the RTC tamper interrupt (TAMPIE bit in the RTC_TAFCR register)
  • b) Clear the Tamper (TAMP1F/TSF) flag
  • c) Clear the PWR Wakeup (WUF) flag
  • d) Enable the RTC tamper interrupt
  • e) Re-enter the low-power mode
• • When using RTC time stamp to wake up the device from the low-power modes:
  • a) Disable the RTC time stamp interrupt (TSIE bit in RTC_CR)
  • b) Clear the RTC time stamp (TSF) flag
  • c) Clear the PWR Wakeup (WUF) flag
  • d) Enable the RTC TimeStamp interrupt
  • e) Re-enter the low-power mode

5.4 Power control registers

5.4.1 PWR power control register (PWR_CR)

Address offset: 0x00

Reset value: 0x0000 C000 (reset by wakeup from Standby mode)

Bits 31:22 Reserved, must be kept at reset value.

Bit 21 FISSR : Flash Interface Stop while System Run

0: Flash interface clock run (Default value)

1: Flash Interface clock off.

Note: This bit could not be set while executing with the Flash itself. It should be done with a specific routine executed from RAM.

Bit 20 FMSSR : Flash Memory Stop while System Run

0: Flash standard mode (Default value)

1: Flash forced to be in STOP or Deep Power Down mode (depending of FPDS value bit) by hardware.

Note: This bit could not be set while executing with the Flash itself. It should be done with a specific routine executed from RAM

Bits 19:18 UDEN[1:0] : Under-drive enable in stop mode

These bits are set by software. They allow to achieve a lower power consumption in Stop mode but with a longer wakeup time.

When set, the digital area has less leakage consumption when the device enters Stop mode.

00: Under-drive disable

01: Reserved

10: Reserved

11: Under-drive enable

Bit 17 ODSWEN : Over-drive switching enabled.

This bit is set by software. It is cleared automatically by hardware after exiting from Stop mode or when the ODEN bit is reset. When set, It is used to switch to Over-drive mode.

To set or reset the ODSWEN bit, the HSI or HSE must be selected as system clock.

The ODSWEN bit must only be set when the ODRDY flag is set to switch to Over-drive mode.

0: Over-drive switching disabled

1: Over-drive switching enabled

Note: On any over-drive switch (enabled or disabled), the system clock will be stalled during the internal voltage set up.

This bit is set by software. It is cleared automatically by hardware after exiting from Stop mode. It is used to enable the Over-drive mode in order to reach a higher frequency.

To set or reset the ODEN bit, the HSI or HSE must be selected as system clock. When the ODEN bit is set, the application must first wait for the Over-drive ready flag (ODRDY) to be set before setting the ODSWEN bit.

0: Over-drive disabled

1: Over-drive enabled

These bits control the main internal voltage regulator output voltage to achieve a trade-off between performance and power consumption when the device does not operate at the maximum frequency (refer to the STM32F446xx datasheet for more details).

These bits can be modified only when the PLL is OFF. The new value programmed is active only when the PLL is ON. When the PLL is OFF, the voltage scale 3 is automatically selected.

00: Reserved (Scale 3 mode selected)

01: Scale 3 mode

10: Scale 2 mode

11: Scale 1 mode (reset value)

0: No effect.

1: Refer to AN4073 for details on how to use this bit.

Note: This bit can only be set when operating at supply voltage range 2.7 to 3.6V and when the Prefetch is OFF.

Bit 12 Reserved, must be kept at reset value.

This bit is set and cleared by software.

0: Main regulator ON when the device is in Stop mode

1: Main Regulator in under-drive mode and Flash memory in power-down when the device is in Stop under-drive mode.

This bit is set and cleared by software.

0: Low-power regulator ON if LPDS bit is set when the device is in Stop mode

1: Low-power regulator in under-drive mode if LPDS bit is set and Flash memory in power-down when the device is in Stop under-drive mode.

When set, the Flash memory enters power-down mode when the device enters Stop mode. This allows to achieve a lower consumption in stop mode but a longer restart time.

0: Flash memory not in power-down when the device is in Stop mode

1: Flash memory in power-down when the device is in Stop mode

In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), and the BRE bit of the PWR_CSR register, are protected against parasitic write access. This bit must be set to enable write access to these registers.

0: Access to RTC and RTC Backup registers and backup SRAM disabled

1: Access to RTC and RTC Backup registers and backup SRAM enabled

Bits 7:5 PLS[2:0] : Programmable voltage detector level selection

These bits are written by software to select the voltage threshold detected by the PVD

000: 2.0 V

001: 2.1 V

010: 2.3 V

011: 2.5 V

100: 2.6 V

101: 2.7 V

110: 2.8 V

111: 2.9 V

Note: Refer to the electrical characteristics of the datasheet for more details.

Bit 4 PVDE : Programmable voltage detector enable

This bit is set and cleared by software.

0: PVD disabled

1: PVD enabled

Bit 3 CSBF : Clear standby flag

This bit is always read as 0.

0: No effect

1: Clear the SBF Standby Flag (write).

Bit 2 CWUF : Clear wakeup flag

This bit is always read as 0.

0: No effect

1: Clear the WUF wake-up Flag after 2 System clock cycles

Bit 1 PDDS : Power-down deepsleep

This bit is set and cleared by software. It works together with the LPDS bit.

0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the LPDS bit.

1: Enter Standby mode when the CPU enters deepsleep.

Bit 0 LPDS : Low-power deepsleep

This bit is set and cleared by software. It works together with the PDDS bit.

0: Main voltage regulator ON during Stop mode

1: Low-power voltage regulator ON during Stop mode

5.4.2 PWR power control/status register (PWR_CSR)

Address offset: 0x04

Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)

Additional APB cycles are needed to read this register versus a standard APB read.

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:18 UDRDY[1:0] : Under-drive ready flag

These bits are set by hardware when MCU entered stop Under-drive mode and exited. When the under-drive mode is enabled, these bits are not set as long as the MCU has not entered stop mode yet. They are cleared by programming them to 1.

00: Under-drive is disabled
01: Reserved
10: Reserved
11: Under-drive mode is activated in Stop mode.

Bit 17 ODSWRDY : Over-drive mode switching ready

0: Over-drive mode is not active.

1: Over-drive mode is active on digital area on 1.2 V domain

Bit 16 ODRDY : Over-drive mode ready

0: Over-drive mode not ready.

1: Over-drive mode ready

Bit 14 VOSRDY : Regulator voltage scaling output selection ready bit

0: Not ready

1: Ready

Bits 13:10 Reserved, must be kept at reset value.

Bit 9 BRE : Backup regulator enable

When set, the Backup regulator (used to maintain backup SRAM content in Standby and \( V_{BAT} \) modes) is enabled. If BRE is reset, the backup regulator is switched off. The backup SRAM can still be used but its content is lost in the Standby and \( V_{BAT} \) modes. Once set, the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that the data written into the RAM are maintained in the Standby and \( V_{BAT} \) modes.

The DBP bit of PWR_CR register must be set to 1 before writing this bit.

0: Backup regulator disabled

1: Backup regulator enabled

Note: This bit is reset by a Backup domain reset, not reset when the device wakes up from Standby mode, by a system reset, or by a power reset.

Bit 8 EWUP1 : Enable WKUP1 pin

This bit is set and cleared by software.

0: WKUP1 pin is used for general purpose I/O. An event on the WKUP1 pin does not wakeup the device from Standby mode.

1: WKUP1 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP1 pin wakes-up the system from Standby mode).

Note: This bit is reset by a system reset.

Bit 7 EWUP2 : Enable WKUP2 pin

This bit is set and cleared by software

0: WKUP2 pin is used for general purpose I/O. An event on the WKUP2 pin does not wakeup the device from Standby mode.

1: WKUP2 pin is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP2 pin wakes-up the system from Standby mode).

Note: This bit is reset by a system reset.

Bits 7:4 Reserved, must be kept at reset value.

Bit 3 BRR : Backup regulator ready

Set by hardware to indicate that the Backup Regulator is ready.

0: Backup Regulator not ready

1: Backup Regulator ready

Note: This bit is reset by a Backup domain reset, not reset when the device wakes up from Standby mode or by a system reset or power reset.

Bit 2 PVDO : PVD output

This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.

0: \( V_{DD} \) is higher than the PVD threshold selected with the PLS[2:0] bits.

1: \( V_{DD} \) is lower than the PVD threshold selected with the PLS[2:0] bits.

Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after Standby or reset until the PVDE bit is set.

Bit 1 SBF : Standby flag

This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down reset) or by setting the CSBF bit in the PWR power control register (PWR_CR)

0: Device has not been in Standby mode

1: Device has been in Standby mode

Bit 0 WUF : Wakeup flag

This bit is set by hardware and cleared either by a system reset or by setting the CWUF bit in the PWR_CR register.

0: No wakeup event occurred

1: A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup).

Note: An additional wakeup event is detected if the WKUP pin is enabled (by setting the EWUP bit) when the WKUP pin level is already high.

5.5 PWR register map

The following table summarizes the PWR registers.

Table 20. PWR - register map and reset values

Refer to Section 2.2 on page 56 for the register boundary addresses.