1. Documentation conventions
1.1 General information
The STM32F446xx devices have an Arm ® Cortex ® -M4 with FPU core.
Note: Arm and Cortex are registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere.
The Arm word and logo are trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved.
1.2 List of abbreviations for registers
The following abbreviations (a) are used in register descriptions:
| read/write (rw) | Software can read and write to this bit. |
| read-only (r) | Software can only read this bit. |
| write-only (w) | Software can only write to this bit. Reading this bit returns the reset value. |
| read/clear write0 (rc_w0) | Software can read as well as clear this bit by writing 0. Writing 1 has no effect on the bit value. |
| read/clear write1 (rc_w1) | Software can read as well as clear this bit by writing 1. Writing 0 has no effect on the bit value. |
| read/clear write (rc_w) | Software can read as well as clear this bit by writing to the register. The value written to this bit is not important. |
| read/clear by read (rc_r) | Software can read this bit. Reading this bit automatically clears it to 0. Writing this bit has no effect on the bit value. |
| read/set by read (rs_r) | Software can read this bit. Reading this bit automatically sets it to 1. Writing this bit has no effect on the bit value. |
| read/set (rs) | Software can read as well as set this bit. Writing 0 has no effect on the bit value. |
| read/write once (rwo) | Software can only write once to this bit and can also read it at any time. Only a reset can return the bit to its reset value. |
| toggle (t) | The software can toggle this bit by writing 1. Writing 0 has no effect. |
| read-only write trigger (rt_w1) | Software can read this bit. Writing 1 triggers an event but has no effect on the bit value. |
| Reserved (Res.) | Reserved bit, must be kept at reset value. |
a. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of them may not be used in the current document.
1.3 Register reset value
Bits (binary notation) or bits nibbles (hexadecimal notation) of which the reset value is undefined are marked as X.
Bits (binary notation) or bits nibbles (hexadecimal notation) of which the reset value is unmodified are marked as U.
1.4 Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
- • The CPU core integrates two debug ports:
- – JTAG debug port ( JTAG-DP ) provides a 5-pin standard interface based on the Joint Test Action Group (JTAG) protocol.
- – SWD debug port ( SWD-DP ) provides a 2-pin (clock and data) interface based on the Serial Wire Debug (SWD) protocol.
For both the JTAG and SWD protocols, refer to the Cortex®-M4 with FPU Technical Reference Manual.
- • Word : data of 32-bit length.
- • Half-word : data of 16-bit length.
- • Byte : data of 8-bit length.
- • Double word : data of 64-bit length.
- • IAP (in-application programming) : IAP is the ability to re-program the flash memory of a microcontroller while the user program is running.
- • ICP (in-circuit programming) : ICP is the ability to program the flash memory of a microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the device is mounted on the user application board.
- • I-Code : this bus connects the Instruction bus of the CPU core to the flash instruction interface. Prefetch is performed on this bus.
- • D-Code : this bus connects the D-Code bus (literal load and debug access) of the CPU to the flash data interface.
- • Option bytes : device configuration bits stored in the flash memory.
- • OBL : option byte loader.
- • AHB : advanced high-performance bus.
- • CPU : refers to the Cortex®-M4 with FPU core.
1.5 Availability of peripherals
For availability of peripherals and their number across all devices, refer to the particular device datasheet.