RM0390-STM32F446

This document is addressed to application developers. It provides complete information on how to use the memory and peripherals of STM32F446xx microcontrollers.

The STM32F446xx constitute a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics refer to the corresponding datasheets.

For information on the Arm ^®Cortex ^®-M4 with FPU core refer to the Cortex ^®-M4 Technical Reference Manual.

STM32F446xx microcontrollers include ST state-of-the-art patented technology

Available from STMicroelectronics web site www.st.com :

• DS10693: STM32F446xx datasheet
• ES0298: STM32F446xC/xE device errata

For information on the Cortex ^®-M4 with FPU, refer to STM32 Cortex ^®-M4 MCUs and MPUs programming manual (PM0214).

1	Documentation conventions . . . . .	51
1.1	General information . . . . .	51
1.2	List of abbreviations for registers . . . . .	51
1.3	Register reset value . . . . .	52
1.4	Glossary . . . . .	52
1.5	Availability of peripherals . . . . .	52
2	Memory and bus architecture . . . . .	53
2.1	System architecture . . . . .	53
2.1.1	I-bus . . . . .	54
2.1.2	D-bus . . . . .	54
2.1.3	S-bus . . . . .	54
2.1.4	DMA memory bus . . . . .	54
2.1.5	DMA peripheral bus . . . . .	55
2.1.6	USB OTG HS DMA bus . . . . .	55
2.1.7	BusMatrix . . . . .	55
2.1.8	AHB/APB bridges (APB) . . . . .	55
2.2	Memory organization . . . . .	56
2.2.1	Introduction . . . . .	56
2.2.2	Memory map and register boundary addresses . . . . .	57
2.2.3	Embedded SRAM . . . . .	60
2.2.4	Flash memory overview . . . . .	60
2.2.5	Bit banding . . . . .	60
2.3	Boot configuration . . . . .	61
3	Embedded flash memory interface . . . . .	64
3.1	Introduction . . . . .	64
3.2	Main features . . . . .	64
3.3	Embedded flash memory . . . . .	65
3.4	Read interface . . . . .	66
3.4.1	Relation between CPU clock frequency and flash memory read time . . . . .	66
3.4.2	Adaptive real-time memory accelerator (ART Accelerator™) . . . . .	67
3.5	Erase and program operations . . . . .	69

3.5.1	Unlocking the control register .....	69
3.5.2	Program/erase parallelism .....	70
3.5.3	Erase .....	70
3.5.4	Programming .....	71
3.5.5	Interrupts .....	72
3.6	Option bytes .....	72
3.6.1	Description of user option bytes .....	72
3.6.2	Programming user option bytes .....	74
3.6.3	Read protection (RDP) .....	74
3.6.4	Write protection .....	77
3.6.5	Proprietary code readout protection (PCROP) .....	78
3.7	One-time programmable bytes .....	79
3.8	Flash interface registers .....	80
3.8.1	Flash access control register (FLASH_ACR) .....	80
3.8.2	Flash key register (FLASH_KEYR) .....	81
3.8.3	Flash option key register (FLASH_OPTKEYR) .....	81
3.8.4	Flash status register (FLASH_SR) .....	82
3.8.5	Flash control register (FLASH_CR) .....	83
3.8.6	Flash option control register (FLASH_OPTCR) .....	84
3.8.7	Flash interface register map .....	87
4	CRC calculation unit .....	88
4.1	CRC introduction .....	88
4.2	CRC main features .....	88
4.3	CRC functional description .....	88
4.4	CRC registers .....	89
4.4.1	Data register (CRC_DR) .....	89
4.4.2	Independent data register (CRC_IDR) .....	90
4.4.3	Control register (CRC_CR) .....	90
4.4.4	CRC register map .....	91
5	Power controller (PWR) .....	92
5.1	Power supplies .....	92
5.1.1	Independent A/D converter supply and reference voltage .....	93
5.1.2	Battery backup domain (also known as RTC domain) .....	93
5.1.3	Voltage regulator .....	95

5.2	Power supply supervisor . . . . .	98
5.2.1	Power-on reset (POR) / power-down reset (PDR) . . . . .	98
5.2.2	Brownout reset (BOR) . . . . .	98
5.2.3	Programmable voltage detector (PVD) . . . . .	99
5.3	Low-power modes . . . . .	100
5.3.1	Slowing down system clocks . . . . .	101
5.3.2	Peripheral clock gating . . . . .	101
5.3.3	Low power mode . . . . .	102
5.3.4	Sleep mode . . . . .	102
5.3.5	Stop mode . . . . .	103
5.3.6	Standby mode . . . . .	106
5.3.7	Programming the RTC alternate functions to wake up the device from the Stop and Standby modes . . . . .	108
5.4	Power control registers . . . . .	111
5.4.1	PWR power control register (PWR_CR) . . . . .	111
5.4.2	PWR power control/status register (PWR_CSR) . . . . .	113
5.5	PWR register map . . . . .	115
6	Reset and clock control (RCC) . . . . .	116
6.1	Reset . . . . .	116
6.1.1	System reset . . . . .	116
6.1.2	Power reset . . . . .	116
6.1.3	Backup domain reset . . . . .	117
6.2	Clocks . . . . .	117
6.2.1	HSE clock . . . . .	120
6.2.2	HSI clock . . . . .	121
6.2.3	PLL configuration . . . . .	121
6.2.4	LSE clock . . . . .	122
6.2.5	LSI clock . . . . .	122
6.2.6	System clock (SYSCLK) selection . . . . .	122
6.2.7	Clock security system (CSS) . . . . .	123
6.2.8	RTC/AWU clock . . . . .	123
6.2.9	Watchdog clock . . . . .	124
6.2.10	Clock-out capability . . . . .	124
6.2.11	Internal/external clock measurement using TIM5/TIM11 . . . . .	124
6.3	RCC registers . . . . .	127
6.3.1	RCC clock control register (RCC_CR) . . . . .	127

6.3.2	RCC PLL configuration register (RCC_PLLCFGR) . . . . .	128
6.3.3	RCC clock configuration register (RCC_CFGR) . . . . .	130
6.3.4	RCC clock interrupt register (RCC_CIR) . . . . .	133
6.3.5	RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .	135
6.3.6	RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .	137
6.3.7	RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . .	138
6.3.8	RCC APB1 peripheral reset register (RCC_APB1RSTR) . . . . .	138
6.3.9	RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .	141
6.3.10	RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . .	142
6.3.11	RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . .	144
6.3.12	RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . .	145
6.3.13	RCC APB1 peripheral clock enable register (RCC_APB1ENR) . . . . .	145
6.3.14	RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .	148
6.3.15	RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR) . . . . .	150
6.3.16	RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR) . . . . .	152
6.3.17	RCC AHB3 peripheral clock enable in low power mode register (RCC_AHB3LPENR) . . . . .	152
6.3.18	RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR) . . . . .	153
6.3.19	RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) . . . . .	156
6.3.20	RCC Backup domain control register (RCC_BDCR) . . . . .	158
6.3.21	RCC clock control and status register (RCC_CSR) . . . . .	159
6.3.22	RCC spread spectrum clock generation register (RCC_SSCGR) . . . . .	160
6.3.23	RCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . .	161
6.3.24	RCC PLL configuration register (RCC_PLLSAICFGR) . . . . .	163
6.3.25	RCC dedicated clock configuration register (RCC_DCKCFGR) . . . . .	165
6.3.26	RCC clocks gated enable register (CKGATENR) . . . . .	167
6.3.27	RCC dedicated clocks configuration register 2 (DCKCFGR2) . . . . .	168
6.3.28	RCC register map . . . . .	170
7	General-purpose I/Os (GPIO) . . . . .	174
7.1	GPIO introduction . . . . .	174
7.2	GPIO main features . . . . .	174
7.3	GPIO functional description . . . . .	174
7.3.1	General-purpose I/O (GPIO) . . . . .	176

7.3.2	I/O pin multiplexer and mapping . . . . .	176
7.3.3	I/O port control registers . . . . .	178
7.3.4	I/O port data registers . . . . .	179
7.3.5	I/O data bitwise handling . . . . .	179
7.3.6	GPIO locking mechanism . . . . .	179
7.3.7	I/O alternate function input/output . . . . .	180
7.3.8	External interrupt/wakeup lines . . . . .	180
7.3.9	Input configuration . . . . .	180
7.3.10	Output configuration . . . . .	181
7.3.11	Alternate function configuration . . . . .	181
7.3.12	Analog configuration . . . . .	182
7.3.13	Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins . . . . .	183
7.3.14	Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins . . . . .	183
7.3.15	Selection of RTC additional_AF1 and RTC_AF2 alternate functions . . . . .	183
7.4	GPIO registers . . . . .	185
7.4.1	GPIO port mode register (GPIOx_MODER) (x = A..H) . . . . .	185
7.4.2	GPIO port output type register (GPIOx_OTYPER) (x = A..H) . . . . .	185
7.4.3	GPIO port output speed register (GPIOx_OSPEEDR) (x = A..H) . . . . .	186
7.4.4	GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..H) . . . . .	186
7.4.5	GPIO port input data register (GPIOx_IDR) (x = A..H) . . . . .	187
7.4.6	GPIO port output data register (GPIOx_ODR) (x = A..H) . . . . .	187
7.4.7	GPIO port bit set/reset register (GPIOx_BSRR) (x = A..H) . . . . .	187
7.4.8	GPIO port configuration lock register (GPIOx_LCKR) (x = A..H) . . . . .	188
7.4.9	GPIO alternate function low register (GPIOx_AFRL) (x = A..H) . . . . .	189
7.4.10	GPIO alternate function high register (GPIOx_AFRH) (x = A..H) . . . . .	189
7.4.11	GPIO register map . . . . .	191
8	System configuration controller (SYSCFG) . . . . .	193
8.1	I/O compensation cell . . . . .	193
8.2	SYSCFG registers . . . . .	193
8.2.1	SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .	193
8.2.2	SYSCFG peripheral mode configuration register (SYSCFG_PMC) . . . . .	194
8.2.3	SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . .	195
8.2.4	SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) . . . . .	195

8.2.5	SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) .....	196
8.2.6	SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) .....	196
8.2.7	Compensation cell control register (SYSCFG_CMPCR) .....	197
8.2.8	SYSCFG configuration register (SYSCFG_CFGR) .....	197
8.2.9	SYSCFG register map .....	199
9	Direct memory access controller (DMA) .....	200
9.1	DMA introduction .....	200
9.2	DMA main features .....	200
9.3	DMA functional description .....	202
9.3.1	DMA block diagram .....	202
9.3.2	DMA overview .....	202
9.3.3	DMA transactions .....	203
9.3.4	Channel selection .....	203
9.3.5	Arbiter .....	205
9.3.6	DMA streams .....	205
9.3.7	Source, destination and transfer modes .....	205
9.3.8	Pointer incrementation .....	209
9.3.9	Circular mode .....	210
9.3.10	Double-buffer mode .....	210
9.3.11	Programmable data width, packing/unpacking, endianness .....	211
9.3.12	Single and burst transfers .....	212
9.3.13	FIFO .....	213
9.3.14	DMA transfer completion .....	216
9.3.15	DMA transfer suspension .....	217
9.3.16	Flow controller .....	218
9.3.17	Summary of the possible DMA configurations .....	219
9.3.18	Stream configuration procedure .....	219
9.3.19	Error management .....	220
9.4	DMA interrupts .....	221
9.5	DMA registers .....	222
9.5.1	DMA low interrupt status register (DMA_LISR) .....	222
9.5.2	DMA high interrupt status register (DMA_HISR) .....	223
9.5.3	DMA low interrupt flag clear register (DMA_LIFCR) .....	223
9.5.4	DMA high interrupt flag clear register (DMA_HIFCR) .....	224

- 9.5.5 DMA stream x configuration register (DMA_SxCR) . . . . . . . . . . . . . . . . . . . 225
- 9.5.6 DMA stream x number of data register (DMA_SxNDTR) . . . . . . . . . . . . . 228
- 9.5.7 DMA stream x peripheral address register (DMA_SxPAR) . . . . . . . . . . . . 228
- 9.5.8 DMA stream x memory 0 address register
  (DMA_SxM0AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
- 9.5.9 DMA stream x memory 1 address register
  (DMA_SxM1AR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
- 9.5.10 DMA stream x FIFO control register (DMA_SxFCR) . . . . . . . . . . . . . . . . . 230
- 9.5.11 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
10 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
- 10.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . . . . 235
  - 10.1.1 NVIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
  - 10.1.2 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
  - 10.1.3 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
- 10.2 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
  - 10.2.1 EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
  - 10.2.2 EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
  - 10.2.3 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
  - 10.2.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
  - 10.2.5 External interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 242
- 10.3 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
  - 10.3.1 Interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
  - 10.3.2 Event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
  - 10.3.3 Rising trigger selection register (EXTI_RTSR) . . . . . . . . . . . . . . . . . . . 244
  - 10.3.4 Falling trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . . . . . . 244
  - 10.3.5 Software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . . . . . . 245
  - 10.3.6 Pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
  - 10.3.7 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
11 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
- 11.1 FMC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
- 11.2 FMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
- 11.3 FMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
- 11.4 AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
  - 11.4.1 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . 249
- 11.5 External device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

11.5.1	NOR/PSRAM address mapping . . . . .	251
11.5.2	NAND flash memory address mapping . . . . .	252
11.5.3	SDRAM address mapping . . . . .	253
11.6	NOR flash/PSRAM controller . . . . .	255
11.6.1	External memory interface signals . . . . .	257
11.6.2	Supported memories and transactions . . . . .	258
11.6.3	General timing rules . . . . .	260
11.6.4	NOR flash/PSRAM controller asynchronous transactions . . . . .	260
11.6.5	Synchronous transactions . . . . .	277
11.6.6	NOR/PSRAM controller registers . . . . .	284
11.7	NAND flash controller . . . . .	291
11.7.1	External memory interface signals . . . . .	291
11.7.2	NAND flash supported memories and transactions . . . . .	292
11.7.3	Timing diagrams for NAND flash memory . . . . .	293
11.7.4	NAND flash operations . . . . .	294
11.7.5	NAND flash prewait functionality . . . . .	294
11.7.6	Computation of the error correction code (ECC) in NAND flash memory . . . . .	295
11.7.7	NAND flash controller registers . . . . .	296
11.8	SDRAM controller . . . . .	302
11.8.1	SDRAM controller main features . . . . .	302
11.8.2	SDRAM External memory interface signals . . . . .	302
11.8.3	SDRAM controller functional description . . . . .	303
11.8.4	Low-power modes . . . . .	309
11.8.5	SDRAM controller registers . . . . .	312
11.8.6	FMC register map . . . . .	318
12	Quad-SPI interface (QUADSPI) . . . . .	321
12.1	Introduction . . . . .	321
12.2	QUADSPI main features . . . . .	321
12.3	QUADSPI functional description . . . . .	321
12.3.1	QUADSPI block diagram . . . . .	321
12.3.2	QUADSPI pins . . . . .	322
12.3.3	QUADSPI command sequence . . . . .	322
12.3.4	QUADSPI signal interface protocol modes . . . . .	325
12.3.5	QUADSPI indirect mode . . . . .	327
12.3.6	QUADSPI automatic status-polling mode . . . . .	329

12.3.7	QUADSPI memory-mapped mode . . . . .	329
12.3.8	QUADSPI flash memory configuration . . . . .	330
12.3.9	QUADSPI delayed data sampling . . . . .	330
12.3.10	QUADSPI configuration . . . . .	330
12.3.11	QUADSPI use . . . . .	331
12.3.12	Sending the instruction only once . . . . .	333
12.3.13	QUADSPI error management . . . . .	333
12.3.14	QUADSPI busy bit and abort functionality . . . . .	333
12.3.15	NCS behavior . . . . .	334
12.4	QUADSPI interrupts . . . . .	336
12.5	QUADSPI registers . . . . .	336
12.5.1	QUADSPI control register (QUADSPI_CR) . . . . .	336
12.5.2	QUADSPI device configuration register (QUADSPI_DCR) . . . . .	339
12.5.3	QUADSPI status register (QUADSPI_SR) . . . . .	340
12.5.4	QUADSPI flag clear register (QUADSPI_FCR) . . . . .	341
12.5.5	QUADSPI data length register (QUADSPI_DLR) . . . . .	341
12.5.6	QUADSPI communication configuration register (QUADSPI_CCR) . . . . .	342
12.5.7	QUADSPI address register (QUADSPI_AR) . . . . .	344
12.5.8	QUADSPI alternate-byte register (QUADSPI_ABR) . . . . .	345
12.5.9	QUADSPI data register (QUADSPI_DR) . . . . .	345
12.5.10	QUADSPI polling status mask register (QUADSPI_PSMKR) . . . . .	346
12.5.11	QUADSPI polling status match register (QUADSPI_PSMAR) . . . . .	346
12.5.12	QUADSPI polling interval register (QUADSPI_PIR) . . . . .	347
12.5.13	QUADSPI low-power timeout register (QUADSPI_LPTR) . . . . .	347
12.5.14	QUADSPI register map . . . . .	348
13	Analog-to-digital converter (ADC) . . . . .	349
13.1	ADC introduction . . . . .	349
13.2	ADC main features . . . . .	349
13.3	ADC functional description . . . . .	350
13.3.1	ADC on-off control . . . . .	351
13.3.2	ADC1/2 and ADC3 connectivity . . . . .	352
13.3.3	ADC clock . . . . .	355
13.3.4	Channel selection . . . . .	355
13.3.5	Single conversion mode . . . . .	356
13.3.6	Continuous conversion mode . . . . .	356
13.3.7	Timing diagram . . . . .	356

13.3.8	Analog watchdog . . . . .	357
13.3.9	Scan mode . . . . .	358
13.3.10	Injected channel management . . . . .	358
13.3.11	Discontinuous mode . . . . .	359
13.4	Data alignment . . . . .	360
13.5	Channel-wise programmable sampling time . . . . .	361
13.6	Conversion on external trigger and trigger polarity . . . . .	362
13.7	Fast conversion mode . . . . .	363
13.8	Data management . . . . .	364
13.8.1	Using the DMA . . . . .	364
13.8.2	Managing a sequence of conversions without using the DMA . . . . .	364
13.8.3	Conversions without DMA and without overrun detection . . . . .	365
13.9	Multi ADC mode . . . . .	365
13.9.1	Injected simultaneous mode . . . . .	368
13.9.2	Regular simultaneous mode . . . . .	369
13.9.3	Interleaved mode . . . . .	370
13.9.4	Alternate trigger mode . . . . .	372
13.9.5	Combined regular/injected simultaneous mode . . . . .	374
13.9.6	Combined regular simultaneous + alternate trigger mode . . . . .	374
13.10	Temperature sensor . . . . .	375
13.11	Battery charge monitoring . . . . .	377
13.12	ADC interrupts . . . . .	377
13.13	ADC registers . . . . .	378
13.13.1	ADC status register (ADC_SR) . . . . .	378
13.13.2	ADC control register 1 (ADC_CR1) . . . . .	379
13.13.3	ADC control register 2 (ADC_CR2) . . . . .	381
13.13.4	ADC sample time register 1 (ADC_SMPR1) . . . . .	383
13.13.5	ADC sample time register 2 (ADC_SMPR2) . . . . .	383
13.13.6	ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) . . . . .	384
13.13.7	ADC watchdog higher threshold register (ADC_HTR) . . . . .	384
13.13.8	ADC watchdog lower threshold register (ADC_LTR) . . . . .	385
13.13.9	ADC regular sequence register 1 (ADC_SQR1) . . . . .	385
13.13.10	ADC regular sequence register 2 (ADC_SQR2) . . . . .	386
13.13.11	ADC regular sequence register 3 (ADC_SQR3) . . . . .	386
13.13.12	ADC injected sequence register (ADC_JSQR) . . . . .	387
13.13.13	ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . .	388

13.13.14	ADC regular data register (ADC_DR) . . . . .	388
13.13.15	ADC Common status register (ADC_CSR) . . . . .	388
13.13.16	ADC common control register (ADC_CCR) . . . . .	390
13.13.17	ADC common regular data register for dual and triple modes (ADC_CDR) . . . . .	391
13.13.18	ADC register map . . . . .	392
14	Digital-to-analog converter (DAC) . . . . .	395
14.1	DAC introduction . . . . .	395
14.2	DAC main features . . . . .	395
14.3	DAC functional description . . . . .	396
14.3.1	DAC channel enable . . . . .	396
14.3.2	DAC output buffer enable . . . . .	397
14.3.3	DAC data format . . . . .	397
14.3.4	DAC conversion . . . . .	398
14.3.5	DAC output voltage . . . . .	399
14.3.6	DAC trigger selection . . . . .	399
14.3.7	DMA request . . . . .	400
14.3.8	Noise generation . . . . .	400
14.3.9	Triangle-wave generation . . . . .	401
14.4	Dual DAC channel conversion . . . . .	402
14.4.1	Independent trigger without wave generation . . . . .	403
14.4.2	Independent trigger with single LFSR generation . . . . .	403
14.4.3	Independent trigger with different LFSR generation . . . . .	403
14.4.4	Independent trigger with single triangle generation . . . . .	404
14.4.5	Independent trigger with different triangle generation . . . . .	404
14.4.6	Simultaneous software start . . . . .	404
14.4.7	Simultaneous trigger without wave generation . . . . .	405
14.4.8	Simultaneous trigger with single LFSR generation . . . . .	405
14.4.9	Simultaneous trigger with different LFSR generation . . . . .	405
14.4.10	Simultaneous trigger with single triangle generation . . . . .	406
14.4.11	Simultaneous trigger with different triangle generation . . . . .	406
14.5	DAC registers . . . . .	407
14.5.1	DAC control register (DAC_CR) . . . . .	407
14.5.2	DAC software trigger register (DAC_SWTRIGR) . . . . .	410
14.5.3	DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . .	410

14.5.4	DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) .....	411
14.5.5	DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) .....	411
14.5.6	DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) .....	412
14.5.7	DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) .....	412
14.5.8	DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) .....	412
14.5.9	Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) .....	413
14.5.10	DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) .....	413
14.5.11	DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) .....	414
14.5.12	DAC channel1 data output register (DAC_DOR1) .....	414
14.5.13	DAC channel2 data output register (DAC_DOR2) .....	414
14.5.14	DAC status register (DAC_SR) .....	415
14.5.15	DAC register map .....	416
15	Digital camera interface (DCMI) .....	417
15.1	DCMI introduction .....	417
15.2	DCMI main features .....	417
15.3	DCMI functional description .....	417
15.3.1	DCMI block diagram .....	418
15.3.2	DCMI pins .....	418
15.3.3	DCMI clocks .....	418
15.3.4	DCMI DMA interface .....	419
15.3.5	DCMI physical interface .....	419
15.3.6	DCMI synchronization .....	421
15.3.7	DCMI capture modes .....	423
15.3.8	DCMI crop feature .....	424
15.3.9	DCMI JPEG format .....	425
15.3.10	DCMI FIFO .....	425
15.3.11	DCMI data format description .....	426
15.4	DCMI interrupts .....	428
15.5	DCMI registers .....	428
15.5.1	DCMI control register (DCMI_CR) .....	428

15.5.2	DCMI status register (DCMI_SR) . . . . .	431
15.5.3	DCMI raw interrupt status register (DCMI_RIS) . . . . .	431
15.5.4	DCMI interrupt enable register (DCMI_IER) . . . . .	432
15.5.5	DCMI masked interrupt status register (DCMI_MIS) . . . . .	433
15.5.6	DCMI interrupt clear register (DCMI_ICR) . . . . .	434
15.5.7	DCMI embedded synchronization code register (DCMI_ESCR) . . . . .	435
15.5.8	DCMI embedded synchronization unmask register (DCMI_ESUR) . . . . .	435
15.5.9	DCMI crop window start (DCMI_CWSTRTR) . . . . .	436
15.5.10	DCMI crop window size (DCMI_CWSIZE) . . . . .	437
15.5.11	DCMI data register (DCMI_DR) . . . . .	437
15.5.12	DCMI register map . . . . .	438
16	Advanced-control timers (TIM1&TIM8) . . . . .	439
16.1	TIM1&TIM8 introduction . . . . .	439
16.2	TIM1&TIM8 main features . . . . .	439
16.3	TIM1&TIM8 functional description . . . . .	441
16.3.1	Time-base unit . . . . .	441
16.3.2	Counter modes . . . . .	443
16.3.3	Repetition counter . . . . .	452
16.3.4	Clock selection . . . . .	455
16.3.5	Capture/compare channels . . . . .	458
16.3.6	Input capture mode . . . . .	461
16.3.7	PWM input mode . . . . .	462
16.3.8	Forced output mode . . . . .	462
16.3.9	Output compare mode . . . . .	463
16.3.10	PWM mode . . . . .	464
16.3.11	Complementary outputs and dead-time insertion . . . . .	467
16.3.12	Using the break function . . . . .	469
16.3.13	Clearing the OCxREF signal on an external event . . . . .	472
16.3.14	6-step PWM generation . . . . .	473
16.3.15	One-pulse mode . . . . .	474
16.3.16	Encoder interface mode . . . . .	475
16.3.17	Timer input XOR function . . . . .	478
16.3.18	Interfacing with Hall sensors . . . . .	478
16.3.19	TIMx and external trigger synchronization . . . . .	480
16.3.20	Timer synchronization . . . . .	483
16.3.21	Debug mode . . . . .	483

16.4	TIM1&TIM8 registers . . . . .	484
16.4.1	TIM1&TIM8 control register 1 (TIMx_CR1) . . . . .	484
16.4.2	TIM1&TIM8 control register 2 (TIMx_CR2) . . . . .	485
16.4.3	TIM1&TIM8 slave mode control register (TIMx_SMCR) . . . . .	487
16.4.4	TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . .	489
16.4.5	TIM1&TIM8 status register (TIMx_SR) . . . . .	491
16.4.6	TIM1&TIM8 event generation register (TIMx_EGR) . . . . .	492
16.4.7	TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . . . .	493
16.4.8	TIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . . . .	496
16.4.9	TIM1&TIM8 capture/compare enable register (TIMx_CCER) . . . . .	498
16.4.10	TIM1&TIM8 counter (TIMx_CNT) . . . . .	502
16.4.11	TIM1&TIM8 prescaler (TIMx_PSC) . . . . .	502
16.4.12	TIM1&TIM8 auto-reload register (TIMx_ARR) . . . . .	502
16.4.13	TIM1&TIM8 repetition counter register (TIMx_RCR) . . . . .	502
16.4.14	TIM1&TIM8 capture/compare register 1 (TIMx_CCR1) . . . . .	503
16.4.15	TIM1&TIM8 capture/compare register 2 (TIMx_CCR2) . . . . .	503
16.4.16	TIM1&TIM8 capture/compare register 3 (TIMx_CCR3) . . . . .	504
16.4.17	TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) . . . . .	504
16.4.18	TIM1&TIM8 break and dead-time register (TIMx_BDTR) . . . . .	504
16.4.19	TIM1&TIM8 DMA control register (TIMx_DCR) . . . . .	506
16.4.20	TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) . . . . .	507
16.4.21	TIM1&TIM8 register map . . . . .	508
17	General-purpose timers (TIM2 to TIM5) . . . . .	510
17.1	TIM2 to TIM5 introduction . . . . .	510
17.2	TIM2 to TIM5 main features . . . . .	510
17.3	TIM2 to TIM5 functional description . . . . .	511
17.3.1	Time-base unit . . . . .	511
17.3.2	Counter modes . . . . .	513
17.3.3	Clock selection . . . . .	522
17.3.4	Capture/compare channels . . . . .	525
17.3.5	Input capture mode . . . . .	527
17.3.6	PWM input mode . . . . .	528
17.3.7	Forced output mode . . . . .	529
17.3.8	Output compare mode . . . . .	529
17.3.9	PWM mode . . . . .	531
17.3.10	One-pulse mode . . . . .	534

17.3.11	Clearing the OCxREF signal on an external event .....	535
17.3.12	Encoder interface mode .....	536
17.3.13	Timer input XOR function .....	538
17.3.14	Timers and external trigger synchronization .....	538
17.3.15	Timer synchronization .....	542
17.3.16	Debug mode .....	547
17.4	TIM2 to TIM5 registers .....	548
17.4.1	TIMx control register 1 (TIMx_CR1) .....	548
17.4.2	TIMx control register 2 (TIMx_CR2) .....	550
17.4.3	TIMx slave mode control register (TIMx_SMCR) .....	551
17.4.4	TIMx DMA/Interrupt enable register (TIMx_DIER) .....	553
17.4.5	TIMx status register (TIMx_SR) .....	554
17.4.6	TIMx event generation register (TIMx_EGR) .....	556
17.4.7	TIMx capture/compare mode register 1 (TIMx_CCMR1) .....	557
17.4.8	TIMx capture/compare mode register 2 (TIMx_CCMR2) .....	560
17.4.9	TIMx capture/compare enable register (TIMx_CCER) .....	561
17.4.10	TIMx counter (TIMx_CNT) .....	563
17.4.11	TIMx prescaler (TIMx_PSC) .....	563
17.4.12	TIMx auto-reload register (TIMx_ARR) .....	563
17.4.13	TIMx capture/compare register 1 (TIMx_CCR1) .....	564
17.4.14	TIMx capture/compare register 2 (TIMx_CCR2) .....	564
17.4.15	TIMx capture/compare register 3 (TIMx_CCR3) .....	565
17.4.16	TIMx capture/compare register 4 (TIMx_CCR4) .....	565
17.4.17	TIMx DMA control register (TIMx_DCR) .....	566
17.4.18	TIMx DMA address for full transfer (TIMx_DMAR) .....	566
17.4.19	TIM2 option register (TIM2_OR) .....	567
17.4.20	TIM5 option register (TIM5_OR) .....	568
17.4.21	TIMx register map .....	569
18	General-purpose timers (TIM9 to TIM14) .....	571
18.1	TIM9 to TIM14 introduction .....	571
18.2	TIM9 to TIM14 main features .....	571
18.2.1	TIM9/TIM12 main features .....	571
18.2.2	TIM10/TIM11 and TIM13/TIM14 main features .....	572
18.3	TIM9 to TIM14 functional description .....	574
18.3.1	Time-base unit .....	574
18.3.2	Counter modes .....	576

18.3.3	Clock selection . . . . .	579
18.3.4	Capture/compare channels . . . . .	581
18.3.5	Input capture mode . . . . .	582
18.3.6	PWM input mode (only for TIM9/12) . . . . .	583
18.3.7	Forced output mode . . . . .	584
18.3.8	Output compare mode . . . . .	585
18.3.9	PWM mode . . . . .	586
18.3.10	One-pulse mode . . . . .	587
18.3.11	TIM9/12 external trigger synchronization . . . . .	589
18.3.12	Timer synchronization (TIM9/12) . . . . .	592
18.3.13	Debug mode . . . . .	592
18.4	TIM9 and TIM12 registers . . . . .	592
18.4.1	TIM9/12 control register 1 (TIMx_CR1) . . . . .	592
18.4.2	TIM9/12 slave mode control register (TIMx_SMCR) . . . . .	594
18.4.3	TIM9/12 Interrupt enable register (TIMx_DIER) . . . . .	595
18.4.4	TIM9/12 status register (TIMx_SR) . . . . .	596
18.4.5	TIM9/12 event generation register (TIMx_EGR) . . . . .	598
18.4.6	TIM9/12 capture/compare mode register 1 (TIMx_CCMR1) . . . . .	598
18.4.7	TIM9/12 capture/compare enable register (TIMx_CCER) . . . . .	602
18.4.8	TIM9/12 counter (TIMx_CNT) . . . . .	603
18.4.9	TIM9/12 prescaler (TIMx_PSC) . . . . .	603
18.4.10	TIM9/12 auto-reload register (TIMx_ARR) . . . . .	603
18.4.11	TIM9/12 capture/compare register 1 (TIMx_CCR1) . . . . .	604
18.4.12	TIM9/12 capture/compare register 2 (TIMx_CCR2) . . . . .	604
18.4.13	TIM9/12 register map . . . . .	605
18.5	TIM10/11/13/14 registers . . . . .	607
18.5.1	TIM10/11/13/14 control register 1 (TIMx_CR1) . . . . .	607
18.5.2	TIM10/11/13/14 Interrupt enable register (TIMx_DIER) . . . . .	608
18.5.3	TIM10/11/13/14 status register (TIMx_SR) . . . . .	608
18.5.4	TIM10/11/13/14 event generation register (TIMx_EGR) . . . . .	609
18.5.5	TIM10/11/13/14 capture/compare mode register 1 (TIMx_CCMR1) . . . . .	610
18.5.6	TIM10/11/13/14 capture/compare enable register (TIMx_CCER) . . . . .	613
18.5.7	TIM10/11/13/14 counter (TIMx_CNT) . . . . .	614
18.5.8	TIM10/11/13/14 prescaler (TIMx_PSC) . . . . .	614
18.5.9	TIM10/11/13/14 auto-reload register (TIMx_ARR) . . . . .	614

18.5.10	TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) . . . . .	615
18.5.11	TIM11 option register 1 (TIM11_OR) . . . . .	615
18.5.12	TIM10/11/13/14 register map . . . . .	616
19	Basic timers (TIM6&TIM7) . . . . .	618
19.1	TIM6&TIM7 introduction . . . . .	618
19.2	TIM6&TIM7 main features . . . . .	618
19.3	TIM6&TIM7 functional description . . . . .	619
19.3.1	Time-base unit . . . . .	619
19.3.2	Counting mode . . . . .	621
19.3.3	Clock source . . . . .	623
19.3.4	Debug mode . . . . .	624
19.4	TIM6&TIM7 registers . . . . .	624
19.4.1	TIM6&TIM7 control register 1 (TIMx_CR1) . . . . .	624
19.4.2	TIM6&TIM7 control register 2 (TIMx_CR2) . . . . .	626
19.4.3	TIM6&TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . .	626
19.4.4	TIM6&TIM7 status register (TIMx_SR) . . . . .	627
19.4.5	TIM6&TIM7 event generation register (TIMx_EGR) . . . . .	627
19.4.6	TIM6&TIM7 counter (TIMx_CNT) . . . . .	627
19.4.7	TIM6&TIM7 prescaler (TIMx_PSC) . . . . .	628
19.4.8	TIM6&TIM7 auto-reload register (TIMx_ARR) . . . . .	628
19.4.9	TIM6&TIM7 register map . . . . .	629
20	Independent watchdog (IWDG) . . . . .	630
20.1	IWDG introduction . . . . .	630
20.2	IWDG main features . . . . .	630
20.3	IWDG functional description . . . . .	630
20.3.1	Hardware watchdog . . . . .	630
20.3.2	Register access protection . . . . .	630
20.3.3	Debug mode . . . . .	631
20.4	IWDG registers . . . . .	632
20.4.1	Key register (IWDG_KR) . . . . .	632
20.4.2	Prescaler register (IWDG_PR) . . . . .	633
20.4.3	Reload register (IWDG_RLR) . . . . .	634
20.4.4	Status register (IWDG_SR) . . . . .	634
20.4.5	IWDG register map . . . . .	635

21	Window watchdog (WWDG) . . . . .	636
21.1	WWDG introduction . . . . .	636
21.2	WWDG main features . . . . .	636
21.3	WWDG functional description . . . . .	636
21.4	How to program the watchdog timeout . . . . .	638
21.5	Debug mode . . . . .	639
21.6	WWDG registers . . . . .	640
21.6.1	Control register (WWDG_CR) . . . . .	640
21.6.2	Configuration register (WWDG_CFR) . . . . .	641
21.6.3	Status register (WWDG_SR) . . . . .	641
21.6.4	WWDG register map . . . . .	642
22	Real-time clock (RTC) . . . . .	643
22.1	Introduction . . . . .	643
22.2	RTC main features . . . . .	643
22.3	RTC functional description . . . . .	645
22.3.1	Clock and prescalers . . . . .	645
22.3.2	Real-time clock and calendar . . . . .	645
22.3.3	Programmable alarms . . . . .	646
22.3.4	Periodic auto-wakeup . . . . .	646
22.3.5	RTC initialization and configuration . . . . .	647
22.3.6	Reading the calendar . . . . .	649
22.3.7	Resetting the RTC . . . . .	650
22.3.8	RTC synchronization . . . . .	650
22.3.9	RTC reference clock detection . . . . .	651
22.3.10	RTC coarse digital calibration . . . . .	651
22.3.11	RTC smooth digital calibration . . . . .	652
22.3.12	Timestamp function . . . . .	654
22.3.13	Tamper detection . . . . .	655
22.3.14	Calibration clock output . . . . .	657
22.3.15	Alarm output . . . . .	657
22.4	RTC and low power modes . . . . .	658
22.5	RTC interrupts . . . . .	658
22.6	RTC registers . . . . .	660
22.6.1	RTC time register (RTC_TR) . . . . .	660
22.6.2	RTC date register (RTC_DR) . . . . .	660

22.6.3	RTC control register (RTC_CR) . . . . .	661
22.6.4	RTC initialization and status register (RTC_ISR) . . . . .	664
22.6.5	RTC prescaler register (RTC_PRER) . . . . .	666
22.6.6	RTC wakeup timer register (RTC_WUTR) . . . . .	666
22.6.7	RTC calibration register (RTC_CALIBR) . . . . .	667
22.6.8	RTC alarm A register (RTC_ALRMAR) . . . . .	668
22.6.9	RTC alarm B register (RTC_ALRMBR) . . . . .	669
22.6.10	RTC write protection register (RTC_WPR) . . . . .	670
22.6.11	RTC sub second register (RTC_SSR) . . . . .	670
22.6.12	RTC shift control register (RTC_SHIFTR) . . . . .	671
22.6.13	RTC time stamp time register (RTC_TSTR) . . . . .	672
22.6.14	RTC time stamp date register (RTC_TSDR) . . . . .	673
22.6.15	RTC timestamp sub second register (RTC_TSSSR) . . . . .	673
22.6.16	RTC calibration register (RTC_CALR) . . . . .	674
22.6.17	RTC tamper and alternate function configuration register (RTC_TAMPCR) . . . . .	674
22.6.18	RTC alarm A sub second register (RTC_ALRMASSR) . . . . .	676
22.6.19	RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .	677
22.6.20	RTC backup registers (RTC_BKPxR) . . . . .	678
22.6.21	RTC register map . . . . .	679
23	Fast-mode Plus Inter-integrated circuit interface (FMPI2C) . . . . .	681
23.1	FMPI2C introduction . . . . .	681
23.2	FMPI2C main features . . . . .	681
23.3	FMPI2C implementation . . . . .	682
23.4	FMPI2C functional description . . . . .	682
23.4.1	FMPI2C block diagram . . . . .	683
23.4.2	FMPI2C pins and internal signals . . . . .	683
23.4.3	FMPI2C clock requirements . . . . .	684
23.4.4	FMPI2C mode selection . . . . .	684
23.4.5	FMPI2C initialization . . . . .	685
23.4.6	FMPI2C reset . . . . .	689
23.4.7	FMPI2C data transfer . . . . .	690
23.4.8	FMPI2C target mode . . . . .	692
23.4.9	FMPI2C controller mode . . . . .	701
23.4.10	FMPI2C_TIMINGR register configuration examples . . . . .	712
23.4.11	SMBus specific features . . . . .	714

23.4.12	SMBus initialization . . . . .	716
23.4.13	SMBus FMPI2C_TIMEOUTR register configuration examples . . . . .	718
23.4.14	SMBus target mode . . . . .	719
23.4.15	SMBus controller mode . . . . .	722
23.4.16	Error conditions . . . . .	725
23.5	FMPI2C in low-power modes . . . . .	727
23.6	FMPI2C interrupts . . . . .	727
23.7	FMPI2C DMA requests . . . . .	728
23.7.1	Transmission using DMA . . . . .	728
23.7.2	Reception using DMA . . . . .	728
23.8	FMPI2C debug modes . . . . .	729
23.9	FMPI2C registers . . . . .	729
23.9.1	FMPI2C control register 1 (FMPI2C_CR1) . . . . .	729
23.9.2	FMPI2C control register 2 (FMPI2C_CR2) . . . . .	732
23.9.3	FMPI2C own address 1 register (FMPI2C_OAR1) . . . . .	734
23.9.4	FMPI2C own address 2 register (FMPI2C_OAR2) . . . . .	734
23.9.5	FMPI2C timing register (FMPI2C_TIMINGR) . . . . .	735
23.9.6	FMPI2C timeout register (FMPI2C_TIMEOUTR) . . . . .	736
23.9.7	FMPI2C interrupt and status register (FMPI2C_ISR) . . . . .	737
23.9.8	FMPI2C interrupt clear register (FMPI2C_ICR) . . . . .	740
23.9.9	FMPI2C PEC register (FMPI2C_PECR) . . . . .	741
23.9.10	FMPI2C receive data register (FMPI2C_RXDR) . . . . .	741
23.9.11	FMPI2C transmit data register (FMPI2C_TXDR) . . . . .	742
23.9.12	FMPI2C register map . . . . .	743
24	Inter-integrated circuit (I ²C) interface . . . . .	744
24.1	I ²C introduction . . . . .	744
24.2	I ²C main features . . . . .	744
24.3	I ²C functional description . . . . .	745
24.3.1	Mode selection . . . . .	745
24.3.2	I2C target mode . . . . .	747
24.3.3	I2C controller mode . . . . .	749
24.3.4	Error conditions . . . . .	754
24.3.5	Programmable noise filter . . . . .	755
24.3.6	SDA/SCL line control . . . . .	755
24.3.7	SMBus . . . . .	756

24.3.8	DMA requests . . . . .	758
24.3.9	Packet error checking . . . . .	760
24.4	I ²C interrupts . . . . .	760
24.5	I ²C debug mode . . . . .	761
24.6	I ²C registers . . . . .	762
24.6.1	I ²C control register 1 (I2C_CR1) . . . . .	762
24.6.2	I ²C control register 2 (I2C_CR2) . . . . .	764
24.6.3	I ²C own address register 1 (I2C_OAR1) . . . . .	765
24.6.4	I ²C own address register 2 (I2C_OAR2) . . . . .	766
24.6.5	I ²C data register (I2C_DR) . . . . .	766
24.6.6	I ²C status register 1 (I2C_SR1) . . . . .	766
24.6.7	I ²C status register 2 (I2C_SR2) . . . . .	769
24.6.8	I ²C clock control register (I2C_CCR) . . . . .	770
24.6.9	I ²C TRISE register (I2C_TRISE) . . . . .	771
24.6.10	I ²C FLTR register (I2C_FLTR) . . . . .	772
24.6.11	I2C register map . . . . .	773
25	Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmitter (UART) . . . . .	774
25.1	USART introduction . . . . .	774
25.2	USART main features . . . . .	775
25.3	USART implementation . . . . .	776
25.4	USART functional description . . . . .	776
25.4.1	USART character description . . . . .	778
25.4.2	Transmitter . . . . .	779
25.4.3	Receiver . . . . .	782
25.4.4	Fractional baud rate generation . . . . .	787
25.4.5	USART receiver tolerance to clock deviation . . . . .	796
25.4.6	Multiprocessor communication . . . . .	797
25.4.7	Parity control . . . . .	799
25.4.8	LIN (local interconnection network) mode . . . . .	800
25.4.9	USART synchronous mode . . . . .	802
25.4.10	Single-wire half-duplex communication . . . . .	804
25.4.11	Smartcard . . . . .	805
25.4.12	IrDA SIR ENDEC block . . . . .	807
25.4.13	Continuous communication using DMA . . . . .	809

25.4.14	Hardware flow control .....	811
25.5	USART interrupts .....	813
25.6	USART registers .....	814
25.6.1	Status register (USART_SR) .....	814
25.6.2	Data register (USART_DR) .....	816
25.6.3	Baud rate register (USART_BRR) .....	817
25.6.4	Control register 1 (USART_CR1) .....	817
25.6.5	Control register 2 (USART_CR2) .....	819
25.6.6	Control register 3 (USART_CR3) .....	821
25.6.7	Guard time and prescaler register (USART_GTPR) .....	822
25.6.8	USART register map .....	824
26	Serial peripheral interface/ inter-IC sound (SPI/I2S) .....	825
26.1	Introduction .....	825
26.1.1	SPI main features .....	825
26.1.2	SPI extended features .....	826
26.1.3	I2S features .....	826
26.2	SPI/I2S implementation .....	826
26.3	SPI functional description .....	827
26.3.1	General description .....	827
26.3.2	Communications between one master and one slave .....	828
26.3.3	Standard multislave communication .....	830
26.3.4	Multimaster communication .....	831
26.3.5	Slave select (NSS) pin management .....	832
26.3.6	Communication formats .....	834
26.3.7	SPI configuration .....	836
26.3.8	Procedure for enabling SPI .....	836
26.3.9	Data transmission and reception procedures .....	837
26.3.10	Procedure for disabling the SPI .....	839
26.3.11	Communication using DMA (direct memory addressing) .....	840
26.3.12	SPI status flags .....	842
26.3.13	SPI error flags .....	843
26.4	SPI special features .....	844
26.4.1	TI mode .....	844
26.4.2	CRC calculation .....	845
26.5	SPI interrupts .....	847

26.6	I ²S functional description . . . . .	848
26.6.1	I ²S general description . . . . .	848
26.6.2	I ²S full-duplex . . . . .	849
26.6.3	Supported audio protocols . . . . .	850
26.6.4	Clock generator . . . . .	857
26.6.5	I ²S master mode . . . . .	859
26.6.6	I ²S slave mode . . . . .	861
26.6.7	I ²S status flags . . . . .	862
26.6.8	I ²S error flags . . . . .	863
26.6.9	I ²S interrupts . . . . .	864
26.6.10	DMA features . . . . .	864
26.7	SPI and I ²S registers . . . . .	865
26.7.1	SPI control register 1 (SPI_CR1) (not used in I ²S mode) . . . . .	865
26.7.2	SPI control register 2 (SPI_CR2) . . . . .	867
26.7.3	SPI status register (SPI_SR) . . . . .	868
26.7.4	SPI data register (SPI_DR) . . . . .	869
26.7.5	SPI CRC polynomial register (SPI_CRCPR) (not used in I ²S mode) . . . . .	870
26.7.6	SPI RX CRC register (SPI_RXCRCR) (not used in I ²S mode) . . . . .	870
26.7.7	SPI TX CRC register (SPI_TXCRCR) (not used in I ²S mode) . . . . .	870
26.7.8	SPI_I ²S configuration register (SPI_I2SCFGR) . . . . .	871
26.7.9	SPI_I ²S prescaler register (SPI_I2SPR) . . . . .	872
26.7.10	SPI register map . . . . .	874
27	SPDIFRX interface (SPDIFRX) . . . . .	875
27.1	SPDIFRX interface introduction . . . . .	875
27.2	SPDIFRX main features . . . . .	875
27.3	SPDIFRX functional description . . . . .	875
27.3.1	S/PDIF protocol (IEC-60958) . . . . .	876
27.3.2	SPDIFRX decoder (SPDIFRX_DC) . . . . .	879
27.3.3	SPDIFRX tolerance to clock deviation . . . . .	882
27.3.4	SPDIFRX synchronization . . . . .	882
27.3.5	SPDIFRX handling . . . . .	884
27.3.6	Data reception management . . . . .	886
27.3.7	Dedicated control flow . . . . .	888
27.3.8	Reception errors . . . . .	889
27.3.9	Clocking strategy . . . . .	891

27.3.10	DMA interface . . . . .	891
27.3.11	Interrupt generation . . . . .	892
27.3.12	Register protection . . . . .	893
27.4	Programming procedures . . . . .	894
27.4.1	Initialization phase . . . . .	894
27.4.2	Handling of interrupts coming from SPDIFRX . . . . .	895
27.4.3	Handling of interrupts coming from DMA . . . . .	895
27.5	SPDIFRX interface registers . . . . .	896
27.5.1	SPDIFRX control register (SPDIFRX_CR) . . . . .	896
27.5.2	SPDIFRX interrupt mask register (SPDIFRX_IMR) . . . . .	898
27.5.3	SPDIFRX status register (SPDIFRX_SR) . . . . .	899
27.5.4	SPDIFRX interrupt flag clear register (SPDIFRX_IFCR) . . . . .	901
27.5.5	SPDIFRX data input register (SPDIFRX_FMT0_DR) . . . . .	902
27.5.6	SPDIFRX data input register (SPDIFRX_FMT1_DR) . . . . .	902
27.5.7	SPDIFRX data input register (SPDIFRX_FMT2_DR) . . . . .	903
27.5.8	SPDIFRX channel status register (SPDIFRX_CSR) . . . . .	904
27.5.9	SPDIFRX debug information register (SPDIFRX_DIR) . . . . .	904
27.5.10	SPDIFRX interface register map . . . . .	905
28	Serial audio interface (SAI) . . . . .	906
28.1	SAI introduction . . . . .	906
28.2	SAI main features . . . . .	906
28.3	SAI functional description . . . . .	908
28.3.1	SAI block diagram . . . . .	908
28.3.2	SAI pins and internal signals . . . . .	909
28.3.3	Main SAI modes . . . . .	910
28.3.4	SAI synchronization mode . . . . .	911
28.3.5	Audio data size . . . . .	912
28.3.6	Frame synchronization . . . . .	912
28.3.7	Slot configuration . . . . .	915
28.3.8	SAI clock generator . . . . .	917
28.3.9	Internal FIFOs . . . . .	919
28.3.10	AC'97 link controller . . . . .	921
28.3.11	SPDIF output . . . . .	923
28.3.12	Specific features . . . . .	926
28.3.13	Error flags . . . . .	930
28.3.14	Disabling the SAI . . . . .	933

28.3.15	SAI DMA interface . . . . .	933
28.4	SAI interrupts . . . . .	934
28.5	SAI registers . . . . .	936
28.5.1	SAI global configuration register (SAI_GCR) . . . . .	936
28.5.2	SAI configuration register 1 (SAI_ACR1) . . . . .	936
28.5.3	SAI configuration register 2 (SAI_ACR2) . . . . .	939
28.5.4	SAI frame configuration register (SAI_AFRCR) . . . . .	941
28.5.5	SAI slot register (SAI_ASLOTR) . . . . .	942
28.5.6	SAI interrupt mask register (SAI_AIM) . . . . .	943
28.5.7	SAI status register (SAI_ASR) . . . . .	944
28.5.8	SAI clear flag register (SAI_ACLRFR) . . . . .	946
28.5.9	SAI data register (SAI_ADR) . . . . .	947
28.5.10	SAI configuration register 1 (SAI_BCR1) . . . . .	948
28.5.11	SAI configuration register 2 (SAI_BCR2) . . . . .	950
28.5.12	SAI frame configuration register (SAI_BFRCR) . . . . .	952
28.5.13	SAI slot register (SAI_BSLOTR) . . . . .	953
28.5.14	SAI interrupt mask register (SAI_BIM) . . . . .	954
28.5.15	SAI status register (SAI_BSR) . . . . .	955
28.5.16	SAI clear flag register (SAI_BCLRFR) . . . . .	957
28.5.17	SAI data register (SAI_BDR) . . . . .	958
28.5.18	SAI register map . . . . .	959
29	Secure digital input/output interface (SDIO) . . . . .	960
29.1	SDIO main features . . . . .	960
29.2	SDIO bus topology . . . . .	960
29.3	SDIO functional description . . . . .	962
29.3.1	SDIO adapter . . . . .	964
29.3.2	SDIO APB2 interface . . . . .	975
29.4	Card functional description . . . . .	976
29.4.1	Card identification mode . . . . .	976
29.4.2	Card reset . . . . .	977
29.4.3	Operating voltage range validation . . . . .	977
29.4.4	Card identification process . . . . .	977
29.4.5	Block write . . . . .	978
29.4.6	Block read . . . . .	979
29.4.7	Stream access, stream write and stream read (MultiMediaCard only) . . . . .	979

29.4.8	Erase: group erase and sector erase .....	981
29.4.9	Wide bus selection or deselection .....	981
29.4.10	Protection management .....	981
29.4.11	Card status register .....	985
29.4.12	SD status register .....	988
29.4.13	SD I/O mode .....	992
29.4.14	Commands and responses .....	993
29.5	Response formats .....	996
29.5.1	R1 (normal response command) .....	997
29.5.2	R1b .....	997
29.5.3	R2 (CID, CSD register) .....	997
29.5.4	R3 (OCR register) .....	998
29.5.5	R4 (Fast I/O) .....	998
29.5.6	R4b .....	998
29.5.7	R5 (interrupt request) .....	999
29.5.8	R6 .....	999
29.6	SDIO I/O card-specific operations .....	1000
29.6.1	SDIO I/O read wait operation by SDIO_D2 signalling .....	1000
29.6.2	SDIO read wait operation by stopping SDIO_CK .....	1001
29.6.3	SDIO suspend/resume operation .....	1001
29.6.4	SDIO interrupts .....	1001
29.7	HW flow control .....	1001
29.8	SDIO registers .....	1002
29.8.1	SDIO power control register (SDIO_POWER) .....	1002
29.8.2	SDIO clock control register (SDIO_CLKCR) .....	1002
29.8.3	SDIO argument register (SDIO_ARG) .....	1004
29.8.4	SDIO command register (SDIO_CMD) .....	1004
29.8.5	SDIO command response register (SDIO_RESPCMD) .....	1005
29.8.6	SDIO response 1..4 register (SDIO_RESPx) .....	1005
29.8.7	SDIO data timer register (SDIO_DTIMER) .....	1006
29.8.8	SDIO data length register (SDIO_DLEN) .....	1007
29.8.9	SDIO data control register (SDIO_DCTRL) .....	1007
29.8.10	SDIO data counter register (SDIO_DCOUNT) .....	1009
29.8.11	SDIO status register (SDIO_STA) .....	1009
29.8.12	SDIO interrupt clear register (SDIO_ICR) .....	1010
29.8.13	SDIO mask register (SDIO_MASK) .....	1012
29.8.14	SDIO FIFO counter register (SDIO_FIFOCNT) .....	1014

- 29.8.15 SDIO data FIFO register (SDIO_FIFO) . . . . . 1015
- 29.8.16 SDIO register map . . . . . 1016
30 Controller area network (bxCAN) . . . . . 1018
- 30.1 Introduction . . . . . 1018
- 30.2 bxCAN main features . . . . . 1018
- 30.3 bxCAN general description . . . . . 1019
  - 30.3.1 CAN 2.0B active core . . . . . 1019
  - 30.3.2 Control, status, and configuration registers . . . . . 1019
  - 30.3.3 Tx mailboxes . . . . . 1019
  - 30.3.4 Acceptance filters . . . . . 1020
- 30.4 bxCAN operating modes . . . . . 1021
  - 30.4.1 Initialization mode . . . . . 1021
  - 30.4.2 Normal mode . . . . . 1021
  - 30.4.3 Sleep mode (low-power) . . . . . 1022
- 30.5 Test mode . . . . . 1023
  - 30.5.1 Silent mode . . . . . 1023
  - 30.5.2 Loop back mode . . . . . 1023
  - 30.5.3 Loop back combined with silent mode . . . . . 1024
- 30.6 Behavior in debug mode . . . . . 1024
- 30.7 bxCAN functional description . . . . . 1024
  - 30.7.1 Transmission handling . . . . . 1024
  - 30.7.2 Time triggered communication mode . . . . . 1026
  - 30.7.3 Reception handling . . . . . 1026
  - 30.7.4 Identifier filtering . . . . . 1028
  - 30.7.5 Message storage . . . . . 1032
  - 30.7.6 Error management . . . . . 1033
  - 30.7.7 Bit timing . . . . . 1033
- 30.8 bxCAN interrupts . . . . . 1037
- 30.9 CAN registers . . . . . 1038
  - 30.9.1 Register access protection . . . . . 1038
  - 30.9.2 CAN control and status registers . . . . . 1038
  - 30.9.3 CAN mailbox registers . . . . . 1048
  - 30.9.4 CAN filter registers . . . . . 1054
  - 30.9.5 bxCAN register map . . . . . 1058

31	USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS) . . . . .	1062
31.1	Introduction . . . . .	1062
31.2	OTG_FS/OTG_HS main features . . . . .	1064
31.2.1	General features . . . . .	1064
31.2.2	Host-mode features . . . . .	1065
31.2.3	Peripheral-mode features . . . . .	1065
31.3	OTG_FS/OTG_HS implementation . . . . .	1066
31.4	OTG_FS/OTG_HS functional description . . . . .	1067
31.4.1	OTG_FS/OTG_HS block diagram . . . . .	1067
31.4.2	OTG_FS/OTG_HS pin and internal signals . . . . .	1068
31.4.3	OTG_FS/OTG_HS core . . . . .	1069
31.4.4	Embedded full-speed OTG PHY connected to OTG_FS . . . . .	1069
31.4.5	Embedded full-speed OTG PHY connected to OTG_HS . . . . .	1070
31.4.6	OTG detections . . . . .	1070
31.4.7	High-speed OTG PHY connected to OTG_HS . . . . .	1070
31.5	OTG_FS/OTG_HS dual role device (DRD) . . . . .	1071
31.5.1	ID line detection . . . . .	1071
31.5.2	HNP dual role device . . . . .	1071
31.5.3	SRP dual role device . . . . .	1072
31.6	OTG_FS/OTG_HS as a USB peripheral . . . . .	1072
31.6.1	SRP-capable peripheral . . . . .	1073
31.6.2	Peripheral states . . . . .	1073
31.6.3	Peripheral endpoints . . . . .	1074
31.7	OTG_FS/OTG_HS as a USB host . . . . .	1076
31.7.1	SRP-capable host . . . . .	1077
31.7.2	USB host states . . . . .	1077
31.7.3	Host channels . . . . .	1079
31.7.4	Host scheduler . . . . .	1080
31.8	OTG_FS/OTG_HS SOF trigger . . . . .	1081
31.8.1	Host SOFs . . . . .	1081
31.8.2	Peripheral SOFs . . . . .	1081
31.9	OTG_FS/OTG_HS low-power modes . . . . .	1082
31.10	OTG_FS/OTG_HS dynamic update of the OTG_HFIR register . . . . .	1083
31.11	OTG_FS/OTG_HS data FIFOs . . . . .	1083
31.11.1	FIFO allocation for DMA address register storage . . . . .	1084

31.11.2	Peripheral FIFO architecture . . . . .	1085
31.11.3	Host FIFO architecture . . . . .	1087
31.11.4	FIFO RAM allocation . . . . .	1089
31.12	OTG_FS system performance . . . . .	1091
31.13	OTG_FS/ OTG_HS interrupts . . . . .	1091
31.14	OTG_FS/ OTG_HS control and status registers . . . . .	1093
31.14.1	CSR memory map . . . . .	1093
31.15	OTG_FS/ OTG_HS registers . . . . .	1099
31.15.1	OTG control and status register (OTG_GOTGCTL) . . . . .	1099
31.15.2	OTG interrupt register (OTG_GOTGINT) . . . . .	1102
31.15.3	OTG AHB configuration register (OTG_GAHBCFG) . . . . .	1103
31.15.4	OTG USB configuration register (OTG_GUSBCFG) . . . . .	1105
31.15.5	OTG reset register (OTG_GRSTCTL) . . . . .	1108
31.15.6	OTG core interrupt register (OTG_GINTSTS) . . . . .	1111
31.15.7	OTG interrupt mask register (OTG_GINTMSK) . . . . .	1116
31.15.8	OTG receive status debug read register (OTG_GRXSTSR) . . . . .	1119
31.15.9	OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . .	1120
31.15.10	OTG status read and pop registers (OTG_GRXSTSP) . . . . .	1121
31.15.11	OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . . . .	1122
31.15.12	OTG receive FIFO size register (OTG_GRXFSIZ) . . . . .	1123
31.15.13	OTG host nonperiodic transmit FIFO size register (OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size (OTG_DIEPTXF0) . . . . .	1124
31.15.14	OTG nonperiodic transmit FIFO/queue status register (OTG_HNPTXSTS) . . . . .	1125
31.15.15	OTG general core configuration register (OTG_GCCFG) . . . . .	1126
31.15.16	OTG core ID register (OTG_CID) . . . . .	1126
31.15.17	OTG core LPM configuration register (OTG_GLPMCFG) . . . . .	1127
31.15.18	OTG interrupt register (OTG_GDFIFOFCFG) . . . . .	1131
31.15.19	OTG host periodic transmit FIFO size register (OTG_HPTXFSIZ) . . . . .	1131
31.15.20	OTG device IN endpoint transmit FIFO x size register (OTG_DIEPTXFx) . . . . .	1132
31.15.21	Host-mode registers . . . . .	1132
31.15.22	OTG host configuration register (OTG_HCFG) . . . . .	1133
31.15.23	OTG host frame interval register (OTG_HFIR) . . . . .	1133
31.15.24	OTG host frame number/frame time remaining register (OTG_HFNUM) . . . . .	1134

31.15.25	OTG_Host periodic transmit FIFO/queue status register (OTG_HPTXSTS)	1135
31.15.26	OTG host all channels interrupt register (OTG_HAINT)	1136
31.15.27	OTG host all channels interrupt mask register (OTG_HAINTMSK)	1137
31.15.28	OTG host port control and status register (OTG_HPRT)	1137
31.15.29	OTG host channel x characteristics register (OTG_HCCHARx)	1140
31.15.30	OTG host channel x split control register (OTG_HCSPLTx)	1141
31.15.31	OTG host channel x interrupt register (OTG_HCINTx)	1142
31.15.32	OTG host channel x interrupt mask register (OTG_HCINTMSKx)	1143
31.15.33	OTG host channel x transfer size register (OTG_HCTSIZx)	1145
31.15.34	OTG host channel x DMA address register (OTG_HCDMAx)	1146
31.15.35	Device-mode registers	1146
31.15.36	OTG device configuration register (OTG_DCFG)	1146
31.15.37	OTG device control register (OTG_DCTL)	1148
31.15.38	OTG device status register (OTG_DSTS)	1151
31.15.39	OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK)	1152
31.15.40	OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK)	1153
31.15.41	OTG device all endpoints interrupt register (OTG_DAINT)	1155
31.15.42	OTG all endpoints interrupt mask register (OTG_DaintMSK)	1155
31.15.43	OTG device V _BUSdischarge time register (OTG_DVBUSDIS)	1156
31.15.44	OTG device V _BUSpulsing time register (OTG_DVBUSPULSE)	1156
31.15.45	OTG device threshold control register (OTG_DTHRCTL)	1157
31.15.46	OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK)	1158
31.15.47	OTG device each endpoint interrupt register (OTG_DEACHINT)	1159
31.15.48	OTG device each endpoint interrupt mask register (OTG_DEACHINTMSK)	1159
31.15.49	OTG device each IN endpoint-1 interrupt mask register (OTG_HS_DIEPEACHMSK1)	1160
31.15.50	OTG device each OUT endpoint-1 interrupt mask register (OTG_HS_DOEPEACHMSK1)	1161
31.15.51	OTG device control IN endpoint 0 control register (OTG_DIEPCTL0)	1162
31.15.52	OTG device IN endpoint x control register (OTG_DIEPCTLx)	1164
31.15.53	OTG device IN endpoint x interrupt register (OTG_DIEPINTx)	1166

31.15.54	OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0) .....	1168
31.15.55	OTG device IN endpoint x DMA address register (OTG_DIEPDMAx) .....	1169
31.15.56	OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) .....	1169
31.15.57	OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) .....	1170
31.15.58	OTG device control OUT endpoint 0 control register (OTG_DOEPCTL0) .....	1171
31.15.59	OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) .....	1172
31.15.60	OTG device OUT endpoint 0 transfer size register (OTG_DOEPTSIZ0) .....	1174
31.15.61	OTG device OUT endpoint x DMA address register (OTG_DOEPDMAx) .....	1175
31.15.62	OTG device OUT endpoint x control register (OTG_DOEPCTLx) .....	1176
31.15.63	OTG device OUT endpoint x transfer size register (OTG_DOEPTSIZx) .....	1178
31.15.64	OTG power and clock gating control register (OTG_PCGCCTL) .....	1179
31.15.65	OTG_FS/OTG_HS register map .....	1180
31.16	OTG_FS/OTG_HS programming model .....	1193
31.16.1	Core initialization .....	1193
31.16.2	Host initialization .....	1194
31.16.3	Device initialization .....	1195
31.16.4	DMA mode .....	1195
31.16.5	Host programming model .....	1195
31.16.6	Device programming model .....	1229
31.16.7	Worst case response time .....	1250
31.16.8	OTG programming model .....	1252
32	HDMI-CEC controller (CEC) .....	1259
32.1	HDMI-CEC introduction .....	1259
32.2	HDMI-CEC controller main features .....	1259
32.3	HDMI-CEC functional description .....	1260
32.3.1	HDMI-CEC pin .....	1260
32.3.2	HDMI-CEC block diagram .....	1260
32.3.3	Message description .....	1260
32.3.4	Bit timing .....	1261
32.4	Arbitration .....	1262

32.4.1	SFT option bit .....	1263
32.5	Error handling .....	1264
32.5.1	Bit error .....	1264
32.5.2	Message error .....	1264
32.5.3	Bit rising error (BRE) .....	1264
32.5.4	Short bit period error (SBPE) .....	1265
32.5.5	Long bit period error (LBPE) .....	1265
32.5.6	Transmission error detection (TXERR) .....	1266
32.6	HDMI-CEC interrupts .....	1268
32.7	HDMI-CEC registers .....	1269
32.7.1	CEC control register (CEC_CR) .....	1269
32.7.2	CEC configuration register (CEC_CFGR) .....	1270
32.7.3	CEC Tx data register (CEC_TXDR) .....	1272
32.7.4	CEC Rx data register (CEC_RXDR) .....	1272
32.7.5	CEC interrupt and status register (CEC_ISR) .....	1272
32.7.6	CEC interrupt enable register (CEC_IER) .....	1274
32.7.7	HDMI-CEC register map .....	1276
33	Debug support (DBG) .....	1277
33.1	Overview .....	1277
33.2	Reference Arm® documentation .....	1278
33.3	SWJ debug port (serial wire and JTAG) .....	1278
33.3.1	Mechanism to select the JTAG-DP or the SW-DP .....	1279
33.4	Pinout and debug port pins .....	1279
33.4.1	SWJ debug port pins .....	1280
33.4.2	Flexible SWJ-DP pin assignment .....	1280
33.4.3	Internal pull-up and pull-down on JTAG pins .....	1280
33.4.4	Using serial wire and releasing the unused debug pins as GPIOs ..	1281
33.5	STM32F446xx JTAG TAP connection .....	1281
33.6	ID codes and locking mechanism .....	1283
33.6.1	MCU device ID code .....	1283
33.6.2	Boundary scan TAP .....	1283
33.6.3	Cortex®-M4 with FPU TAP .....	1283
33.6.4	Cortex®-M4 with FPU JEDEC-106 ID code .....	1284
33.7	JTAG debug port .....	1284
33.8	SW debug port .....	1286

33.8.1	SW protocol introduction . . . . .	1286
33.8.2	SW protocol sequence . . . . .	1286
33.8.3	SW-DP state machine (reset, idle states, ID code) . . . . .	1287
33.8.4	DP and AP read/write accesses . . . . .	1288
33.8.5	SW-DP registers . . . . .	1288
33.8.6	SW-AP registers . . . . .	1289
33.9	AHB-AP (AHB access port), valid for JTAG-DP and SW-DP . . . . .	1290
33.10	Core debug . . . . .	1291
33.11	Capability of the debugger host to connect under system reset . . . . .	1292
33.12	FPB (Flash patch breakpoint) . . . . .	1292
33.13	DWT (data watchpoint trigger) . . . . .	1293
33.14	ITM (instrumentation trace macrocell) . . . . .	1293
33.14.1	General description . . . . .	1293
33.14.2	Time stamp packets, synchronization and overflow packets . . . . .	1293
33.15	ETM (Embedded trace macrocell) . . . . .	1295
33.15.1	General description . . . . .	1295
33.15.2	Signal protocol, packet types . . . . .	1295
33.15.3	Main ETM registers . . . . .	1296
33.15.4	Configuration example . . . . .	1296
33.16	MCU debug component (DBGMCU) . . . . .	1296
33.16.1	Debug support for low-power modes . . . . .	1297
33.16.2	Debug support for timers, watchdog, bxCAN and I ²C . . . . .	1297
33.16.3	Debug MCU configuration register . . . . .	1297
33.16.4	Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . .	1299
33.16.5	Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ) . . . . .	1301
33.17	TPIU (trace port interface unit) . . . . .	1302
33.17.1	Introduction . . . . .	1302
33.17.2	TRACE pin assignment . . . . .	1302
33.17.3	TPUI formatter . . . . .	1304
33.17.4	TPUI frame synchronization packets . . . . .	1305
33.17.5	Transmission of the synchronization frame packet . . . . .	1305
33.17.6	Synchronous mode . . . . .	1305
33.17.7	Asynchronous mode . . . . .	1306
33.17.8	TRACECLKIN connection in STM32F446xx . . . . .	1306
33.17.9	TPIU registers . . . . .	1306
33.17.10	Example of configuration . . . . .	1307

33.18 DBG register map . . . . . 1308
34 Device electronic signature . . . . . 1309
- 34.1 Unique device ID register (96 bits) . . . . . 1309
- 34.2 Flash memory size register . . . . . 1310
- 34.3 Package data register . . . . . 1310
35 Important security notice . . . . . 1312
36 Revision history . . . . . 1313

List of tables

Table 1.	STM32F446xx register boundary addresses . . . . .	57
Table 2.	Boot modes . . . . .	61
Table 3.	Memory mapping vs. Boot mode/physical remap in STM32F446xx. . . . .	62
Table 4.	Flash memory module organization . . . . .	65
Table 5.	Number of wait states according to CPU clock (HCLK) frequency. . . . .	66
Table 6.	Program/erase parallelism . . . . .	70
Table 7.	Flash interrupt request . . . . .	72
Table 8.	Option byte organization. . . . .	72
Table 9.	Description of the option bytes . . . . .	73
Table 10.	Access versus read protection level . . . . .	75
Table 11.	OTP area organization . . . . .	79
Table 12.	Flash register map and reset value . . . . .	87
Table 13.	CRC calculation unit register map and reset values. . . . .	91
Table 14.	Voltage regulator configuration mode versus device operating mode . . . . .	96
Table 15.	Low-power mode summary . . . . .	101
Table 16.	Sleep-now entry and exit . . . . .	103
Table 17.	Stop operating modes. . . . .	104
Table 18.	Stop mode entry and exit for STM32F446xx . . . . .	106
Table 19.	Standby mode entry and exit . . . . .	107
Table 20.	PWR - register map and reset values. . . . .	115
Table 21.	RCC register map and reset values . . . . .	170
Table 22.	Port bit configuration table . . . . .	175
Table 23.	Flexible SWJ-DP pin assignment . . . . .	177
Table 24.	RTC_AF1 pin . . . . .	184
Table 25.	RTC_AF2 pin . . . . .	184
Table 26.	GPIO register map and reset values . . . . .	191
Table 27.	SYSCFG register map and reset values. . . . .	199
Table 28.	DMA1 request mapping . . . . .	204
Table 29.	DMA2 request mapping . . . . .	204
Table 30.	Source and destination address . . . . .	205
Table 31.	Source and destination address registers in double-buffer mode (DBM = 1). . . . .	211
Table 32.	Packing/unpacking and endian behavior (bit PINC = MINC = 1) . . . . .	212
Table 33.	Restriction on NDT versus PSIZE and MSIZE . . . . .	212
Table 34.	FIFO threshold configurations . . . . .	215
Table 35.	Possible DMA configurations . . . . .	219
Table 36.	DMA interrupt requests. . . . .	221
Table 37.	DMA register map and reset values . . . . .	231
Table 38.	Vector table for STM32F446xx . . . . .	235
Table 39.	External interrupt/event controller register map and reset values. . . . .	246
Table 40.	NOR/PSRAM bank selection . . . . .	251
Table 41.	NOR/PSRAM External memory address . . . . .	252
Table 42.	NAND memory mapping and timing registers. . . . .	252
Table 43.	NAND bank selection . . . . .	252
Table 44.	SDRAM bank selection. . . . .	253
Table 45.	SDRAM address mapping . . . . .	253
Table 46.	SDRAM address mapping with 8-bit data bus width. . . . .	254
Table 47.	SDRAM address mapping with 16-bit data bus width. . . . .	254
Table 48.	Programmable NOR/PSRAM access parameters . . . . .	256

Table 49.	Non-multiplexed I/O NOR flash memory. . . . .	257
Table 50.	16-bit multiplexed I/O NOR flash memory . . . . .	257
Table 51.	Non-multiplexed I/Os PSRAM/SRAM . . . . .	258
Table 52.	16-Bit multiplexed I/O PSRAM . . . . .	258
Table 53.	NOR flash/PSRAM: example of supported memories and transactions . . . . .	259
Table 54.	FMC_BCRx bitfields (mode 1) . . . . .	262
Table 55.	FMC_BTRx bitfields (mode 1) . . . . .	262
Table 56.	FMC_BCRx bitfields (mode A) . . . . .	264
Table 57.	FMC_BTRx bitfields (mode A) . . . . .	264
Table 58.	FMC_BWTRx bitfields (mode A) . . . . .	265
Table 59.	FMC_BCRx bitfields (mode 2/B) . . . . .	267
Table 60.	FMC_BTRx bitfields (mode 2/B) . . . . .	267
Table 61.	FMC_BWTRx bitfields (mode 2/B) . . . . .	268
Table 62.	FMC_BCRx bitfields (mode C) . . . . .	269
Table 63.	FMC_BTRx bitfields (mode C) . . . . .	270
Table 64.	FMC_BWTRx bitfields (mode C) . . . . .	270
Table 65.	FMC_BCRx bitfields (mode D) . . . . .	272
Table 66.	FMC_BTRx bitfields (mode D) . . . . .	272
Table 67.	FMC_BWTRx bitfields (mode D) . . . . .	273
Table 68.	FMC_BCRx bitfields (Muxed mode) . . . . .	274
Table 69.	FMC_BTRx bitfields (Muxed mode) . . . . .	275
Table 70.	FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .	280
Table 71.	FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .	281
Table 72.	FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .	282
Table 73.	FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .	283
Table 74.	Programmable NAND flash access parameters . . . . .	291
Table 75.	8-bit NAND flash . . . . .	291
Table 76.	16-bit NAND flash . . . . .	292
Table 77.	Supported memories and transactions . . . . .	292
Table 78.	ECC result relevant bits . . . . .	301
Table 79.	SDRAM signals . . . . .	302
Table 80.	FMC register map and reset values . . . . .	318
Table 81.	QUADSPI pins . . . . .	322
Table 82.	QUADSPI interrupt requests . . . . .	336
Table 83.	QUADSPI register map and reset values . . . . .	348
Table 84.	ADC pins . . . . .	351
Table 85.	Analog watchdog channel selection . . . . .	357
Table 86.	Configuring the trigger polarity . . . . .	362
Table 87.	External trigger for regular channels . . . . .	362
Table 88.	External trigger for injected channels . . . . .	363
Table 89.	ADC interrupts . . . . .	377
Table 90.	ADC global register map . . . . .	392
Table 91.	ADC register map and reset values for each ADC . . . . .	392
Table 92.	ADC register map and reset values (common ADC registers) . . . . .	394
Table 93.	DAC pins . . . . .	396
Table 94.	External triggers . . . . .	399
Table 95.	DAC register map . . . . .	416
Table 96.	DCMI input/output pins . . . . .	418
Table 97.	Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .	420
Table 98.	Positioning of captured data bytes in 32-bit words (10-bit width) . . . . .	420
Table 99.	Positioning of captured data bytes in 32-bit words (12-bit width) . . . . .	420

Table 100.	Positioning of captured data bytes in 32-bit words (14-bit width) . . . . .	421
Table 101.	Data storage in monochrome progressive video format . . . . .	426
Table 102.	Data storage in RGB progressive video format . . . . .	427
Table 103.	Data storage in YCbCr progressive video format . . . . .	427
Table 104.	Data storage in YCbCr progressive video format - Y extraction mode . . . . .	427
Table 105.	DCMI interrupts . . . . .	428
Table 106.	DCMI register map and reset values . . . . .	438
Table 107.	Counting direction versus encoder signals . . . . .	476
Table 108.	TIMx Internal trigger connection . . . . .	489
Table 109.	Output control bits for complementary OCx and OCxN channels with break feature . . . . .	501
Table 110.	TIM1&TIM8 register map and reset values . . . . .	508
Table 111.	Counting direction versus encoder signals . . . . .	537
Table 112.	TIMx internal trigger connections . . . . .	552
Table 113.	Output control bit for standard OCx channels . . . . .	562
Table 114.	TIM2 to TIM5 register map and reset values . . . . .	569
Table 115.	TIMx internal trigger connections . . . . .	595
Table 116.	Output control bit for standard OCx channels . . . . .	603
Table 117.	TIM9/12 register map and reset values . . . . .	605
Table 118.	Output control bit for standard OCx channels . . . . .	613
Table 119.	TIM10/11/13/14 register map and reset values . . . . .	616
Table 120.	TIM6&TIM7 register map and reset values . . . . .	629
Table 121.	Min/max IWDG timeout periods (ms) at 32 kHz (LSI) . . . . .	631
Table 122.	IWDG register map and reset values . . . . .	635
Table 123.	WWDG register map and reset values . . . . .	642
Table 124.	Effect of low power modes on RTC . . . . .	658
Table 125.	Interrupt control bits . . . . .	659
Table 126.	RTC register map and reset values . . . . .	679
Table 127.	FMPI2C implementation . . . . .	682
Table 128.	FMPI2C input/output pins . . . . .	683
Table 129.	FMPI2C internal input/output signals . . . . .	683
Table 130.	Comparison of analog and digital filters . . . . .	686
Table 131.	I ²C-bus and SMBus specification data setup and hold times . . . . .	688
Table 132.	FMPI2C configuration . . . . .	692
Table 133.	I ²C-bus and SMBus specification clock timings . . . . .	703
Table 134.	Timing settings for f _I2CCLKof 8 MHz . . . . .	713
Table 135.	Timing settings for f _I2CCLKof 16 MHz . . . . .	713
Table 136.	SMBus timeout specifications . . . . .	715
Table 137.	SMBus with PEC configuration . . . . .	717
Table 138.	TIMEOUTA[11:0] for maximum t _TIMEOUTof 25 ms . . . . .	718
Table 139.	TIMEOUTB[11:0] for maximum t _LOW:SEXTand t _LOW:MEXTof 8 ms . . . . .	718
Table 140.	TIMEOUTA[11:0] for maximum t _IDLEof 50 µs . . . . .	718
Table 141.	Effect of low-power modes to FMPI2C . . . . .	727
Table 142.	FMPI2C interrupt requests . . . . .	727
Table 143.	FMPI2C register map and reset values . . . . .	743
Table 144.	Maximum DNF[3:0] value to be compliant with Thd:dat(max) . . . . .	755
Table 145.	SMBus vs. I ²C . . . . .	756
Table 146.	I ²C interrupt requests . . . . .	760
Table 147.	I ²C register map and reset values . . . . .	773
Table 148.	USART features . . . . .	776
Table 149.	Noise detection from sampled data . . . . .	786
Table 150.	Error calculation for programmed baud rates at f _PCLK= 8 MHz or f _PCLK= 12 MHz,

oversampling by 16. . . . .	789
Table 151. Error calculation for programmed baud rates at $f_{PCLK} = 8$ MHz or $f_{PCLK} = 12$ MHz, oversampling by 8. . . . .	790
Table 152. Error calculation for programmed baud rates at $f_{PCLK} = 16$ MHz or $f_{PCLK} = 24$ MHz, oversampling by 16. . . . .	790
Table 153. Error calculation for programmed baud rates at $f_{PCLK} = 16$ MHz or $f_{PCLK} = 24$ MHz, oversampling by 8. . . . .	791
Table 154. Error calculation for programmed baud rates at $f_{PCLK} = 8$ MHz or $f_{PCLK} = 16$ MHz, oversampling by 16. . . . .	792
Table 155. Error calculation for programmed baud rates at $f_{PCLK} = 8$ MHz or $f_{PCLK} = 16$ MHz, oversampling by 8. . . . .	792
Table 156. Error calculation for programmed baud rates at $f_{PCLK} = 30$ MHz or $f_{PCLK} = 60$ MHz, oversampling by 16. . . . .	793
Table 157. Error calculation for programmed baud rates at $f_{PCLK} = 30$ MHz or $f_{PCLK} = 60$ MHz, oversampling by 8 . . . . .	793
Table 158. Error calculation for programmed baud rates at $f_{PCLK} = 42$ MHz or $f_{PCLK} = 84$ Hz, oversampling by 16. . . . .	794
Table 159. Error calculation for programmed baud rates at $f_{PCLK} = 42$ MHz or $f_{PCLK} = 84$ MHz, oversampling by 8. . . . .	795
Table 160. USART receiver tolerance when DIV fraction is 0 . . . . .	797
Table 161. USART receiver tolerance when DIV_Fraction is different from 0 . . . . .	797
Table 162. Frame formats . . . . .	799
Table 163. USART interrupt requests. . . . .	813
Table 164. USART register map and reset values . . . . .	824
Table 165. STM32F446xx SPI implementation . . . . .	826
Table 166. SPI interrupt requests. . . . .	847
Table 167. Audio-frequency precision using standard 8 MHz HSE . . . . .	858
Table 168. I ²S interrupt requests . . . . .	864
Table 169. SPI register map and reset values . . . . .	874
Table 170. Transition sequence for preamble . . . . .	881
Table 171. Minimum SPDIFRX_CLK frequency versus audio sampling rate. . . . .	891
Table 172. Bit field property versus SPDIFRX state. . . . .	893
Table 173. SPDIFRX interface register map and reset values . . . . .	905
Table 174. SAI internal input/output signals . . . . .	909
Table 175. SAI input/output pins. . . . .	909
Table 176. External synchronization selection . . . . .	912
Table 177. Example of possible audio frequency sampling range . . . . .	918
Table 178. SOPD pattern . . . . .	924
Table 179. Parity bit calculation . . . . .	924
Table 180. Audio sampling frequency versus symbol rates . . . . .	925
Table 181. SAI interrupt sources . . . . .	934
Table 182. SAI register map and reset values . . . . .	959
Table 183. SDIO I/O definitions . . . . .	963
Table 184. Command format . . . . .	968
Table 185. Short response format . . . . .	969
Table 186. Long response format. . . . .	969
Table 187. Command path status flags . . . . .	969
Table 188. Data token format. . . . .	972
Table 189. DPSM flags. . . . .	973
Table 190. Transmit FIFO status flags . . . . .	974
Table 191. Receive FIFO status flags . . . . .	974
Table 192. Card status . . . . .	985

Table 193.	SD status . . . . .	988
Table 194.	Speed class code field . . . . .	989
Table 195.	Performance move field . . . . .	990
Table 196.	AU_SIZE field . . . . .	990
Table 197.	Maximum AU size . . . . .	990
Table 198.	Erase size field . . . . .	991
Table 199.	Erase timeout field . . . . .	991
Table 200.	Erase offset field . . . . .	991
Table 201.	Block-oriented write commands . . . . .	994
Table 202.	Block-oriented write protection commands . . . . .	995
Table 203.	Erase commands . . . . .	995
Table 204.	I/O mode commands . . . . .	995
Table 205.	Lock card . . . . .	996
Table 206.	Application-specific commands . . . . .	996
Table 207.	R1 response . . . . .	997
Table 208.	R2 response . . . . .	997
Table 209.	R3 response . . . . .	998
Table 210.	R4 response . . . . .	998
Table 211.	R4b response . . . . .	998
Table 212.	R5 response . . . . .	999
Table 213.	R6 response . . . . .	1000
Table 214.	Response type and SDIO_RESPx registers . . . . .	1006
Table 215.	SDIO register map . . . . .	1016
Table 216.	Transmit mailbox mapping . . . . .	1032
Table 217.	Receive mailbox mapping . . . . .	1032
Table 218.	bxCAN register map and reset values . . . . .	1058
Table 219.	OTG_HS speeds supported . . . . .	1063
Table 220.	OTG_FS speeds supported . . . . .	1063
Table 221.	OTG_FS/OTG_HS implementation . . . . .	1066
Table 222.	OTG_FS input/output pins . . . . .	1068
Table 223.	OTG_HS input/output pins . . . . .	1068
Table 224.	OTG_FS/OTG_HS input/output signals . . . . .	1069
Table 225.	Compatibility of STM32 low power modes with the OTG . . . . .	1082
Table 226.	FIFO allocation for DMA address register storage (OTG_DIEPDMAX/DOEPDMAX and OTG_HCDMAX) . . . . .	1084
Table 227.	Core global control and status registers (CSRs) . . . . .	1093
Table 228.	Host-mode control and status registers (CSRs) . . . . .	1094
Table 229.	Device-mode control and status registers . . . . .	1096
Table 230.	Data FIFO (DFIFO) access register map . . . . .	1099
Table 231.	Power and clock gating control and status registers . . . . .	1099
Table 232.	TRDT values (FS) . . . . .	1108
Table 233.	TRDT values (HS) . . . . .	1108
Table 234.	Minimum duration for soft disconnect . . . . .	1150
Table 235.	OTG_FS/OTG_HS register map and reset values . . . . .	1180
Table 236.	HDMI pin . . . . .	1260
Table 237.	Error handling timing parameters . . . . .	1266
Table 238.	TXERR timing parameters . . . . .	1267
Table 239.	HDMI-CEC interrupts . . . . .	1268
Table 240.	HDMI-CEC register map and reset values . . . . .	1276
Table 241.	SWJ debug port pins . . . . .	1280
Table 242.	Flexible SWJ-DP pin assignment . . . . .	1280
Table 243.	JTAG debug port data registers . . . . .	1284

Table 244.	32-bit debug port registers addressed through the shifted value A[3:2] . . . . .	1286
Table 245.	Packet request (8-bits) . . . . .	1287
Table 246.	ACK response (3 bits). . . . .	1287
Table 247.	DATA transfer (33 bits). . . . .	1287
Table 248.	SW-DP registers . . . . .	1288
Table 249.	Cortex ^®-M4 with FPU AHB-AP registers . . . . .	1290
Table 250.	Core debug registers . . . . .	1291
Table 251.	Main ITM registers . . . . .	1294
Table 252.	Main ETM registers. . . . .	1296
Table 253.	Asynchronous TRACE pin assignment. . . . .	1302
Table 254.	Synchronous TRACE pin assignment . . . . .	1303
Table 255.	Flexible TRACE pin assignment. . . . .	1303
Table 256.	Important TPIU registers. . . . .	1306
Table 257.	DBG register map and reset values . . . . .	1308
Table 258.	Document revision history . . . . .	1313

List of figures

Figure 1. System architecture for STM32F446xx devices . . . . . 54

Figure 2. Memory map . . . . . 57

Figure 3. Flash memory interface connection inside system architecture . . . . . 64

Figure 4. Sequential 32-bit instruction execution . . . . . 68

Figure 5. RDP levels . . . . . 77

Figure 6. PCROP levels . . . . . 79

Figure 7. CRC calculation unit block diagram . . . . . 88

Figure 8. Power supply overview for STM32F446xx . . . . . 92

Figure 9. Backup domain . . . . . 95

Figure 10. Power-on reset/power-down reset waveform . . . . . 98

Figure 11. BOR thresholds . . . . . 99

Figure 12. PVD thresholds . . . . . 100

Figure 13. Simplified diagram of the reset circuit . . . . . 117

Figure 14. Clock tree . . . . . 118

Figure 15. HSE/ LSE clock sources (hardware configuration) . . . . . 120

Figure 16. Frequency measurement with TIM5 in Input capture mode . . . . . 125

Figure 17. Frequency measurement with TIM11 in Input capture mode . . . . . 126

Figure 18. Basic structure of a 5 V tolerant I/O port bit . . . . . 175

Figure 19. Selecting an alternate function on STM32F446xx . . . . . 178

Figure 20. Input floating/pull up/pull down configurations . . . . . 180

Figure 21. Output configuration . . . . . 181

Figure 22. Alternate function configuration . . . . . 182

Figure 23. High impedance-analog configuration . . . . . 182

Figure 24. DMA block diagram . . . . . 202

Figure 25. Channel selection . . . . . 203

Figure 26. Peripheral-to-memory mode . . . . . 207

Figure 27. Memory-to-peripheral mode . . . . . 208

Figure 28. Memory-to-memory mode . . . . . 209

Figure 29. FIFO structure . . . . . 214

Figure 30. External interrupt/event controller block diagram . . . . . 240

Figure 31. External interrupt/event GPIO mapping . . . . . 242

Figure 32. FMC block diagram. . . . . 248

Figure 33. FMC memory banks . . . . . 251

Figure 34. Mode 1 read access waveforms . . . . . 261

Figure 35. Mode 1 write access waveforms . . . . . 261

Figure 36. Mode A read access waveforms . . . . . 263

Figure 37. Mode A write access waveforms . . . . . 263

Figure 38. Mode 2 and mode B read access waveforms. . . . . 265

Figure 39. Mode 2 write access waveforms. . . . . 266

Figure 40. Mode B write access waveforms . . . . . 266

Figure 41. Mode C read access waveforms . . . . . 268

Figure 42. Mode C write access waveforms . . . . . 269

Figure 43. Mode D read access waveforms . . . . . 271

Figure 44. Mode D write access waveforms . . . . . 271

Figure 45. Muxed read access waveforms . . . . . 273

Figure 46. Muxed write access waveforms . . . . . 274

Figure 47. Asynchronous wait during a read access waveforms . . . . . 276

Figure 48. Asynchronous wait during a write access waveforms. . . . . 277

Figure 49.	Wait configuration waveforms. . . . .	279
Figure 50.	Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM). . . . .	280
Figure 51.	Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . .	282
Figure 52.	NAND flash controller waveforms for common memory access. . . . .	293
Figure 53.	Access to non 'CE don't care' NAND-flash. . . . .	295
Figure 54.	Burst write SDRAM access waveforms . . . . .	304
Figure 55.	Burst read SDRAM access . . . . .	305
Figure 56.	Logic diagram of Read access with RBURST bit set (CAS=1, RPIPE=0) . . . . .	306
Figure 57.	Read access crossing row boundary . . . . .	308
Figure 58.	Write access crossing row boundary . . . . .	308
Figure 59.	Self-refresh mode . . . . .	310
Figure 60.	Power-down mode . . . . .	311
Figure 61.	QUADSPI block diagram when dual-flash mode is disabled . . . . .	321
Figure 62.	QUADSPI block diagram when dual-flash mode is enabled . . . . .	322
Figure 63.	Example of read command in quad-SPI mode . . . . .	323
Figure 64.	Example of a DDR command in quad-SPI mode . . . . .	326
Figure 65.	NCS when CKMODE = 0 (T = CLK period) . . . . .	334
Figure 66.	NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .	334
Figure 67.	NCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . .	335
Figure 68.	NCS when CKMODE = 1 with an abort (T = CLK period). . . . .	335
Figure 69.	Single ADC block diagram . . . . .	350
Figure 70.	ADC1 connectivity . . . . .	352
Figure 71.	ADC2 connectivity . . . . .	353
Figure 72.	ADC3 connectivity . . . . .	354
Figure 73.	Timing diagram . . . . .	357
Figure 74.	Analog watchdog's guarded area . . . . .	357
Figure 75.	Injected conversion latency . . . . .	359
Figure 76.	Right alignment of 12-bit data. . . . .	361
Figure 77.	Left alignment of 12-bit data . . . . .	361
Figure 78.	Left alignment of 6-bit data . . . . .	361
Figure 79.	Multi ADC block diagram ⁽¹⁾. . . . .	366
Figure 80.	Injected simultaneous mode on 4 channels: dual ADC mode . . . . .	369
Figure 81.	Injected simultaneous mode on 4 channels: triple ADC mode . . . . .	369
Figure 82.	Regular simultaneous mode on 16 channels: dual ADC mode . . . . .	370
Figure 83.	Regular simultaneous mode on 16 channels: triple ADC mode . . . . .	370
Figure 84.	Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode. . . . .	371
Figure 85.	Interleaved mode on 1 channel in continuous conversion mode: triple ADC mode . . . . .	372
Figure 86.	Alternate trigger: injected group of each ADC . . . . .	373
Figure 87.	Alternate trigger: 4 injected channels (each ADC) in discontinuous mode. . . . .	373
Figure 88.	Alternate trigger: injected group of each ADC . . . . .	374
Figure 89.	Alternate + regular simultaneous . . . . .	375
Figure 90.	Case of trigger occurring during injected conversion . . . . .	375
Figure 91.	Temperature sensor and VREFINT channel block diagram . . . . .	376
Figure 92.	DAC channel block diagram . . . . .	396
Figure 93.	DAC output buffer connection. . . . .	397
Figure 94.	Data registers in single DAC channel mode . . . . .	398
Figure 95.	Data registers in dual DAC channel mode . . . . .	398
Figure 96.	Timing diagram for conversion with trigger disabled TEN = 0 . . . . .	399
Figure 97.	DAC LFSR register calculation algorithm . . . . .	401
Figure 98.	DAC conversion (SW trigger enabled) with LFSR wave generation. . . . .	401
Figure 99.	DAC triangle wave generation . . . . .	402
Figure 100.	DAC conversion (SW trigger enabled) with triangle wave generation . . . . .	402

Figure 101. DCMI block diagram . . . . .	418
Figure 102. Top-level block diagram . . . . .	418
Figure 103. DCMI signal waveforms . . . . .	419
Figure 104. Timing diagram . . . . .	421
Figure 105. Frame capture waveforms in snapshot mode . . . . .	423
Figure 106. Frame capture waveforms in continuous grab mode . . . . .	424
Figure 107. Coordinates and size of the window after cropping . . . . .	424
Figure 108. Data capture waveforms . . . . .	425
Figure 109. Pixel raster scan order . . . . .	426
Figure 110. Advanced-control timer block diagram . . . . .	440
Figure 111. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	442
Figure 112. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	442
Figure 113. Counter timing diagram, internal clock divided by 1 . . . . .	443
Figure 114. Counter timing diagram, internal clock divided by 2 . . . . .	444
Figure 115. Counter timing diagram, internal clock divided by 4 . . . . .	444
Figure 116. Counter timing diagram, internal clock divided by N . . . . .	444
Figure 117. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	445
Figure 118. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	445
Figure 119. Counter timing diagram, internal clock divided by 1 . . . . .	447
Figure 120. Counter timing diagram, internal clock divided by 2 . . . . .	447
Figure 121. Counter timing diagram, internal clock divided by 4 . . . . .	448
Figure 122. Counter timing diagram, internal clock divided by N . . . . .	448
Figure 123. Counter timing diagram, update event when repetition counter is not used . . . . .	449
Figure 124. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .	450
Figure 125. Counter timing diagram, internal clock divided by 2 . . . . .	450
Figure 126. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	451
Figure 127. Counter timing diagram, internal clock divided by N . . . . .	451
Figure 128. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .	452
Figure 129. Counter timing diagram, update event with ARPE=1 (counter overflow) . . . . .	452
Figure 130. Update rate examples depending on mode and TIMx_RCR register settings . . . . .	454
Figure 131. Control circuit in normal mode, internal clock divided by 1 . . . . .	455
Figure 132. TI2 external clock connection example . . . . .	456
Figure 133. Control circuit in external clock mode 1 . . . . .	457
Figure 134. External trigger input block . . . . .	457
Figure 135. Control circuit in external clock mode 2 . . . . .	458
Figure 136. Capture/compare channel (example: channel 1 input stage) . . . . .	459
Figure 137. Capture/compare channel 1 main circuit . . . . .	459
Figure 138. Output stage of capture/compare channel (channels 1 to 3) . . . . .	460
Figure 139. Output stage of capture/compare channel (channel 4) . . . . .	460
Figure 140. PWM input mode timing . . . . .	462
Figure 141. Output compare mode, toggle on OC1 . . . . .	464
Figure 142. Edge-aligned PWM waveforms (ARR=8) . . . . .	465
Figure 143. Center-aligned PWM waveforms (ARR=8) . . . . .	466
Figure 144. Complementary output with dead-time insertion . . . . .	468
Figure 145. Dead-time waveforms with delay greater than the negative pulse . . . . .	468
Figure 146. Dead-time waveforms with delay greater than the positive pulse . . . . .	468
Figure 147. Output behavior in response to a break . . . . .	471
Figure 148. Clearing TIMx_OCxREF . . . . .	472
Figure 149. 6-step generation, COM example (OSSR=1) . . . . .	473
Figure 150. Example of one pulse mode . . . . .	474

Figure 151. Example of counter operation in encoder interface mode . . . . .	477
Figure 152. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .	477
Figure 153. Example of Hall sensor interface . . . . .	479
Figure 154. Control circuit in reset mode . . . . .	480
Figure 155. Control circuit in gated mode . . . . .	481
Figure 156. Control circuit in trigger mode . . . . .	482
Figure 157. Control circuit in external clock mode 2 + trigger mode . . . . .	483
Figure 158. General-purpose timer block diagram . . . . .	511
Figure 159. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	512
Figure 160. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	513
Figure 161. Counter timing diagram, internal clock divided by 1 . . . . .	514
Figure 162. Counter timing diagram, internal clock divided by 2 . . . . .	514
Figure 163. Counter timing diagram, internal clock divided by 4 . . . . .	514
Figure 164. Counter timing diagram, internal clock divided by N . . . . .	515
Figure 165. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .	515
Figure 166. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .	516
Figure 167. Counter timing diagram, internal clock divided by 1 . . . . .	517
Figure 168. Counter timing diagram, internal clock divided by 2 . . . . .	517
Figure 169. Counter timing diagram, internal clock divided by 4 . . . . .	517
Figure 170. Counter timing diagram, internal clock divided by N . . . . .	518
Figure 171. Counter timing diagram, Update event . . . . .	518
Figure 172. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .	519
Figure 173. Counter timing diagram, internal clock divided by 2 . . . . .	520
Figure 174. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	520
Figure 175. Counter timing diagram, internal clock divided by N . . . . .	520
Figure 176. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .	521
Figure 177. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .	521
Figure 178. Control circuit in normal mode, internal clock divided by 1 . . . . .	522
Figure 179. TI2 external clock connection example. . . . .	523
Figure 180. Control circuit in external clock mode 1 . . . . .	524
Figure 181. External trigger input block . . . . .	524
Figure 182. Control circuit in external clock mode 2 . . . . .	525
Figure 183. Capture/compare channel (example: channel 1 input stage). . . . .	526
Figure 184. Capture/compare channel 1 main circuit . . . . .	526
Figure 185. Output stage of capture/compare channel (channel 1). . . . .	527
Figure 186. PWM input mode timing . . . . .	529
Figure 187. Output compare mode, toggle on OC1 . . . . .	530
Figure 188. Edge-aligned PWM waveforms (ARR=8). . . . .	532
Figure 189. Center-aligned PWM waveforms (ARR=8). . . . .	533
Figure 190. Example of one-pulse mode . . . . .	534
Figure 191. Clearing TIMx_OCxREF . . . . .	536
Figure 192. Example of counter operation in encoder interface mode . . . . .	537
Figure 193. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .	538
Figure 194. Control circuit in reset mode . . . . .	539
Figure 195. Control circuit in gated mode . . . . .	540
Figure 196. Control circuit in trigger mode . . . . .	540
Figure 197. Control circuit in external clock mode 2 + trigger mode . . . . .	541
Figure 198. Master/Slave timer example . . . . .	542
Figure 199. Gating timer 2 with OC1REF of timer 1 . . . . .	543
Figure 200. Gating timer 2 with Enable of timer 1 . . . . .	544
Figure 201. Triggering timer 2 with update of timer 1 . . . . .	545
Figure 202. Triggering timer 2 with Enable of timer 1 . . . . .	545

Figure 203. Triggering timer 1 and 2 with timer 1 TI1 input . . . . .	547
Figure 204. General-purpose timer block diagram (TIM9 and TIM12) . . . . .	572
Figure 205. General-purpose timer block diagram (TIM10/11/13/14) . . . . .	573
Figure 206. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	575
Figure 207. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	575
Figure 208. Counter timing diagram, internal clock divided by 1 . . . . .	576
Figure 209. Counter timing diagram, internal clock divided by 2 . . . . .	577
Figure 210. Counter timing diagram, internal clock divided by 4 . . . . .	577
Figure 211. Counter timing diagram, internal clock divided by N . . . . .	577
Figure 212. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	578
Figure 213. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	578
Figure 214. Control circuit in normal mode, internal clock divided by 1 . . . . .	579
Figure 215. TI2 external clock connection example . . . . .	580
Figure 216. Control circuit in external clock mode 1 . . . . .	580
Figure 217. Capture/compare channel (example: channel 1 input stage) . . . . .	581
Figure 218. Capture/compare channel 1 main circuit . . . . .	582
Figure 219. Output stage of capture/compare channel (channel 1) . . . . .	582
Figure 220. PWM input mode timing . . . . .	584
Figure 221. Output compare mode, toggle on OC1 . . . . .	586
Figure 222. Edge-aligned PWM waveforms (ARR=8) . . . . .	587
Figure 223. Example of One-pulse mode . . . . .	588
Figure 224. Control circuit in reset mode . . . . .	590
Figure 225. Control circuit in gated mode . . . . .	591
Figure 226. Control circuit in trigger mode . . . . .	591
Figure 227. Basic timer block diagram . . . . .	618
Figure 228. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	620
Figure 229. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	620
Figure 230. Counter timing diagram, internal clock divided by 1 . . . . .	621
Figure 231. Counter timing diagram, internal clock divided by 2 . . . . .	622
Figure 232. Counter timing diagram, internal clock divided by 4 . . . . .	622
Figure 233. Counter timing diagram, internal clock divided by N . . . . .	622
Figure 234. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) . . . . .	623
Figure 235. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	623
Figure 236. Control circuit in normal mode, internal clock divided by 1 . . . . .	624
Figure 237. Independent watchdog block diagram . . . . .	631
Figure 238. Watchdog block diagram . . . . .	637
Figure 239. Window watchdog timing diagram . . . . .	638
Figure 240. RTC block diagram . . . . .	644
Figure 241. Block diagram . . . . .	683
Figure 242. I ²C-bus protocol . . . . .	685
Figure 243. Setup and hold timings . . . . .	686
Figure 244. FMPI2C initialization flow . . . . .	689
Figure 245. Data reception . . . . .	690
Figure 246. Data transmission . . . . .	691
Figure 247. Target initialization flow . . . . .	694
Figure 248. Transfer sequence flow for FMPI2C target transmitter, NOSTRETCH = 0 . . . . .	696
Figure 249. Transfer sequence flow for FMPI2C target transmitter, NOSTRETCH = 1 . . . . .	697
Figure 250. Transfer bus diagrams for FMPI2C target transmitter (mandatory events only) . . . . .	698

Figure 251.	Transfer sequence flow for FMPI2C target receiver, NOSTRETCH = 0 . . . . .	699
Figure 252.	Transfer sequence flow for FMPI2C target receiver, NOSTRETCH = 1 . . . . .	700
Figure 253.	Transfer bus diagrams for FMPI2C target receiver (mandatory events only) . . . . .	700
Figure 254.	Controller clock generation . . . . .	702
Figure 255.	Controller initialization flow . . . . .	704
Figure 256.	10-bit address read access with HEAD10R = 0 . . . . .	704
Figure 257.	10-bit address read access with HEAD10R = 1 . . . . .	705
Figure 258.	Transfer sequence flow for FMPI2C controller transmitter, N ≤ 255 bytes . . . . .	706
Figure 259.	Transfer sequence flow for FMPI2C controller transmitter, N > 255 bytes . . . . .	707
Figure 260.	Transfer bus diagrams for FMPI2C controller transmitter (mandatory events only) . . . . .	708
Figure 261.	Transfer sequence flow for FMPI2C controller receiver, N ≤ 255 bytes . . . . .	710
Figure 262.	Transfer sequence flow for FMPI2C controller receiver, N > 255 bytes . . . . .	711
Figure 263.	Transfer bus diagrams for FMPI2C controller receiver (mandatory events only) . . . . .	712
Figure 264.	Timeout intervals for $t_{LOW:SEXT}$ , $t_{LOW:MEXT}$ . . . . .	716
Figure 265.	Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .	719
Figure 266.	Transfer bus diagram for SMBus target transmitter (SBC = 1) . . . . .	720
Figure 267.	Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .	721
Figure 268.	Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .	722
Figure 269.	Bus transfer diagrams for SMBus controller transmitter . . . . .	723
Figure 270.	Bus transfer diagrams for SMBus controller receiver . . . . .	725
Figure 271.	I2C bus protocol . . . . .	746
Figure 272.	I2C block diagram . . . . .	746
Figure 273.	Transfer sequence diagram for target transmitter . . . . .	748
Figure 274.	Transfer sequence diagram for target receiver . . . . .	749
Figure 275.	Transfer sequence diagram for controller transmitter . . . . .	752
Figure 276.	Transfer sequence diagram for controller receiver . . . . .	753
Figure 277.	I2C interrupt mapping diagram . . . . .	761
Figure 278.	USART block diagram . . . . .	778
Figure 279.	Word length programming . . . . .	779
Figure 280.	Configurable stop bits . . . . .	780
Figure 281.	TC/TXE behavior when transmitting . . . . .	782
Figure 282.	Start bit detection when oversampling by 16 or 8 . . . . .	783
Figure 283.	Data sampling when oversampling by 16 . . . . .	786
Figure 284.	Data sampling when oversampling by 8 . . . . .	786
Figure 285.	Mute mode using Idle line detection . . . . .	798
Figure 286.	Mute mode using address mark detection . . . . .	798
Figure 287.	Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .	801
Figure 288.	Break detection in LIN mode vs. Framing error detection . . . . .	802
Figure 289.	USART example of synchronous transmission . . . . .	803
Figure 290.	USART data clock timing diagram (M=0) . . . . .	803
Figure 291.	USART data clock timing diagram (M=1) . . . . .	804
Figure 292.	RX data setup/hold time . . . . .	804
Figure 293.	ISO 7816-3 asynchronous protocol . . . . .	805
Figure 294.	Parity error detection using the 1.5 stop bits . . . . .	806
Figure 295.	IrDA SIR ENDEC- block diagram . . . . .	808
Figure 296.	IrDA data modulation (3/16) -Normal mode . . . . .	808
Figure 297.	Transmission using DMA . . . . .	810
Figure 298.	Reception using DMA . . . . .	811
Figure 299.	Hardware flow control between 2 USARTs . . . . .	811

Figure 300. RTS flow control . . . . .	812
Figure 301. CTS flow control . . . . .	812
Figure 302. USART interrupt mapping diagram . . . . .	814
Figure 303. SPI block diagram. . . . .	827
Figure 304. Full-duplex single master/ single slave application. . . . .	828
Figure 305. Half-duplex single master/ single slave application . . . . .	829
Figure 306. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . .	830
Figure 307. Master and three independent slaves. . . . .	831
Figure 308. Multimaster application. . . . .	832
Figure 309. Hardware/software slave select management . . . . .	833
Figure 310. Data clock timing diagram . . . . .	835
Figure 311. TXE/RXNE/BSY behavior in master / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers . . . . .	838
Figure 312. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers . . . . .	839
Figure 313. Transmission using DMA . . . . .	841
Figure 314. Reception using DMA. . . . .	842
Figure 315. TI mode transfer . . . . .	845
Figure 316. I ²S block diagram . . . . .	848
Figure 317. Full-duplex communication. . . . .	850
Figure 318. I ²S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . .	851
Figure 319. I ²S Philips standard waveforms (24-bit frame with CPOL = 0). . . . .	851
Figure 320. Transmitting 0x8EAA33 . . . . .	852
Figure 321. Receiving 0x8EAA33 . . . . .	852
Figure 322. I ²S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . .	852
Figure 323. Example of 16-bit data frame extended to 32-bit channel frame . . . . .	853
Figure 324. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . .	853
Figure 325. MSB justified 24-bit frame length with CPOL = 0 . . . . .	853
Figure 326. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .	854
Figure 327. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . .	854
Figure 328. LSB justified 24-bit frame length with CPOL = 0 . . . . .	854
Figure 329. Operations required to transmit 0x3478AE. . . . .	855
Figure 330. Operations required to receive 0x3478AE . . . . .	855
Figure 331. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .	855
Figure 332. Example of 16-bit data frame extended to 32-bit channel frame . . . . .	856
Figure 333. PCM standard waveforms (16-bit) . . . . .	856
Figure 334. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .	856
Figure 335. Audio sampling frequency definition . . . . .	857
Figure 336. I ²S clock generator architecture . . . . .	857
Figure 337. SPDIFRX block diagram . . . . .	876
Figure 338. S/PDIF sub-frame format . . . . .	877
Figure 339. S/PDIF block format . . . . .	877
Figure 340. S/PDIF preambles . . . . .	878
Figure 341. Channel coding example . . . . .	878
Figure 342. SPDIFRX decoder . . . . .	879
Figure 343. Noise filtering and edge detection . . . . .	880
Figure 344. Thresholds . . . . .	881
Figure 345. Synchronization flowchart. . . . .	883
Figure 346. Synchronization process scheduling . . . . .	884
Figure 347. SPDIFRX states . . . . .	885
Figure 348. SPDIFRX_FMTx_DR register format . . . . .	887

Figure 349. Channel/user data format . . . . .	888
Figure 350. S/PDIF overrun error when RXSTEO = 0 . . . . .	890
Figure 351. S/PDIF overrun error when RXSTEO = 1 . . . . .	891
Figure 352. SPDIFRX interface interrupt mapping diagram . . . . .	892
Figure 353. SAI functional block diagram . . . . .	908
Figure 354. Audio frame . . . . .	912
Figure 355. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .	914
Figure 356. FS role is start of frame (FSDEF = 0) . . . . .	915
Figure 357. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .	916
Figure 358. First bit offset . . . . .	916
Figure 359. Audio block clock generator overview . . . . .	917
Figure 360. AC'97 audio frame . . . . .	921
Figure 361. Example of typical AC'97 configuration on devices featuring at least two embedded SAIs (three external AC'97 decoders) . . . . .	922
Figure 362. SPDIF format . . . . .	923
Figure 363. SAI_xDR register ordering . . . . .	924
Figure 364. Data companding hardware in an audio block in the SAI . . . . .	927
Figure 365. Tristate strategy on SD output line on an inactive slot . . . . .	929
Figure 366. Tristate on output data line in a protocol like I2S . . . . .	930
Figure 367. Overrun detection error . . . . .	931
Figure 368. FIFO underrun event . . . . .	931
Figure 369. "No response" and "no data" operations . . . . .	961
Figure 370. (Multiple) block read operation . . . . .	961
Figure 371. (Multiple) block write operation . . . . .	961
Figure 372. Sequential read operation . . . . .	962
Figure 373. Sequential write operation . . . . .	962
Figure 374. SDIO block diagram . . . . .	962
Figure 375. SDIO adapter . . . . .	964
Figure 376. Control unit . . . . .	965
Figure 377. SDIO_CK clock dephasing (BYPASS = 0) . . . . .	965
Figure 378. SDIO adapter command path . . . . .	966
Figure 379. Command path state machine (SDIO) . . . . .	967
Figure 380. SDIO command transfer . . . . .	968
Figure 381. Data path . . . . .	970
Figure 382. Data path state machine (DPSM) . . . . .	971
Figure 383. CAN network topology . . . . .	1019
Figure 384. Dual-CAN block diagram . . . . .	1020
Figure 385. bxCAN operating modes . . . . .	1022
Figure 386. bxCAN in silent mode . . . . .	1023
Figure 387. bxCAN in Loop back mode . . . . .	1023
Figure 388. bxCAN in combined mode . . . . .	1024
Figure 389. Transmit mailbox states . . . . .	1026
Figure 390. Receive FIFO states . . . . .	1027
Figure 391. Filter bank scale configuration - Register organization . . . . .	1029
Figure 392. Example of filter numbering . . . . .	1030
Figure 393. Filtering mechanism example . . . . .	1031
Figure 394. CAN error state diagram . . . . .	1033
Figure 395. Bit timing . . . . .	1035
Figure 396. CAN frames . . . . .	1036
Figure 397. Event flags and interrupt generation . . . . .	1037
Figure 398. CAN mailbox registers . . . . .	1049
Figure 399. OTG_FS full-speed block diagram . . . . .	1067

Figure 400.	OTG_HS high-speed block diagram . . . . .	1068
Figure 401.	OTG_FS/OTG_HS A-B device connection . . . . .	1071
Figure 402.	OTG_FS/OTG_HS peripheral-only connection . . . . .	1073
Figure 403.	OTG_FS/OTG_HS host-only connection . . . . .	1077
Figure 404.	SOF connectivity (SOF trigger output to TIM and ITRx connection). . . . .	1081
Figure 405.	Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .	1083
Figure 406.	Device-mode FIFO address mapping and AHB FIFO access mapping (for OTG_FS) . . . . .	1085
Figure 407.	Device-mode FIFO address mapping and AHB FIFO access mapping (for OTG_HS) . . . . .	1086
Figure 408.	Host-mode FIFO address mapping and AHB FIFO access mapping (for OTG_FS) . . . . .	1087
Figure 409.	Host-mode FIFO address mapping and AHB FIFO access mapping (for OTG_HS) . . . . .	1088
Figure 410.	Interrupt hierarchy. . . . .	1092
Figure 411.	Transmit FIFO write task . . . . .	1198
Figure 412.	Receive FIFO read task . . . . .	1199
Figure 413.	Normal bulk/control OUT/SETUP . . . . .	1201
Figure 414.	Bulk/control IN transactions . . . . .	1205
Figure 415.	Normal interrupt OUT . . . . .	1208
Figure 416.	Normal interrupt IN . . . . .	1213
Figure 417.	Isochronous OUT transactions . . . . .	1215
Figure 418.	Isochronous IN transactions . . . . .	1218
Figure 419.	Normal bulk/control OUT/SETUP transactions - DMA . . . . .	1220
Figure 420.	Normal bulk/control IN transaction - DMA. . . . .	1222
Figure 421.	Normal interrupt OUT transactions - DMA mode . . . . .	1223
Figure 422.	Normal interrupt IN transactions - DMA mode . . . . .	1224
Figure 423.	Normal isochronous OUT transaction - DMA mode . . . . .	1225
Figure 424.	Normal isochronous IN transactions - DMA mode . . . . .	1226
Figure 425.	Receive FIFO packet read . . . . .	1232
Figure 426.	Processing a SETUP packet . . . . .	1234
Figure 427.	Bulk OUT transaction . . . . .	1241
Figure 428.	TRDT max timing case . . . . .	1252
Figure 429.	A-device SRP . . . . .	1253
Figure 430.	B-device SRP . . . . .	1254
Figure 431.	A-device HNP . . . . .	1255
Figure 432.	B-device HNP . . . . .	1257
Figure 433.	HDMI-CEC block diagram . . . . .	1260
Figure 434.	Message structure . . . . .	1261
Figure 435.	Blocks . . . . .	1261
Figure 436.	Bit timings . . . . .	1262
Figure 437.	Signal free time. . . . .	1262
Figure 438.	Arbitration phase. . . . .	1263
Figure 439.	SFT of three nominal bit periods. . . . .	1263
Figure 440.	Error bit timing . . . . .	1264
Figure 441.	Error handling . . . . .	1265
Figure 442.	TXERR detection . . . . .	1267
Figure 443.	Block diagram of STM32 MCU and Cortex ^®-M4 with FPU-level debug support . . . . .	1277
Figure 444.	SWJ debug port . . . . .	1279
Figure 445.	JTAG TAP connections . . . . .	1282
Figure 446.	TPIU block diagram . . . . .	1302

RM0390-STM32F446

Contents

List of tables

List of figures

Chapters

RM0390-STM32F446

Related documents

Contents

List of tables

List of figures

Chapters