40. Revision history

Table 297. Document revision history

DateRevisionChanges
22-Sep-20151Initial release.
19-Nov-20152Updated Section 6.3.13: RCC APB1 peripheral clock enable register (RCC_APB1ENR) .
Updated Section 8.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP) and Table 28: SYSCFG register map and reset values .
Updated SRAM/NOR-flash write timing registers x (FMC_BWTRx) .
Updated Section 14.13.2: ADC control register 1 (ADC_CR1) .
Updated Section 40.3.3: LTDC reset and clocks and Section 40.5: LTDC interrupts .
Added Table 403: Clock domain for each register .
Updated Section 29.12.4: DSI PLL control .
Updated Section 24.5.11: TIM11 option register 1 (TIM11_OR) .
Added Section 30.3: USART implementation and removed former Section 30.5: USART mode configuration .
Updated tables 189 , 190 , 191 , 194 , 195 , 196 and 197 in Section 30.4.4: Fractional baud rate generation .
Added Section 31.3.4: Multimaster communication .
Updated figures 349 , 350 , 351 , 352 and their footnotes in Section 31.3: SPI functional description .
Updated Section 35.15.4: OTG USB configuration register (OTG_GUSBCFG) and Choosing the value of TRDT in OTG_GUSBCFG .
Added footnotes to figures from 440 to 450 in Section 35.16.5: Host programming model .
Updated Ethernet PTP PPS control register (ETH_PTPPPSCR) .
05-Jan-20173Updated Table 6: STM32F469xx and STM32F479xx register boundary addresses .
Updated Section 1.2: List of abbreviations for registers and Section 5.6.1: PWR power control register (PWR_CR) , Section 6.3.13: RCC APB1 peripheral clock enable register (RCC_APB1ENR) , Section 6.3.25: RCC dedicated clock configuration register (RCC_DCKCFGR) and Section 10.3: GPIO functional description .
Replaced former Section 9.3.1: General description with Section 9.3.1: DMA block diagram and Section 9.3.2: DMA overview .

Table 297. Document revision history (continued)

DateRevisionChanges
05-Jan-20173
(cont'd)

Updated Section 12.2: FMC main features , Section 12.4: AHB interface , SRAM/NOR-flash chip-select timing register for bank x (FMC_BTRx) , SRAM/NOR-flash write timing registers x (FMC_BWTRx) , Section 12.7.5: NAND flash prewait functionality , Table 65: FMC_BCRx bitfields (mode 1) , Common memory space timing register (FMC_PMEM) , Attribute memory space timing register (FMC_PATT) and SDRAM control register x (FMC_SDCRx) .

Updated Table 67: FMC_BCRx bitfields (mode A) .

Updated Figure 56: NAND flash controller waveforms for common memory access and added footnote 2 to it.

Updated Section 13.3.13: QUADSPI error management .

Added notes in Section 14.13.7: ADC watchdog higher threshold register (ADC_HTR) and in Section 14.13.8: ADC watchdog lower threshold register (ADC_LTR) .

Updated title of Section 40: LCD-TFT display controller (LTDC) .

Updated Section 40.2: LTDC main features , Section 40.3.3: LTDC reset and clocks , Example of synchronous timings configuration and Section 40.7.15: LTDC layer x window horizontal position configuration register (LTDC_LxWHPCR) .

Updated Figure 425: Layer window programmable parameters .

Updated Table 258: LTDC pins and signal interface and Table 175: Location of color components in the LTDC interface .

Updated Section 19.2: RNG main features , Section 19.7.1: RNG control register (RNG_CR) , Section 19.7.2: RNG status register (RNG_SR) and Section 19.7.2: RNG status register (RNG_SR) .

Updated Figure 156: RNG block diagram .

Replaced former Section 19.3.1: Operation and Section 19.3.2: Error management with Section 19.3.8: RNG low-power use , Section 19.4: RNG interrupts , Section 19.5: RNG processing time and Section 19.6: RNG entropy source validation .

Updated Section 20.2: CRYP main features , Section 20.5: CRYP interrupts , Section 20.7.1: CRYP control register (CRYP_CR) , Section 20.7.2: CRYP status register (CRYP_SR) and Sections 20.7.5 to 20.7.21 .

Replaced former Section 20.3.1 and Sections 20.3.3 to 20.3.7 with new Section 20.4.1: CRYP block diagram , Section 20.4.2: CRYP internal signals and Sections 20.4.4 to 20.4.20 .

Updated Figure 283: CRYP block diagram and figures 159 to 164.

Added Section 20.6: CRYP processing time .

Removed former Section 20.5: CRYP DMA interface .

Updated Section 21.2: HASH main features and Section 21.4: HASH functional description and their subsections, and added Section 21.5: HASH interrupts and Section 21.4.11: HASH processing time .

Updated Section 31.1: Introduction .

Updated Figure 361: I 2 S block diagram and added footnote 1 to it.

Added Section 31.6.2: I2S full-duplex .

Updated Section 31.7.1: SPI control register 1 (SPI_CR1) (not used in I 2 S mode) .

Table 297. Document revision history (continued)

DateRevisionChanges
05-Jan-20173
(cont'd)

Added Section 32.4.2: SAI pins and internal signals .

Updated Section 32.4.8: SAI clock generator , Section 32.4.9: Internal FIFOs and its subsections, and Sections 32.5.1 to 32.6.17 .

Updated Figure 382: SAI functional block diagram , Figure 388: Audio block clock generator overview and footnote 1 of Figure 392

Updated Table 211: Example of possible audio frequency sampling range .

Updated Section 33.3: SDIO functional description , Section 33.8.1: SDIO power control register (SDIO_POWER) , Section 33.8.2: SDIO clock control register (SDIO_CLKCR) and Section 33.8.4: SDIO command register (SDIO_CMD) .

Updated Section 34.2: bxCAN main features and added Figure 412: Dual-CAN block diagram

Updated Section 35.1: Introduction , Section 35.11.3: FIFO RAM allocation , Section 35.15.1: OTG control and status register (OTG_GOTGCTL) , Section 35.15.3: OTG AHB configuration register (OTG_GAHBCFG) , Section 35.15.4: OTG USB configuration register (OTG_GUSBCFG) , Section 35.15.5: OTG reset register (OTG_GRSTCTL) , Section 35.15.9: OTG receive status debug read [alternate] (OTG_GRXSTSR) , Section 35.15.39: OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) , Section 35.15.51: OTG device IN endpoint x control register (OTG_DIEPCTLx) , Section 35.15.61: OTG device OUT endpoint x control register (OTG_DOEPCTLx) , Section 35.15.52: OTG device IN endpoint x interrupt register (OTG_DIEPINTx) , Section 35.15.58: OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) , Section 35.15.56: OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) , Section 35.15.55: OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) .

Added Table 253: OTG_HS speeds supported and Table 254: OTG_FS speeds supported , and updated Table 268: OTG_FS/OTG_HS register map and reset values .

15-Feb-20184

Updated Introduction and Section 1.2: List of abbreviations for registers .

Updated Section 2.2.1: Introduction and Section 2.3.2: Memory map and register boundary addresses , and added Figure 3: Memory map .

Updated Table 8: Memory mapping versus Boot mode/physical remap .

Updated Section 3.7.6: Flash option control register (FLASH_OPTCR) .

Updated Section 5.6.2: PWR power control/status register (PWR_CSR) .

Updated Section 6.3.14: RCC APB2 peripheral clock enable register (RCC_APB2ENR) and Figure 16: Clock tree .

Table 297. Document revision history (continued)

DateRevisionChanges
15-Feb-20184
(cont'd)

Updated Section 8.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP) , Section 8.2.3: SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) , Section 8.2.4: SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) , Section 8.2.5: SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) and Section 8.2.6: SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) .

Updated Section 9.1: DMA introduction , Section 9.2: DMA main features and Section 9.3.10: Double-buffer mode , and title of Table 42: CLUT data order in system memory .

Updated Section 10.3.4: DMA2D foreground and background pixel format converter (PFC) , Section 10.5.1: DMA2D control register (DMA2D_CR) and Section 10.5.10: DMA2D background PFC control register (DMA2D_BGPFCR) .

Updated Figure 49: Muxed read access waveforms .

Updated Section 13.3.1: QUADSPI block diagram , Section 13.3.7: QUADSPI memory-mapped mode , Section 13.5.4: QUADSPI flag clear register (QUADSPI_FCR) , and added Section 13.3.2: QUADSPI pins .

Replaced HSYNC, VSYNC and PIXCLK with, respectively, DCMI_HSYNC, DCMI_VSYNC and DCMI_PIXCLK in Section 16: Digital camera interface (DCMI) .

Removed former Section 16.3: DCMI pins , and added Section 16.4.1: DCMI block diagram .

Added Section 31.3.2: LTDC pins and external signal interface .

Updated title of Section 18: DSI Host (DSI) , and replaced “ro” with “r” in registers access types in the whole section.

Updated Section 18.1: Introduction and Table 127: Frame requirement configuration registers .

Updated Noise source , Post processing , Section 19.3.6: RNG clocking , Clock error detection , Section 19.7.1: RNG control register (RNG_CR) and Section 19.7.2: RNG status register (RNG_SR) .

Updated Section 20.7.1: CRYP control register (CRYP_CR) , Section 20.7.1: CRYP control register (CRYP_CR) and bit description in Sections 20.7.9 to 20.7.20.

Updated Figure 335: USART data clock timing diagram (M=0) .

Added Section 32.3: SAI implementation , and updated Configuring and enabling SAI modes , Frame synchronization polarity , Clock generator programming in SPDIF generator mode , Anticipated frame synchronization detection (AFSDET) , Wrong clock configuration in master mode (with NODIV = 0) , Section 32.4.14: Disabling the SAI , Section 32.6.1: SAI configuration register 1 (SAI_ACR1) and Section 32.6.3: SAI frame configuration register (SAI_AFRCR) .

Removed former Section 47.6.1: Global configuration register (SAI_GCR)

Updated Figure 382: SAI functional block diagram , Table 209: SAI internal input/output signals , Table 210: SAI input/output pins and Table 216: SAI register map and reset values .

Table 297. Document revision history (continued)

DateRevisionChanges
15-Feb-20184
(cont'd)

Updated Section 34.2: bxCAN main features , Section 34.3.4: Acceptance filters , Section 34.6: Behavior in debug mode , Section 34.9.4: CAN filter registers

Updated Figure 419: Filter bank scale configuration - Register organization , Figure 420: Example of filter numbering , Figure 421: Filtering mechanism example , Figure 421: Filtering mechanism example , Figure 425: Event flags and interrupt generation and Figure 426: CAN mailbox registers .

Updated Section 35.1: Introduction , Section 35.2: OTG_FS/OTG_HS main features , Section 35.2.2: Host-mode features , Section 35.3: OTG_FS/OTG_HS implementation , Section 35.4.3: OTG_FS/OTG_HS core , Section 35.4.4: Embedded full-speed OTG PHY connected to OTG_FS , Section 35.7: OTG_FS/OTG_HS as a USB host , Section 35.9: OTG_FS/OTG_HS low-power modes , Section 35.15.1: OTG control and status register (OTG_GOTGCTL) , Section 35.15.3: OTG AHB configuration register (OTG_GAHBCFG) , Section 35.15.4: OTG USB configuration register (OTG_GUSBCFG) , Section 35.15.6: OTG core interrupt register (OTG_GINTSTS) , Section 35.15.7: OTG interrupt mask register (OTG_GINTMSK) , Section 35.15.9: OTG receive status debug read [alternate] (OTG_GRXSTSR) , Section 35.15.15: OTG general core configuration register (OTG_GCCFG) , Section 35.15.16: OTG core ID register (OTG_CID) , Section 35.15.19: OTG device IN endpoint transmit FIFO x size register (OTG_DIEPTXFx) , Section 35.15.22: OTG host frame interval register (OTG_HFIR) , Section 35.15.35: OTG device configuration register (OTG_DCFG) , Section 35.15.38: OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK) , Section 35.15.39: OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) and Section 35.15.55: OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) .

Added Section 35.4.2: OTG_FS/OTG_HS pin and internal signals , Section 35.15.45: OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPMSK) , Section 35.15.48: OTG device each IN endpoint-1 interrupt mask register (OTG_HS_DIEPEACHMSK1) , Section 35.15.49: OTG device each OUT endpoint-1 interrupt mask register (OTG_HS_DOEPEACHMSK1)

Removed former Section 35.4.6: External Full-speed OTG PHY using the I2C interface , Section 35.15.12: OTG I2C access register (OTG_GI2CCTL) , and former footnote 1 from Figure 436 .

Added Table 255: OTG_FS/OTG_HS implementation , Table 256: OTG_FS input/output pins and Table 257: OTG_HS input/output pins .

Updated Figure 427: OTG_FS full-speed block diagram , Figure 428: OTG_HS high-speed block diagram , Figure 433: Updating OTG_HFIR dynamically (RLDCTRL = 1) , and Figure 436: Interrupt hierarchy and its footnote . Updated Table 260: Core global control and status registers (CSRs) , Table 261: Host-mode control and status registers (CSRs) , Table 262: Device-mode control and status registers , Table 264: Power and clock gating control and status registers , Table 268: OTG_FS/OTG_HS register map and reset values .

Updated Section 38.1: Unique device ID register (96 bits) and Section 38.1: Unique device ID register (96 bits) .

Table 297. Document revision history (continued)

DateRevisionChanges
07-Jun-20185

Updated Introduction , Section 1.2: List of abbreviations for registers , Section 7.4.1: GPIO port mode register (GPIOx_MODER) (x = A to K) to Section 7.4.10: GPIO alternate function high register (GPIOx_AFRH) (x = A to J) , Section 9.5.1: DMA low interrupt status register (DMA_LISR) to Section 9.5.10: DMA stream x FIFO control register (DMA_SxFCR) , Section 12.6.6: NOR/PSRAM controller registers, SRAM/NOR-flash chip-select control register for bank x (FMC_BCRx) , SDRAM timing register x (FMC_SDTRx) , Section 14.13.3: ADC control register 2 (ADC_CR2) , Section 16.5.1: Data formats , title of Section 31.3.2: LTDC pins and external signal interface , Section 21.6.1: HASH control register (HASH_CR) , Section 21.6.4: HASH digest registers , title of Section 30: Universal synchronous receiver transmitter (USART) /universal asynchronous receiver transmitter (UART) , Resetting the SPIx_TXCRC and SPIx_RXCRC values , Anticipated frame synchronization detection (AFSDET) , all subsections in Section 32.6: SAI registers , Section 35.8.1: Host SOFs , Section 35.11.3: FIFO RAM allocation , Section 35.15.43: OTG device V BUS pulsing time register (OTG_DVBUSPULSE) and Section 37.6.1: MCU device ID code .

Added Section 1.1: General information .

Minor text edits across the whole document.

Updated Table 268: OTG_FS/OTG_HS register map and reset values .

Updated caption of Table 258: LTDC pins and signal interface .

Updated Figure 37: FMC memory banks , Figure 427: OTG_FS full-speed block diagram and Figure 451: Receive FIFO packet read .

Table 297. Document revision history (continued)

DateRevisionChanges
20-May-20246

Updated Introduction , Related documents , Section 3.3.1: Flash memory organization , Section 7.3.1: General-purpose I/O (GPIO) , Section 8.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP) , Section 9.3.4: Channel selection , Section 14.2: ADC main features , Section 14.9: Multi ADC mode , Section 16.3: DCMI functional description and its subsections, Example of synchronous timings configuration , Section 19.3.5: RNG operation , Section 20.4: CRYP functional description and its subsections, Section 20.5: CRYP interrupts , Section 29.6.8: I 2 C clock control register (I2C_CCR) , Section 21.2: HASH main features , Section 21.4: HASH functional description and its subsections, Section 21.6.1: HASH control register (HASH_CR) , Section 21.6.4: HASH digest registers , Section 21.6.7: HASH context swap registers , Section 35.15.2: OTG interrupt register (OTG_GOTGINT) , Section 35.15.5: OTG reset register (OTG_GRSTCTL) , Section 35.15.6: OTG core interrupt register (OTG_GINTSTS) , Section 35.15.8: OTG receive status debug read register (OTG_GRXSTSR) , Section 35.15.19: OTG device IN endpoint transmit FIFO x size register (OTG_DIEPTXFx) , and sections 35.15.37 to 35.15.39.

Added Section 18.12.2: D-PHY HS2LP and LP2HS durations , Section 20.3: CRYP implementation , Section 21.3: HASH implementation , sections 35.15.9 to 35.15.11, and Section 39: Important security notice .

Rearranged sequence of registers in Section 32: Serial audio interface (SAI) .

Updated Table 3: Memory mapping versus Boot mode/physical remap , Table 98: External trigger for regular channels , Table 99: External trigger for injected channels , Table 138: RNG interrupt requests , Table 207: SPI register map and reset values , and Table 268: OTG_FS/OTG_HS register map and reset values .

Added Table 8: 512 Kbytes single bank flash memory organization and Table 139: RNG configurations .

Updated figures 65 to 72 in Section 13: Quad-SPI interface (QUADSPI) , Figure 114: LTDC block diagram , Figure 151: PLL block diagram , Figure 156: RNG block diagram , figures 159 to 164 in Section 20: Cryptographic processor (CRYP) , Figure 182: HASH block diagram , Figure 183: Message data swapping feature , Figure 185: Advanced-control timer block diagram , Figure 315: RTC block diagram , Figure 326: TC/TXE behavior when transmitting , Figure 327: Start bit detection when oversampling by 16 or 8 , Figure 340: IrDA SIR ENDEC- block diagram , and Figure 424: CAN frames .

Minor text edits across the whole document.

Index

A

ADC_CCR439
ADC_CDR442
ADC_CR1429
ADC_CR2431
ADC_CSR438
ADC_DR438
ADC_HTR433
ADC_JDRx437
ADC_JOFRx433
ADC_JSQR437
ADC_LTR434
ADC_SMPR1432
ADC_SMPR2433
ADC_SQR1434
ADC_SQR2435
ADC_SQR3436
ADC_SR428

C

CAN_BTR1251
CAN_ESR1250
CAN_FA1R1260
CAN_FFA1R1259
CAN_FIRx1260
CAN_FM1R1258
CAN_FMR1258
CAN_FS1R1259
CAN_IER1249
CAN_MCR1242
CAN_MSR1244
CAN_RDHxR1257
CAN_RDLxR1257
CAN_RDTxR1256
CAN_RF0R1248
CAN_RF1R1248
CAN_RIxR1255
CAN_TDHxR1255
CAN_TDLxR1254
CAN_TDTxR1254
CAN_TIxR1253
CAN_TSR1245
CRC_DR106
CRC_IDR107
CRYP_CR699
CRYP_DIN702
CRYP_DMACR703
CRYP_DOUT702
CRYP_IMSCR704
CRYP_IV0LR710
CRYP_IV0RR710
CRYP_IV1LR711
CRYP_IV1RR711
CRYP_K0LR706
CRYP_K0RR706
CRYP_K1LR707
CRYP_K1RR707
CRYP_K2LR708
CRYP_K2RR708
CRYP_K3LR709
CRYP_K3RR709
CRYP_MISR705
CRYP_RISR704
CRYP_SR701

D

DAC_CR457
DAC_DHR12L1461
DAC_DHR12L2462
DAC_DHR12LD463
DAC_DHR12R1460
DAC_DHR12R2462
DAC_DHR12RD463
DAC_DHR8R1461
DAC_DHR8R2462
DAC_DHR8RD464
DAC_DOR1464
DAC_DOR2464
DAC_SR465
DAC_SWTRIGR460
DBGMCU_APB11600
DBGMCU_APB2_FZ1602
DBGMCU_CR1599
DBGMCU_IDCODE1584
DCMI_CR478
DCMI_CWSIZE487
DCMI_CWSTRT486
DCMI_DR487
DCMI_ESCR485
DCMI_ESUR485
DCMI_ICR484
DCMI_IER482
DCMI_MIS483
DCMI_RIS481
DCMI_SR481
DMA_HIFCR244DSI_LPCR585
DMA_HISR243DSI_LPMCCR614
DMA_LIFCR244DSI_LPMCR585
DMA_LISR242DSI_LVCIDR584
DMA_SxCR245DSI_MCR587
DMA_SxFCR250DSI_PCONFR602
DMA_SxM0AR249DSI_PCR586
DMA_SxM1AR249DSI_PCTLR601
DMA_SxNDTR248DSI_PSR603
DMA_SxPAR249DSI_PTTCR603
DMA2D_AMTCR280DSI_PUCR602
DMA2D_BGCLUTx281DSI_TCCR0597
DMA2D_BGCMAR275DSI_TCCR1597
DMA2D_BGCOLR274DSI_TCCR2598
DMA2D_BGMAR270DSI_TCCR3598
DMA2D_BGOR270DSI_TCCR4599
DMA2D_BGPFCCR273DSI_TCCR5599
DMA2D_CR266DSI_VCCCR617
DMA2D_FGCLUTx281DSI_VCCR589
DMA2D_FGCMAR275DSI_VHBPCCR618
DMA2D_FGCOLR272DSI_VHBPCR590
DMA2D_FGMAR269DSI_VHSACCR617
DMA2D_FGOR269DSI_VHSACR590
DMA2D_FGPFCCR271DSI_VLCCR618
DMA2D_IFCR268DSI_VLCR591
DMA2D_ISR268DSI_VMCCR615
DMA2D_LWR280DSI_VMCR587
DMA2D_NLR279DSI_VNPCCR617
DMA2D_OCOLR276-278DSI_VNPCR590
DMA2D_OMAR278DSI_VPCCR616
DMA2D_OOR279DSI_VPCR589
DMA2D_OPFCCR276DSI_VR583
DSI_CCR583DSI_VSCR613
DSI_CLCR600DSI_VVACCR620
DSI_CLTCR600DSI_VVACR592
DSI_CMCR593DSI_VVBPCCR619
DSI_CR583DSI_VVBPCR592
DSI_DLTCR601DSI_VVFPCCR620
DSI_FIR0610DSI_VVFPC R592
DSI_FIR1612DSI_VVSACCR619
DSI_GHCR595DSI_VVSACR591
DSI_GPDR595DSI_WCFGR621
DSI_GPSR596DSI_WCR622
DSI_GVCIDR587DSI_WIER622
DSI_IER0606DSI_WIFCR624
DSI_IER1609DSI_WISR623
DSI_ISR0604DSI_WPCR0625
DSI_ISR1605DSI_WPCR1627
DSI_LCCCR614DSI_WPCR2629
DSI_LCCR593DSI_WPCR3630
DSI_LCOLCR584DSI_WPCR4630
DSI_LCVCIDR613DSI_WRPCR631
E
ETH_DMABMR1559ETH_PTPSHUR1555
ETH_DMACHRBAR1573ETH_PTPSLR1554
ETH_DMACHRDR1572ETH_PTPSLUR1556
ETH_DMACHTBAR1572ETH_PTPSSR1557
ETH_DMACHTDR1571ETH_PTPTHR1557
ETH_DMAIER1568ETH_PPTTLR1557
ETH_DMAMFBOCR1570EXTI_EMR292
ETH_DMAOMR1565EXTI_FTSR293
ETH_DMARDLAR1561EXTI_IMR292
ETH_DMARPDR1561EXTI_PR294
ETH_DMARSWTR1571EXTI_RTSR293
ETH_DMASR1562EXTI_SWIER294
ETH_DMATDLAR1562F
ETH_DMATPDR1560FLASH_ACR96
ETH_MACA0HR1540FLASH_CR100
ETH_MACA0LR1541FLASH_KEYR97
ETH_MACA1HR1541FLASH_OPTCR101
ETH_MACA1LR1542FLASH_OPTCR1103
ETH_MACA2HR1542FLASH_OPTKEYR98
ETH_MACA2LR1543FLASH_SR98
ETH_MACA3HR1544FMC_BCRx333
ETH_MACA3LR1544FMC_BTRx335
ETH_MACCR1526FMC_BWTRx338
ETH_MACDBGGR1538FMC_ECCR350
ETH_MACFCR1533FMC_PATT349
ETH_MACFFR1529FMC_PCR345
ETH_MACHTHR1530FMC_PMEM348
ETH_MACHTLR1531FMC_SDCMR365
ETH_MACIMR1540FMC_SDCRx362
ETH_MACMIIAR1531FMC_SDRTR366
ETH_MACMIIIDR1532FMC_SDSR368
ETH_MACPMTCSR1537FMC_SDTRx363
ETH_MACRWUFR1535FMC_SR347
ETH_MACSR1539G
ETH_MACVLANTR1534GPIOx_AFRH211
ETH_MMCCR1546GPIOx_AFRL210
ETH_MMCRFAECR1550GPIOx_BSRR208
ETH_MMCRFCECR1550GPIOx_IDR208
ETH_MMCRGUFCCR1551GPIOx_LCKR209
ETH_MMCRIMR1548GPIOx_MODER206
ETH_MMCRIR1546GPIOx_ODR208
ETH_MMCTGFCR1550GPIOx_OSPEEDR207
ETH_MMCTGFMSCCR1549GPIOx_OTYPER206
ETH_MMCTGFSCCR1549GPIOx_PUPDR207
ETH_MMCTIMR1548H
ETH_MMCTIR1547HASH_CR726
ETH_PTPPPSCR1558HASH_CSRx733
ETH_PTPSSIR1553
ETH_PTPTSAR1556
ETH_PTPTSCR1551
ETH_PTPTSHR1554
HASH_DIN728
HASH_HRAx730
HASH_HRx730-731
HASH_IMR731
HASH_SR732
HASH_STR729

I

I2C_CCR1006
I2C_CR1998
I2C_CR21000
I2C_DR1002
I2C_OAR11001
I2C_OAR21002
I2C_SR11002
I2C_SR21005
I2C_TRISE1007
IWDG_KR928
IWDG_PR929
IWDG_RLR930
IWDG_SR930

L

LTDC_AWCR504
LTDC_BCCR507
LTDC_BPCR503
LTDC_CDSR510
LTDC_CPSR510
LTDC_GCR505
LTDC_ICR509
LTDC_IER507
LTDC_ISR508
LTDC_LIPCR509
LTDC_LxBFCR516
LTDC_LxCACR515
LTDC_LxCFBAR517
LTDC_LxCFBLNR518
LTDC_LxCFBLR517
LTDC_LxCKCR514
LTDC_LxCLUTWR518
LTDC_LxCRC511
LTDC_LxDCCR515
LTDC_LxPFCR514
LTDC_LxWHPER512
LTDC_LxWVPER513
LTDC_SRCR506
LTDC_SSCR501
LTDC_TWCR504

O

OTG_CID1329
OTG_DAINIT1356
OTG_DAINITMSK1356
OTG_DCFG1348
OTG_DCTL1350
OTG_DEACHINT1359
OTG_DEACHINTMSK1360
OTG_DIEPCTL01363
OTG_DIEPCTLx1364
OTG_DIEPDMAx1369
OTG_DIEPEPMSK1359
OTG_DIEPINTx1366
OTG_DIEPMSK1353
OTG_DIEPTSIZ01368
OTG_DIEPTSIZx1370
OTG_DIEPTXF01326
OTG_DIEPTXFx1333
OTG_DOEPCTL01371
OTG_DOEPCTLx1375
OTG_DOEPDMAx1375
OTG_DOEPINTx1372
OTG_DOEPMSK1354
OTG_DOEPTSIZ01374
OTG_DOEPTSIZx1377
OTG_DSTS1352
OTG_DTHRCCTL1358
OTG_DTXFSTSx1369
OTG_DVBUSDIS1357
OTG_DVBUSPULSE1357
OTG_GAHBCFG1305
OTG_GCCFG1328
OTG_GINTMSK1318
OTG_GINTSTS1313
OTG_GLPMLCFG1329
OTG_GOTGCTL1300
OTG_GOTGINT1303
OTG_GRSTCTL1310
OTG_GRXFSIZ1325
OTG_GRXSTSP1323-1324
OTG_GRXSTSR1321-1322
OTG_GUSBBCFG1307
OTG_HAINT1337
OTG_HAINTMSK1338
OTG_HCCHARx1341
OTG_HCDMAx1347
OTG_HCFG1334
OTG_HCINTMSKx1345
OTG_HCINTx1343
OTG_HCSPLTx1342
OTG_HCTSIZx1346
OTG_HFIR1335
OTG_HFNUM1336
OTG_HNPTXFSIZ1326
OTG_HNPTXSTS1327
OTG_HPRT1339
OTG_HPTXFSIZ1333
OTG_HPTXSTS1336
OTG_HS_DIEPEACHMSK11360
OTG_HS_DOEPEACHMSK11361
OTG_PCGCCTL1378

P

PWR_CR131
PWR_CSR133

Q

QUADSPI_ABR394
QUADSPI_AR394
QUADSPI_CCR392
QUADSPI_CR386
QUADSPI_DCR389
QUADSPI_DLR391
QUADSPI_DR395
QUADSPI_FCR391
QUADSPI_LPTR397
QUADSPI_PIR396
QUADSPI_PSMAR396
QUADSPI_PSMKR395
QUADSPI_SR390

R

RCC_AHB1ENR165
RCC_AHB1LPENR174
RCC_AHB1RSTR157
RCC_AHB2ENR168
RCC_AHB2LPENR177
RCC_AHB2RSTR159
RCC_AHB3ENR169
RCC_AHB3LPENR177
RCC_AHB3RSTR160
RCC_APB1ENR169
RCC_APB1LPENR178
RCC_APB1RSTR160
RCC_APB2ENR172
RCC_APB2LPENR181
RCC_APB2RSTR163
RCC_BDCR183
RCC_CFGR152
RCC_CIR154
RCC_CR148
RCC_CSR184
RCC_DCKCFGR190
RCC_PLLCFGR150, 187-188
RCC_SSCGR186
RNG_CR645
RNG_DR646
RNG_SR645
RTC_ALRMAR965
RTC_ALRMBR966
RTC_ALRMBSSR974
RTC_BKxR975
RTC_CALIBR963
RTC_CALR970
RTC_CR958
RTC_DR957
RTC_ISR960
RTC_PRER962
RTC_SHIFT968
RTC_SSR967
RTC_TR956
RTC_TSDR969
RTC_TSSSR970
RTC_TSTR969
RTC_WPR967
RTC_WUTR963

S

SAI_ACLRFR1149
SAI_ACR11140
SAI_ACR21142
SAI_ADR1150
SAI_AFR1144
SAI_AIM1146
SAI_ASLOTR1145
SAI_ASR1147
SAI_BCLRFR1160
SAI_BCR11151
SAI_BCR21153
SAI_BDR1161
SAI_BFRCR1155
SAI_BIM1157
SAI_BSLOTR1156
SAI_BSR1158
SDIO_ARG1207
SDIO_CLKCR1205
SDIO_DCOUNT1213
SDIO_DCTRL1210
SDIO_DLEN1210
SDIO_DTIMER1209
SDIO_FIFO1219
SDIO_FIFOCNT1218
SDIO_ICR1214
SDIO_MASK1216
SDIO_POWER1205
SDIO_RESPCMD1208
SDIO_RESPx1208
SDIO_STA1213
SPI_CR11102
SPI_CR21104
SPI_CRCPR1107
SPI_DR1107
SPI_I2SCFGR1109
SPI_I2SPR1110
SPI_RXCRCR1108
SPI_SR1105
SPI_TXCRCR1108
SYSCFG_EXTICR1216
SYSCFG_EXTICR2217
SYSCFG_EXTICR3217
SYSCFG_EXTICR4218
SYSCFG_MEMRMP214

T

TIM2_OR863
TIM5_OR864
TIMx_ARR859, 899, 910, 924
TIMx_BDTR800
TIMx_CCER794, 857, 898, 909
TIMx_CCMR1789, 853, 894, 906
TIMx_CCMR2792, 856
TIMx_CCR1799, 860, 900, 911
TIMx_CCR2799, 860, 900
TIMx_CCR3800, 861
TIMx_CCR4800, 861
TIMx_CNT798, 859, 899, 910, 923
TIMx_CR1780, 844, 888, 903, 920
TIMx_CR2781, 846, 922
TIMx_DCR802, 862
TIMx_DIER785, 849, 891, 904, 922
TIMx_DMAR803, 862
TIMx_EGR788, 852, 894, 905, 923
TIMx_PSC798, 859, 899, 910, 924
TIMx_RCR798
TIMx_SMCR783, 847, 890
TIMx_SR787, 850, 892, 904, 923

U

USART_BRR1054
USART_CR11055
USART_CR21057
USART_CR31058
USART_DR1054
USART_GTPR1060
USART_SR1051

W

WWDG_CFR937
WWDG_CR936
WWDG_SR937

IMPORTANT NOTICE – READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers' products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks . All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2024 STMicroelectronics – All rights reserved