RM0386-STM32F469-479

This document is addressed to application developers. It provides complete information on how to use the STM32F469xx and STM32F479xx microcontroller memory and peripherals.

The STM32F469xx and STM32F479xx constitute a family of microcontrollers based on an Arm ® Cortex ® -M4 core, with different memory sizes, packages and peripherals. They include ST state-of-the-art patented technology.

For information on the Arm ® Cortex ® -M4 with FPU core, refer to the Cortex ® -M4 with FPU Technical Reference Manual.

Available from STMicroelectronics web site www.st.com :

For information on the Arm ® Cortex ® -M4 with FPU, refer to the STM32F3xx/F4xxx Cortex ® -M4 with FPU programming manual (PM0214).

Contents

3.3.3Flash erase and program operations . . . . .85
3.3.4Programming . . . . .87
3.3.5Read-while-write (RWW) . . . . .88
3.4Flash option bytes . . . . .89
3.4.1Option bytes description . . . . .89
3.4.2Programming user option bytes . . . . .91
3.4.3Read protection (RDP) . . . . .91
3.4.4Write protections . . . . .93
3.4.5Proprietary code readout protection (PCROP) . . . . .94
3.5One-time programmable bytes . . . . .95
3.6Interrupts . . . . .96
3.7Flash interface registers . . . . .96
3.7.1Flash access control register (FLASH_ACR) . . . . .96
3.7.2Flash key register (FLASH_KEYR) . . . . .97
3.7.3Flash option key register (FLASH_OPTKEYR) . . . . .98
3.7.4Flash status register (FLASH_SR) . . . . .98
3.7.5Flash control register (FLASH_CR) . . . . .100
3.7.6Flash option control register (FLASH_OPTCR) . . . . .101
3.7.7Flash option control register (FLASH_OPTCR1) . . . . .103
3.7.8Flash interface register map . . . . .104
4CRC calculation unit . . . . .105
4.1CRC introduction . . . . .105
4.2CRC main features . . . . .105
4.3CRC functional description . . . . .105
4.4CRC registers . . . . .106
4.4.1Data register (CRC_DR) . . . . .106
4.4.2Independent data register (CRC_IDR) . . . . .107
4.4.3Control register (CRC_CR) . . . . .107
4.4.4CRC register map . . . . .108
5Power controller (PWR) . . . . .109
5.1Power supplies . . . . .109
5.1.1Independent A/D converter supply and reference voltage . . . . .110
5.1.2Independent USB transceivers supply . . . . .111
5.1.3Independent DSI supply . . . . .112

6 Reset and clock control (RCC) . . . . . 136

6.2.9Watchdog clock .....145
6.2.10Clock-out capability .....146
6.2.11Internal/external clock measurement using TIM5/TIM11 .....146
6.3RCC registers .....148
6.3.1RCC clock control register (RCC_CR) .....148
6.3.2RCC PLL configuration register (RCC_PLLCFGR) .....150
6.3.3RCC clock configuration register (RCC_CFGR) .....152
6.3.4RCC clock interrupt register (RCC_CIR) .....154
6.3.5RCC AHB1 peripheral reset register (RCC_AHB1RSTR) .....157
6.3.6RCC AHB2 peripheral reset register (RCC_AHB2RSTR) .....159
6.3.7RCC AHB3 peripheral reset register (RCC_AHB3RSTR) .....160
6.3.8RCC APB1 peripheral reset register (RCC_APB1RSTR) .....160
6.3.9RCC APB2 peripheral reset register (RCC_APB2RSTR) .....163
6.3.10RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) .....165
6.3.11RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) .....168
6.3.12RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) .....169
6.3.13RCC APB1 peripheral clock enable register (RCC_APB1ENR) .....169
6.3.14RCC APB2 peripheral clock enable register (RCC_APB2ENR) .....172
6.3.15RCC AHB1 peripheral clock enable in low power mode register
(RCC_AHB1LPENR) .....		174
6.3.16RCC AHB2 peripheral clock enable in low power mode register
(RCC_AHB2LPENR) .....		177
6.3.17RCC AHB3 peripheral clock enable in low power mode register
(RCC_AHB3LPENR) .....		177
6.3.18RCC APB1 peripheral clock enable in low power mode register
(RCC_APB1LPENR) .....		178
6.3.19RCC APB2 peripheral clock enabled in low power mode register
(RCC_APB2LPENR) .....		181
6.3.20RCC Backup domain control register (RCC_BDCR) .....183
6.3.21RCC clock control & status register (RCC_CSR) .....184
6.3.22RCC spread spectrum clock generation register (RCC_SSCGR) .....186
6.3.23RCC PLLI2S configuration register (RCC_PLLI2SCFGR) .....187
6.3.24RCC PLL configuration register (RCC_PLLSAICFGR) .....188
6.3.25RCC dedicated clock configuration register (RCC_DCKCFGR) .....190
6.3.26RCC register map .....193
7General-purpose I/Os (GPIO) .....197
7.1Introduction .....197
7.2GPIO main features . . . . .197
7.3GPIO functional description . . . . .197
7.3.1General-purpose I/O (GPIO) . . . . .200
7.3.2I/O pin alternate function multiplexer and mapping . . . . .200
7.3.3I/O port control registers . . . . .201
7.3.4I/O port data registers . . . . .201
7.3.5I/O data bitwise handling . . . . .201
7.3.6GPIO locking mechanism . . . . .202
7.3.7I/O alternate function input/output . . . . .202
7.3.8External interrupt/wakeup lines . . . . .202
7.3.9Input configuration . . . . .202
7.3.10Output configuration . . . . .203
7.3.11Alternate function configuration . . . . .204
7.3.12Analog configuration . . . . .205
7.3.13Using the HSE or LSE oscillator pins as GPIOs . . . . .205
7.3.14Using the GPIO pins in the backup supply domain . . . . .205
7.4GPIO registers . . . . .206
7.4.1GPIO port mode register (GPIOx_MODER) (x = A to K) . . . . .206
7.4.2GPIO port output type register (GPIOx_OTYPER) (x = A to K) . . . . .206
7.4.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to K) . . . . .		207
7.4.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to K) . . . . .		207
7.4.5GPIO port input data register (GPIOx_IDR) (x = A to K) . . . . .208
7.4.6GPIO port output data register (GPIOx_ODR) (x = A to K) . . . . .208
7.4.7GPIO port bit set/reset register (GPIOx_BRR) (x = A to K) . . . . .208
7.4.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to K) . . . . .		209
7.4.9GPIO alternate function low register (GPIOx_AFRL)
(x = A to K) . . . . .		210
7.4.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to J) . . . . .		211
7.4.11GPIO register map . . . . .212
8System configuration controller (SYSCFG) . . . . .214
8.1I/O compensation cell . . . . .214
8.2SYSCFG registers . . . . .214
8.2.1SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .214
8.2.2SYSCFG peripheral mode configuration register (SYSCFG_PMC) . . .215
8.2.3SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . .		216
8.2.4SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . .		217
8.2.5SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . .		217
8.2.6SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . .		218
8.2.7Compensation cell control register (SYSCFG_CMPCR) . . . . .218
8.2.8SYSCFG register maps . . . . .219
9Direct memory access controller (DMA) . . . . .220
9.1DMA introduction . . . . .220
9.2DMA main features . . . . .220
9.3DMA functional description . . . . .222
9.3.1DMA block diagram . . . . .222
9.3.2DMA overview . . . . .222
9.3.3DMA transactions . . . . .223
9.3.4Channel selection . . . . .223
9.3.5Arbiter . . . . .225
9.3.6DMA streams . . . . .225
9.3.7Source, destination and transfer modes . . . . .225
9.3.8Pointer incrementation . . . . .229
9.3.9Circular mode . . . . .230
9.3.10Double-buffer mode . . . . .230
9.3.11Programmable data width, packing/unpacking, endianness . . . . .231
9.3.12Single and burst transfers . . . . .232
9.3.13FIFO . . . . .233
9.3.14DMA transfer completion . . . . .236
9.3.15DMA transfer suspension . . . . .237
9.3.16Flow controller . . . . .238
9.3.17Summary of the possible DMA configurations . . . . .239
9.3.18Stream configuration procedure . . . . .239
9.3.19Error management . . . . .240
9.4DMA interrupts . . . . .241
9.5DMA registers . . . . .242
9.5.1DMA low interrupt status register (DMA_LISR) . . . . .242

10.5.4DMA2D foreground memory address register (DMA2D_FGMAR) . . .269
10.5.5DMA2D foreground offset register (DMA2D_FGOR) . . . . .269
10.5.6DMA2D background memory address register (DMA2D_BGMAR) . .270
10.5.7DMA2D background offset register (DMA2D_BGOR) . . . . .270
10.5.8DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . .271
10.5.9DMA2D foreground color register (DMA2D_FGCOLR) . . . . .272
10.5.10DMA2D background PFC control register (DMA2D_BGPFCCR) . . . . .273
10.5.11DMA2D background color register (DMA2D_BGCOLR) . . . . .274
10.5.12DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR) . . . . .		275
10.5.13DMA2D background CLUT memory address register
(DMA2D_BGCMAR) . . . . .		275
10.5.14DMA2D output PFC control register (DMA2D_OPFCCR) . . . . .276
10.5.15DMA2D output color register (DMA2D_OCOLR) . . . . .276
10.5.16DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .277
10.5.17DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .277
10.5.18DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .278
10.5.19DMA2D output memory address register (DMA2D_OMAR) . . . . .278
10.5.20DMA2D output offset register (DMA2D_OOR) . . . . .279
10.5.21DMA2D number of line register (DMA2D_NLR) . . . . .279
10.5.22DMA2D line watermark register (DMA2D_LWR) . . . . .280
10.5.23DMA2D AHB master timer configuration register (DMA2D_AMTCR) .280
10.5.24DMA2D foreground CLUT (DMA2D_FGCLUTx) . . . . .281
10.5.25DMA2D background CLUT (DMA2D_BGCLUTx) . . . . .281
10.5.26DMA2D register map . . . . .282
11Interrupts and events . . . . .284
11.1Nested vectored interrupt controller (NVIC) . . . . .284
11.1.1NVIC features . . . . .284
11.1.2SysTick calibration value register . . . . .284
11.1.3Interrupt and exception vectors . . . . .284
11.2External interrupt/event controller (EXTI) . . . . .284
11.2.1EXTI main features . . . . .288
11.2.2EXTI block diagram . . . . .289
11.2.3Wake-up event management . . . . .289
11.2.4Functional description . . . . .289
11.2.5External interrupt/event line mapping . . . . .291
11.3EXTI registers . . . . .292
11.3.1Interrupt mask register (EXTI_IMR) . . . . .292
11.3.2Event mask register (EXTI_EMR) . . . . .292
11.3.3Rising trigger selection register (EXTI_RTSR) . . . . .293
11.3.4Falling trigger selection register (EXTI_FTSR) . . . . .293
11.3.5Software interrupt event register (EXTI_SWIER) . . . . .294
11.3.6Pending register (EXTI_PR) . . . . .294
11.3.7EXTI register map . . . . .295
12Flexible memory controller (FMC) . . . . .296
12.1Introduction . . . . .296
12.2FMC main features . . . . .296
12.3FMC block diagram . . . . .297
12.4AHB interface . . . . .298
12.4.1Supported memories and transactions . . . . .298
12.5External device address mapping . . . . .299
12.5.1NOR/PSRAM address mapping . . . . .300
12.5.2NAND flash memory address mapping . . . . .301
12.5.3SDRAM address mapping . . . . .302
12.6NOR flash/PSRAM controller . . . . .305
12.6.1External memory interface signals . . . . .306
12.6.2Supported memories and transactions . . . . .308
12.6.3General timing rules . . . . .310
12.6.4NOR flash/PSRAM controller asynchronous transactions . . . . .310
12.6.5Synchronous transactions . . . . .327
12.6.6NOR/PSRAM controller registers . . . . .333
12.7NAND flash controller . . . . .340
12.7.1External memory interface signals . . . . .340
12.7.2NAND flash supported memories and transactions . . . . .341
12.7.3Timing diagrams for NAND flash memory . . . . .342
12.7.4NAND flash operations . . . . .343
12.7.5NAND flash prewait functionality . . . . .343
12.7.6Computation of the error correction code (ECC)
in NAND flash memory . . . . .		344
12.7.7NAND flash controller registers . . . . .345
12.8SDRAM controller . . . . .351
12.8.1SDRAM controller main features . . . . .351
12.8.2SDRAM External memory interface signals . . . . .351
12.8.3SDRAM controller functional description . . . . .352
12.8.4Low-power modes . . . . .358
12.8.5SDRAM controller registers . . . . .362
12.8.6FMC register map . . . . .368
13Quad-SPI interface (QUADSPI) . . . . .371
13.1Introduction . . . . .371
13.2QUADSPI main features . . . . .371
13.3QUADSPI functional description . . . . .371
13.3.1QUADSPI block diagram . . . . .371
13.3.2QUADSPI pins . . . . .372
13.3.3QUADSPI command sequence . . . . .372
13.3.4QUADSPI signal interface protocol modes . . . . .375
13.3.5QUADSPI indirect mode . . . . .377
13.3.6QUADSPI automatic status-polling mode . . . . .379
13.3.7QUADSPI memory-mapped mode . . . . .379
13.3.8QUADSPI flash memory configuration . . . . .380
13.3.9QUADSPI delayed data sampling . . . . .380
13.3.10QUADSPI configuration . . . . .380
13.3.11QUADSPI use . . . . .381
13.3.12Sending the instruction only once . . . . .383
13.3.13QUADSPI error management . . . . .383
13.3.14QUADSPI busy bit and abort functionality . . . . .383
13.3.15NCS behavior . . . . .384
13.4QUADSPI interrupts . . . . .386
13.5QUADSPI registers . . . . .386
13.5.1QUADSPI control register (QUADSPI_CR) . . . . .386
13.5.2QUADSPI device configuration register (QUADSPI_DCR) . . . . .389
13.5.3QUADSPI status register (QUADSPI_SR) . . . . .390
13.5.4QUADSPI flag clear register (QUADSPI_FCR) . . . . .391
13.5.5QUADSPI data length register (QUADSPI_DLR) . . . . .391
13.5.6QUADSPI communication configuration register (QUADSPI_CCR) . . . . .392
13.5.7QUADSPI address register (QUADSPI_AR) . . . . .394
13.5.8QUADSPI alternate-byte register (QUADSPI_ABR) . . . . .394
13.5.9QUADSPI data register (QUADSPI_DR) . . . . .395
14.10Temperature sensor . . . . .425
14.11Battery charge monitoring . . . . .426
14.12ADC interrupts . . . . .427
14.13ADC registers . . . . .428
14.13.1ADC status register (ADC_SR) . . . . .428
14.13.2ADC control register 1 (ADC_CR1) . . . . .429
14.13.3ADC control register 2 (ADC_CR2) . . . . .431
14.13.4ADC sample time register 1 (ADC_SMPR1) . . . . .432
14.13.5ADC sample time register 2 (ADC_SMPR2) . . . . .433
14.13.6ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) . . . . .433
14.13.7ADC watchdog higher threshold register (ADC_HTR) . . . . .433
14.13.8ADC watchdog lower threshold register (ADC_LTR) . . . . .434
14.13.9ADC regular sequence register 1 (ADC_SQR1) . . . . .434
14.13.10ADC regular sequence register 2 (ADC_SQR2) . . . . .435
14.13.11ADC regular sequence register 3 (ADC_SQR3) . . . . .436
14.13.12ADC injected sequence register (ADC_JSQR) . . . . .437
14.13.13ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . .437
14.13.14ADC regular data register (ADC_DR) . . . . .438
14.13.15ADC Common status register (ADC_CSR) . . . . .438
14.13.16ADC common control register (ADC_CCR) . . . . .439
14.13.17ADC common regular data register for dual and triple modes
(ADC_CDR) . . . . .		442
14.13.18ADC register map . . . . .442
15Digital-to-analog converter (DAC) . . . . .445
15.1DAC introduction . . . . .445
15.2DAC main features . . . . .445
15.3DAC functional description . . . . .446
15.3.1DAC channel enable . . . . .446
15.3.2DAC output buffer enable . . . . .447
15.3.3DAC data format . . . . .447
15.3.4DAC conversion . . . . .448
15.3.5DAC output voltage . . . . .449
15.3.6DAC trigger selection . . . . .449
15.3.7DMA request . . . . .450
15.3.8Noise generation . . . . .450
15.3.9Triangle-wave generation . . . . .451
15.4Dual DAC channel conversion . . . . .452
15.4.1Independent trigger without wave generation . . . . .453
15.4.2Independent trigger with single LFSR generation . . . . .453
15.4.3Independent trigger with different LFSR generation . . . . .453
15.4.4Independent trigger with single triangle generation . . . . .454
15.4.5Independent trigger with different triangle generation . . . . .454
15.4.6Simultaneous software start . . . . .454
15.4.7Simultaneous trigger without wave generation . . . . .455
15.4.8Simultaneous trigger with single LFSR generation . . . . .455
15.4.9Simultaneous trigger with different LFSR generation . . . . .455
15.4.10Simultaneous trigger with single triangle generation . . . . .456
15.4.11Simultaneous trigger with different triangle generation . . . . .456
15.5DAC registers . . . . .457
15.5.1DAC control register (DAC_CR) . . . . .457
15.5.2DAC software trigger register (DAC_SWTRIGR) . . . . .460
15.5.3DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . .		460
15.5.4DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . .		461
15.5.5DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . .		461
15.5.6DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . .		462
15.5.7DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2) . . . . .		462
15.5.8DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . .		462
15.5.9Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . .		463
15.5.10DUAL DAC 12-bit left aligned data holding register
(DAC_DHR12LD) . . . . .		463
15.5.11DUAL DAC 8-bit right aligned data holding register
(DAC_DHR8RD) . . . . .		464
15.5.12DAC channel1 data output register (DAC_DOR1) . . . . .464
15.5.13DAC channel2 data output register (DAC_DOR2) . . . . .464
15.5.14DAC status register (DAC_SR) . . . . .465
15.5.15DAC register map . . . . .466
16Digital camera interface (DCMI) . . . . .467
16.1Introduction .....467
16.2DCMI main features .....467
16.3DCMI functional description .....467
16.3.1DCMI block diagram .....468
16.3.2DCMI pins .....468
16.3.3DCMI clocks .....468
16.3.4DCMI DMA interface .....469
16.3.5DCMI physical interface .....469
16.3.6DCMI synchronization .....471
16.3.7DCMI capture modes .....473
16.3.8DCMI crop feature .....474
16.3.9DCMI JPEG format .....475
16.3.10DCMI FIFO .....475
16.3.11DCMI data format description .....476
16.4DCMI interrupts .....478
16.5DCMI registers .....478
16.5.1DCMI control register (DCMI_CR) .....478
16.5.2DCMI status register (DCMI_SR) .....481
16.5.3DCMI raw interrupt status register (DCMI_RIS) .....481
16.5.4DCMI interrupt enable register (DCMI_IER) .....482
16.5.5DCMI masked interrupt status register (DCMI_MIS) .....483
16.5.6DCMI interrupt clear register (DCMI_ICR) .....484
16.5.7DCMI embedded synchronization code register (DCMI_ESCR) .....485
16.5.8DCMI embedded synchronization unmask register (DCMI_ESUR) .....485
16.5.9DCMI crop window start (DCMI_CWSTRT) .....486
16.5.10DCMI crop window size (DCMI_CWSIZE) .....487
16.5.11DCMI data register (DCMI_DR) .....487
16.5.12DCMI register map .....488
17LCD-TFT display controller (LTDC) .....489
17.1Introduction .....489
17.2LTDC main features .....489
17.3LTDC functional description .....490
17.3.1LTDC block diagram .....490
17.3.2LTDC pins and external signal interface .....490
17.3.3LTDC reset and clocks .....491
17.4LTDC programmable parameters . . . . .492
17.4.1LTDC global configuration parameters . . . . .492
17.4.2Layer programmable parameters . . . . .495
17.5LTDC interrupts . . . . .500
17.6LTDC programming procedure . . . . .500
17.7LTDC registers . . . . .501
17.7.1LTDC synchronization size configuration register (LTDC_SSCR) . . . . .501
17.7.2LTDC back porch configuration register (LTDC_BPCR) . . . . .503
17.7.3LTDC active width configuration register (LTDC_AWCR) . . . . .504
17.7.4LTDC total width configuration register (LTDC_TWCR) . . . . .504
17.7.5LTDC global control register (LTDC_GCR) . . . . .505
17.7.6LTDC shadow reload configuration register (LTDC_SRCR) . . . . .506
17.7.7LTDC background color configuration register (LTDC_BCCR) . . . . .507
17.7.8LTDC interrupt enable register (LTDC_IER) . . . . .507
17.7.9LTDC interrupt status register (LTDC_ISR) . . . . .508
17.7.10LTDC Interrupt clear register (LTDC_ICR) . . . . .509
17.7.11LTDC line interrupt position configuration register (LTDC_LIPCR) . . . . .509
17.7.12LTDC current position status register (LTDC_CPSR) . . . . .510
17.7.13LTDC current display status register (LTDC_CDSR) . . . . .510
17.7.14LTDC layer x control register (LTDC_LxCR) . . . . .511
17.7.15LTDC layer x window horizontal position configuration register
(LTDC_LxWHPCR) . . . . .		512
17.7.16LTDC layer x window vertical position configuration register
(LTDC_LxWVPCR) . . . . .		513
17.7.17LTDC layer x color keying configuration register
(LTDC_LxCKCR) . . . . .		514
17.7.18LTDC layer x pixel format configuration register
(LTDC_LxPFCR) . . . . .		514
17.7.19LTDC layer x constant alpha configuration register
(LTDC_LxCACR) . . . . .		515
17.7.20LTDC layer x default color configuration register
(LTDC_LxDCCR) . . . . .		515
17.7.21LTDC layer x blending factors configuration register
(LTDC_LxBFCR) . . . . .		516
17.7.22LTDC layer x color frame buffer address register
(LTDC_LxCFBAR) . . . . .		517
17.7.23LTDC layer x color frame buffer length register
(LTDC_LxCFBLR) . . . . .		517
17.7.24LTDC layer x color frame buffer line number register
(LTDC_LxCFBLNR) . . . . .		518
17.7.25LTDC layer x CLUT write register (LTDC_LxCLUTWR)518
17.7.26LTDC register map519
18DSI Host (DSI)522
18.1Introduction522
18.2Standard and references522
18.3DSI Host main features523
18.4DSI Host functional description524
18.4.1General description524
18.4.2Supported resolutions and frame rates524
18.4.3System level architecture525
18.5Functional description: video mode on LTDC interface527
18.5.1Video transmission mode528
18.5.2Updating the LTDC interface configuration in video mode530
18.6Functional description: adapted command mode on LTDC interface532
18.7Functional description: APB slave generic interface536
18.7.1Packet transmission using the generic interface536
18.8Functional description: timeout counters540
18.8.1Contention error detection timeout counters540
18.8.2Peripheral response timeout counters541
18.9Functional description: transmission of commands546
18.9.1Transmission of commands in video mode546
18.9.2Transmission of commands in low-power mode548
18.9.3Transmission of commands in high-speed552
18.9.4Read command transmission552
18.9.5Clock lane in low-power mode553
18.10Functional description: virtual channels555
18.11Functional description: video mode pattern generator556
18.11.1Color bar pattern556
18.11.2Color coding558
18.11.3BER testing pattern558
18.11.4Video mode pattern generator resolution559
18.12Functional description: D-PHY management560
18.12.1D-PHY configuration560
18.12.2D-PHY HS2LP and LP2HS durations562
18.12.3Special D-PHY operations562
18.12.4Special low-power D-PHY functions . . . . .562
18.12.5DSI PLL control . . . . .563
18.12.6Regulator control . . . . .564
18.13Functional description: interrupts and errors . . . . .564
18.13.1DSI Wrapper interrupts . . . . .564
18.13.2DSI Host interrupts and errors . . . . .565
18.14Programing procedure . . . . .572
18.14.1Programing procedure overview . . . . .572
18.14.2Configuring the D-PHY parameters . . . . .572
18.14.3Configuring the DSI Host timing . . . . .573
18.14.4Configuring flow control and DBI interface . . . . .574
18.14.5Configuring the DSI Host LTDC interface . . . . .574
18.14.6Configuring the video mode . . . . .575
18.14.7Configuring the adapted command mode . . . . .579
18.14.8Configuring the video mode pattern generator . . . . .579
18.14.9Managing ULPM . . . . .580
18.15DSI Host registers . . . . .583
18.15.1DSI Host version register (DSI_VR) . . . . .583
18.15.2DSI Host control register (DSI_CR) . . . . .583
18.15.3DSI Host clock control register (DSI_CCR) . . . . .583
18.15.4DSI Host LTDC VCID register (DSI_LVCIDR) . . . . .584
18.15.5DSI Host LTDC color coding register (DSI_LCOLCR) . . . . .584
18.15.6DSI Host LTDC polarity configuration register (DSI_LPCR) . . . . .585
18.15.7DSI Host low-power mode configuration register (DSI_LPMCR) . . . . .585
18.15.8DSI Host protocol configuration register (DSI_PCR) . . . . .586
18.15.9DSI Host generic VCID register (DSI_GVCIDR) . . . . .587
18.15.10DSI Host mode configuration register (DSI_MCR) . . . . .587
18.15.11DSI Host video mode configuration register (DSI_VMCR) . . . . .587
18.15.12DSI Host video packet configuration register (DSI_VPCR) . . . . .589
18.15.13DSI Host video chunks configuration register (DSI_VCCR) . . . . .589
18.15.14DSI Host video null packet configuration register (DSI_VNPCR) . . . . .590
18.15.15DSI Host video HSA configuration register (DSI_VHSACR) . . . . .590
18.15.16DSI Host video HBP configuration register (DSI_VHBPCR) . . . . .590
18.15.17DSI Host video line configuration register (DSI_VLCR) . . . . .591
18.15.18DSI Host video VSA configuration register (DSI_VVSACR) . . . . .591
18.15.19DSI Host video VBP configuration register (DSI_VVBPCR) . . . . .592
18.15.20DSI Host video VFP configuration register (DSI_VVPCR) . . . . .592
18.15.21 DSI Host video VA configuration register (DSI_VVACR) . . . . .592
18.15.22 DSI Host LTDC command configuration register (DSI_LCCR) . . . . .593
18.15.23 DSI Host command mode configuration register (DSI_CMCR) . . . . .593
18.15.24 DSI Host generic header configuration register (DSI_GHCR) . . . . .595
18.15.25 DSI Host generic payload data register (DSI_GPDR) . . . . .595
18.15.26 DSI Host generic packet status register (DSI_GPSR) . . . . .596
18.15.27 DSI Host timeout counter configuration register 0 (DSI_TCCR0) . . . . .597
18.15.28 DSI Host timeout counter configuration register 1 (DSI_TCCR1) . . . . .597
18.15.29 DSI Host timeout counter configuration register 2 (DSI_TCCR2) . . . . .598
18.15.30 DSI Host timeout counter configuration register 3 (DSI_TCCR3) . . . . .598
18.15.31 DSI Host timeout counter configuration register 4 (DSI_TCCR4) . . . . .599
18.15.32 DSI Host timeout counter configuration register 5 (DSI_TCCR5) . . . . .599
18.15.33 DSI Host clock lane configuration register (DSI_CLCR) . . . . .600
18.15.34 DSI Host clock lane timer configuration register (DSI_CLTCR) . . . . .600
18.15.35 DSI Host data lane timer configuration register (DSI_DLTCR) . . . . .601
18.15.36 DSI Host PHY control register (DSI_PCTLR) . . . . .601
18.15.37 DSI Host PHY configuration register (DSI_PCONFRR) . . . . .602
18.15.38 DSI Host PHY ULPS control register (DSI_PUCR) . . . . .602
18.15.39 DSI Host PHY TX triggers configuration register (DSI_PTTCCR) . . . . .603
18.15.40 DSI Host PHY status register (DSI_PSR) . . . . .603
18.15.41 DSI Host interrupt and status register 0 (DSI_ISR0) . . . . .604
18.15.42 DSI Host interrupt and status register 1 (DSI_ISR1) . . . . .605
18.15.43 DSI Host interrupt enable register 0 (DSI_IER0) . . . . .606
18.15.44 DSI Host interrupt enable register 1 (DSI_IER1) . . . . .609
18.15.45 DSI Host force interrupt register 0 (DSI_FIR0) . . . . .610
18.15.46 DSI Host force interrupt register 1 (DSI_FIR1) . . . . .612
18.15.47 DSI Host video shadow control register (DSI_VSCR) . . . . .613
18.15.48 DSI Host LTDC current VCID register (DSI_LCVCIDR) . . . . .613
18.15.49 DSI Host LTDC current color coding register (DSI_LCCCR) . . . . .614
18.15.50 DSI Host low-power mode current configuration register
(DSI_LPMCCR) . . . . .		614
18.15.51 DSI Host video mode current configuration register
(DSI_VMCCR) . . . . .		615
18.15.52 DSI Host video packet current configuration register
(DSI_VPCCR) . . . . .		616
18.15.53 DSI Host video chunks current configuration register
(DSI_VCCCR) . . . . .		617
19.3.7Error management . . . . .642
19.3.8RNG low-power use . . . . .643
19.4RNG interrupts . . . . .643
19.5RNG processing time . . . . .643
19.6RNG entropy source validation . . . . .644
19.6.1Introduction . . . . .644
19.6.2Validation conditions . . . . .644
19.6.3Data collection . . . . .644
19.7RNG registers . . . . .645
19.7.1RNG control register (RNG_CR) . . . . .645
19.7.2RNG status register (RNG_SR) . . . . .645
19.7.3RNG data register (RNG_DR) . . . . .646
19.7.4RNG register map . . . . .647
20Cryptographic processor (CRYP) . . . . .648
20.1Introduction . . . . .648
20.2CRYP main features . . . . .648
20.3CRYP implementation . . . . .649
20.4CRYP functional description . . . . .650
20.4.1CRYP block diagram . . . . .650
20.4.2CRYP internal signals . . . . .650
20.4.3CRYP DES/TDES cryptographic core . . . . .651
20.4.4CRYP AES cryptographic core . . . . .652
20.4.5CRYP procedure to perform a cipher operation . . . . .658
20.4.6CRYP busy state . . . . .660
20.4.7Preparing the CRYP AES key for decryption . . . . .661
20.4.8CRYP stealing and data padding . . . . .661
20.4.9CRYP suspend/resume operations . . . . .663
20.4.10CRYP DES/TDES basic chaining modes (ECB, CBC) . . . . .664
20.4.11CRYP AES basic chaining modes (ECB, CBC) . . . . .669
20.4.12CRYP AES counter mode (AES-CTR) . . . . .674
20.4.13CRYP AES Galois/counter mode (GCM) . . . . .678
20.4.14CRYP AES Galois message authentication code (GMAC) . . . . .683
20.4.15CRYP AES Counter with CBC-MAC (CCM) . . . . .684
20.4.16CRYP data registers and data swapping . . . . .689
20.4.17CRYP key registers . . . . .693
20.4.18CRYP initialization vector registers . . . . .693
20.4.19CRYP DMA interface . . . . .694
20.4.20CRYP error management . . . . .696
20.5CRYP interrupts . . . . .697
20.6CRYP processing time . . . . .698
20.7CRYP registers . . . . .699
20.7.1CRYP control register (CRYP_CR) . . . . .699
20.7.2CRYP status register (CRYP_SR) . . . . .701
20.7.3CRYP data input register (CRYP_DIN) . . . . .702
20.7.4CRYP data output register (CRYP_DOUT) . . . . .702
20.7.5CRYP DMA control register (CRYP_DMACR) . . . . .703
20.7.6CRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . .704
20.7.7CRYP raw interrupt status register (CRYP_RISR) . . . . .704
20.7.8CRYP masked interrupt status register (CRYP_MISR) . . . . .705
20.7.9CRYP key register 0L (CRYP_K0LR) . . . . .706
20.7.10CRYP key register 0R (CRYP_K0RR) . . . . .706
20.7.11CRYP key register 1L (CRYP_K1LR) . . . . .707
20.7.12CRYP key register 1R (CRYP_K1RR) . . . . .707
20.7.13CRYP key register 2L (CRYP_K2LR) . . . . .708
20.7.14CRYP key register 2R (CRYP_K2RR) . . . . .708
20.7.15CRYP key register 3L (CRYP_K3LR) . . . . .709
20.7.16CRYP key register 3R (CRYP_K3RR) . . . . .709
20.7.17CRYP initialization vector register 0L (CRYP_IV0LR) . . . . .710
20.7.18CRYP initialization vector register 0R (CRYP_IV0RR) . . . . .710
20.7.19CRYP initialization vector register 1L (CRYP_IV1LR) . . . . .711
20.7.20CRYP initialization vector register 1R (CRYP_IV1RR) . . . . .711
20.7.21CRYP register map . . . . .711
21Hash processor (HASH) . . . . .713
21.1Introduction . . . . .713
21.2HASH main features . . . . .713
21.3HASH implementation . . . . .714
21.4HASH functional description . . . . .714
21.4.1HASH block diagram . . . . .714
21.4.2HASH internal signals . . . . .715
21.4.3About secure hash algorithms . . . . .715
21.4.4Message data feeding . . . . .715
21.4.5Message digest computing . . . . .717
21.4.6Message padding . . . . .718
21.4.7HMAC operation . . . . .720
21.4.8HASH suspend/resume operations . . . . .722
21.4.9HASH DMA interface . . . . .724
21.4.10HASH error management . . . . .724
21.4.11HASH processing time . . . . .724
21.5HASH interrupts . . . . .725
21.6HASH registers . . . . .726
21.6.1HASH control register (HASH_CR) . . . . .726
21.6.2HASH data input register (HASH_DIN) . . . . .728
21.6.3HASH start register (HASH_STR) . . . . .729
21.6.4HASH digest registers . . . . .730
21.6.5HASH interrupt enable register (HASH_IMR) . . . . .731
21.6.6HASH status register (HASH_SR) . . . . .732
21.6.7HASH context swap registers . . . . .732
21.6.8HASH register map . . . . .733
22Advanced-control timers (TIM1&TIM8) . . . . .735
22.1TIM1&TIM8 introduction . . . . .735
22.2TIM1&TIM8 main features . . . . .735
22.3TIM1&TIM8 functional description . . . . .737
22.3.1Time-base unit . . . . .737
22.3.2Counter modes . . . . .739
22.3.3Repetition counter . . . . .748
22.3.4Clock selection . . . . .751
22.3.5Capture/compare channels . . . . .754
22.3.6Input capture mode . . . . .757
22.3.7PWM input mode . . . . .758
22.3.8Forced output mode . . . . .758
22.3.9Output compare mode . . . . .759
22.3.10PWM mode . . . . .760
22.3.11Complementary outputs and dead-time insertion . . . . .763
22.3.12Using the break function . . . . .765
22.3.13Clearing the OCxREF signal on an external event . . . . .768
22.3.146-step PWM generation . . . . .769
22.3.15One-pulse mode . . . . .770
22.3.16Encoder interface mode . . . . .771
22.3.17Timer input XOR function . . . . .774
22.3.18Interfacing with Hall sensors . . . . .774
22.3.19TIMx and external trigger synchronization . . . . .776
22.3.20Timer synchronization . . . . .779
22.3.21Debug mode . . . . .779
22.4TIM1&TIM8 registers . . . . .780
22.4.1TIM1&TIM8 control register 1 (TIMx_CR1) . . . . .780
22.4.2TIM1&TIM8 control register 2 (TIMx_CR2) . . . . .781
22.4.3TIM1&TIM8 slave mode control register (TIMx_SMCR) . . . . .783
22.4.4TIM1&TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . .785
22.4.5TIM1&TIM8 status register (TIMx_SR) . . . . .787
22.4.6TIM1&TIM8 event generation register (TIMx_EGR) . . . . .788
22.4.7TIM1&TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . . . .789
22.4.8TIM1&TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . . . .792
22.4.9TIM1&TIM8 capture/compare enable register (TIMx_CCER) . . . . .794
22.4.10TIM1&TIM8 counter (TIMx_CNT) . . . . .798
22.4.11TIM1&TIM8 prescaler (TIMx_PSC) . . . . .798
22.4.12TIM1&TIM8 auto-reload register (TIMx_ARR) . . . . .798
22.4.13TIM1&TIM8 repetition counter register (TIMx_RCR) . . . . .798
22.4.14TIM1&TIM8 capture/compare register 1 (TIMx_CCR1) . . . . .799
22.4.15TIM1&TIM8 capture/compare register 2 (TIMx_CCR2) . . . . .799
22.4.16TIM1&TIM8 capture/compare register 3 (TIMx_CCR3) . . . . .800
22.4.17TIM1&TIM8 capture/compare register 4 (TIMx_CCR4) . . . . .800
22.4.18TIM1&TIM8 break and dead-time register (TIMx_BDTR) . . . . .800
22.4.19TIM1&TIM8 DMA control register (TIMx_DCR) . . . . .802
22.4.20TIM1&TIM8 DMA address for full transfer (TIMx_DMAR) . . . . .803
22.4.21TIM1&TIM8 register map . . . . .804
23General-purpose timers (TIM2 to TIM5) . . . . .806
23.1TIM2 to TIM5 introduction . . . . .806
23.2TIM2 to TIM5 main features . . . . .806
23.3TIM2 to TIM5 functional description . . . . .807
23.3.1Time-base unit . . . . .807
23.3.2Counter modes . . . . .809
23.3.3Clock selection . . . . .818
23.3.4Capture/compare channels . . . . .821
23.3.5Input capture mode . . . . .823
23.3.6PWM input mode . . . . .824
23.3.7Forced output mode . . . . .825
23.3.8Output compare mode . . . . .825
23.3.9PWM mode . . . . .827
23.3.10One-pulse mode . . . . .830
23.3.11Clearing the OCxREF signal on an external event . . . . .831
23.3.12Encoder interface mode . . . . .832
23.3.13Timer input XOR function . . . . .834
23.3.14Timers and external trigger synchronization . . . . .834
23.3.15Timer synchronization . . . . .838
23.3.16Debug mode . . . . .843
23.4TIM2 to TIM5 registers . . . . .844
23.4.1TIMx control register 1 (TIMx_CR1) . . . . .844
23.4.2TIMx control register 2 (TIMx_CR2) . . . . .846
23.4.3TIMx slave mode control register (TIMx_SMCR) . . . . .847
23.4.4TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . .849
23.4.5TIMx status register (TIMx_SR) . . . . .850
23.4.6TIMx event generation register (TIMx_EGR) . . . . .852
23.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . .853
23.4.8TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . .856
23.4.9TIMx capture/compare enable register (TIMx_CCER) . . . . .857
23.4.10TIMx counter (TIMx_CNT) . . . . .859
23.4.11TIMx prescaler (TIMx_PSC) . . . . .859
23.4.12TIMx auto-reload register (TIMx_ARR) . . . . .859
23.4.13TIMx capture/compare register 1 (TIMx_CCR1) . . . . .860
23.4.14TIMx capture/compare register 2 (TIMx_CCR2) . . . . .860
23.4.15TIMx capture/compare register 3 (TIMx_CCR3) . . . . .861
23.4.16TIMx capture/compare register 4 (TIMx_CCR4) . . . . .861
23.4.17TIMx DMA control register (TIMx_DCR) . . . . .862
23.4.18TIMx DMA address for full transfer (TIMx_DMAR) . . . . .862
23.4.19TIM2 option register (TIM2_OR) . . . . .863
23.4.20TIM5 option register (TIM5_OR) . . . . .864
23.4.21TIMx register map . . . . .865
24General-purpose timers (TIM9 to TIM14) . . . . .867
24.5.4TIM10/11/13/14 event generation register (TIMx_EGR) . . . . .905
24.5.5TIM10/11/13/14 capture/compare mode register 1
(TIMx_CCMR1) . . . . .		906
24.5.6TIM10/11/13/14 capture/compare enable register
(TIMx_CCER) . . . . .		909
24.5.7TIM10/11/13/14 counter (TIMx_CNT) . . . . .910
24.5.8TIM10/11/13/14 prescaler (TIMx_PSC) . . . . .910
24.5.9TIM10/11/13/14 auto-reload register (TIMx_ARR) . . . . .910
24.5.10TIM10/11/13/14 capture/compare register 1 (TIMx_CCR1) . . . . .911
24.5.11TIM11 option register 1 (TIM11_OR) . . . . .911
24.5.12TIM10/11/13/14 register map . . . . .912
25Basic timers (TIM6&TIM7) . . . . .914
25.1TIM6&TIM7 introduction . . . . .914
25.2TIM6&TIM7 main features . . . . .914
25.3TIM6&TIM7 functional description . . . . .915
25.3.1Time-base unit . . . . .915
25.3.2Counting mode . . . . .917
25.3.3Clock source . . . . .919
25.3.4Debug mode . . . . .920
25.4TIM6&TIM7 registers . . . . .920
25.4.1TIM6&TIM7 control register 1 (TIMx_CR1) . . . . .920
25.4.2TIM6&TIM7 control register 2 (TIMx_CR2) . . . . .922
25.4.3TIM6&TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . .922
25.4.4TIM6&TIM7 status register (TIMx_SR) . . . . .923
25.4.5TIM6&TIM7 event generation register (TIMx_EGR) . . . . .923
25.4.6TIM6&TIM7 counter (TIMx_CNT) . . . . .923
25.4.7TIM6&TIM7 prescaler (TIMx_PSC) . . . . .924
25.4.8TIM6&TIM7 auto-reload register (TIMx_ARR) . . . . .924
25.4.9TIM6&TIM7 register map . . . . .925
26Independent watchdog (IWDG) . . . . .926
26.1IWDG introduction . . . . .926
26.2IWDG main features . . . . .926
26.3IWDG functional description . . . . .926
26.3.1Hardware watchdog . . . . .926
26.3.2Register access protection . . . . .926
28.3.13Tamper detection . . . . .951
28.3.14Calibration clock output . . . . .953
28.3.15Alarm output . . . . .953
28.4RTC and low power modes . . . . .954
28.5RTC interrupts . . . . .954
28.6RTC registers . . . . .956
28.6.1RTC time register (RTC_TR) . . . . .956
28.6.2RTC date register (RTC_DR) . . . . .957
28.6.3RTC control register (RTC_CR) . . . . .958
28.6.4RTC initialization and status register (RTC_ISR) . . . . .960
28.6.5RTC prescaler register (RTC_PRER) . . . . .962
28.6.6RTC wakeup timer register (RTC_WUTR) . . . . .963
28.6.7RTC calibration register (RTC_CALIBR) . . . . .963
28.6.8RTC alarm A register (RTC_ALRMAR) . . . . .965
28.6.9RTC alarm B register (RTC_ALRMBR) . . . . .966
28.6.10RTC write protection register (RTC_WPR) . . . . .967
28.6.11RTC sub second register (RTC_SSR) . . . . .967
28.6.12RTC shift control register (RTC_SHIFTTR) . . . . .968
28.6.13RTC time stamp time register (RTC_TSTR) . . . . .969
28.6.14RTC time stamp date register (RTC_TSDR) . . . . .969
28.6.15RTC timestamp sub second register (RTC_TSSSR) . . . . .970
28.6.16RTC calibration register (RTC_CALR) . . . . .970
28.6.17RTC tamper and alternate function configuration register
(RTC_TAFCR) . . . . .		971
28.6.18RTC alarm A sub second register (RTC_ALRMASSR) . . . . .973
28.6.19RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .974
28.6.20RTC backup registers (RTC_BKPxR) . . . . .975
28.6.21RTC register map . . . . .976
29Inter-integrated circuit (I 2 C) interface . . . . .978
29.1I 2 C introduction . . . . .978
29.2I 2 C main features . . . . .979
29.3I 2 C functional description . . . . .980
29.3.1Mode selection . . . . .980
29.3.2I2C slave mode . . . . .981
29.3.3I2C master mode . . . . .984
29.3.4Error conditions . . . . .989

30 Universal synchronous receiver transmitter (USART)
/universal asynchronous receiver transmitter (UART) ..... 1010

30.4.11Smartcard .....1042
30.4.12IrDA SIR ENDEC block .....1044
30.4.13Continuous communication using DMA .....1046
30.4.14Hardware flow control .....1048
30.5USART interrupts .....1050
30.6USART registers .....1051
30.6.1Status register (USART_SR) .....1051
30.6.2Data register (USART_DR) .....1054
30.6.3Baud rate register (USART_BRR) .....1054
30.6.4Control register 1 (USART_CR1) .....1055
30.6.5Control register 2 (USART_CR2) .....1057
30.6.6Control register 3 (USART_CR3) .....1058
30.6.7Guard time and prescaler register (USART_GTPR) .....1060
30.6.8USART register map .....1061
31Serial peripheral interface/ inter-IC sound (SPI/I2S) .....1062
31.1Introduction .....1062
31.1.1SPI main features .....1062
31.1.2SPI extended features .....1063
31.1.3I2S features .....1063
31.2SPI/I2S implementation .....1063
31.3SPI functional description .....1064
31.3.1General description .....1064
31.3.2Communications between one master and one slave .....1065
31.3.3Standard multislave communication .....1068
31.3.4Multimaster communication .....1069
31.3.5Slave select (NSS) pin management .....1069
31.3.6Communication formats .....1071
31.3.7SPI configuration .....1073
31.3.8Procedure for enabling SPI .....1073
31.3.9Data transmission and reception procedures .....1074
31.3.10Procedure for disabling the SPI .....1076
31.3.11Communication using DMA (direct memory addressing) .....1077
31.3.12SPI status flags .....1079
31.3.13SPI error flags .....1080
31.4SPI special features .....1081
32.4.6Frame synchronization . . . . .1117
32.4.7Slot configuration . . . . .1120
32.4.8SAI clock generator . . . . .1122
32.4.9Internal FIFOs . . . . .1124
32.4.10AC'97 link controller . . . . .1126
32.4.11SPDIF output . . . . .1127
32.4.12Specific features . . . . .1130
32.4.13Error flags . . . . .1134
32.4.14Disabling the SAI . . . . .1137
32.4.15SAI DMA interface . . . . .1137
32.5SAI interrupts . . . . .1138
32.6SAI registers . . . . .1140
32.6.1SAI configuration register 1 (SAI_ACR1) . . . . .1140
32.6.2SAI configuration register 2 (SAI_ACR2) . . . . .1142
32.6.3SAI frame configuration register (SAI_AFRCR) . . . . .1144
32.6.4SAI slot register (SAI_ASLOTR) . . . . .1145
32.6.5SAI interrupt mask register (SAI_AIM) . . . . .1146
32.6.6SAI status register (SAI_ASR) . . . . .1147
32.6.7SAI clear flag register (SAI_ACLRFR) . . . . .1149
32.6.8SAI data register (SAI_ADR) . . . . .1150
32.6.9SAI configuration register 1 (SAI_BCR1) . . . . .1151
32.6.10SAI configuration register 2 (SAI_BCR2) . . . . .1153
32.6.11SAI frame configuration register (SAI_BFRCR) . . . . .1155
32.6.12SAI slot register (SAI_BSLOTR) . . . . .1156
32.6.13SAI interrupt mask register (SAI_BIM) . . . . .1157
32.6.14SAI status register (SAI_BSR) . . . . .1158
32.6.15SAI clear flag register (SAI_BCLRFR) . . . . .1160
32.6.16SAI data register (SAI_BDR) . . . . .1161
32.6.17SAI register map . . . . .1162
33Secure digital input/output interface (SDIO) . . . . .1163
33.1SDIO main features . . . . .1163
33.2SDIO bus topology . . . . .1163
33.3SDIO functional description . . . . .1165
33.3.1SDIO adapter . . . . .1167
33.3.2SDIO APB2 interface . . . . .1178
33.4Card functional description . . . . .1179
33.4.1Card identification mode . . . . .1179
33.4.2Card reset . . . . .1180
33.4.3Operating voltage range validation . . . . .1180
33.4.4Card identification process . . . . .1180
33.4.5Block write . . . . .1181
33.4.6Block read . . . . .1182
33.4.7Stream access, stream write and stream read
(MultiMediaCard only) . . . . .		1182
33.4.8Erase: group erase and sector erase . . . . .1184
33.4.9Wide bus selection or deselection . . . . .1184
33.4.10Protection management . . . . .1184
33.4.11Card status register . . . . .1188
33.4.12SD status register . . . . .1191
33.4.13SD I/O mode . . . . .1195
33.4.14Commands and responses . . . . .1196
33.5Response formats . . . . .1199
33.5.1R1 (normal response command) . . . . .1200
33.5.2R1b . . . . .1200
33.5.3R2 (CID, CSD register) . . . . .1200
33.5.4R3 (OCR register) . . . . .1201
33.5.5R4 (Fast I/O) . . . . .1201
33.5.6R4b . . . . .1201
33.5.7R5 (interrupt request) . . . . .1202
33.5.8R6 . . . . .1202
33.6SDIO I/O card-specific operations . . . . .1203
33.6.1SDIO I/O read wait operation by SDIO_D2 signalling . . . . .1203
33.6.2SDIO read wait operation by stopping SDIO_CK . . . . .1204
33.6.3SDIO suspend/resume operation . . . . .1204
33.6.4SDIO interrupts . . . . .1204
33.7HW flow control . . . . .1204
33.8SDIO registers . . . . .1205
33.8.1SDIO power control register (SDIO_POWER) . . . . .1205
33.8.2SDIO clock control register (SDIO_CLKCR) . . . . .1205
33.8.3SDIO argument register (SDIO_ARG) . . . . .1207
33.8.4SDIO command register (SDIO_CMD) . . . . .1207
33.8.5SDIO command response register (SDIO_RESPCMD) . . . . .1208
33.8.6SDIO response 1..4 register (SDIO_RESPx)1208
33.8.7SDIO data timer register (SDIO_DTIMER)1209
33.8.8SDIO data length register (SDIO_DLEN)1210
33.8.9SDIO data control register (SDIO_DCTRL)1210
33.8.10SDIO data counter register (SDIO_DCOUNT)1213
33.8.11SDIO status register (SDIO_STA)1213
33.8.12SDIO interrupt clear register (SDIO_ICR)1214
33.8.13SDIO mask register (SDIO_MASK)1216
33.8.14SDIO FIFO counter register (SDIO_FIFOCNT)1218
33.8.15SDIO data FIFO register (SDIO_FIFO)1219
33.8.16SDIO register map1220
34Controller area network (bxCAN)1222
34.1Introduction1222
34.2bxCAN main features1222
34.3bxCAN general description1223
34.3.1CAN 2.0B active core1223
34.3.2Control, status, and configuration registers1223
34.3.3Tx mailboxes1223
34.3.4Acceptance filters1224
34.4bxCAN operating modes1225
34.4.1Initialization mode1225
34.4.2Normal mode1225
34.4.3Sleep mode (low-power)1226
34.5Test mode1227
34.5.1Silent mode1227
34.5.2Loop back mode1227
34.5.3Loop back combined with silent mode1228
34.6Behavior in debug mode1228
34.7bxCAN functional description1228
34.7.1Transmission handling1228
34.7.2Time triggered communication mode1230
34.7.3Reception handling1230
34.7.4Identifier filtering1232
34.7.5Message storage1236
34.7.6Error management1237
34.7.7Bit timing .....1237
34.8bxCAN interrupts .....1241
34.9CAN registers .....1242
34.9.1Register access protection .....1242
34.9.2CAN control and status registers .....1242
34.9.3CAN mailbox registers .....1252
34.9.4CAN filter registers .....1258
34.9.5bxCAN register map .....1262
35USB on-the-go full-speed/high-speed
(OTG_FS/OTG_HS) .....		1266
35.1Introduction .....1266
35.2OTG_FS/OTG_HS main features .....1268
35.2.1General features .....1268
35.2.2Host-mode features .....1269
35.2.3Peripheral-mode features .....1269
35.3OTG_FS/OTG_HS implementation .....1270
35.4OTG_FS/OTG_HS functional description .....1271
35.4.1OTG_FS/OTG_HS block diagram .....1271
35.4.2OTG_FS/OTG_HS pin and internal signals .....1272
35.4.3OTG_FS/OTG_HS core .....1273
35.4.4Embedded full-speed OTG PHY connected to OTG_FS .....1273
35.4.5Embedded full-speed OTG PHY connected to OTG_HS .....1274
35.4.6OTG detections .....1274
35.4.7High-speed OTG PHY connected to OTG_HS .....1274
35.5OTG_FS/OTG_HS dual role device (DRD) .....1275
35.5.1ID line detection .....1275
35.5.2HNP dual role device .....1275
35.5.3SRP dual role device .....1276
35.6OTG_FS/OTG_HS as a USB peripheral .....1276
35.6.1SRP-capable peripheral .....1277
35.6.2Peripheral states .....1277
35.6.3Peripheral endpoints .....1278
35.7OTG_FS/OTG_HS as a USB host .....1280
35.7.1SRP-capable host .....1281
35.7.2USB host states .....1281
35.7.3Host channels . . . . .1283
35.7.4Host scheduler . . . . .1284
35.8OTG_FS/OTG_HS SOF trigger . . . . .1285
35.8.1Host SOFs . . . . .1285
35.8.2Peripheral SOFs . . . . .1285
35.9OTG_FS/OTG_HS low-power modes . . . . .1286
35.10OTG_FS/OTG_HS Dynamic update of the OTG_HFIR register . . . . .1287
35.11OTG_FS/OTG_HS data FIFOs . . . . .1287
35.11.1Peripheral FIFO architecture . . . . .1288
35.11.2Host FIFO architecture . . . . .1289
35.11.3FIFO RAM allocation . . . . .1290
35.12OTG_FS system performance . . . . .1292
35.13OTG_FS/ OTG_HS interrupts . . . . .1292
35.14OTG_FS/ OTG_HS control and status registers . . . . .1294
35.14.1CSR memory map . . . . .1294
35.15OTG_FS/ OTG_HS registers . . . . .1300
35.15.1OTG control and status register (OTG_GOTGCTL) . . . . .1300
35.15.2OTG interrupt register (OTG_GOTGINT) . . . . .1303
35.15.3OTG AHB configuration register (OTG_GAHBCFG) . . . . .1305
35.15.4OTG USB configuration register (OTG_GUSBCFG) . . . . .1307
35.15.5OTG reset register (OTG_GRSTCTL) . . . . .1310
35.15.6OTG core interrupt register (OTG_GINTSTS) . . . . .1313
35.15.7OTG interrupt mask register (OTG_GINTMSK) . . . . .1318
35.15.8OTG receive status debug read register (OTG_GRXSTSR) . . . . .1321
35.15.9OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . .1322
35.15.10OTG status read and pop registers (OTG_GRXSTSP) . . . . .1323
35.15.11OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . . . .1324
35.15.12OTG receive FIFO size register (OTG_GRXFSIZ) . . . . .1325
35.15.13OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0) . . . . .		1326
35.15.14OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . .		1327
35.15.15OTG general core configuration register (OTG_GCCFG) . . . . .1328
35.15.16OTG core ID register (OTG_CID) . . . . .1329
35.15.17OTG core LPM configuration register (OTG_GLPMCFG) . . . . .1329
35.15.18OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . .		1333
35.15.19OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx) . . . . .		1333
35.15.20Host-mode registers . . . . .1334
35.15.21OTG host configuration register (OTG_HCFG) . . . . .1334
35.15.22OTG host frame interval register (OTG_HFIR) . . . . .1335
35.15.23OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . .		1336
35.15.24OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . .		1336
35.15.25OTG host all channels interrupt register (OTG_HAINT) . . . . .1337
35.15.26OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . .		1338
35.15.27OTG host port control and status register (OTG_HPRT) . . . . .1339
35.15.28OTG host channel x characteristics register (OTG_HCCHARx) . . . . .1341
35.15.29OTG host channel x split control register (OTG_HCSPLTx) . . . . .1342
35.15.30OTG host channel x interrupt register (OTG_HCINTx) . . . . .1343
35.15.31OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . . . .1345
35.15.32OTG host channel x transfer size register (OTG_HCTSIZx) . . . . .1346
35.15.33OTG host channel x DMA address register (OTG_HCDMAx) . . . . .1347
35.15.34Device-mode registers . . . . .1348
35.15.35OTG device configuration register (OTG_DCFG) . . . . .1348
35.15.36OTG device control register (OTG_DCTL) . . . . .1350
35.15.37OTG device status register (OTG_DSTS) . . . . .1352
35.15.38OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . .		1353
35.15.39OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . .		1354
35.15.40OTG device all endpoints interrupt register (OTG_DAININT) . . . . .1356
35.15.41OTG all endpoints interrupt mask register
(OTG_DAININTMSK) . . . . .		1356
35.15.42OTG device V BUS discharge time register
(OTG_DVBUSDIS) . . . . .		1357
35.15.43OTG device V BUS pulsing time register
(OTG_DVBUSPULSE) . . . . .		1357
35.15.44OTG device threshold control register (OTG_DTHRCTL) . . . . .1358
35.15.45OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK) . . . . .		1359
35.15.46OTG device each endpoint interrupt register (OTG_DEACHINT) . . . . .1359
35.15.47OTG device each endpoint interrupt mask register
(OTG_DEACHINTMSK) .....		1360
35.15.48OTG device each IN endpoint-1 interrupt mask register
(OTG_HS_DIEPEACHMSK1) .....		1360
35.15.49OTG device each OUT endpoint-1 interrupt mask register
(OTG_HS_DOEPEACHMSK1) .....		1361
35.15.50OTG device control IN endpoint 0 control register
(OTG_DIEPCTL0) .....		1363
35.15.51OTG device IN endpoint x control register (OTG_DIEPCTLx) .....1364
35.15.52OTG device IN endpoint x interrupt register (OTG_DIEPINTx) .....1366
35.15.53OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0) .....		1368
35.15.54OTG device IN endpoint x DMA address register
(OTG_DIEPDMAx) .....		1369
35.15.55OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) .....		1369
35.15.56OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) .1370
35.15.57OTG device control OUT endpoint 0 control register
(OTG_DOECTL0) .....		1371
35.15.58OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . .1372
35.15.59OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0) .....		1374
35.15.60OTG device OUT endpoint x DMA address register
(OTG_DOEPDMAx) .....		1375
35.15.61OTG device OUT endpoint x control register
(OTG_DOECTLx) .....		1375
35.15.62OTG device OUT endpoint x transfer size register
(OTG_DOEPTSIZx) .....		1377
35.15.63OTG power and clock gating control register (OTG_PCGCCTL) . . .1378
35.15.64OTG_FS/OTG_HS register map .....1379
35.16OTG_FS/OTG_HS programming model .....1392
35.16.1Core initialization .....1392
35.16.2Host initialization .....1393
35.16.3Device initialization .....1394
35.16.4DMA mode .....1394
35.16.5Host programming model .....1394
35.16.6Device programming model .....1428
35.16.7Worst case response time .....1448
35.16.8OTG programming model .....1450

36 Ethernet (ETH): media access control (MAC) with DMA controller . . . . . 1456

36.8.2MMC register description . . . . .1546
36.8.3IEEE 1588 time stamp registers . . . . .1551
36.8.4DMA register description . . . . .1559
36.8.5Ethernet register maps . . . . .1574
37Debug support (DBG) . . . . .1578
37.1Overview . . . . .1578
37.2Reference Arm® documentation . . . . .1579
37.3SWJ debug port (serial wire and JTAG) . . . . .1579
37.3.1Mechanism to select the JTAG-DP or the SW-DP . . . . .1580
37.4Pinout and debug port pins . . . . .1580
37.4.1SWJ debug port pins . . . . .1581
37.4.2Flexible SWJ-DP pin assignment . . . . .1581
37.4.3Internal pull-up and pull-down on JTAG pins . . . . .1581
37.4.4Using serial wire and releasing the unused debug pins as GPIOs . . . . .1582
37.5STM32F469xx and STM32F479xx JTAG TAP connection . . . . .1582
37.6ID codes and locking mechanism . . . . .1584
37.6.1MCU device ID code . . . . .1584
37.6.2Boundary scan TAP . . . . .1584
37.6.3Cortex®-M4 TAP . . . . .1584
37.6.4Cortex®-M4 JEDEC-106 ID code . . . . .1585
37.7JTAG debug port . . . . .1585
37.8SW debug port . . . . .1587
37.8.1SW protocol introduction . . . . .1587
37.8.2SW protocol sequence . . . . .1587
37.8.3SW-DP state machine (reset, idle states, ID code) . . . . .1588
37.8.4DP and AP read/write accesses . . . . .1589
37.8.5SW-DP registers . . . . .1589
37.8.6SW-AP registers . . . . .1590
37.9AHB-AP (AHB access port), valid for JTAG-DP and SW-DP . . . . .1591
37.10Core debug . . . . .1592
37.11Capability of the debugger host to connect under system reset . . . . .1593
37.12FPB (Flash patch breakpoint) . . . . .1593
37.13DWT (data watchpoint trigger) . . . . .1594
37.14ITM (instrumentation trace macrocell) . . . . .1594
37.14.1General description . . . . .1594
37.14.2Time stamp packets, synchronization and overflow packets . . . . .1594
37.15ETM (Embedded trace macrocell) . . . . .1596
37.15.1General description . . . . .1596
37.15.2Signal protocol, packet types . . . . .1596
37.15.3Main ETM registers . . . . .1597
37.15.4Configuration example . . . . .1597
37.16MCU debug component (DBGMCU) . . . . .1597
37.16.1Debug support for low-power modes . . . . .1598
37.16.2Debug support for timers, watchdog, bxCAN and I 2 C . . . . .1598
37.16.3Debug MCU configuration register . . . . .1598
37.16.4Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . .1600
37.16.5Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ) . . . . .1602
37.17TPIU (trace port interface unit) . . . . .1603
37.17.1Introduction . . . . .1603
37.17.2TRACE pin assignment . . . . .1603
37.17.3TPUI formatter . . . . .1605
37.17.4TPUI frame synchronization packets . . . . .1606
37.17.5Transmission of the synchronization frame packet . . . . .1606
37.17.6Synchronous mode . . . . .1606
37.17.7Asynchronous mode . . . . .1607
37.17.8TRACECLKIN connection in STM32F469xx and STM32F479xx . . . . .1607
37.17.9TPIU registers . . . . .1607
37.17.10Example of configuration . . . . .1608
37.18DBG register map . . . . .1609
38Device electronic signature . . . . .1610
38.1Unique device ID register (96 bits) . . . . .1610
38.2Flash memory size register . . . . .1611
38.3Package data register . . . . .1611
39Important security notice . . . . .1613
40Revision history . . . . .1614

List of tables

Table 1.STM32F469xx and STM32F479xx register boundary addresses. . . . .68
Table 2.Boot modes. . . . .73
Table 3.Memory mapping versus Boot mode/physical remap . . . . .74
Table 4.Flash module - 2 Mbytes dual bank organization . . . . .78
Table 5.1 Mbyte flash memory single bank vs. dual bank organization. . . . .79
Table 6.1 Mbyte single bank flash memory organization. . . . .79
Table 7.1 Mbyte dual bank flash memory organization . . . . .80
Table 8.512 Kbytes single bank flash memory organization . . . . .81
Table 9.Number of wait states according to CPU clock (HCLK) frequency. . . . .81
Table 10.Program/erase parallelism . . . . .86
Table 11.Option byte organization. . . . .89
Table 12.Description of the option bytes . . . . .89
Table 13.Access versus read protection level . . . . .92
Table 14.OTP area organization . . . . .95
Table 15.Flash interrupt request . . . . .96
Table 16.Flash register map and reset values. . . . .104
Table 17.CRC calculation unit register map and reset values. . . . .108
Table 18.Voltage regulator configuration mode versus device operating mode . . . . .116
Table 19.Low-power mode summary . . . . .121
Table 20.Sleep-now entry and exit . . . . .123
Table 21.Stop operating modes. . . . .124
Table 22.Stop mode entry and exit for STM32F469xx and STM32F479xx. . . . .126
Table 23.Standby mode entry and exit . . . . .127
Table 24.PWR - register map and reset values. . . . .135
Table 25.RCC register map and reset values . . . . .193
Table 26.Port bit configuration table . . . . .199
Table 27.GPIO register map and reset values . . . . .212
Table 28.SYSCFG register map and reset values. . . . .219
Table 29.DMA1 request mapping . . . . .224
Table 30.DMA2 request mapping . . . . .224
Table 31.Source and destination address . . . . .225
Table 32.Source and destination address registers in double-buffer mode (DBM = 1). . . . .231
Table 33.Packing/unpacking and endian behavior (bit PINC = MINC = 1) . . . . .232
Table 34.Restriction on NDT versus PSIZE and MSIZE . . . . .232
Table 35.FIFO threshold configurations . . . . .235
Table 36.Possible DMA configurations . . . . .239
Table 37.DMA interrupt requests. . . . .241
Table 38.DMA register map and reset values . . . . .251
Table 39.Supported color mode in input . . . . .257
Table 40.Data order in memory . . . . .258
Table 41.Alpha mode configuration. . . . .259
Table 42.Supported CLUT color mode . . . . .260
Table 43.CLUT data order in system memory. . . . .260
Table 44.Supported color mode in output . . . . .261
Table 45.Data order in memory . . . . .261
Table 46.DMA2D interrupt requests . . . . .266
Table 47.DMA2D register map and reset values. . . . .282
Table 48.Vector table for STM32F469xx and STM32F479xx . . . . .284
Table 49.External interrupt/event controller register map and reset values . . . . .295
Table 50.NOR/PSRAM bank selection . . . . .300
Table 51.NOR/PSRAM External memory address . . . . .301
Table 52.NAND memory mapping and timing registers. . . . .301
Table 53.NAND bank selection . . . . .301
Table 54.SDRAM bank selection. . . . .302
Table 55.SDRAM address mapping . . . . .302
Table 56.SDRAM address mapping with 8-bit data bus width. . . . .303
Table 57.SDRAM address mapping with 16-bit data bus width. . . . .303
Table 58.SDRAM address mapping with 32-bit data bus width. . . . .304
Table 59.Programmable NOR/PSRAM access parameters . . . . .306
Table 60.Non-multiplexed I/O NOR flash memory. . . . .307
Table 61.16-bit multiplexed I/O NOR flash memory . . . . .307
Table 62.Non-multiplexed I/Os PSRAM/SRAM . . . . .307
Table 63.16-Bit multiplexed I/O PSRAM . . . . .308
Table 64.NOR flash/PSRAM: example of supported memories
and transactions . . . . .		309
Table 65.FMC_BCRx bitfields (mode 1) . . . . .312
Table 66.FMC_BTRx bitfields (mode 1) . . . . .312
Table 67.FMC_BCRx bitfields (mode A) . . . . .314
Table 68.FMC_BTRx bitfields (mode A) . . . . .314
Table 69.FMC_BWTRx bitfields (mode A). . . . .315
Table 70.FMC_BCRx bitfields (mode 2/B). . . . .317
Table 71.FMC_BTRx bitfields (mode 2/B). . . . .317
Table 72.FMC_BWTRx bitfields (mode 2/B) . . . . .318
Table 73.FMC_BCRx bitfields (mode C) . . . . .319
Table 74.FMC_BTRx bitfields (mode C) . . . . .320
Table 75.FMC_BWTRx bitfields (mode C). . . . .320
Table 76.FMC_BCRx bitfields (mode D) . . . . .322
Table 77.FMC_BTRx bitfields (mode D) . . . . .322
Table 78.FMC_BWTRx bitfields (mode D). . . . .323
Table 79.FMC_BCRx bitfields (Muxed mode) . . . . .324
Table 80.FMC_BTRx bitfields (Muxed mode) . . . . .325
Table 81.FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .330
Table 82.FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .330
Table 83.FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .331
Table 84.FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .332
Table 85.Programmable NAND flash access parameters . . . . .340
Table 86.8-bit NAND flash . . . . .340
Table 87.16-bit NAND flash . . . . .341
Table 88.Supported memories and transactions . . . . .341
Table 89.ECC result relevant bits . . . . .350
Table 90.SDRAM signals. . . . .351
Table 91.FMC register map and reset values . . . . .368
Table 92.QUADSPI pins . . . . .372
Table 93.QUADSPI interrupt requests. . . . .386
Table 94.QUADSPI register map and reset values . . . . .397
Table 95.ADC pins. . . . .401
Table 96.Analog watchdog channel selection . . . . .407
Table 97.Configuring the trigger polarity . . . . .412
Table 98.External trigger for regular channels. . . . .412
Table 99.External trigger for injected channels . . . . .413
Table 100.ADC interrupts . . . . .427
Table 101.ADC global register map. . . . .442
Table 102.ADC register map and reset values for each ADC . . . . .442
Table 103.ADC register map and reset values (common ADC registers) . . . . .444
Table 104.DAC pins. . . . .446
Table 105.External triggers . . . . .449
Table 106.DAC register map . . . . .466
Table 107.DCMI input/output pins . . . . .468
Table 108.Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .470
Table 109.Positioning of captured data bytes in 32-bit words (10-bit width) . . . . .470
Table 110.Positioning of captured data bytes in 32-bit words (12-bit width) . . . . .470
Table 111.Positioning of captured data bytes in 32-bit words (14-bit width) . . . . .471
Table 112.Data storage in monochrome progressive video format . . . . .476
Table 113.Data storage in RGB progressive video format . . . . .477
Table 114.Data storage in YCbCr progressive video format . . . . .477
Table 115.Data storage in YCbCr progressive video format - Y extraction mode . . . . .477
Table 116.DCMI interrupts. . . . .478
Table 117.DCMI register map and reset values . . . . .488
Table 118.LTDC pins and signal interface . . . . .490
Table 119.Clock domain for each register . . . . .491
Table 120.Pixel data mapping versus color format . . . . .496
Table 121.LTDC interrupt requests . . . . .500
Table 122.LTDC register map and reset values . . . . .519
Table 123.Location of color components in the LTDC interface . . . . .527
Table 124.Multiplicity of the payload size in pixels for each data type . . . . .528
Table 125.Contention detection timeout counters configuration . . . . .540
Table 126.List of events of different categories of the PRESP_TO counter . . . . .541
Table 127.PRESP_TO counter configuration . . . . .544
Table 128.Frame requirement configuration registers . . . . .556
Table 129.RGB components . . . . .558
Table 130.Slew-rate and delay tuning . . . . .560
Table 131.Custom lane configuration . . . . .561
Table 132.Custom timing parameters . . . . .561
Table 133.HS2LP and LP2HS values . . . . .562
Table 134.DSI Wrapper interrupt requests . . . . .565
Table 135.Error causes and recovery . . . . .566
Table 136.DSI register map and reset values . . . . .632
Table 137.RNG internal input/output signals . . . . .638
Table 138.RNG interrupt requests . . . . .643
Table 139.RNG configurations . . . . .644
Table 140.RNG register map and reset map. . . . .647
Table 141.CRYP internal input/output signals . . . . .650
Table 142.Counter mode initialization vector. . . . .676
Table 143.GCM last block definition . . . . .679
Table 144.GCM mode IV registers initialization. . . . .679
Table 145.CCM mode IV registers initialization. . . . .686
Table 146.DES/TDES data swapping example . . . . .690
Table 147.AES data swapping example . . . . .691
Table 148.Key endianness in CRYP_KxR/LR registers (AES 128/192/256-bit keys) . . . . .693
Table 149.Key endianness in CRYP_KxR/LR registers (DES K1 and TDES K1/2/3) . . . . .693
Table 150.Initialization vector endianness in CRYP_IVx(L/R)R registers (AES) . . . . .694
Table 151.Initialization vector endianness in CRYP_IVx(L/R)R registers (DES/TDES) . . . . .694
Table 152.Cryptographic processor configuration for memory-to-peripheral DMA transfers . . . . .694
Table 153.Cryptographic processor configuration for peripheral-to-memory DMA transfers . . . . .695
Table 154.CRYP interrupt requests . . . . .697
Table 155.Processing latency for ECB, CBC and CTR . . . . .698
Table 156.Processing time (in clock cycle) for GCM and CCM per 128-bit block . . . . .698
Table 157.CRYP register map and reset values . . . . .711
Table 158.HASH internal input/output signals . . . . .715
Table 159.Hash processor outputs . . . . .718
Table 160.Processing time (in clock cycle) . . . . .724
Table 161.HASH interrupt requests . . . . .725
Table 162.HASH register map and reset values . . . . .733
Table 163.Counting direction versus encoder signals . . . . .772
Table 164.TIMx Internal trigger connection . . . . .785
Table 165.Output control bits for complementary OCx and OCxN channels with break feature . . . . .797
Table 166.TIM1&TIM8 register map and reset values . . . . .804
Table 167.Counting direction versus encoder signals . . . . .833
Table 168.TIMx internal trigger connections . . . . .848
Table 169.Output control bit for standard OCx channels . . . . .858
Table 170.TIM2 to TIM5 register map and reset values . . . . .865
Table 171.TIMx internal trigger connections . . . . .891
Table 172.Output control bit for standard OCx channels . . . . .899
Table 173.TIM9/12 register map and reset values . . . . .901
Table 174.Output control bit for standard OCx channels . . . . .909
Table 175.TIM10/11/13/14 register map and reset values . . . . .912
Table 176.TIM6&TIM7 register map and reset values . . . . .925
Table 177.Min/max IWDG timeout periods (ms) at 32 kHz (LSI) . . . . .927
Table 178.IWDG register map and reset values . . . . .931
Table 179.WWDG register map and reset values . . . . .938
Table 180.Effect of low power modes on RTC . . . . .954
Table 181.Interrupt control bits . . . . .955
Table 182.RTC register map and reset values . . . . .976
Table 183.Maximum DNF[3:0] value to be compliant with Thd:dat(max) . . . . .990
Table 184.SMBus vs. I2C . . . . .991
Table 185.I2C Interrupt requests . . . . .996
Table 186.I2C register map and reset values . . . . .1009
Table 187.USART features . . . . .1012
Table 188.Noise detection from sampled data . . . . .1023
Table 189.Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 12 \) MHz, oversampling by 16. . . . .1026
Table 190.Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 12 \) MHz, oversampling by 8. . . . .1026
Table 191.Error calculation for programmed baud rates at \( f_{PCLK} = 16 \) MHz or \( f_{PCLK} = 24 \) MHz, oversampling by 16. . . . .1027
Table 192.Error calculation for programmed baud rates at \( f_{PCLK} = 16 \) MHz or \( f_{PCLK} = 24 \) MHz, oversampling by 8. . . . .1028
Table 193.Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 16 \) MHz, oversampling by 16. . . . .1028
Table 194.Error calculation for programmed baud rates at \( f_{PCLK} = 8 \) MHz or \( f_{PCLK} = 16 \) MHz, oversampling by 8. . . . .1029
Table 195.Error calculation for programmed baud rates at \( f_{PCLK} = 30 \) MHz or \( f_{PCLK} = 60 \) MHz, oversampling by 16. . . . .1030
Table 196.Error calculation for programmed baud rates at \( f_{PCLK} = 30 \) MHz or \( f_{PCLK} = 60 \) MHz, oversampling by 8 . . . . .1030
Table 197.Error calculation for programmed baud rates at \( f_{PCLK} = 42 \) MHz or \( f_{PCLK} = 84 \) Hz, oversampling by 16. . . . .1031
Table 198.Error calculation for programmed baud rates at \( f_{PCLK} = 42 \) MHz or \( f_{PCLK} = 84 \) MHz, oversampling by 8. . . . .1032
Table 199.USART receiver tolerance when DIV fraction is 0 . . . . .1033
Table 200.USART receiver tolerance when DIV_Fraction is different from 0 . . . . .1034
Table 201.Frame formats . . . . .1036
Table 202.USART interrupt requests. . . . .1050
Table 203.USART register map and reset values . . . . .1061
Table 204.SPI interrupt requests. . . . .1084
Table 205.Audio-frequency precision using standard 8 MHz HSE . . . . .1095
Table 206.I 2 S interrupt requests . . . . .1101
Table 207.SPI register map and reset values . . . . .1111
Table 208.STM32F469xx and STM32F479xxSAI features . . . . .1113
Table 209.SAI internal input/output signals . . . . .1115
Table 210.SAI input/output pins. . . . .1115
Table 211.Example of possible audio frequency sampling range . . . . .1123
Table 212.SOPD pattern . . . . .1128
Table 213.Parity bit calculation . . . . .1128
Table 214.Audio sampling frequency versus symbol rates . . . . .1129
Table 215.SAI interrupt sources . . . . .1138
Table 216.SAI register map and reset values . . . . .1162
Table 217.SDIO I/O definitions . . . . .1166
Table 218.Command format . . . . .1171
Table 219.Short response format . . . . .1172
Table 220.Long response format. . . . .1172
Table 221.Command path status flags . . . . .1172
Table 222.Data token format . . . . .1175
Table 223.DPSM flags. . . . .1176
Table 224.Transmit FIFO status flags . . . . .1177
Table 225.Receive FIFO status flags . . . . .1177
Table 226.Card status . . . . .1188
Table 227.SD status . . . . .1191
Table 228.Speed class code field . . . . .1192
Table 229.Performance move field . . . . .1193
Table 230.AU_SIZE field . . . . .1193
Table 231.Maximum AU size. . . . .1193
Table 232.Erase size field . . . . .1194
Table 233.Erase timeout field . . . . .1194
Table 234.Erase offset field . . . . .1194
Table 235.Block-oriented write commands . . . . .1197
Table 236.Block-oriented write protection commands. . . . .1198
Table 237.Erase commands . . . . .1198
Table 238.I/O mode commands . . . . .1198
Table 239.Lock card . . . . .1199
Table 240.Application-specific commands . . . . .1199
Table 241.R1 response . . . . .1200
Table 242.R2 response . . . . .1200
Table 243.R3 response . . . . .1201
Table 244.R4 response . . . . .1201
Table 245.R4b response . . . . .1201
Table 246.R5 response . . . . .1202
Table 247.R6 response . . . . .1203
Table 248.Response type and SDIO_RESPx registers. . . . .1209
Table 249.SDIO register map . . . . .1220
Table 250.Transmit mailbox mapping . . . . .1236
Table 251.Receive mailbox mapping. . . . .1236
Table 252.bxCAN register map and reset values . . . . .1262
Table 253.OTG_HS speeds supported . . . . .1267
Table 254.OTG_FS speeds supported . . . . .1267
Table 255.OTG_FS/OTG_HS implementation . . . . .1270
Table 256.OTG_FS input/output pins . . . . .1272
Table 257.OTG_HS input/output pins . . . . .1272
Table 258.OTG_FS/OTG_HS input/output signals . . . . .1273
Table 259.Compatibility of STM32 low power modes with the OTG . . . . .1286
Table 260.Core global control and status registers (CSRs). . . . .1294
Table 261.Host-mode control and status registers (CSRs) . . . . .1295
Table 262.Device-mode control and status registers . . . . .1297
Table 263.Data FIFO (DFIFO) access register map . . . . .1300
Table 264.Power and clock gating control and status registers . . . . .1300
Table 265.TRDT values (FS). . . . .1310
Table 266.TRDT values (HS) . . . . .1310
Table 267.Minimum duration for soft disconnect . . . . .1351
Table 268.OTG_FS/OTG_HS register map and reset values . . . . .1379
Table 269.Alternate function mapping. . . . .1459
Table 270.Management frame format . . . . .1461
Table 271.Clock range. . . . .1463
Table 272.TX interface signal encoding . . . . .1465
Table 273.RX interface signal encoding . . . . .1465
Table 274.Frame statuses . . . . .1481
Table 275.Destination address filtering . . . . .1487
Table 276.Source address filtering . . . . .1488
Table 277.Receive descriptor 0 - encoding for bits 7, 5 and 0 (normal descriptor format only, EDFE=0). . . . .1519
Table 278.Time stamp snapshot dependency on registers bits . . . . .1553
Table 279.Ethernet register map and reset values . . . . .1574
Table 280.SWJ debug port pins . . . . .1581
Table 281.Flexible SWJ-DP pin assignment . . . . .1581
Table 282.JTAG debug port data registers . . . . .1585
Table 283.32-bit debug port registers addressed through the shifted value A[3:2] . . . . .1587
Table 284.Packet request (8-bits) . . . . .1588
Table 285.ACK response (3 bits). . . . .1588
Table 286.DATA transfer (33 bits). . . . .1588
Table 287.SW-DP registers . . . . .1589
Table 288.Cortex ® -M4 AHB-AP registers . . . . .1591
Table 289.Core debug registers . . . . .1592
Table 290.Main ITM registers . . . . .1595
Table 291.Main ETM registers. . . . .1597
Table 292.Asynchronous TRACE pin assignment. . . . .1603
Table 293.Synchronous TRACE pin assignment . . . . .1604
Table 294. Flexible TRACE pin assignment . . . . .1604
Table 295. Important TPIU registers. . . . .1607
Table 296. DBG register map and reset values . . . . .1609
Table 297. Document revision history . . . . .1614

List of figures

Figure 1. System architecture . . . . . 63

Figure 2. Memory map . . . . . 67

Figure 3. Flash memory interface connection inside system architecture . . . . . 76

Figure 4. Sequential 32-bit instruction execution . . . . . 84

Figure 5. RDP levels . . . . . 93

Figure 6. PCROP levels . . . . . 95

Figure 7. CRC calculation unit block diagram . . . . . 105

Figure 8. Power supply overview for STM32F469xx and STM32F479xx . . . . . 110

Figure 9. VDDUSB connected to VDD power supply . . . . . 111

Figure 10. VDDUSB connected to external independent power supply . . . . . 112

Figure 11. Backup domain . . . . . 115

Figure 12. Power-on reset/power-down reset waveform . . . . . 118

Figure 13. BOR thresholds . . . . . 119

Figure 14. PVD thresholds . . . . . 120

Figure 15. Simplified diagram of the reset circuit . . . . . 137

Figure 16. Clock tree . . . . . 138

Figure 17. DSI clock tree . . . . . 139

Figure 18. HSE/ LSE clock sources (hardware configuration) . . . . . 142

Figure 19. Frequency measurement with TIM5 in Input capture mode . . . . . 147

Figure 20. Frequency measurement with TIM11 in Input capture mode . . . . . 147

Figure 21. Basic structure of an I/O port bit . . . . . 198

Figure 22. Basic structure of a 5-Volt tolerant I/O port bit . . . . . 198

Figure 23. Input floating/pull up/pull down configurations . . . . . 203

Figure 24. Output configuration . . . . . 204

Figure 25. Alternate function configuration . . . . . 204

Figure 26. High impedance-analog configuration . . . . . 205

Figure 27. DMA block diagram . . . . . 222

Figure 28. Channel selection . . . . . 223

Figure 29. Peripheral-to-memory mode . . . . . 227

Figure 30. Memory-to-peripheral mode . . . . . 228

Figure 31. Memory-to-memory mode . . . . . 229

Figure 32. FIFO structure . . . . . 234

Figure 33. DMA2D block diagram . . . . . 256

Figure 34. External interrupt/event controller block diagram . . . . . 289

Figure 35. External interrupt/event GPIO mapping . . . . . 291

Figure 36. FMC block diagram . . . . . 297

Figure 37. FMC memory banks . . . . . 300

Figure 38. Mode 1 read access waveforms . . . . . 311

Figure 39. Mode 1 write access waveforms . . . . . 311

Figure 40. Mode A read access waveforms . . . . . 313

Figure 41. Mode A write access waveforms . . . . . 313

Figure 42. Mode 2 and mode B read access waveforms . . . . . 315

Figure 43. Mode 2 write access waveforms . . . . . 316

Figure 44. Mode B write access waveforms . . . . . 316

Figure 45. Mode C read access waveforms . . . . . 318

Figure 46. Mode C write access waveforms . . . . . 319

Figure 47. Mode D read access waveforms . . . . . 321

Figure 48. Mode D write access waveforms . . . . . 321

Figure 49.Muxed read access waveforms . . . . .323
Figure 50.Muxed write access waveforms . . . . .324
Figure 51.Asynchronous wait during a read access waveforms . . . . .326
Figure 52.Asynchronous wait during a write access waveforms . . . . .327
Figure 53.Wait configuration waveforms . . . . .329
Figure 54.Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . .329
Figure 55.Synchronous multiplexed write mode waveforms - PSRAM (CRAM) . . . . .331
Figure 56.NAND flash controller waveforms for common memory access . . . . .342
Figure 57.Access to non 'CE don't care' NAND-flash . . . . .344
Figure 58.Burst write SDRAM access waveforms . . . . .353
Figure 59.Burst read SDRAM access . . . . .354
Figure 60.Logic diagram of Read access with RBURST bit set (CAS=1, RPIPE=0) . . . . .355
Figure 61.Read access crossing row boundary . . . . .357
Figure 62.Write access crossing row boundary . . . . .357
Figure 63.Self-refresh mode . . . . .360
Figure 64.Power-down mode . . . . .361
Figure 65.QUADSPI block diagram when dual-flash mode is disabled . . . . .371
Figure 66.QUADSPI block diagram when dual-flash mode is enabled . . . . .372
Figure 67.Example of read command in quad-SPI mode . . . . .373
Figure 68.Example of a DDR command in quad-SPI mode . . . . .376
Figure 69.NCS when CKMODE = 0 (T = CLK period) . . . . .384
Figure 70.NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .384
Figure 71.NCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . .385
Figure 72.NCS when CKMODE = 1 with an abort (T = CLK period) . . . . .385
Figure 73.Single ADC block diagram . . . . .400
Figure 74.ADC1 connectivity . . . . .402
Figure 75.ADC2 connectivity . . . . .403
Figure 76.ADC3 connectivity . . . . .404
Figure 77.Timing diagram . . . . .407
Figure 78.Analog watchdog's guarded area . . . . .407
Figure 79.Injected conversion latency . . . . .409
Figure 80.Right alignment of 12-bit data . . . . .411
Figure 81.Left alignment of 12-bit data . . . . .411
Figure 82.Left alignment of 6-bit data . . . . .411
Figure 83.Multi ADC block diagram (1) . . . . .416
Figure 84.Injected simultaneous mode on 4 channels: dual ADC mode . . . . .419
Figure 85.Injected simultaneous mode on 4 channels: triple ADC mode . . . . .419
Figure 86.Regular simultaneous mode on 16 channels: dual ADC mode . . . . .420
Figure 87.Regular simultaneous mode on 16 channels: triple ADC mode . . . . .420
Figure 88.Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode . . . . .421
Figure 89.Interleaved mode on 1 channel in continuous conversion mode: triple ADC mode . . . . .422
Figure 90.Alternate trigger: injected group of each ADC . . . . .423
Figure 91.Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . .423
Figure 92.Alternate trigger: injected group of each ADC . . . . .424
Figure 93.Alternate + regular simultaneous . . . . .425
Figure 94.Case of trigger occurring during injected conversion . . . . .425
Figure 95.Temperature sensor and VREFINT channel block diagram . . . . .426
Figure 96.DAC channel block diagram . . . . .446
Figure 97.DAC output buffer connection . . . . .447
Figure 98.Data registers in single DAC channel mode . . . . .448
Figure 99.Data registers in dual DAC channel mode . . . . .448
Figure 100.Timing diagram for conversion with trigger disabled TEN = 0 . . . . .449
Figure 101. DAC LFSR register calculation algorithm . . . . .451
Figure 102. DAC conversion (SW trigger enabled) with LFSR wave generation. . . . .451
Figure 103. DAC triangle wave generation . . . . .452
Figure 104. DAC conversion (SW trigger enabled) with triangle wave generation . . . . .452
Figure 105. DCMI block diagram . . . . .468
Figure 106. Top-level block diagram . . . . .468
Figure 107. DCMI signal waveforms . . . . .469
Figure 108. Timing diagram . . . . .471
Figure 109. Frame capture waveforms in snapshot mode. . . . .473
Figure 110. Frame capture waveforms in continuous grab mode . . . . .474
Figure 111. Coordinates and size of the window after cropping . . . . .474
Figure 112. Data capture waveforms. . . . .475
Figure 113. Pixel raster scan order . . . . .476
Figure 114. LTDC block diagram . . . . .490
Figure 115. LCD-TFT synchronous timings . . . . .493
Figure 116. Layer window programmable parameters . . . . .496
Figure 117. Blending two layers with background . . . . .499
Figure 118. Interrupt events. . . . .500
Figure 119. DSI block diagram . . . . .524
Figure 120. DSI Host architecture . . . . .525
Figure 121. Flow to update the LTDC interface configuration using shadow registers . . . . .530
Figure 122. Immediate update procedure . . . . .531
Figure 123. Configuration update during the transmission of a frame. . . . .531
Figure 124. Adapted command mode usage flow . . . . .533
Figure 125. 24 bpp APB pixel to byte organization . . . . .537
Figure 126. 18 bpp APB pixel to byte organization . . . . .538
Figure 127. 16 bpp APB pixel to byte organization . . . . .538
Figure 128. 12 bpp APB pixel to byte organization . . . . .539
Figure 129. 8 bpp APB pixel to byte organization . . . . .539
Figure 130. Timing of PRESP_TO after a bus-turn-around. . . . .542
Figure 131. Timing of PRESP_TO after a read request (HS or LP). . . . .543
Figure 132. Timing of PRESP_TO after a write request (HS or LP) . . . . .544
Figure 133. Effect of prep mode at 1 . . . . .545
Figure 134. Command transmission periods within the image area . . . . .546
Figure 135. Transmission of commands on the last line of a frame. . . . .547
Figure 136. LPSIZE for non-burst with sync pulses. . . . .548
Figure 137. LPSIZE for burst or non-burst with sync events . . . . .548
Figure 138. VLPSIZE for non-burst with sync pulses . . . . .550
Figure 139. VLPSIZE for non-burst with sync events . . . . .550
Figure 140. VLPSIZE for burst mode. . . . .550
Figure 141. Location of LPSIZE and VLPSIZE in the image area . . . . .552
Figure 142. Clock lane and data lane in HS . . . . .553
Figure 143. Clock lane in HS and data lanes in LP . . . . .554
Figure 144. Clock lane and data lane in LP. . . . .554
Figure 145. Command transmission by the generic interface . . . . .555
Figure 146. Vertical color bar mode. . . . .557
Figure 147. Horizontal color bar mode. . . . .557
Figure 148. RGB888 BER testing pattern . . . . .558
Figure 149. Vertical pattern (103x15) . . . . .559
Figure 150. Horizontal pattern (103x15) . . . . .559
Figure 151. PLL block diagram . . . . .563
Figure 152. Error sources . . . . .566
Figure 153. Video packet transmission configuration flow diagram. . . . .577
Figure 154. Programming sequence to send a test pattern. . . . .579
Figure 155. Frame configuration registers. . . . .580
Figure 156. RNG block diagram . . . . .638
Figure 157. Entropy source model. . . . .639
Figure 158. CRYPT block diagram . . . . .650
Figure 159. AES-ECB mode overview. . . . .653
Figure 160. AES-CBC mode overview. . . . .654
Figure 161. AES-CTR mode overview. . . . .655
Figure 162. AES-GCM mode overview . . . . .656
Figure 163. AES-GMAC mode overview . . . . .656
Figure 164. AES-CCM mode overview . . . . .657
Figure 165. Example of suspend mode management. . . . .663
Figure 166. DES/TDES-ECB mode encryption . . . . .664
Figure 167. DES/TDES-ECB mode decryption . . . . .665
Figure 168. DES/TDES-CBC mode encryption . . . . .666
Figure 169. DES/TDES-CBC mode decryption . . . . .667
Figure 170. AES-ECB mode encryption . . . . .669
Figure 171. AES-ECB mode decryption . . . . .670
Figure 172. AES-CBC mode encryption . . . . .671
Figure 173. AES-CBC mode decryption . . . . .672
Figure 174. Message construction for the Counter mode . . . . .674
Figure 175. AES-CTR mode encryption . . . . .675
Figure 176. AES-CTR mode decryption . . . . .676
Figure 177. Message construction for the Galois/counter mode . . . . .678
Figure 178. Message construction for the Galois Message Authentication Code mode . . . . .683
Figure 179. Message construction for the Counter with CBC-MAC mode. . . . .684
Figure 180. 64-bit block construction according to the data type (IN FIFO). . . . .691
Figure 181. 128-bit block construction according to the data type. . . . .692
Figure 182. HASH block diagram . . . . .714
Figure 183. Message data swapping feature. . . . .716
Figure 184. HASH suspend/resume mechanism. . . . .722
Figure 185. Advanced-control timer block diagram . . . . .736
Figure 186. Counter timing diagram with prescaler division change from 1 to 2. . . . .738
Figure 187. Counter timing diagram with prescaler division change from 1 to 4. . . . .738
Figure 188. Counter timing diagram, internal clock divided by 1 . . . . .739
Figure 189. Counter timing diagram, internal clock divided by 2 . . . . .740
Figure 190. Counter timing diagram, internal clock divided by 4 . . . . .740
Figure 191. Counter timing diagram, internal clock divided by N. . . . .740
Figure 192. Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded). . . . .		741
Figure 193. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded). . . . .		741
Figure 194. Counter timing diagram, internal clock divided by 1 . . . . .743
Figure 195. Counter timing diagram, internal clock divided by 2 . . . . .743
Figure 196. Counter timing diagram, internal clock divided by 4 . . . . .744
Figure 197. Counter timing diagram, internal clock divided by N. . . . .744
Figure 198. Counter timing diagram, update event when repetition counter is not used. . . . .745
Figure 199. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .746
Figure 200. Counter timing diagram, internal clock divided by 2 . . . . .746
Figure 201. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .747
Figure 202. Counter timing diagram, internal clock divided by N. . . . .747
Figure 203. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .748
Figure 204. Counter timing diagram, update event with ARPE=1 (counter overflow) . . . . .748
Figure 205. Update rate examples depending on mode and TIMx_RCR register settings . . . . .750
Figure 206. Control circuit in normal mode, internal clock divided by 1 . . . . .751
Figure 207. TI2 external clock connection example. . . . .752
Figure 208. Control circuit in external clock mode 1 . . . . .753
Figure 209. External trigger input block . . . . .753
Figure 210. Control circuit in external clock mode 2 . . . . .754
Figure 211. Capture/compare channel (example: channel 1 input stage) . . . . .755
Figure 212. Capture/compare channel 1 main circuit . . . . .755
Figure 213. Output stage of capture/compare channel (channels 1 to 3) . . . . .756
Figure 214. Output stage of capture/compare channel (channel 4). . . . .756
Figure 215. PWM input mode timing . . . . .758
Figure 216. Output compare mode, toggle on OC1. . . . .760
Figure 217. Edge-aligned PWM waveforms (ARR=8) . . . . .761
Figure 218. Center-aligned PWM waveforms (ARR=8) . . . . .762
Figure 219. Complementary output with dead-time insertion . . . . .764
Figure 220. Dead-time waveforms with delay greater than the negative pulse . . . . .764
Figure 221. Dead-time waveforms with delay greater than the positive pulse. . . . .764
Figure 222. Output behavior in response to a break . . . . .767
Figure 223. Clearing TIMx_OCxREF . . . . .768
Figure 224. 6-step generation, COM example (OSSR=1) . . . . .769
Figure 225. Example of one pulse mode . . . . .770
Figure 226. Example of counter operation in encoder interface mode . . . . .773
Figure 227. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .773
Figure 228. Example of Hall sensor interface . . . . .775
Figure 229. Control circuit in reset mode . . . . .776
Figure 230. Control circuit in gated mode . . . . .777
Figure 231. Control circuit in trigger mode . . . . .778
Figure 232. Control circuit in external clock mode 2 + trigger mode . . . . .779
Figure 233. General-purpose timer block diagram . . . . .807
Figure 234. Counter timing diagram with prescaler division change from 1 to 2 . . . . .808
Figure 235. Counter timing diagram with prescaler division change from 1 to 4 . . . . .809
Figure 236. Counter timing diagram, internal clock divided by 1 . . . . .810
Figure 237. Counter timing diagram, internal clock divided by 2 . . . . .810
Figure 238. Counter timing diagram, internal clock divided by 4 . . . . .810
Figure 239. Counter timing diagram, internal clock divided by N. . . . .811
Figure 240. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .811
Figure 241. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .812
Figure 242. Counter timing diagram, internal clock divided by 1 . . . . .813
Figure 243. Counter timing diagram, internal clock divided by 2 . . . . .813
Figure 244. Counter timing diagram, internal clock divided by 4 . . . . .813
Figure 245. Counter timing diagram, internal clock divided by N. . . . .814
Figure 246. Counter timing diagram, Update event . . . . .814
Figure 247. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .815
Figure 248. Counter timing diagram, internal clock divided by 2 . . . . .816
Figure 249. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .816
Figure 250. Counter timing diagram, internal clock divided by N. . . . .816
Figure 251. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .817
Figure 252. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .817
Figure 253. Control circuit in normal mode, internal clock divided by 1 . . . . .818
Figure 254. TI2 external clock connection example. . . . .819
Figure 255. Control circuit in external clock mode 1 . . . . .820
Figure 256. External trigger input block . . . . .820
Figure 257. Control circuit in external clock mode 2 . . . . .821
Figure 258. Capture/compare channel (example: channel 1 input stage) . . . . .822
Figure 259. Capture/compare channel 1 main circuit . . . . .822
Figure 260. Output stage of capture/compare channel (channel 1). . . . .823
Figure 261. PWM input mode timing . . . . .825
Figure 262. Output compare mode, toggle on OC1 . . . . .826
Figure 263. Edge-aligned PWM waveforms (ARR=8) . . . . .828
Figure 264. Center-aligned PWM waveforms (ARR=8). . . . .829
Figure 265. Example of one-pulse mode . . . . .830
Figure 266. Clearing TIMx_OCxREF . . . . .832
Figure 267. Example of counter operation in encoder interface mode . . . . .833
Figure 268. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .834
Figure 269. Control circuit in reset mode . . . . .835
Figure 270. Control circuit in gated mode . . . . .836
Figure 271. Control circuit in trigger mode . . . . .836
Figure 272. Control circuit in external clock mode 2 + trigger mode . . . . .837
Figure 273. Master/Slave timer example . . . . .838
Figure 274. Gating timer 2 with OC1REF of timer 1 . . . . .839
Figure 275. Gating timer 2 with Enable of timer 1 . . . . .840
Figure 276. Triggering timer 2 with update of timer 1 . . . . .841
Figure 277. Triggering timer 2 with Enable of timer 1 . . . . .841
Figure 278. Triggering timer 1 and 2 with timer 1 TI1 input . . . . .843
Figure 279. General-purpose timer block diagram (TIM9 and TIM12) . . . . .868
Figure 280. General-purpose timer block diagram (TIM10/11/13/14) . . . . .869
Figure 281. Counter timing diagram with prescaler division change from 1 to 2 . . . . .871
Figure 282. Counter timing diagram with prescaler division change from 1 to 4 . . . . .871
Figure 283. Counter timing diagram, internal clock divided by 1 . . . . .872
Figure 284. Counter timing diagram, internal clock divided by 2 . . . . .873
Figure 285. Counter timing diagram, internal clock divided by 4 . . . . .873
Figure 286. Counter timing diagram, internal clock divided by N . . . . .873
Figure 287. Counter timing diagram, update event when ARPE=0
(TIMx_ARR not preloaded) . . . . .		874
Figure 288. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded) . . . . .		874
Figure 289. Control circuit in normal mode, internal clock divided by 1 . . . . .875
Figure 290. TI2 external clock connection example . . . . .876
Figure 291. Control circuit in external clock mode 1 . . . . .876
Figure 292. Capture/compare channel (example: channel 1 input stage) . . . . .877
Figure 293. Capture/compare channel 1 main circuit . . . . .878
Figure 294. Output stage of capture/compare channel (channel 1). . . . .878
Figure 295. PWM input mode timing . . . . .880
Figure 296. Output compare mode, toggle on OC1 . . . . .882
Figure 297. Edge-aligned PWM waveforms (ARR=8) . . . . .883
Figure 298. Example of One-pulse mode . . . . .884
Figure 299. Control circuit in reset mode . . . . .886
Figure 300. Control circuit in gated mode . . . . .887
Figure 301. Control circuit in trigger mode . . . . .887
Figure 302. Basic timer block diagram . . . . .914
Figure 303. Counter timing diagram with prescaler division change from 1 to 2 . . . . .916
Figure 304. Counter timing diagram with prescaler division change from 1 to 4 . . . . .916
Figure 305. Counter timing diagram, internal clock divided by 1 . . . . .917
Figure 306. Counter timing diagram, internal clock divided by 2 . . . . .918
Figure 307. Counter timing diagram, internal clock divided by 4 . . . . .918
Figure 308. Counter timing diagram, internal clock divided by N . . . . .918
Figure 309. Counter timing diagram, update event when ARPE = 0
(TIMx_ARR not preloaded). . . . .		919
Figure 310. Counter timing diagram, update event when ARPE=1
(TIMx_ARR preloaded). . . . .		919
Figure 311. Control circuit in normal mode, internal clock divided by 1 . . . . .920
Figure 312. Independent watchdog block diagram . . . . .927
Figure 313. Watchdog block diagram . . . . .933
Figure 314. Window watchdog timing diagram . . . . .934
Figure 315. RTC block diagram . . . . .940
Figure 316. I2C bus protocol . . . . .980
Figure 317. I2C block diagram . . . . .981
Figure 318. Transfer sequence diagram for slave transmitter . . . . .983
Figure 319. Transfer sequence diagram for slave receiver . . . . .984
Figure 320. Transfer sequence diagram for master transmitter . . . . .987
Figure 321. Transfer sequence diagram for master receiver . . . . .988
Figure 322. I2C interrupt mapping diagram . . . . .997
Figure 323. USART block diagram . . . . .1014
Figure 324. Word length programming . . . . .1015
Figure 325. Configurable stop bits . . . . .1017
Figure 326. TC/TXE behavior when transmitting . . . . .1018
Figure 327. Start bit detection when oversampling by 16 or 8 . . . . .1019
Figure 328. Data sampling when oversampling by 16 . . . . .1022
Figure 329. Data sampling when oversampling by 8 . . . . .1023
Figure 330. Mute mode using Idle line detection . . . . .1035
Figure 331. Mute mode using address mark detection . . . . .1035
Figure 332. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .1038
Figure 333. Break detection in LIN mode vs. Framing error detection. . . . .1039
Figure 334. USART example of synchronous transmission. . . . .1040
Figure 335. USART data clock timing diagram (M=0) . . . . .1040
Figure 336. USART data clock timing diagram (M=1) . . . . .1041
Figure 337. RX data setup/hold time . . . . .1041
Figure 338. ISO 7816-3 asynchronous protocol . . . . .1042
Figure 339. Parity error detection using the 1.5 stop bits . . . . .1043
Figure 340. IrDA SIR ENDEC- block diagram . . . . .1045
Figure 341. IrDA data modulation (3/16) -Normal mode . . . . .1045
Figure 342. Transmission using DMA . . . . .1047
Figure 343. Reception using DMA . . . . .1048
Figure 344. Hardware flow control between 2 USARTs . . . . .1048
Figure 345. RTS flow control . . . . .1049
Figure 346. CTS flow control . . . . .1049
Figure 347. USART interrupt mapping diagram . . . . .1051
Figure 348. SPI block diagram. . . . .1064
Figure 349. Full-duplex single master/ single slave application. . . . .1065
Figure 350. Half-duplex single master/ single slave application . . . . .1066
Figure 351. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		1067
Figure 352. Master and three independent slaves. . . . .1068
Figure 353. Multimaster application . . . . .1069
Figure 354. Hardware/software slave select management . . . . .1070
Figure 355. Data clock timing diagram . . . . .1072
Figure 356. TXE/RXNE/BSY behavior in master / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers . . . . .1075
Figure 357. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers . . . . .1076
Figure 358. Transmission using DMA . . . . .1078
Figure 359. Reception using DMA . . . . .1079
Figure 360. TI mode transfer . . . . .1082
Figure 361. I 2 S block diagram . . . . .1085
Figure 362. I2S full-duplex block diagram . . . . .1086
Figure 363. I 2 S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . .1088
Figure 364. I 2 S Philips standard waveforms (24-bit frame with CPOL = 0). . . . .1088
Figure 365. Transmitting 0x8EAA33 . . . . .1088
Figure 366. Receiving 0x8EAA33 . . . . .1089
Figure 367. I 2 S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . .1089
Figure 368. Example of 16-bit data frame extended to 32-bit channel frame . . . . .1089
Figure 369. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . .1090
Figure 370. MSB justified 24-bit frame length with CPOL = 0 . . . . .1090
Figure 371. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .1090
Figure 372. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . .1091
Figure 373. LSB justified 24-bit frame length with CPOL = 0 . . . . .1091
Figure 374. Operations required to transmit 0x3478AE. . . . .1091
Figure 375. Operations required to receive 0x3478AE . . . . .1092
Figure 376. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .1092
Figure 377. Example of 16-bit data frame extended to 32-bit channel frame . . . . .1092
Figure 378. PCM standard waveforms (16-bit) . . . . .1093
Figure 379. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .1093
Figure 380. Audio sampling frequency definition . . . . .1094
Figure 381. I 2 S clock generator architecture . . . . .1094
Figure 382. SAI functional block diagram . . . . .1114
Figure 383. Audio frame . . . . .1117
Figure 384. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .1119
Figure 385. FS role is start of frame (FSDEF = 0). . . . .1120
Figure 386. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .1121
Figure 387. First bit offset . . . . .1121
Figure 388. Audio block clock generator overview . . . . .1122
Figure 389. AC'97 audio frame . . . . .1126
Figure 390. SPDIF format . . . . .1127
Figure 391. SAI_xDR register ordering . . . . .1128
Figure 392. Data companding hardware in an audio block in the SAI . . . . .1131
Figure 393. Tristate strategy on SD output line on an inactive slot . . . . .1133
Figure 394. Tristate on output data line in a protocol like I2S . . . . .1134
Figure 395. Overrun detection error. . . . .1135
Figure 396. FIFO underrun event . . . . .1135
Figure 397. “No response” and “no data” operations. . . . .1164
Figure 398. (Multiple) block read operation . . . . .1164
Figure 399. (Multiple) block write operation . . . . .1164
Figure 400. Sequential read operation. . . . .1165
Figure 401. Sequential write operation . . . . .1165
Figure 402. SDIO block diagram . . . . .1165
Figure 403. SDIO adapter . . . . .1167
Figure 404. Control unit . . . . .1168
Figure 405. SDIO_CK clock dephasing (BYPASS = 0) . . . . .1168
Figure 406. SDIO adapter command path . . . . .1169
Figure 407. Command path state machine (SDIO) . . . . .1170
Figure 408. SDIO command transfer . . . . .1171
Figure 409. Data path . . . . .1173
Figure 410. Data path state machine (DPSM) . . . . .1174
Figure 411. CAN network topology . . . . .1223
Figure 412. Dual-CAN block diagram . . . . .1224
Figure 413. bxCAN operating modes . . . . .1226
Figure 414. bxCAN in silent mode . . . . .1227
Figure 415. bxCAN in Loop back mode . . . . .1227
Figure 416. bxCAN in combined mode . . . . .1228
Figure 417. Transmit mailbox states . . . . .1230
Figure 418. Receive FIFO states . . . . .1231
Figure 419. Filter bank scale configuration - Register organization . . . . .1233
Figure 420. Example of filter numbering . . . . .1234
Figure 421. Filtering mechanism example . . . . .1235
Figure 422. CAN error state diagram . . . . .1237
Figure 423. Bit timing . . . . .1239
Figure 424. CAN frames . . . . .1240
Figure 425. Event flags and interrupt generation . . . . .1241
Figure 426. CAN mailbox registers . . . . .1253
Figure 427. OTG_FS full-speed block diagram . . . . .1271
Figure 428. OTG_HS high-speed block diagram . . . . .1272
Figure 429. OTG_FS/OTG_HS A-B device connection . . . . .1275
Figure 430. OTG_FS/OTG_HS peripheral-only connection . . . . .1277
Figure 431. OTG_FS/OTG_HS host-only connection . . . . .1281
Figure 432. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . .1285
Figure 433. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .1287
Figure 434. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .1288
Figure 435. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . .1289
Figure 436. Interrupt hierarchy . . . . .1293
Figure 437. Transmit FIFO write task . . . . .1397
Figure 438. Receive FIFO read task . . . . .1398
Figure 439. Normal bulk/control OUT/SETUP . . . . .1400
Figure 440. Bulk/control IN transactions . . . . .1404
Figure 441. Normal interrupt OUT . . . . .1407
Figure 442. Normal interrupt IN . . . . .1412
Figure 443. Isochronous OUT transactions . . . . .1414
Figure 444. Isochronous IN transactions . . . . .1417
Figure 445. Normal bulk/control OUT/SETUP transactions - DMA . . . . .1419
Figure 446. Normal bulk/control IN transaction - DMA . . . . .1421
Figure 447. Normal interrupt OUT transactions - DMA mode . . . . .1422
Figure 448. Normal interrupt IN transactions - DMA mode . . . . .1423
Figure 449. Normal isochronous OUT transaction - DMA mode . . . . .1424
Figure 450. Normal isochronous IN transactions - DMA mode . . . . .1425
Figure 451. Receive FIFO packet read . . . . .1431
Figure 452. Processing a SETUP packet . . . . .1433
Figure 453. Bulk OUT transaction . . . . .1440
Figure 454. TRDT max timing case . . . . .1449
Figure 455. A-device SRP . . . . .1450
Figure 456. B-device SRP . . . . .1451
Figure 457. A-device HNP . . . . .1452
Figure 458. B-device HNP . . . . .1454
Figure 459. ETH block diagram . . . . .1460
Figure 460. SMI interface signals . . . . .1461
Figure 461. MDIO timing and frame structure - Write cycle . . . . .1462
Figure 462. MDIO timing and frame structure - Read cycle . . . . .1463
Figure 463. Media independent interface signals . . . . .1464
Figure 464. MII clock sources . . . . .1466
Figure 465. Reduced media-independent interface signals . . . . .1466
Figure 466. RMII clock sources- . . . . .1467
Figure 467. Clock scheme . . . . .1467
Figure 468. Address field format . . . . .1469
Figure 469. MAC frame format . . . . .1471
Figure 470. Tagged MAC frame format . . . . .1471
Figure 471. Transmission bit order . . . . .1478
Figure 472. Transmission with no collision . . . . .1478
Figure 473. Transmission with collision . . . . .1479
Figure 474. Frame transmission in MMI and RMII modes . . . . .1479
Figure 475. Receive bit order . . . . .1483
Figure 476. Reception with no error . . . . .1484
Figure 477. Reception with errors . . . . .1484
Figure 478. Reception with false carrier indication . . . . .1484
Figure 479. MAC core interrupt masking scheme . . . . .1485
Figure 480. Wakeup frame filter register . . . . .1490
Figure 481. Networked time synchronization . . . . .1493
Figure 482. System time update using the Fine correction method . . . . .1495
Figure 483. PTP trigger output to TIM2 ITR1 connection . . . . .1497
Figure 484. PPS output . . . . .1498
Figure 485. Descriptor ring and chain structure . . . . .1499
Figure 486. TxDMA operation in default mode . . . . .1503
Figure 487. TxDMA operation in OSF mode . . . . .1505
Figure 488. Normal transmit descriptor . . . . .1506
Figure 489. Enhanced transmit descriptor . . . . .1512
Figure 490. Receive DMA operation . . . . .1514
Figure 491. Normal Rx DMA descriptor structure . . . . .1516
Figure 492. Enhanced receive descriptor field format with IEEE1588 time stamp enabled . . . . .1522
Figure 493. Interrupt scheme . . . . .1525
Figure 494. Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR) . . . . .1536
Figure 495. Block diagram of STM32 MCU and Cortex ® -M4-level debug support . . . . .1578
Figure 496. SWJ debug port . . . . .1580
Figure 497. JTAG TAP connections . . . . .1583
Figure 498. TPIU block diagram . . . . .1603

Chapters