43. Revision history

Updated FMC Section:

Updated Table 83: Programmable NAND flash access parameters memory setup time, memory hold max value.

Updated c7amba_fmc_V2_UserSpec :

• - Updated Section : Common memory space timing register (FMC_PMEM) MEMSEY, MEMHOLD, MEMHIZ registers.
• - Updated Section : Attribute memory space timing register (FMC_PATT) ATTSET, ATTHOLD, ATTHIZ register.
• - Updated Table 89: FMC register map and reset values and the bitfield description adding [x:x].
  and FMC_SDCR2 Bit 13 to bit 31 reserved.
• - Updated Section : SRAM/NOR-flash chip-select control register for bank x (FMC_BCRx) CPSIZE[2:0] bits description adding 011 configuration.

Updated SYSARCHI section:

• - Updated Section 2.1.8: DMA memory bus and Section 2.1.9: DMA peripheral bus adding 'internal Flash memory'.
• - Updated Section 2.1.6: CPU AHBS bus .

Updated Flash memory section:

• - Updated Section 3.3.1: Flash memory organization .
• - Updated Section 3.3.8: Flash Interrupts replacing FLASH_SR by FLASH_CR register.

Updated c7amba_ioport_UserSpec removing GPIO port bit reset register (GPIOx_BRR) (x = A..K) in the bit field and in Table 23: GPIO register map and reset values .

Updated c7amba_spi2s1_v3_x_UserSpec Section 32.1: Introduction hiding "full duplex and".

Updated LTDC section:

• - All registers updated, adding [x:x] in the register bit description, register map and putting bold character format.
• - Updated Section 18.4.2: Layer programmable parameters .
• - Updated Section 18.7.4: LTDC Total Width Configuration Register (LTDC_TWCR) TOTALW[11:0] bit field.
• - Updated Section 18.7.5: LTDC Global Control Register (LTDC_GCR) bit 29 description.

Updated USART section:

• - Updated note in Section 31.5.13: USART Smartcard mode about the RTO counter start.
• - Updated Table 178: USART interrupt requests removing error in the line receiver timeout error.

• - Updated Section 32.5.2: Communications between one master and one slave and Section 32.5.3: Standard multislave communication figures 340, 341, 342 and 343.
• - Notes updated and added below the figures.
• - Added Section 32.5.4: Multimaster communication .

• - Updated Section 13.5.3: SDRAM address mapping .
• - Updated Section 13.8.6: FMC register map .
• - Changed figures for Mode1, ModeA, Mode2, ModeB, ModeC and Mixed write access waveforms (from FSMC to FMC).
• - Updated Section 13.6.4: NOR flash/PSRAM controller asynchronous transactions .
• - Updated Section : FIFO status and interrupt register (FMC_SR) adding note for Bit0 (IRS) and Bit2 (IFS).
• - Updated Section : SRAM/NOR-flash chip-select timing register for bank x (FMC_BTRx) .
• Updated Section : SRAM/NOR-flash write timing registers x (FMC_BWTRx) .

• - Updated Section 2.5: Boot configuration embedded bootloader description.

• - Updated : I2C timings and Figure 301: Setup and hold timings .

• - Updated Section 37: USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS) .

Replaced nCTS by CTS - nRTS by RTS - SCLK by CK everywhere in the document.

Replaced "w" by "rc_w1" in Section 31.8.9: Interrupt flag clear register (USARTx_ICR) .

Updated RTOF bit description in USARTx_ISR .

Removed LPTIM1 option register (LPTIM1_OR).

Updated Section 22.3.16: Using the break function description.

• Updated Section : Choosing the value of TRDT in OTG_GUSBCFG .
• Updated TRDT bit description in Section 37.15.4: OTG USB configuration register (OTG_GUSBCFG) .
• Added Table 234: TRDT values (FS) and Table 235: TRDT values (HS) .
• Updated Section 37.15.4: OTG USB configuration register (OTG_GUSBCFG) PHYSEL bit "r" to "rw" and PHYSEL description for USB OTG_HS.

Updated RTC section:
Updated reference to TAMPTS bit in Section 29.3.13: Time-stamp function .

Updated ADC section:
Added note in Section 15.13.7: ADC watchdog higher threshold register (ADC_HTR) and Section 15.13.8: ADC watchdog lower threshold register (ADC_LTR) .

Updated LTDC section:
Updated Section 18.3.2: LTDC reset and clocks .

Updated SDMMC section:
Updated limit from 48 to 50 MHz in Section 35.1: SDMMC main features , Section 35.3: SDMMC functional description , Section 35.8.1: SDMMC power control register (SDMMC_POWER) , Section 35.8.2: SDMMC clock control register (SDMMC_CLKCR) and in Section 35.8.4: SDMMC command register (SDMMC_CMD) .

Updated general purpose timer section:
Updated reset value to 0xFFFF in Section 23.4.15: TIMx auto-reload register (TIMx_ARR)(x = 2 to 5) .
Updated CC1IF bit description in Section 23.4.5: TIMx status register (TIMx_SR)(x = 2 to 5) .
Added Section 23.3.14: Retriggerable one pulse mode .

Update PWR power controller section:
Updated Section 4.4.2: PWR power control/status register (PWR_CSR1) 'EIWUP' bit 8 introduced in the register field and register map.
Updated Table 18 and Table 19 PPDs bit is cleared in Power Control register (PWR_CR1).
Updated Table 19: Standby mode entry and exit WUIF bit is cleared in PWR_CSR1, EIWUP bit is set in PWR_CSR1.
Updated Section : RTC alternate functions to wake up the device from the Standby mode adding new "c" bullet for the three cases.

Updated USART section:
Updated Section 31.8.3: Control register 3 (USARTx_CR3) 'ONEBIT' bit 11 description adding a note.

Updated Electronic signature section:
Updated Section 41.1: Unique device ID register (96 bits) UID[31:0] bits used for X,Y coordinates on the wafer, Lot number and Wafer number.

Updated interrupts section:
Updated Section 11.9.1: Interrupt mask register (EXTI_IMR) MRx to IMx bit description in the bit field and register map.
Updated Section 11.9.2: Event mask register (EXTI_EMR) MRx to EMx bit description in the bit field and register map.

Updated FMC section:

Updated BUSTURN bit description in Section : SRAM/NOR-flash chip-select timing register for bank x (FMC_BTRx) .

Updated Section 13.8.3: SDRAM controller functional description .

Updated Figure 53: NAND flash controller waveforms for common memory access adding note 2.

Updated Section 13.7.5: NAND flash prewait functionality .

Updated Common memory space timing register (FMC_PMEM) MEMHOLD[7:0] description.

Updated Attribute memory space timing register (FMC_PATT) ATTHOLD[7:0] description.

Updated Section 13.4: AHB interface .

Updated Table 63: FMC_BCRx bitfields (mode 1) bit 10 and 11 description.

Updated Flash memory section:

Updated Section 3.5: FLASH memory protection read protection (RDP) description and note added.

Updated PWR section:

• – Updated Table 14: Features over all modes cryptographic processor (CRYP), USB OTG_FS, USB OTG_HS and Ethernet rows.

Updated DMA section:

• – Updated Section 8.5.5: DMA stream x configuration register (DMA_SxCR) bit 18 “DBM or reserved” by “DBM” and “rw or r” by “rw”.

Updated DMA2D1 section:

• – Updated Section 9.3.12: DMA2D transfer control (start, suspend, abort and completion) putting “automatic CLUT transfers can also be aborted or suspended by using the ABORT or the SUSP bit of the DMA2D_CR register”.
• – Updated Section 9.5.8: DMA2D foreground PFC control register (DMA2D_FGPFCCR) START bit property in the table by “rs”.
• – Updated Section 9.5.10: DMA2D background PFC control register (DMA2D_BGPFCCR) START bit property in the table by “rs”. and START bit description putting “data transfer or automatic foreground CLUT transfer”.

Updated RTC section:

• – Added case of RTC clocked by LSE in Section 29.3.9: Resetting the RTC .

Updated RCC section:

• – Updated Section 5.2.8: RTC/AWU clock adding “the RTC remains clocked and functional under system reset” when the RTC clock is LSE.
• – Updated Section 5.3.26: RCC dedicated clocks configuration register (DCKCFGR2) and Section 5.3.27: RCC register map bit28 renamed SDMMC1SEL.

Updated HASH section:

• – Updated Figure 143: Message data swapping feature .

Updated TIMER section:

• – Updated Section 25.4.7: TIMx prescaler (TIMx_PSC)(x = 6 to 7) PSC[15:0] bits description.
• – Updated Section 24.4.10: TIMx prescaler (TIMx_PSC)(x = 9, 12) PSC[15:0] bits description.
• – Updated Section 24.5.1: TIMx control register 1 (TIMx_CR1)(x = 10, 11, 13, 14) adding OPM bit-field.
• – Updated Section 24.5.13: TIM10/TIM11/TIM13/TIM14 register map adding OPM bit.
• – Updated Section 22.4.5: TIMx status register (TIMx_SR)(x = 1, 8) and Section 22.4.27: TIM8 register map CC5IF and CC6IF bit names.
• – Updated Section 26: Low-power timer (LPTIM) changing register name LPTIMx_regrname in LPTIM_regrname.

Updated FMC section:

• – Updated Section : SRAM/NOR-flash chip-select timing register for bank x (FMC_BTRx) busturn bits description.
• – Updated Figure 47: Muxed write access waveforms NWE signal negative edge.
• – Updated Figure 53: NAND flash controller waveforms for common memory access replacing 'MEMxHIZ' by 'MEMxHIZ+1'.
• – Updated Section : Common memory space timing register (FMC_PMEM) MEMHOLD[7:0] and Section : Attribute memory space timing register (FMC_PATT) ATTHOLD[7:0] replacing 257 HCLK by 256 HCLK.
• – Updated Section : SDRAM control register x (FMC_SDCRx) adding RPIPE[1:0] description.

Updated I2C2 section:

• – Updated Section 48.4.5: I2C initialization, Section 30.4.9: I2C controller mode and Section 30.7.5: Timing register (I2C_TIMINGR).

Updated cover adding the PM0253 programming manual in the related document list.

Updated system configuration:

• – Updated Section 2.1.12: LCD-TFT controller DMA bus description.

Updated USART section:

• – Updated Section 31: Universal synchronous/asynchronous receiver transmitter (USART/UART) changing register name USARTx_regrname in USART_regrname.

• – Updated Section 40: LCD-TFT display controller (LTDC) .
• – Updated Section 40.7.15: LTDC layer x window horizontal position configuration register (LTDC_LxWHPCR) removing “all values within this range are allowed” and updating the WHSPPPOS[11:0] and WHSTPOS[11:0] bit description.
• – Updated Section 40.7.15: LTDC layer x window horizontal position configuration register (LTDC_LxWHPCR) removing “all values within this range are allowed” and updating the WVSPPOS[10:0] and WVSTPOS[10:0] bit description.
• – Updated Table 116: LTDC pins and signal interface modifying ‘Data Enable’ by ‘Not Data Enable’.

• – Updated Section 4.1.4: Voltage regulator removing low voltage mode in under-drive mode.
• – Updated Section : Entering low-power mode removing low voltage.

• – Updated Section 3.3.7: Flash programming sequences adding note about the FLASH_CR register.
• – Updated Section 3.3.7: Flash programming sequences adding a note in Section : Standard programming .
• – Updated Section : Modifying user option bytes adding a note about the FLASH_OPTCR register.

Updated RCC section:

• – Updated Section 5.3.3: RCC clock configuration register (RCC_CFGR) two cautions replacing 90 MHz by 108 MHz and 45 MHz by 54 MHz.
• – Updated Section 5.3.2: RCC PLL configuration register (RCC_PLLCFGR) PLLP[1:0] bit description replacing '180 MHz' by '216 MHz'.

Updated RTC section:

• – Updated Figure 284: RTC block diagram RTC_WUTR 'ck_spre' input.
• – Updated ADD1H and SUB1H bit descriptions in Section 29.6.3: RTC control register (RTC_CR) .
• – Updated Section : RTC backup registers and Section 29.6.20: RTC backup registers (RTC_BKPxR) RTC_BKPxR registers cannot be reset when the Flash readout protection is disabled.
• – Added caution at the end of Section 29.6.3: RTC control register (RTC_CR) .
• – Updated caution at the end of Section 29.6.16: RTC tamper configuration register (RTC_TAMPCR) .

Updated FMC section:

• – Updated Section : SDRAM control register x (FMC_SDCRx) replacing 'KCK_FMC' by 'HCLK' in RPIPE[1:0] description.
• – Updated Section : SRAM/NOR-flash chip-select timing register for bank x (FMC_BTRx) and Section : SRAM/NOR-flash write timing registers x (FMC_BWTRx) BUSTURN[3:0] bit description replacing 'FMC' by 'HCLK' clock cycle.

Updated LCD-TFT section:

• – Updated Section 40.4.2: Layer programmable parameters modifying configuring 'WHSTPOS[10:0]' and 'WHSPPPOS[10:0]' by 'WVSTPOS[10:0]' and 'WVSPPOS[10:0]' in the LTDC_LxWVPCR register.
• – Updated Figure 421: Layer window programmable parameters .
• – Updated Section : Example of synchronous timings configuration LTDC_SSCR register.

Updated USART section:

• – Updated Section 31.8.8: USART interrupt and status register (USART_ISR) RWU bit available independently of the wakeup from stop feature availability.
• – Updated Section 31.8.12: USART register map .
• – Updated Table 199: Error calculation for programmed baud rates at \( f_{CK} = 216\text{ MHz} \) in both cases of oversampling by 8 (OVER8 = 1) .

Updated I2C2 section:

• – Updated Section 30.4.9: I2C controller mode note in Master communication initialization (address phase) paragraph.
• – Updated Section 30.7.2: Control register 2 (I2C_CR2) completing the note of bit 13 'START' description.

Updated DEBUG section:

• – Updated Section 40.16.2: Debug support for timers, watchdog, bxCAN and I ² C adding a paragraph for timers having complementary outputs.
• – Updated Section 40.16.5: Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) and Section 40.16.6: Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ) DBG_TIMx_STOP bit description.

Updated TIMER section:

• – Updated Section 22.3.27: DMA burst mode adding note 'reserved registers can be written with a null value'.
• – Updated Section 22.3.28: Debug mode adding 'for safety purposes' paragraph.
• – Updated Table 150: Output control bits for complementary OCx and OCxN channels with break feature in Section 22: Advanced-control timers (TIM1/TIM8) .
• – Updated Section 23.4.16: TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) , Section 23.4.17: TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) , Section 23.4.18: TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5) and Section 23.4.19: TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5) bit description adding 'the CCRx register is read-only and cannot written' and putting rw/r for all the bits.

Updated ADC section:

Updated all 'CCx' by 'CHx' references and removing 'event' in:

• – Figure 70: Single ADC block diagram .
• – Table 96: External trigger for regular channels .
• – Table 97: External trigger for injected channels .
• – Section 15.13.3: ADC control register 2 (ADC_CR2) EXTSEL[3:0] and JEXTSEL[3:0] bit description .

Updated Arm word and added logo.

Updated USB section:

• – Complete re-mastering of the section
• – Added Section 37.4.2: OTG_FS/OTG_HS pin and internal signals.
• – Updated Section 37.15.16: OTG core ID register (OTG_CID).
• – Updated Section 37.15.41: OTG all endpoints interrupt mask register (OTG_DAINTEMSK) replacing bit 18 by bit 19 in OEPM bit description.

Updated memory organization section

Added Figure 2: Memory map.

Updated SPDIFRX section:

• – All reference to spdifrx_ck_symb removed.
• – Updated Figure 413: SPDIFRX block diagram.
• – Removed 'symbol clock generation' paragraph.

Updated general-purpose timer section:

• – Updated Section 24.5.12: TIM11 option register 1 (TIM11_OR) TI1_RMP[1:0] bits 1/0 description by SPDIFRX_FRAME_SYNC .... SPDIF frames.
• – Updated Section 23.4.3: TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) Bits 6:4 TS: Trigger selection description removing 'reserved'.
• – Updated Section : SDRAM control register x (FMC_SDCRx) bits [1:0] '01' description for SPDIFRX_FRAME_SYNC'.
• – Added Section 24.3.12: Retriggerable one pulse mode (TIM12 only).
• – Added Section 24.3.13: UIF bit remapping.
• – Added Section 24.3.15: Timer input XOR function.

Updated RCC section

• – Updated Figure 13: Clock tree OTG_HS_SCL renamed by OTG_HS_ULPI_CK.
• – Updated Section 5.3.21: RCC clock control & status register (RCC_CSR) bit RMVF put in read/write.
• – Updated Section 5.3.27: RCC register map PADRSTF in PINRSTF.
• – Updated Section 5.3.20: RCC backup domain control register (RCC_BDCR) adding LSEDRV[1:0] in the description.
• – Updated Section 5.3.14: RCC APB2 peripheral clock enable register (RCC_APB2ENR) ADC1EN, ADC2EN and ADC2EN are enabled when bit set to '1'.

Updated Document conventions section:

• – Updated Section 1.2: List of abbreviations for registers

Updated PWR section:

• – Updated Section 4.1.5: Battery backup domain note removing 'only one I/O at a time can be used as an output' sentence.
• – Updated Section 4.4.2: PWR power control/status register (PWR_CSR1) bits[19:18] UDRDY[1:0] description.
• – Updated Section 4.1.3: Battery backup domain step 3 of 'Access to the backup SRAM' paragraph.

Updated Flash memory section:

• – Updated Section 3.7.7: Flash option control register (FLASH_OPTCR1) and Section 3.7.8: Flash interface register map reset value at '0x0040 0000'.

Updated FMC section:

• – Updated Section : SDRAM control register x (FMC_SDCRx) replacing 'KCK_FMC' by 'HCLK' in RPIPE[1:0] description.080'.
• – Updated SDRAM controller read cycle: CAS latency = 3, RPIPE delay = 0 to 2: Five data.

Updated RTC section.:

• – Updated Section 29.6.3: RTC control register (RTC_CR) WUTE bit description adding note.
• – Updated Figure 298: RTC block diagram WUCKSEL dividers for /2,4,8,16.

Updated ETHERNET section:

• – Updated Section : Ethernet MAC MII address register (ETH_MACMIIAR) bits[4:2] clock range of setting 100 is valid for 150-216 MHz.

Updated QUADSPI section:

• – Added Table 90: QUADSPI pins.
• – Updated Section 14.5.1: QUADSPI control register (QUADSPI_CR) PRESCALER[7:0] bit description.

Updated DCMI section:

• – Section DCMI pins merged with Section 17.4.3: DCMI physical interface.
• – External signals HSYNC, VSYNC and PIXCLK standardized to DCMI_HSYNC, DCMI_VSYNC and DCIM_PIXCLK in the whole document.

Updated LTDC section:

• – Updated Section 40.3.3: LTDC reset and clocks.
• – Updated CFBP bitfield size in LTDC_LxCFBLR.

Updated RNG section:

• – Updated Section 19: True random number generator (RNG).

Updated CRYP section:

• – Updated Section 20: Cryptographic processor (CRYP).

Updated HASH section.

• – Updated Section 21: Hash processor (HASH).

Updated LPTIM section:

• – Added Section 26.4.2: LPTIM trigger mapping.
• – Added Table 168: Interrupt events.

• – Updated Figure 301: Setup and hold timings.

• – Updated Section 33.5.18: SAI register map MCJDIV by MCKDIV bit name.
• – Added Section 33.3.2: SAI pins and internal signals.

• – Updated Table 197: STM32F75xxx and STM32F74xxx USART features adding note 2.

• – Removed text note ‘When the SPI is in slave mode ....the clock is stable in steady state’.
• – Updated Section 32.5.9: Data transmission and reception procedures cross reference ‘communication using DMA’.
• – Updated Section 32.7.2: I2S full duplex
• – Updated Section 32.1: Introduction.
• – Updated Section 32.9.9: SPIx_I2S prescaler register (SPIx_I2SPR) removing example.

• – Updated Section 35.8.8: SDMMC data length register (SDMMC_DLEN) note.

Updated system architecture section:

• – Updated Figure 1: System architecture for STM32F75xxx and STM32F74xxx devices .

Updated embedded Flash memory section:

• – Updated Section 3.3.1: Flash memory organization and added Table 4: STM32F750xx Flash memory organization .

Updated LCD-TFT controller section:

• – Updated Section 40: LCD-TFT display controller (LTDC) “STM32F756xx and STM32F46xx” by “STM32F756xx, STM32F750xx and STM32F46xx”.

Updated CRYP section:

• – Updated Section 20: Cryptographic processor (CRYP) adding introduction for the whole STM32F756xx and STM32F750xx devices.

Updated HASH section:

• – Updated Section 21: Hash processor (HASH) “STM32F756xx” by “STM32F756xx and STM32F750xx”.

Updated RCC section:

• – Updated Section 41.3: Package data register 0x1FF0 7BF0" instead of "0x1FFF 7BF0.

Updated RCC section:

• – Updated Section 5.3.25: RCC dedicated clocks configuration register (RCC_DCKCFGR1) name.

Updated I2C section:

Updated Section 48.4.1: I2C block diagram :

• – Removed ‘For I2C I/Os supporting 20mA ... refer to section: I2C implementation’ paragraph.
• – removed ‘this independent clock source .... refer to RCC for more details’ paragraph.

Updated Section 48.4.5: I2C initialization removing the reference to RCC.

Updated Section 30.4.9: I2C controller mode master communication initialization (address phase) note.

Updated Section 30.6: I2C interrupts :

• – Updated Table 195: I2C interrupt requests according to new IP guideline (acronym column).
• – Removed figure: I2C interrupt mapping diagram.
• – Removed ‘depending on the product implementation ..refer to section EXTI’ paragraph.

Updated Section 30.9.2: I2C control register 2 (I2C_CR2) START bit 13 description and note.

Updated Debug support section:

• – Updated Section 40.6.1: MCU device ID code by ‘0x1001 = Revision Z and 1’.

Small text updates in the document.
Updated:

• – Exiting low-power mode
• – Section 3.3.5: Maximum program/erase parallelism
• – PTP clock source in Figure 13: Clock tree
• – Typo in Section 6.4: GPIO registers
• – Section 3.5.1: Read protection (RDP)
• – Table 25: DMA1 request mapping
• – Section 15.10: Temperature sensor
• – Section 22.4.5: TIMx status register (TIMx_SR)(x = 1, 8)
• – Base address for package data register in Section 41: Device electronic signature
• – Base address in Section 41.3: Package data register

Added Section 42: Important security notice

Master and slave terms in Section 30: Inter-integrated circuit interface (I2C) replaced with controller and target, respectively.