16. Digital-to-analog converter (DAC)

16.1 DAC introduction

The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each with its own converter. In dual DAC channel mode, conversions could be done independently or simultaneously when both channels are grouped together for synchronous update operations. An input reference pin, $V_{REF+}$ (shared with ADC) is available for better resolution.

16.2 DAC main features

• Two DAC converters: one output channel each
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• Dual DAC channel for independent or simultaneous conversions
• DMA capability for each channel
• DMA underrun error detection
• External triggers for conversion
• Input voltage reference, $V_{REF+}$

Figure 93 shows the block diagram of a DAC channel and Table 102 gives the pin description.

Figure 93. DAC channel block diagram

Figure 93. DAC channel block diagram. The diagram shows the internal architecture of a DAC channel. On the left, an external trigger (EXTI_9) and a 'trigger selector' block (receiving inputs from SWTRIGx, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO, TIM6_TRGO, TIM7_TRGO, and TIM8_TRGO) are connected to a 'Control logicx' block. The 'Control logicx' block also receives a 12-bit input from 'DHRx' and control signals from a 'DAC control register' (TSELx[2:0] bits, DMAENx, DMA requestx, TENx, MAMPx[3:0] bits, and WAVENx[1:0] bits). The 'Control logicx' block contains 'LFSRx' and 'trianglex' sub-blocks and outputs a 12-bit signal to 'DORx'. 'DORx' then outputs a 12-bit signal to a 'Digital-to-analog converterx' block. The 'Digital-to-analog converterx' block receives V_DDA, V_SSA, and V_REF+ inputs and produces the final output, DAC1_OUT1/2. The identifier 'ai14708d' is present in the bottom right corner of the diagram.

Table 102. DAC pins

Name	Signal type	Remarks
V _REF+	Input, analog reference positive	The higher/positive reference voltage for the DAC, $1.8\text{ V} \leq V_{\text{REF+}} \leq V_{\text{DDA}}$
V _DDA	Input, analog supply	Analog power supply
V _SSA	Input, analog supply ground	Ground for analog power supply
DAC_OUTx	Analog output signal	DAC channelx analog output

Note: Once the DAC channelx is enabled, the corresponding GPIO pin (PA4 or PA5) is automatically connected to the analog converter output (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin should first be configured to analog (AIN).

16.3 DAC functional description

16.3.1 DAC channel enable

Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR register. The DAC channel is then enabled after a startup time $t_{\text{WAKEUP}}$ .

Note: The ENx bit enables the analog DAC channelx macrocell only. The DAC channelx digital interface is enabled even if the ENx bit is reset.

16.3.2 DAC output buffer enable

The DAC integrates two output buffers that can be used to reduce the output impedance, and to drive external loads directly without having to add an external operational amplifier. Each DAC channel output buffer can be enabled and disabled using the corresponding BOFFx bit in the DAC_CR register.

Figure 94. DAC output buffer connection

The diagram illustrates the internal architecture of the DAC output buffers. On the left, two 8-bit input signals, TSEL1[2:0] and TSEL2[2:0], enter the DAC1 block. Inside, they are processed by CH1 and CH2. Each channel has a 12-bit output that connects to a buffer. The buffers are labeled 'Buffer' and are controlled by DAC_CR.BOFF1 and DAC_CR.BOFF2. The output of Buffer 1 is connected to PA4, and the output of Buffer 2 is connected to PA5. The buffers can be bypassed when off, as indicated by the text 'Bypass, when off' next to each buffer.

Figure 94: DAC output buffer connection diagram. The diagram shows two DAC channels, CH1 and CH2, within a DAC1 block. Each channel receives an 8-bit input from TSEL1[2:0] and TSEL2[2:0] respectively. The 12-bit output of each DAC is connected to a buffer. The buffers are controlled by DAC_CR.BOFF1 and DAC_CR.BOFF2. The output of Buffer 1 is connected to PA4, and the output of Buffer 2 is connected to PA5. The buffers can be bypassed when off.

16.3.3 DAC data format

Depending on the selected configuration mode, the data have to be written into the specified register as described below:

• Single DAC channelx, there are three possibilities:
- – 8-bit right alignment: the software has to load data into the DAC_DHR8Rx [7:0] bits (stored into the DHRx[11:4] bits)
- – 12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4] bits (stored into the DHRx[11:0] bits)
- – 12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0] bits (stored into the DHRx[11:0] bits)

Depending on the loaded DAC_DHRyyxx register, the data written by the user is shifted and stored into the corresponding DHRx (data holding registerx, which are internal non-memory-mapped registers). The DHRx register is then loaded into the DORx register either automatically, by software trigger or by an external event trigger.

Figure 95. Data registers in single DAC channel mode

ai14710b

Figure 95: Data registers in single DAC channel mode. A diagram showing a 32-bit register (bits 31 to 0) with three alignment options: 8-bit right aligned, 12-bit left aligned, and 12-bit right aligned. The 8-bit right aligned option shows data in bits 7:0. The 12-bit left aligned option shows data in bits 31:20. The 12-bit right aligned option shows data in bits 11:0.

• Dual DAC channels, there are three possibilities:
- – 8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD [7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits)
- – 12-bit left alignment: data for DAC channel1 to be loaded into the DAC_DHR12LD [15:4] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be loaded into the DAC_DHR12LD [31:20] bits (stored into the DHR2[11:0] bits)
- – 12-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR12RD [11:0] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be loaded into the DAC_DHR12LD [27:16] bits (stored into the DHR2[11:0] bits)

Depending on the loaded DAC_DHRyyD register, the data written by the user is shifted and stored into DHR1 and DHR2 (data holding registers, which are internal non-memory-mapped registers). The DHR1 and DHR2 registers are then loaded into the DOR1 and DOR2 registers, respectively, either automatically, by software trigger or by an external event trigger.

Figure 96. Data registers in dual DAC channel mode

ai14709b

Figure 96: Data registers in dual DAC channel mode. A diagram showing a 32-bit register (bits 31 to 0) with three alignment options: 8-bit right aligned, 12-bit left aligned, and 12-bit right aligned. The 8-bit right aligned option shows data for channel 1 in bits 11:4 and channel 2 in bits 15:8. The 12-bit left aligned option shows data for channel 1 in bits 11:0 and channel 2 in bits 31:20. The 12-bit right aligned option shows data for channel 1 in bits 11:0 and channel 2 in bits 27:16.

16.3.4 DAC conversion

The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register (write to DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12RD).

Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR register is set) and a trigger occurs, the transfer is performed three APB1 clock cycles later.

When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time $t_{\text{SETTLING}}$ that depends on the power supply voltage and the analog output load.

Figure 97. Timing diagram for conversion with trigger disabled TEN = 0

Timing diagram for conversion with trigger disabled (TEN = 0). The diagram shows three signals: APB1_CLK (a periodic square wave), DHR (Digital-to-Analog Register, holding value 0x1AC), and DOR (Output Register, holding value 0x1AC). The DOR signal is shown as a step function that updates its value to 0x1AC after a settling time t_SETTLING. An arrow points from the DOR signal to the text 'Output voltage available on DAC_OUT pin'. The diagram is labeled ai14711b.

16.3.5 DAC output voltage

Digital inputs are converted to output voltages on a linear conversion between 0 and $V_{\text{REF+}}$ . The analog output voltages on each DAC channel pin are determined by the following equation:

\text{DACoutput} = V_{\text{REF}} \times \frac{\text{DOR}}{4096}

16.3.6 DAC trigger selection

If the TENx control bit is set, conversion can then be triggered by an external event (timer counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8 possible events will trigger conversion as shown in Table 103 .

Table 103. External triggers

Source	Type	TSEL[2:0]
Timer 6 TRGO event	Internal signal from on-chip timers	000
Timer 8 TRGO event		001
Timer 7 TRGO event		010
Timer 5 TRGO event		011
Timer 2 TRGO event		100
Timer 4 TRGO event		101
EXTI line9	External pin	110
SWTRIG	Software control bit	111

Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on the selected external interrupt line 9, the last data stored into the DAC_DHRx register are transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1 cycles after the trigger occurs.

If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents.

Note: TSELx[2:0] bit cannot be changed when the ENx bit is set.

When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only one APB1 clock cycle.

16.3.7 DMA request

Each DAC channel has a DMA capability. Two DMA channels are used to service DAC channel DMA requests.

A DAC DMA request is generated when an external trigger (but not a software trigger) occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred into the DAC_DORx register.

In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one DMA request is needed, you should set only the corresponding DMAENx bit. In this way, the application can manage both DAC channels in dual mode by using one DMA request and a unique DMA channel.

DMA underrun

The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgement for the first external trigger is received (first request), then no new request is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set, reporting the error condition. DMA data transfers are then disabled and no further DMA request is treated. The DAC channelx continues to convert old data.

The software should clear the DMAUDRx flag by writing “1”, clear the DMAEN bit of the used DMA stream and re-initialize both DMA and DAC channelx to restart the transfer correctly. The software should modify the DAC trigger conversion frequency or lighten the DMA workload to avoid a new DMA underrun. Finally, the DAC conversion could be resumed by enabling both DMA data transfer and conversion trigger.

For each DAC channelx, an interrupt is also generated if its corresponding DMAUDRIEx bit in the DAC_CR register is enabled.

16.3.8 Noise generation

In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift register) is available. DAC noise generation is selected by setting WAVEx[1:0] to “01”. The preloaded value in LFSR is 0xAAA. This register is updated three APB1 clock cycles after each trigger event, following a specific calculation algorithm.

Figure 98. DAC LFSR register calculation algorithm

Figure 98: DAC LFSR register calculation algorithm diagram. It shows a 12-bit shift register with cells numbered 11 down to 0. The output of cell 0 is labeled X^0. The output of cell 1 is labeled X. The output of cell 4 is labeled X^4. The output of cell 6 is labeled X^6. The output of cell 11 is labeled X^12. These outputs are connected to an XOR gate. The output of the XOR gate is connected to a NOR gate. The output of the NOR gate is connected back to the input of cell 11. A 12-bit bus is shown entering the NOR gate from below.

ai14713c

The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register.

If LFSR is 0x0000, a '1' is injected into it (antilock-up mechanism).

It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.

Figure 99. DAC conversion (SW trigger enabled) with LFSR wave generation

Figure 99: Timing diagram showing APB1_CLK, DHR, DOR, and SWTRIG signals. APB1_CLK is a periodic square wave. DHR is a constant value of 0x00. DOR starts at 0xAAA and changes to 0xD55. SWTRIG is a pulse that triggers the change in DOR. The change in DOR occurs after a SWTRIG pulse and is synchronized with the APB1_CLK signal.

ai14714b

Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DAC_CR register.

16.3.9 Triangle-wave generation

It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVEx[1:0] to "10". The amplitude is configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter is incremented three APB1 clock cycles after each trigger event. The value of this counter is then added to the DAC_DHRx register without overflow and the sum is stored into the DAC_DORx register. The triangle counter is incremented as long as it is less than the maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is reached, the counter is decremented down to 0, then incremented again and so on.

It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits.

Figure 100. DAC triangle wave generation

Figure 100: DAC triangle wave generation graph. The y-axis shows 'MAMPx[3:0] max amplitude + DAC_DHRx base value' at the peak and 'DAC_DHRx base value' at the trough. The x-axis represents time. The waveform is a triangle wave starting at the base value, rising linearly (labeled 'Incrementation'), reaching the peak, falling linearly (labeled 'Decrementation'), and returning to the base value. The graph is labeled 'ai14715c'.

Figure 101. DAC conversion (SW trigger enabled) with triangle wave generation

Figure 101: Timing diagram for DAC conversion with SW trigger enabled. It shows four signals: APB1_CLK (a high-frequency square wave), DHR (Digital Hold Register) which is set to 0x00, DOR (Data Output Register) which shows values 0xAA and 0xD5, and SWTRIG (Software Trigger) which is a pulse. Vertical dashed lines indicate the sequence of events: first, DHR is set to 0x00; then, a SWTRIG pulse occurs, causing the DOR value to change to 0xAA; later, another SWTRIG pulse occurs, causing the DOR value to change to 0xD5. The graph is labeled 'ai14714b'.

Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DAC_CR register.

The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot be changed.

16.4 Dual DAC channel conversion

To efficiently use the bus bandwidth in applications that require the two DAC channels at the same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A unique register access is then required to drive both DAC channels at the same time.

Eleven possible conversion modes are possible using the two DAC channels and these dual registers. All the conversion modes can nevertheless be obtained using separate DHRx registers if needed.

All modes are described in the paragraphs below.