2. System and memory overview

2.1 System architecture

The main system architecture is based on 2 sub-systems:

• • An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol:
  • – 1x AXI to 64-bit AHB bridge connected to the embedded flash
  • – 3x AXI to 32bit AHB bridge connected to AHB bus matrix
• • A multi-AHB Bus-Matrix

Figure 1. System architecture for STM32F75xxx and STM32F74xxx devices

The multi-AHB Bus-Matrix interconnects all the masters and slaves and it consists on:

• – 32-bit multi-AHB Bus-Matrix
• – 64-bit multi-AHB Bus-Matrix: It interconnects the 64-bit AHB bus from CPU through the AXI to AHB bridge and the 32-bit AHB bus from GP DMAs and peripheral DMAs up-sized to 64-bit to the internal flash.

The multi AHB bus matrix interconnects:

• • 12 bus masters:
  • – 3x32-bit AHB bus Cortex ^® -M7 AXI Master bus 64-bits, splitted 4 masters through the AXI to AHB bridge.
  • – 1x64-bit AHB bus connected to the embedded flash
  • – Cortex ^® -M7 AHB Peripherals bus
  • – DMA1 memory bus
  • – DMA2 memory bus
  • – DMA2 peripheral bus
  • – Ethernet DMA bus
  • – USB OTG HS DMA bus
  • – LCD Controller DMA-bus
  • – Chrom-Art Accelerator ^™ (DMA2D) memory bus
• • Eight bus slaves:
  • – the embedded Flash on AHB bus (for Flash read/write access, for code execution and data access)
  • – Cortex ^® -M7 AHBS slave interface for DMAs data transfer on DTCM RAM only.
  • – Main internal SRAM1 (240 KB)
  • – Auxiliary internal SRAM2 (16 KB)
  • – AHB1peripherals including AHB to APB bridges and APB peripherals
  • – AHB2 peripherals including AHB to APB bridges and APB peripherals
  • – FMC
  • – Quad SPI

2.1.1 Multi AHB BusMatrix

The multi AHB BusMatrix manages the access arbitration between masters. The arbitration uses a round-robin algorithm.

It provides access from a master to a slave, enabling concurrent access and efficient operation even when several high-speed peripherals work simultaneously.

The DTCM and ITCM RAMs (tightly coupled memories) are not part of the bus matrix.

The Data TCM RAM is accessible by the GP-DMAs and peripherals DMAs through specific AHB slave bus of the CPU.

The instruction TCM RAM is reserved only for CPU. it is accessed at CPU clock speed with 0 wait states. The architecture is shown in Figure 1 .

2.1.2 AHB/APB bridges (APB)

The two AHB/APB bridges, APB1 and APB2, provide full synchronous connections between the AHB and the two APB buses, allowing flexible selection of the peripheral frequency.

Refer to the device datasheets for more details on APB1 and APB2 maximum frequencies, and to Table 1 for the address mapping of AHB and APB peripherals.

After each device reset, all peripheral clocks are disabled (except for the SRAM, DTCM, ITCM RAM and Flash memory interface). Before using a peripheral its clock has to be enabled in the RCC_AHBxENR or RCC_APBxENR register.

Note: When a 16- or an 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

2.1.3 CPU AXIM bus

This bus connects the Instruction and data bus of the Cortex ^® -M7 with FPU core to the multi-AHB Bus-Matrix through AXI to AHB bridge. There are 4 AXI bus accesses:

• – CPU AXI bus access 1: The target of this AXI bus is the external memory FMC containing code or data. For the NAND Bank mapped at address 0x8000 0000 to 0x8FFF FFFF, the MPU memory attribute for this space must be reconfigured by software to Device.
• – CPU AXI bus access 2: The target of this AXI bus is the external memory Quad SPI containing code or data.
• – CPU AXI bus access 3: The target of this AXI bus is the internal SRAMs (SRAM1 and SRAM2) containing code or data.
• – CPU AXI bus access 4: The target of this AXI bus is the embedded Flash mapped on AXI interface containing code or data.

2.1.4 ITCM bus

This bus is used by the Cortex ^® -M7 for instruction fetches and data access on the embedded flash mapped on ITCM interface and instruction fetches only on ITCM RAM.

2.1.5 DTCM bus

This bus is used by the Cortex ^® -M7 for data access on the DTCM RAM. It can be also used for instruction fetches.

2.1.6 CPU AHBS bus

This bus connects the AHB Slave bus of the Cortex ^® -M7 to the BusMatrix. This bus is used by DMAs and Peripherals DMAs for Data transfer on DTCM RAM only.

The ITCM bus is not accessible on AHBS. So the DMA data transfer to/from ITCM RAM is not supported. For DMA transfer to/from Flash on ITCM interface, all the transfers are forced through AHB bus

2.1.7 AHB peripheral bus

This bus connects the AHB Peripheral bus of the Cortex ^® -M7 to the BusMatrix. This bus is used by the core to perform all data accesses to peripherals.

The target of this bus is the AHB1 peripherals including the APB peripherals and the AHB2 peripherals.

2.1.8 DMA memory bus

This bus connects the DMA memory bus master interface to the BusMatrix. It is used by the DMA to perform transfer to/from memories. The targets of this bus are data memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex ^® -M7) internal Flash memory and external memories through the FMC or Quad SPI.

2.1.9 DMA peripheral bus

This bus connects the DMA peripheral master bus interface to the BusMatrix. This bus is used by the DMA to access AHB peripherals or to perform memory-to-memory transfers. The targets of this bus are the AHB and APB peripherals plus data memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex ^® -M7) internal Flash memory and external memories through the FMC or Quad SPI.

2.1.10 Ethernet DMA bus

This bus connects the Ethernet DMA master interface to the BusMatrix. This bus is used by the Ethernet DMA to load/store data to a memory. The targets of this bus are data memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex ^® -M7) internal Flash memory, and external memories through the FMC or Quad SPI.

2.1.11 USB OTG HS DMA bus

This bus connects the USB OTG HS DMA master interface to the BusMatrix. This bus is used by the USB OTG DMA to load/store data to a memory. The targets of this bus are data memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex ^® -M7), internal Flash memory, and external memories through the FMC or Quad SPI.

2.1.12 LCD-TFT controller DMA bus

This bus connects the LCD controller DMA master interface to the BusMatrix. It is used by the LCD-TFT DMA to load data from a memory. The targets of this bus are data memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex ^® -M7), external memories through FMC or Quad SPI, and internal Flash memory.

2.1.13 DMA2D bus

This bus connects the DMA2D master interface to the BusMatrix. This bus is used by the DMA2D graphic Accelerator to load/store data to a memory. The targets of this bus are data memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex ^® -M7), external memories through FMC or Quad SPI, and internal Flash memory.

2.2 Memory organization

2.2.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant.

The addressable memory space is divided into eight main blocks, of 512 Mbytes each.

2.2.2 Memory map and register boundary addresses

Figure 2. Memory map

MS34165V2

All the memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to the following table.

The following table gives the boundary addresses of the peripherals available in the devices.

Table 1. STM32F75xxx and STM32F74xxx register boundary addresses

Table 1. STM32F75xxx and STM32F74xxx register boundary addresses (continued)

2.3 Embedded SRAM

The STM32F75xxx and STM32F74xxx feature:

• • System SRAM up to 320 Kbytes including Data TCM RAM 64 Kbytes
• • Instruction RAM (ITCM-RAM) 16 Kbytes.
• • 4 Kbytes of backup SRAM (see section 5.1.2: Battery backup domain)

The embedded SRAM is divided into up to four blocks:

• • System SRAM:
  • – SRAM1 mapped at address 0x2001 0000 and accessible by all AHB masters from AHB bus Matrix.
  • – SRAM2 mapped at address 0x2004 C000 and accessible by all AHB masters from AHB bus Matrix.
  • – DTCM-RAM on TCM interface (Tightly Coupled Memory interface) mapped at address 0x2000 0000 and accessible by all AHB masters from AHB bus Matrix but through a specific AHB slave bus of the CPU.
• • Instruction SRAM:
  • – Instruction RAM (ITCM-RAM) mapped at address 0x0000 0000 and accessible only by CPU.

The SRAM1 and SRAM2 can be accessed as bytes, half-words (16 bits) or full words (32 bits). While DTCM and ITCM RAMs can be accessed as bytes, half-words (16 bits), full words (32 bits) or double words (64 bits). These memories can be addressed at maximum system clock frequency without wait state.

The AHB masters support concurrent SRAM accesses (from the Ethernet or the USB OTG HS): for instance, the Ethernet MAC can read/write from/to SRAM2 while the CPU is reading/writing from/to SRAM1.

2.4 Flash memory overview

The Flash memory interface manages CPU AXI and TCM accesses to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. It accelerates code execution with ART on TCM interface or L1-Cache on AXIM interface.

The Flash memory is organized as follows:

• • A main memory block divided into sectors.
• • An information block:
  • – System memory from which the device boots in System memory boot mode
  • – 1024 OTP (one-time programmable) bytes for user data.
  • – Option bytes to configure read and write protection, BOR level, software/hardware watchdog, boot memory base address and reset when the device is in Standby or Stop mode.

Refer to Section 3: Embedded Flash memory (FLASH) for more details.

2.5 Boot configuration

In the STM32F75xxx and STM32F74xxx, two different boot areas can be selected through the BOOT pin and the boot base address programmed in the BOOT_ADD0 and BOOT_ADD1 option bytes as shown in the Table 2 .

Table 2. Boot modes

The values on the BOOT pin are latched on the 4th rising edge of SYSCLK after reset release. It is up to the user to set the BOOT pin after reset.

The BOOT pin is also resampled when the device exits the Standby mode. Consequently, they must be kept in the required Boot mode configuration when the device is in the Standby mode.

After startup delay, the selection of the boot area is done before releasing the processor reset.

The BOOT_ADD0 and BOOT_ADD1 address option bytes allows to program any boot memory address from 0x0000 0000 to 0x2004 FFFF which includes:

• • All Flash address space mapped on ITCM or AXIM interface
• • All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface
• • The System memory bootloader

The BOOT_ADD0 / BOOT_ADD1 option bytes can be modified after reset in order to boot from any other boot address after next reset.

If the programmed boot memory address is out of the memory mapped area or a reserved area, the default boot fetch address is programmed as follows:

• – Boot address 0: ITCM-FLASH at 0x0020 0000
• – Boot address 1: ITCM-RAM at 0x0000 0000

When flash level 2 protection is enabled, only boot from Flash (on ITCM or AXIM interface) or system bootloader will be available. If the already programmed boot address in the BOOT_ADD0 and/or BOOT_ADD1 option bytes is out of the memory range or RAM address (on ITCM or AXIM) the default fetch will be forced from Flash on ITCM interface at address 0x00200000.

Embedded bootloader

The embedded bootloader code is located in the system memory. It is programmed by ST during production. For full information, refer to the application note (AN2606) STM32 microcontroller system memory boot mode.

By default, when the boot from system bootloader is selected, the code is executed from TCM interface. It could be executed from AXIM interface by reprogramming the BOOT_ADDx address option bytes to 0x1FF0 0000.