RM0385-STM32F75-74

Introduction

This reference manual targets application developers. It provides complete information on how to use the STM32F75xxx and STM32F74xxx microcontroller memory and peripherals.

The STM32F75xxx and STM32F74xxx is a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics refer to the datasheets.

For information on the Arm ® Cortex ® -M7 with FPU core, refer to the Cortex ® -M7 with FPU technical reference manual.

STM32F75xxx and STM32F74xxx microcontrollers include ST state-of-the-art patented technology.

Available from STMicroelectronics web site www.st.com :

Contents

3.3.1Flash memory organization .....78
3.3.2Read access latency .....79
3.3.3Flash program and erase operations .....81
3.3.4Unlocking the Flash control register .....82
3.3.5Maximum program/erase parallelism .....82
3.3.6Flash erase sequences .....83
3.3.7Flash programming sequences .....83
3.3.8Flash Interrupts .....84
3.4FLASH Option bytes .....85
3.4.1Option bytes description .....85
3.4.2Option bytes programming .....88
3.5FLASH memory protection .....89
3.5.1Read protection (RDP) .....89
3.5.2Write protections .....90
3.6One-time programmable bytes .....91
3.7FLASH registers .....92
3.7.1Flash access control register (FLASH_ACR) .....92
3.7.2Flash key register (FLASH_KEYR) .....93
3.7.3Flash option key register (FLASH_OPTKEYR) .....93
3.7.4Flash status register (FLASH_SR) .....94
3.7.5Flash control register (FLASH_CR) .....95
3.7.6Flash option control register (FLASH_OPTCR) .....96
3.7.7Flash option control register (FLASH_OPTCR1) .....97
3.7.8Flash interface register map .....99
4Power controller (PWR) .....100
4.1Power supplies .....100
4.1.1Independent A/D converter supply and reference voltage .....101
4.1.2Independent USB transceivers supply .....102
4.1.3Battery backup domain .....103
4.1.4Voltage regulator .....105
4.2Power supply supervisor .....108
4.2.1Power-on reset (POR)/power-down reset (PDR) .....108
4.2.2Brownout reset (BOR) .....109
4.2.3Programmable voltage detector (PVD) .....109
4.3Low-power modes .....110

5 Reset and clock control (RCC) . . . . . 133

5.3.3RCC clock configuration register (RCC_CFGR) . . . . .150
5.3.4RCC clock interrupt register (RCC_CIR) . . . . .152
5.3.5RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .155
5.3.6RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .158
5.3.7RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . .159
5.3.8RCC APB1 peripheral reset register (RCC_APB1RSTR) . . . . .159
5.3.9RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .163
5.3.10RCC AHB1 peripheral clock register (RCC_AHB1ENR) . . . . .165
5.3.11RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . .167
5.3.12RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . .168
5.3.13RCC APB1 peripheral clock enable register (RCC_APB1ENR) . . . . .168
5.3.14RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .172
5.3.15RCC AHB1 peripheral clock enable in low-power mode register
(RCC_AHB1LPENR) . . . . .		175
5.3.16RCC AHB2 peripheral clock enable in low-power mode register
(RCC_AHB2LPENR) . . . . .		177
5.3.17RCC AHB3 peripheral clock enable in low-power mode register
(RCC_AHB3LPENR) . . . . .		178
5.3.18RCC APB1 peripheral clock enable in low-power mode register
(RCC_APB1LPENR) . . . . .		179
5.3.19RCC APB2 peripheral clock enabled in low-power mode register
(RCC_APB2LPENR) . . . . .		183
5.3.20RCC backup domain control register (RCC_BDCR) . . . . .185
5.3.21RCC clock control & status register (RCC_CSR) . . . . .186
5.3.22RCC spread spectrum clock generation register (RCC_SSCGR) . . . . .188
5.3.23RCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . .189
5.3.24RCC PLLSAI configuration register (RCC_PLLSAICFGR) . . . . .192
5.3.25RCC dedicated clocks configuration register (RCC_DCKCFGR1) . . . . .193
5.3.26RCC dedicated clocks configuration register (DCKCFGR2) . . . . .195
5.3.27RCC register map . . . . .198
6General-purpose I/Os (GPIO) . . . . .201
6.1Introduction . . . . .201
6.2GPIO main features . . . . .201
6.3GPIO functional description . . . . .201
6.3.1General-purpose I/O (GPIO) . . . . .204
6.3.2I/O pin alternate function multiplexer and mapping . . . . .204
6.3.3I/O port control registers . . . . .205
7.2.3SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) .....222
7.2.4SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) .....222
7.2.5SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) .....223
7.2.6SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) .....224
7.2.7Compensation cell control register (SYSCFG_CMPCR) .....224
7.2.8SYSCFG register maps .....225
8Direct memory access controller (DMA) .....226
8.1DMA introduction .....226
8.2DMA main features .....226
8.3DMA functional description .....228
8.3.1DMA block diagram .....228
8.3.2DMA overview .....228
8.3.3DMA transactions .....229
8.3.4Channel selection .....229
8.3.5Arbiter .....231
8.3.6DMA streams .....231
8.3.7Source, destination and transfer modes .....231
8.3.8Pointer incrementation .....235
8.3.9Circular mode .....236
8.3.10Double-buffer mode .....236
8.3.11Programmable data width, packing/unpacking, endianness .....237
8.3.12Single and burst transfers .....238
8.3.13FIFO .....239
8.3.14DMA transfer completion .....242
8.3.15DMA transfer suspension .....243
8.3.16Flow controller .....244
8.3.17Summary of the possible DMA configurations .....245
8.3.18Stream configuration procedure .....245
8.3.19Error management .....246
8.4DMA interrupts .....247
8.5DMA registers .....248
8.5.1DMA low interrupt status register (DMA_LISR) .....248
8.5.2DMA high interrupt status register (DMA_HISR) .....249
8.5.3DMA low interrupt flag clear register (DMA_LIFCR)250
8.5.4DMA high interrupt flag clear register (DMA_HIFCR)250
8.5.5DMA stream x configuration register (DMA_SxCR)251
8.5.6DMA stream x number of data register (DMA_SxNDTR)254
8.5.7DMA stream x peripheral address register (DMA_SxPAR)255
8.5.8DMA stream x memory 0 address register
(DMA_SxM0AR)		255
8.5.9DMA stream x memory 1 address register
(DMA_SxM1AR)		255
8.5.10DMA stream x FIFO control register (DMA_SxFCR)256
8.5.11DMA register map257
9Chrom-ART Accelerator controller (DMA2D)261
9.1DMA2D introduction261
9.2DMA2D main features261
9.3DMA2D functional description262
9.3.1DMA2D block diagram262
9.3.2DMA2D control263
9.3.3DMA2D foreground and background FIFOs263
9.3.4DMA2D foreground and background pixel format converter (PFC)263
9.3.5DMA2D foreground and background CLUT interface265
9.3.6DMA2D blender266
9.3.7DMA2D output PFC267
9.3.8DMA2D output FIFO267
9.3.9DMA2D AHB master port timer267
9.3.10DMA2D transactions268
9.3.11DMA2D configuration268
9.3.12DMA2D transfer control (start, suspend, abort and completion)271
9.3.13Watermark271
9.3.14Error management271
9.3.15AHB dead time271
9.4DMA2D interrupts272
9.5DMA2D registers272
9.5.1DMA2D control register (DMA2D_CR)272
9.5.2DMA2D interrupt status register (DMA2D_ISR)274
9.5.3DMA2D interrupt flag clear register (DMA2D_IFCR)274
9.5.4DMA2D foreground memory address register (DMA2D_FGMAR)275
9.5.5DMA2D foreground offset register (DMA2D_FGOR) . . . . .275
9.5.6DMA2D background memory address register (DMA2D_BGMAR) . . .276
9.5.7DMA2D background offset register (DMA2D_BGOR) . . . . .276
9.5.8DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . .277
9.5.9DMA2D foreground color register (DMA2D_FGCOLR) . . . . .278
9.5.10DMA2D background PFC control register (DMA2D_BGPFCCR) . . . . .279
9.5.11DMA2D background color register (DMA2D_BGCOLR) . . . . .280
9.5.12DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR) . . . . .		281
9.5.13DMA2D background CLUT memory address register
(DMA2D_BGCMAR) . . . . .		281
9.5.14DMA2D output PFC control register (DMA2D_OPFCCR) . . . . .282
9.5.15DMA2D output color register (DMA2D_OCOLR) . . . . .282
9.5.16DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .283
9.5.17DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .283
9.5.18DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .284
9.5.19DMA2D output memory address register (DMA2D_OMAR) . . . . .284
9.5.20DMA2D output offset register (DMA2D_OOR) . . . . .285
9.5.21DMA2D number of line register (DMA2D_NLR) . . . . .285
9.5.22DMA2D line watermark register (DMA2D_LWR) . . . . .286
9.5.23DMA2D AHB master timer configuration register (DMA2D_AMTCR) . . .286
9.5.24DMA2D foreground CLUT (DMA2D_FGCLUTx) . . . . .287
9.5.25DMA2D background CLUT (DMA2D_BGCLUTx) . . . . .287
9.5.26DMA2D register map . . . . .288
10Nested vectored interrupt controller (NVIC) . . . . .290
10.1NVIC features . . . . .290
10.1.1SysTick calibration value register . . . . .290
10.1.2Interrupt and exception vectors . . . . .290
11Extended interrupts and events controller (EXTI) . . . . .295
11.1EXTI main features . . . . .295
11.2EXTI block diagram . . . . .295
11.3Wakeup event management . . . . .296
11.4Functional description . . . . .296
11.5Hardware interrupt selection . . . . .296
11.6Hardware event selection . . . . .296
11.7Software interrupt/event selection . . . . .297
11.8External interrupt/event line mapping . . . . .297
11.9EXTI registers . . . . .298
11.9.1Interrupt mask register (EXTI_IMR) . . . . .298
11.9.2Event mask register (EXTI_EMR) . . . . .298
11.9.3Rising trigger selection register (EXTI_RTSR) . . . . .299
11.9.4Falling trigger selection register (EXTI_FTSR) . . . . .299
11.9.5Software interrupt event register (EXTI_SWIER) . . . . .300
11.9.6Pending register (EXTI_PR) . . . . .300
11.9.7EXTI register map . . . . .301
12Cyclic redundancy check calculation unit (CRC) . . . . .302
12.1Introduction . . . . .302
12.2CRC main features . . . . .302
12.3CRC functional description . . . . .303
12.3.1CRC block diagram . . . . .303
12.3.2CRC internal signals . . . . .303
12.3.3CRC operation . . . . .303
12.4CRC registers . . . . .305
12.4.1CRC data register (CRC_DR) . . . . .305
12.4.2CRC independent data register (CRC_IDR) . . . . .305
12.4.3CRC control register (CRC_CR) . . . . .306
12.4.4CRC initial value (CRC_INIT) . . . . .307
12.4.5CRC polynomial (CRC_POL) . . . . .307
12.4.6CRC register map . . . . .308
13Flexible memory controller (FMC) . . . . .309
13.1Introduction . . . . .309
13.2FMC main features . . . . .309
13.3FMC block diagram . . . . .310
13.4AHB interface . . . . .311
13.4.1Supported memories and transactions . . . . .311
13.5External device address mapping . . . . .312
13.5.1NOR/PSRAM address mapping . . . . .313
13.5.2NAND flash memory address mapping . . . . .314
13.5.3SDRAM address mapping . . . . .315
13.6NOR flash/PSRAM controller . . . . .318
13.6.1External memory interface signals . . . . .319
13.6.2Supported memories and transactions . . . . .321
13.6.3General timing rules . . . . .323
13.6.4NOR flash/PSRAM controller asynchronous transactions . . . . .323
13.6.5Synchronous transactions . . . . .340
13.6.6NOR/PSRAM controller registers . . . . .347
13.7NAND flash controller . . . . .354
13.7.1External memory interface signals . . . . .354
13.7.2NAND flash supported memories and transactions . . . . .355
13.7.3Timing diagrams for NAND flash memory . . . . .356
13.7.4NAND flash operations . . . . .357
13.7.5NAND flash prewait functionality . . . . .357
13.7.6Computation of the error correction code (ECC)
in NAND flash memory . . . . .		358
13.7.7NAND flash controller registers . . . . .359
13.8SDRAM controller . . . . .365
13.8.1SDRAM controller main features . . . . .365
13.8.2SDRAM External memory interface signals . . . . .365
13.8.3SDRAM controller functional description . . . . .366
13.8.4Low-power modes . . . . .372
13.8.5SDRAM controller registers . . . . .376
13.8.6FMC register map . . . . .382
14Quad-SPI interface (QUADSPI) . . . . .385
14.1Introduction . . . . .385
14.2QUADSPI main features . . . . .385
14.3QUADSPI functional description . . . . .385
14.3.1QUADSPI block diagram . . . . .385
14.3.2QUADSPI pins . . . . .386
14.3.3QUADSPI command sequence . . . . .386
14.3.4QUADSPI signal interface protocol modes . . . . .389
14.3.5QUADSPI indirect mode . . . . .391
14.3.6QUADSPI automatic status-polling mode . . . . .393
14.3.7QUADSPI memory-mapped mode . . . . .393
14.3.8QUADSPI flash memory configuration . . . . .394
14.3.9QUADSPI delayed data sampling . . . . .394
15.3.11Discontinuous mode . . . . .423
15.4Data alignment . . . . .424
15.5Channel-wise programmable sampling time . . . . .425
15.6Conversion on external trigger and trigger polarity . . . . .426
15.7Fast conversion mode . . . . .427
15.8Data management . . . . .428
15.8.1Using the DMA . . . . .428
15.8.2Managing a sequence of conversions without using the DMA . . . . .428
15.8.3Conversions without DMA and without overrun detection . . . . .429
15.9Multi ADC mode . . . . .429
15.9.1Injected simultaneous mode . . . . .432
15.9.2Regular simultaneous mode . . . . .433
15.9.3Interleaved mode . . . . .434
15.9.4Alternate trigger mode . . . . .436
15.9.5Combined regular/injected simultaneous mode . . . . .438
15.9.6Combined regular simultaneous + alternate trigger mode . . . . .438
15.10Temperature sensor . . . . .439
15.11Battery charge monitoring . . . . .441
15.12ADC interrupts . . . . .442
15.13ADC registers . . . . .443
15.13.1ADC status register (ADC_SR) . . . . .443
15.13.2ADC control register 1 (ADC_CR1) . . . . .444
15.13.3ADC control register 2 (ADC_CR2) . . . . .446
15.13.4ADC sample time register 1 (ADC_SMPR1) . . . . .447
15.13.5ADC sample time register 2 (ADC_SMPR2) . . . . .448
15.13.6ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) . . . . .448
15.13.7ADC watchdog higher threshold register (ADC_HTR) . . . . .449
15.13.8ADC watchdog lower threshold register (ADC_LTR) . . . . .449
15.13.9ADC regular sequence register 1 (ADC_SQR1) . . . . .450
15.13.10ADC regular sequence register 2 (ADC_SQR2) . . . . .450
15.13.11ADC regular sequence register 3 (ADC_SQR3) . . . . .451
15.13.12ADC injected sequence register (ADC_JSQR) . . . . .452
15.13.13ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . .452
15.13.14ADC regular data register (ADC_DR) . . . . .453
15.13.15ADC Common status register (ADC_CSR) . . . . .453
15.13.16ADC common control register (ADC_CCR) . . . . .454
16.5.6DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) .....477
16.5.7DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) .....477
16.5.8DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) .....477
16.5.9Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) .....478
16.5.10DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) .....478
16.5.11DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) .....479
16.5.12DAC channel1 data output register (DAC_DOR1) .....479
16.5.13DAC channel2 data output register (DAC_DOR2) .....479
16.5.14DAC status register (DAC_SR) .....480
16.5.15DAC register map .....481
17Digital camera interface (DCMI) .....482
17.1Introduction .....482
17.2DCMI main features .....482
17.3DCMI functional description .....482
17.3.1DCMI block diagram .....483
17.3.2DCMI pins .....483
17.3.3DCMI clocks .....483
17.3.4DCMI DMA interface .....484
17.3.5DCMI physical interface .....484
17.3.6DCMI synchronization .....486
17.3.7DCMI capture modes .....488
17.3.8DCMI crop feature .....489
17.3.9DCMI JPEG format .....490
17.3.10DCMI FIFO .....490
17.3.11DCMI data format description .....491
17.4DCMI interrupts .....493
17.5DCMI registers .....493
17.5.1DCMI control register (DCMI_CR) .....493
17.5.2DCMI status register (DCMI_SR) .....496
17.5.3DCMI raw interrupt status register (DCMI_RIS) .....496
17.5.4DCMI interrupt enable register (DCMI_IER) .....497
17.5.5DCMI masked interrupt status register (DCMI_MIS) . . . . .498
17.5.6DCMI interrupt clear register (DCMI_ICR) . . . . .499
17.5.7DCMI embedded synchronization code register (DCMI_ESCR) . . . . .500
17.5.8DCMI embedded synchronization unmask register (DCMI_ESUR) . . . . .500
17.5.9DCMI crop window start (DCMI_CWSTRT) . . . . .501
17.5.10DCMI crop window size (DCMI_CWSIZE) . . . . .502
17.5.11DCMI data register (DCMI_DR) . . . . .502
17.5.12DCMI register map . . . . .503
18LCD-TFT display controller (LTDC) . . . . .504
18.1Introduction . . . . .504
18.2LTDC main features . . . . .504
18.3LTDC functional description . . . . .505
18.3.1LTDC block diagram . . . . .505
18.3.2LTDC pins and external signal interface . . . . .505
18.3.3LTDC reset and clocks . . . . .506
18.4LTDC programmable parameters . . . . .507
18.4.1LTDC global configuration parameters . . . . .507
18.4.2Layer programmable parameters . . . . .510
18.5LTDC interrupts . . . . .515
18.6LTDC programming procedure . . . . .515
18.7LTDC registers . . . . .516
18.7.1LTDC synchronization size configuration register (LTDC_SSCR) . . . . .516
18.7.2LTDC back porch configuration register (LTDC_BPCR) . . . . .518
18.7.3LTDC active width configuration register (LTDC_AWCR) . . . . .519
18.7.4LTDC total width configuration register (LTDC_TWCR) . . . . .519
18.7.5LTDC global control register (LTDC_GCR) . . . . .520
18.7.6LTDC shadow reload configuration register (LTDC_SRCR) . . . . .521
18.7.7LTDC background color configuration register (LTDC_BCCR) . . . . .522
18.7.8LTDC interrupt enable register (LTDC_IER) . . . . .522
18.7.9LTDC interrupt status register (LTDC_ISR) . . . . .523
18.7.10LTDC Interrupt clear register (LTDC_ICR) . . . . .524
18.7.11LTDC line interrupt position configuration register (LTDC_LIPCR) . . . . .524
18.7.12LTDC current position status register (LTDC_CPSR) . . . . .525
18.7.13LTDC current display status register (LTDC_CDSR) . . . . .525
18.7.14LTDC layer x control register (LTDC_LxCR) . . . . .526
18.7.15LTDC layer x window horizontal position configuration register (LTDC_LxWHPER) . . . . .527
18.7.16LTDC layer x window vertical position configuration register (LTDC_LxWVPER) . . . . .528
18.7.17LTDC layer x color keying configuration register (LTDC_LxCKPER) . . . . .529
18.7.18LTDC layer x pixel format configuration register (LTDC_LxPFPER) . . . . .529
18.7.19LTDC layer x constant alpha configuration register (LTDC_LxCAPER) . . . . .530
18.7.20LTDC layer x default color configuration register (LTDC_LxDCCPER) . . . . .530
18.7.21LTDC layer x blending factors configuration register (LTDC_LxBFCR) . . . . .531
18.7.22LTDC layer x color frame buffer address register (LTDC_LxCFBAR) . . . . .532
18.7.23LTDC layer x color frame buffer length register (LTDC_LxCFBLR) . . . . .532
18.7.24LTDC layer x color frame buffer line number register (LTDC_LxCFBLNR) . . . . .533
18.7.25LTDC layer x CLUT write register (LTDC_LxCLUTWR) . . . . .533
18.7.26LTDC register map . . . . .534
19True random number generator (RNG) . . . . .537
19.1Introduction . . . . .537
19.2RNG main features . . . . .537
19.3RNG functional description . . . . .538
19.3.1RNG block diagram . . . . .538
19.3.2RNG internal signals . . . . .538
19.3.3Random number generation . . . . .539
19.3.4RNG initialization . . . . .541
19.3.5RNG operation . . . . .541
19.3.6RNG clocking . . . . .542
19.3.7Error management . . . . .542
19.3.8RNG low-power use . . . . .543
19.4RNG interrupts . . . . .543
19.5RNG processing time . . . . .543
19.6RNG entropy source validation . . . . .543
19.6.1Introduction . . . . .543
20.7.1CRYP control register (CRYP_CR) . . . . .599
20.7.2CRYP status register (CRYP_SR) . . . . .601
20.7.3CRYP data input register (CRYP_DIN) . . . . .602
20.7.4CRYP data output register (CRYP_DOUT) . . . . .602
20.7.5CRYP DMA control register (CRYP_DMACR) . . . . .603
20.7.6CRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . .604
20.7.7CRYP raw interrupt status register (CRYP_RISR) . . . . .604
20.7.8CRYP masked interrupt status register (CRYP_MISR) . . . . .605
20.7.9CRYP key register 0L (CRYP_K0LR) . . . . .606
20.7.10CRYP key register 0R (CRYP_K0RR) . . . . .606
20.7.11CRYP key register 1L (CRYP_K1LR) . . . . .607
20.7.12CRYP key register 1R (CRYP_K1RR) . . . . .607
20.7.13CRYP key register 2L (CRYP_K2LR) . . . . .608
20.7.14CRYP key register 2R (CRYP_K2RR) . . . . .608
20.7.15CRYP key register 3L (CRYP_K3LR) . . . . .609
20.7.16CRYP key register 3R (CRYP_K3RR) . . . . .609
20.7.17CRYP initialization vector register 0L (CRYP_IV0LR) . . . . .610
20.7.18CRYP initialization vector register 0R (CRYP_IV0RR) . . . . .610
20.7.19CRYP initialization vector register 1L (CRYP_IV1LR) . . . . .611
20.7.20CRYP initialization vector register 1R (CRYP_IV1RR) . . . . .611
20.7.21CRYP register map . . . . .611
21Hash processor (HASH) . . . . .613
21.1Introduction . . . . .613
21.2HASH main features . . . . .613
21.3HASH implementation . . . . .614
21.4HASH functional description . . . . .614
21.4.1HASH block diagram . . . . .614
21.4.2HASH internal signals . . . . .615
21.4.3About secure hash algorithms . . . . .615
21.4.4Message data feeding . . . . .615
21.4.5Message digest computing . . . . .617
21.4.6Message padding . . . . .618
21.4.7HMAC operation . . . . .620
21.4.8HASH suspend/resume operations . . . . .622
21.4.9HASH DMA interface . . . . .624
21.4.10HASH error management . . . . .624
21.4.11HASH processing time . . . . .624
21.5HASH interrupts . . . . .625
21.6HASH registers . . . . .626
21.6.1HASH control register (HASH_CR) . . . . .626
21.6.2HASH data input register (HASH_DIN) . . . . .628
21.6.3HASH start register (HASH_STR) . . . . .629
21.6.4HASH digest registers . . . . .630
21.6.5HASH interrupt enable register (HASH_IMR) . . . . .631
21.6.6HASH status register (HASH_SR) . . . . .632
21.6.7HASH context swap registers . . . . .632
21.6.8HASH register map . . . . .633
22Advanced-control timers (TIM1/TIM8) . . . . .635
22.1TIM1/TIM8 introduction . . . . .635
22.2TIM1/TIM8 main features . . . . .635
22.3TIM1/TIM8 functional description . . . . .637
22.3.1Time-base unit . . . . .637
22.3.2Counter modes . . . . .639
22.3.3Repetition counter . . . . .650
22.3.4External trigger input . . . . .652
22.3.5Clock selection . . . . .653
22.3.6Capture/compare channels . . . . .657
22.3.7Input capture mode . . . . .659
22.3.8PWM input mode . . . . .660
22.3.9Forced output mode . . . . .661
22.3.10Output compare mode . . . . .662
22.3.11PWM mode . . . . .663
22.3.12Asymmetric PWM mode . . . . .666
22.3.13Combined PWM mode . . . . .667
22.3.14Combined 3-phase PWM mode . . . . .668
22.3.15Complementary outputs and dead-time insertion . . . . .669
22.3.16Using the break function . . . . .671
22.3.17Clearing the OCxREF signal on an external event . . . . .677
22.3.186-step PWM generation . . . . .679
22.3.19One-pulse mode . . . . .680
22.3.20Retriggerable one pulse mode . . . . .681
22.3.21Encoder interface mode . . . . .682
22.3.22UIF bit remapping . . . . .684
22.3.23Timer input XOR function . . . . .685
22.3.24Interfacing with Hall sensors . . . . .685
22.3.25Timer synchronization . . . . .688
22.3.26ADC synchronization . . . . .692
22.3.27DMA burst mode . . . . .692
22.3.28Debug mode . . . . .693
22.4TIM1/TIM8 registers . . . . .694
22.4.1TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . .694
22.4.2TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . .695
22.4.3TIMx slave mode control register
(TIMx_SMCR)(x = 1, 8) . . . . .		698
22.4.4TIMx DMA/interrupt enable register
(TIMx_DIER)(x = 1, 8) . . . . .		700
22.4.5TIMx status register (TIMx_SR)(x = 1, 8) . . . . .702
22.4.6TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . .704
22.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 1, 8) . . . . .705
22.4.8TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . .		706
22.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 1, 8) . . . . .709
22.4.10TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . .		710
22.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 1, 8) . . . . .		711
22.4.12TIMx counter (TIMx_CNT)(x = 1, 8) . . . . .715
22.4.13TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . .715
22.4.14TIMx auto-reload register (TIMx_ARR)(x = 1, 8) . . . . .715
22.4.15TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . .716
22.4.16TIMx capture/compare register 1
(TIMx_CCR1)(x = 1, 8) . . . . .		716
22.4.17TIMx capture/compare register 2
(TIMx_CCR2)(x = 1, 8) . . . . .		717
22.4.18TIMx capture/compare register 3
(TIMx_CCR3)(x = 1, 8) . . . . .		717
22.4.19TIMx capture/compare register 4
(TIMx_CCR4)(x = 1, 8) . . . . .		718
22.4.20TIMx break and dead-time register
(TIMx_BDTR)(x = 1, 8) . . . . .		718
22.4.21TIMx DMA control register
(TIMx_DCR)(x = 1, 8) . . . . .		721
22.4.22TIMx DMA address for full transfer
(TIMx_DMAR)(x = 1, 8) .....		722
22.4.23TIMx capture/compare mode register 3
(TIMx_CCMR3)(x = 1, 8) .....		723
22.4.24TIMx capture/compare register 5
(TIMx_CCR5)(x = 1, 8) .....		724
22.4.25TIMx capture/compare register 6
(TIMx_CCR6)(x = 1, 8) .....		725
22.4.26TIM1 register map .....726
22.4.27TIM8 register map .....728
23General-purpose timers (TIM2/TIM3/TIM4/TIM5) .....731
23.1TIM2/TIM3/TIM4/TIM5 introduction .....731
23.2TIM2/TIM3/TIM4/TIM5 main features .....731
23.3TIM2/TIM3/TIM4/TIM5 functional description .....733
23.3.1Time-base unit .....733
23.3.2Counter modes .....735
23.3.3Clock selection .....745
23.3.4Capture/Compare channels .....749
23.3.5Input capture mode .....751
23.3.6PWM input mode .....752
23.3.7Forced output mode .....753
23.3.8Output compare mode .....754
23.3.9PWM mode .....755
23.3.10Asymmetric PWM mode .....758
23.3.11Combined PWM mode .....759
23.3.12Clearing the OCxREF signal on an external event .....760
23.3.13One-pulse mode .....762
23.3.14Retriggerable one pulse mode .....763
23.3.15Encoder interface mode .....764
23.3.16UIF bit remapping .....766
23.3.17Timer input XOR function .....766
23.3.18Timers and external trigger synchronization .....767
23.3.19Timer synchronization .....770
23.3.20DMA burst mode .....775
23.3.21Debug mode .....776
23.4TIM2/TIM3/TIM4/TIM5 registers .....777
23.4.1TIMx control register 1 (TIMx_CR1)(x = 2 to 5) .....777
23.4.2TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . .778
23.4.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . .780
23.4.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . .783
23.4.5TIMx status register (TIMx_SR)(x = 2 to 5) . . . . .784
23.4.6TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . .785
23.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) . . .786
23.4.8TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 5) . . . . .		788
23.4.9TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5) . . .790
23.4.10TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 5) . . . . .		791
23.4.11TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 5) . . . . .		792
23.4.12TIMx counter (TIMx_CNT)(x = 2 to 5) . . . . .793
23.4.13TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) . . . . .794
23.4.14TIMx prescaler (TIMx_PSC)(x = 2 to 5) . . . . .794
23.4.15TIMx auto-reload register (TIMx_ARR)(x = 2 to 5) . . . . .795
23.4.16TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) . . . . .795
23.4.17TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) . . . . .795
23.4.18TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5) . . . . .796
23.4.19TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5) . . . . .796
23.4.20TIMx DMA control register (TIMx_DCR)(x = 2 to 5) . . . . .797
23.4.21TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) . . . . .798
23.4.22TIM2 option register (TIM2_OR) . . . . .798
23.4.23TIM5 option register (TIM5_OR) . . . . .798
23.4.24TIMx register map . . . . .800
24General-purpose timers (TIM9/TIM10/TIM11/TIM12/TIM13/TIM14) . . .803
24.1TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 introduction . . . . .803
24.2TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 main features . . . . .803
24.2.1TIM9/TIM12 main features . . . . .803
24.2.2TIM10/TIM11/TIM13/TIM14 main features . . . . .804
24.3TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 functional description . . . . .806
24.3.1Time-base unit . . . . .806
24.3.2Counter modes . . . . .808
24.3.3Clock selection . . . . .811
24.3.4Capture/compare channels . . . . .813
24.3.5Input capture mode . . . . .815
24.3.6PWM input mode (only for TIM9/TIM12) . . . . .816
24.3.7Forced output mode . . . . .817
24.3.8Output compare mode . . . . .817
24.3.9PWM mode . . . . .818
24.3.10Combined PWM mode (TIM9/TIM12 only) . . . . .819
24.3.11One-pulse mode . . . . .821
24.3.12Retriggerable one pulse mode (TIM12 only) . . . . .822
24.3.13UIF bit remapping . . . . .823
24.3.14TIM9/TIM12 external trigger synchronization . . . . .823
24.3.15Slave mode – combined reset + trigger mode . . . . .826
24.3.16Timer synchronization (TIM9/TIM12) . . . . .827
24.3.17Using timer output as trigger for other timers (TIM10/TIM11/TIM13/TIM14)
827		827
24.3.18Debug mode . . . . .827
24.4TIM9/TIM12 registers . . . . .827
24.4.1TIMx control register 1 (TIMx_CR1)(x = 9, 12) . . . . .827
24.4.2TIMx slave mode control register (TIMx_SMCR)(x = 9, 12) . . . . .828
24.4.3TIMx Interrupt enable register (TIMx_DIER)(x = 9, 12) . . . . .830
24.4.4TIMx status register (TIMx_SR)(x = 9, 12) . . . . .830
24.4.5TIMx event generation register (TIMx_EGR)(x = 9, 12) . . . . .832
24.4.6TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 9, 12) . . . . .833
24.4.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 9, 12) . . . . .		834
24.4.8TIMx capture/compare enable register (TIMx_CCER)(x = 9, 12) . . . . .836
24.4.9TIMx counter (TIMx_CNT)(x = 9, 12) . . . . .837
24.4.10TIMx prescaler (TIMx_PSC)(x = 9, 12) . . . . .838
24.4.11TIMx auto-reload register (TIMx_ARR)(x = 9, 12) . . . . .838
24.4.12TIMx capture/compare register 1 (TIMx_CCR1)(x = 9, 12) . . . . .838
24.4.13TIMx capture/compare register 2 (TIMx_CCR2)(x = 9, 12) . . . . .839
24.4.14TIM9/TIM12 register map . . . . .840
24.5TIM10/TIM11/TIM13/TIM14 registers . . . . .842
24.5.1TIMx control register 1 (TIMx_CR1)(x = 10, 11, 13, 14) . . . . .842
24.5.2TIMx Interrupt enable register (TIMx_DIER)(x = 10, 11, 13, 14) . . . . .843
24.5.3TIMx status register (TIMx_SR)(x = 10, 11, 13, 14) . . . . .843
24.5.4TIMx event generation register (TIMx_EGR)(x = 10, 11, 13, 14) . . . . .844
24.5.5TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 10, 11, 13, 14) . . . . .		845
24.5.6TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 10, 11, 13, 14) .....		846
24.5.7TIMx capture/compare enable register
(TIMx_CCER)(x = 10, 11, 13, 14) .....		848
24.5.8TIMx counter (TIMx_CNT)(x = 10, 11, 13, 14) .....849
24.5.9TIMx prescaler (TIMx_PSC)(x = 10, 11, 13, 14) .....850
24.5.10TIMx auto-reload register (TIMx_ARR)(x = 10, 11, 13, 14) .....850
24.5.11TIMx capture/compare register 1 (TIMx_CCR1)(x = 10, 11, 13, 14) ..850
24.5.12TIM11 option register 1 (TIM11_OR) .....851
24.5.13TIM10/TIM11/TIM13/TIM14 register map .....851
25Basic timers (TIM6/TIM7) .....853
25.1TIM6/TIM7 introduction .....853
25.2TIM6/TIM7 main features .....853
25.3TIM6/TIM7 functional description .....854
25.3.1Time-base unit .....854
25.3.2Counting mode .....856
25.3.3UIF bit remapping .....859
25.3.4Clock source .....859
25.3.5Debug mode .....860
25.4TIM6/TIM7 registers .....860
25.4.1TIMx control register 1 (TIMx_CR1)(x = 6 to 7) .....860
25.4.2TIMx control register 2 (TIMx_CR2)(x = 6 to 7) .....862
25.4.3TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) .....862
25.4.4TIMx status register (TIMx_SR)(x = 6 to 7) .....863
25.4.5TIMx event generation register (TIMx_EGR)(x = 6 to 7) .....863
25.4.6TIMx counter (TIMx_CNT)(x = 6 to 7) .....863
25.4.7TIMx prescaler (TIMx_PSC)(x = 6 to 7) .....864
25.4.8TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) .....864
25.4.9TIMx register map .....865
26Low-power timer (LPTIM) .....866
26.1Introduction .....866
26.2LPTIM main features .....866
26.3LPTIM implementation .....867
26.4LPTIM functional description .....867
26.4.1LPTIM block diagram .....867

27 Independent watchdog (IWDG) . . . . . 887

27.4IWDG registers . . . . .890
27.4.1IWDG key register (IWDG_KR) . . . . .890
27.4.2IWDG prescaler register (IWDG_PR) . . . . .891
27.4.3IWDG reload register (IWDG_RLR) . . . . .892
27.4.4IWDG status register (IWDG_SR) . . . . .893
27.4.5IWDG window register (IWDG_WINR) . . . . .894
27.4.6IWDG register map . . . . .895
28System window watchdog (WWDG) . . . . .896
28.1Introduction . . . . .896
28.2WWDG main features . . . . .896
28.3WWDG functional description . . . . .896
28.3.1WWDG block diagram . . . . .897
28.3.2Enabling the watchdog . . . . .897
28.3.3Controlling the down-counter . . . . .897
28.3.4How to program the watchdog timeout . . . . .897
28.3.5Debug mode . . . . .899
28.4WWDG interrupts . . . . .899
28.5WWDG registers . . . . .899
28.5.1WWDG control register (WWDG_CR) . . . . .899
28.5.2WWDG configuration register (WWDG_CFR) . . . . .900
28.5.3WWDG status register (WWDG_SR) . . . . .900
28.5.4WWDG register map . . . . .901
29Real-time clock (RTC) . . . . .902
29.1Introduction . . . . .902
29.2RTC main features . . . . .903
29.3RTC functional description . . . . .904
29.3.1RTC block diagram . . . . .904
29.3.2GPIOs controlled by the RTC . . . . .905
29.3.3Clock and prescalers . . . . .907
29.3.4Real-time clock and calendar . . . . .908
29.3.5Programmable alarms . . . . .908
29.3.6Periodic auto-wake-up . . . . .909
29.3.7RTC initialization and configuration . . . . .910
29.3.8Reading the calendar . . . . .911
29.3.9Resetting the RTC .....912
29.3.10RTC synchronization .....913
29.3.11RTC reference clock detection .....913
29.3.12RTC smooth digital calibration .....914
29.3.13Time-stamp function .....916
29.3.14Tamper detection .....917
29.3.15Calibration clock output .....919
29.3.16Alarm output .....919
29.4RTC low-power modes .....919
29.5RTC interrupts .....920
29.6RTC registers .....921
29.6.1RTC time register (RTC_TR) .....921
29.6.2RTC date register (RTC_DR) .....922
29.6.3RTC control register (RTC_CR) .....923
29.6.4RTC initialization and status register (RTC_ISR) .....926
29.6.5RTC prescaler register (RTC_PRER) .....929
29.6.6RTC wake-up timer register (RTC_WUTR) .....930
29.6.7RTC alarm A register (RTC_ALRMAR) .....931
29.6.8RTC alarm B register (RTC_ALRMBR) .....932
29.6.9RTC write protection register (RTC_WPR) .....933
29.6.10RTC sub second register (RTC_SSR) .....933
29.6.11RTC shift control register (RTC_SHIFT) .....934
29.6.12RTC timestamp time register (RTC_TSTR) .....935
29.6.13RTC timestamp date register (RTC_TSDR) .....936
29.6.14RTC time-stamp sub second register (RTC_TSSSR) .....937
29.6.15RTC calibration register (RTC_CALR) .....938
29.6.16RTC tamper configuration register (RTC_TAMPCR) .....939
29.6.17RTC alarm A sub second register (RTC_ALRMASSR) .....942
29.6.18RTC alarm B sub second register (RTC_ALRMBSSR) .....943
29.6.19RTC option register (RTC_OR) .....944
29.6.20RTC backup registers (RTC_BKPxR) .....944
29.6.21RTC register map .....945
30Inter-integrated circuit interface (I2C) .....947
30.1Introduction .....947
30.2I2C main features .....947
30.3I2C implementation . . . . .948
30.4I2C functional description . . . . .948
30.4.1I2C block diagram . . . . .949
30.4.2I2C pins and internal signals . . . . .949
30.4.3I2C clock requirements . . . . .950
30.4.4I2C mode selection . . . . .950
30.4.5I2C initialization . . . . .951
30.4.6I2C reset . . . . .955
30.4.7I2C data transfer . . . . .955
30.4.8I2C target mode . . . . .957
30.4.9I2C controller mode . . . . .966
30.4.10I2C_TIMINGR register configuration examples . . . . .977
30.4.11SMBus specific features . . . . .979
30.4.12SMBus initialization . . . . .982
30.4.13SMBus I2C_TIMEOUTR register configuration examples . . . . .984
30.4.14SMBus target mode . . . . .984
30.4.15SMBus controller mode . . . . .988
30.4.16Error conditions . . . . .991
30.5I2C in low-power modes . . . . .993
30.6I2C interrupts . . . . .993
30.7I2C DMA requests . . . . .994
30.7.1Transmission using DMA . . . . .994
30.7.2Reception using DMA . . . . .994
30.8I2C debug modes . . . . .995
30.9I2C registers . . . . .995
30.9.1I2C control register 1 (I2C_CR1) . . . . .995
30.9.2I2C control register 2 (I2C_CR2) . . . . .998
30.9.3I2C own address 1 register (I2C_OAR1) . . . . .1000
30.9.4I2C own address 2 register (I2C_OAR2) . . . . .1001
30.9.5I2C timing register (I2C_TIMINGR) . . . . .1002
30.9.6I2C timeout register (I2C_TIMEOUTR) . . . . .1003
30.9.7I2C interrupt and status register (I2C_ISR) . . . . .1004
30.9.8I2C interrupt clear register (I2C_ICR) . . . . .1006
30.9.9I2C PEC register (I2C_PECR) . . . . .1007
30.9.10I2C receive data register (I2C_RXDR) . . . . .1007
30.9.11I2C transmit data register (I2C_TXDR) . . . . .1008
30.9.12I2C register map .....1009
31Universal synchronous/asynchronous receiver transmitter (USART/UART) .....1010
31.1Introduction .....1010
31.2USART main features .....1010
31.3USART extended features .....1011
31.4USART implementation .....1012
31.5USART functional description .....1012
31.5.1USART character description .....1015
31.5.2USART transmitter .....1017
31.5.3USART receiver .....1019
31.5.4USART baud rate generation .....1025
31.5.5Tolerance of the USART receiver to clock deviation .....1028
31.5.6USART auto baud rate detection .....1029
31.5.7Multiprocessor communication using USART .....1030
31.5.8Modbus communication using USART .....1032
31.5.9USART parity control .....1033
31.5.10USART LIN (local interconnection network) mode .....1034
31.5.11USART synchronous mode .....1036
31.5.12USART single-wire half-duplex communication .....1039
31.5.13USART smartcard mode .....1039
31.5.14USART IrDA SIR ENDEC block .....1044
31.5.15USART continuous communication in DMA mode .....1046
31.5.16RS232 hardware flow control and RS485 driver enable using USART .....1048
31.6USART in low-power modes .....1050
31.7USART interrupts .....1051
31.8USART registers .....1053
31.8.1USART control register 1 (USART_CR1) .....1053
31.8.2USART control register 2 (USART_CR2) .....1056
31.8.3USART control register 3 (USART_CR3) .....1059
31.8.4USART baud rate register (USART_BRR) .....1062
31.8.5USART guard time and prescaler register (USART_GTPR) .....1063
31.8.6USART receiver timeout register (USART_RTOR) .....1064
31.8.7USART request register (USART_RQR) .....1065
31.8.8USART interrupt and status register (USART_ISR) .....1066
31.8.9USART interrupt flag clear register (USART_ICR) . . . . .1070
31.8.10USART receive data register (USART_RDR) . . . . .1071
31.8.11USART transmit data register (USART_TDR) . . . . .1072
31.8.12USART register map . . . . .1072
32Serial peripheral interface / integrated interchip sound (SPI/I2S) .1074
32.1Introduction . . . . .1074
32.2SPI main features . . . . .1074
32.3I2S main features . . . . .1075
32.4SPI/I2S implementation . . . . .1075
32.5SPI functional description . . . . .1076
32.5.1General description . . . . .1076
32.5.2Communications between one master and one slave . . . . .1077
32.5.3Standard multislave communication . . . . .1079
32.5.4Multimaster communication . . . . .1080
32.5.5Slave select (NSS) pin management . . . . .1081
32.5.6Communication formats . . . . .1082
32.5.7Configuration of SPI . . . . .1084
32.5.8Procedure for enabling SPI . . . . .1085
32.5.9Data transmission and reception procedures . . . . .1085
32.5.10SPI status flags . . . . .1095
32.5.11SPI error flags . . . . .1096
32.5.12NSS pulse mode . . . . .1097
32.5.13TI mode . . . . .1097
32.5.14CRC calculation . . . . .1098
32.6SPI interrupts . . . . .1100
32.7I2S functional description . . . . .1101
32.7.1I2S general description . . . . .1101
32.7.2I2S full duplex . . . . .1102
32.7.3Supported audio protocols . . . . .1103
32.7.4Start-up description . . . . .1110
32.7.5Clock generator . . . . .1112
32.7.6I 2 S master mode . . . . .1115
32.7.7I 2 S slave mode . . . . .1116
32.7.8I2S status flags . . . . .1118
32.7.9I2S error flags . . . . .1119
32.7.10DMA features . . . . .1120
32.8I2S interrupts . . . . .1120
32.9SPI and I2S registers . . . . .1121
32.9.1SPI control register 1 (SPIx_CR1) . . . . .1121
32.9.2SPI control register 2 (SPIx_CR2) . . . . .1123
32.9.3SPI status register (SPIx_SR) . . . . .1125
32.9.4SPI data register (SPIx_DR) . . . . .1127
32.9.5SPI CRC polynomial register (SPIx_CRCPR) . . . . .1127
32.9.6SPI Rx CRC register (SPIx_RXCRCR) . . . . .1127
32.9.7SPI Tx CRC register (SPIx_TXCRCR) . . . . .1128
32.9.8SPIx_I2S configuration register (SPIx_I2SCFGR) . . . . .1128
32.9.9SPIx_I2S prescaler register (SPIx_I2SPR) . . . . .1130
32.9.10SPI/I2S register map . . . . .1132
33Serial audio interface (SAI) . . . . .1133
33.1Introduction . . . . .1133
33.2SAI main features . . . . .1133
33.3SAI functional description . . . . .1135
33.3.1SAI block diagram . . . . .1135
33.3.2SAI pins and internal signals . . . . .1136
33.3.3Main SAI modes . . . . .1136
33.3.4SAI synchronization mode . . . . .1137
33.3.5Audio data size . . . . .1138
33.3.6Frame synchronization . . . . .1139
33.3.7Slot configuration . . . . .1142
33.3.8SAI clock generator . . . . .1144
33.3.9Internal FIFOs . . . . .1146
33.3.10AC'97 link controller . . . . .1148
33.3.11SPDIF output . . . . .1150
33.3.12Specific features . . . . .1153
33.3.13Error flags . . . . .1157
33.3.14Disabling the SAI . . . . .1160
33.3.15SAI DMA interface . . . . .1160
33.4SAI interrupts . . . . .1161
33.5SAI registers . . . . .1163
33.5.1SAI global configuration register (SAI_GCR) . . . . .1163
33.5.2SAI configuration register 1 (SAI_ACR1) . . . . .1163
33.5.3SAI configuration register 2 (SAI_ACR2) . . . . .1166
33.5.4SAI frame configuration register (SAI_AFRCR) . . . . .1168
33.5.5SAI slot register (SAI_ASLOTR) . . . . .1169
33.5.6SAI interrupt mask register (SAI_AIM) . . . . .1170
33.5.7SAI status register (SAI_ASR) . . . . .1171
33.5.8SAI clear flag register (SAI_ACLRFR) . . . . .1173
33.5.9SAI data register (SAI_ADR) . . . . .1174
33.5.10SAI configuration register 1 (SAI_BCR1) . . . . .1175
33.5.11SAI configuration register 2 (SAI_BCR2) . . . . .1177
33.5.12SAI frame configuration register (SAI_BFRCR) . . . . .1179
33.5.13SAI slot register (SAI_BSLOTR) . . . . .1180
33.5.14SAI interrupt mask register (SAI_BIM) . . . . .1181
33.5.15SAI status register (SAI_BSR) . . . . .1182
33.5.16SAI clear flag register (SAI_BCLRFR) . . . . .1184
33.5.17SAI data register (SAI_BDR) . . . . .1185
33.5.18SAI register map . . . . .1186
34SPDIF receiver interface (SPDIFRX) . . . . .1188
34.1SPDIFRX interface introduction . . . . .1188
34.2SPDIFRX main features . . . . .1188
34.3SPDIFRX functional description . . . . .1188
34.3.1S/PDIF protocol (IEC-60958) . . . . .1189
34.3.2SPDIFRX decoder (SPDIFRX_DC) . . . . .1192
34.3.3SPDIFRX tolerance to clock deviation . . . . .1195
34.3.4SPDIFRX synchronization . . . . .1195
34.3.5SPDIFRX handling . . . . .1197
34.3.6Data reception management . . . . .1199
34.3.7Dedicated control flow . . . . .1201
34.3.8Reception errors . . . . .1202
34.3.9Clocking strategy . . . . .1204
34.3.10DMA interface . . . . .1204
34.3.11Interrupt generation . . . . .1205
34.3.12Register protection . . . . .1206
34.4Programming procedures . . . . .1207
34.4.1Initialization phase . . . . .1207
34.4.2Handling of interrupts coming from SPDIFRX . . . . .1208
34.4.3Handling of interrupts coming from DMA . . . . .1208
34.5SPDIFRX interface registers . . . . .1209
34.5.1SPDIFRX control register (SPDIFRX_CR) . . . . .1209
34.5.2SPDIFRX interrupt mask register (SPDIFRX_IMR) . . . . .1211
34.5.3SPDIFRX status register (SPDIFRX_SR) . . . . .1212
34.5.4SPDIFRX interrupt flag clear register (SPDIFRX_IFCR) . . . . .1214
34.5.5SPDIFRX data input register (SPDIFRX_FMT0_DR) . . . . .1215
34.5.6SPDIFRX data input register (SPDIFRX_FMT1_DR) . . . . .1215
34.5.7SPDIFRX data input register (SPDIFRX_FMT2_DR) . . . . .1216
34.5.8SPDIFRX channel status register (SPDIFRX_CSR) . . . . .1217
34.5.9SPDIFRX debug information register (SPDIFRX_DIR) . . . . .1217
34.5.10SPDIFRX interface register map . . . . .1218
35SD/SDIO/MMC card host interface (SDMMC) . . . . .1219
35.1SDMMC main features . . . . .1219
35.2SDMMC bus topology . . . . .1219
35.3SDMMC functional description . . . . .1221
35.3.1SDMMC adapter . . . . .1223
35.3.2SDMMC APB2 interface . . . . .1234
35.4Card functional description . . . . .1235
35.4.1Card identification mode . . . . .1235
35.4.2Card reset . . . . .1236
35.4.3Operating voltage range validation . . . . .1236
35.4.4Card identification process . . . . .1236
35.4.5Block write . . . . .1237
35.4.6Block read . . . . .1238
35.4.7Stream access, stream write and stream read
(MultiMediaCard only) . . . . .		1238
35.4.8Erase: group erase and sector erase . . . . .1240
35.4.9Wide bus selection or deselection . . . . .1240
35.4.10Protection management . . . . .1240
35.4.11Card status register . . . . .1244
35.4.12SD status register . . . . .1247
35.4.13SD I/O mode . . . . .1251
35.4.14Commands and responses . . . . .1252
35.5Response formats . . . . .1255
35.5.1R1 (normal response command) . . . . .1256
35.5.2R1b .....1256
35.5.3R2 (CID, CSD register) .....1256
35.5.4R3 (OCR register) .....1257
35.5.5R4 (Fast I/O) .....1257
35.5.6R4b .....1257
35.5.7R5 (interrupt request) .....1258
35.5.8R6 .....1258
35.6SDIO I/O card-specific operations .....1259
35.6.1SDIO I/O read wait operation by SDMMC_D2 signalling .....1259
35.6.2SDIO read wait operation by stopping SDMMC_CK .....1260
35.6.3SDIO suspend/resume operation .....1260
35.6.4SDIO interrupts .....1260
35.7HW flow control .....1260
35.8SDMMC registers .....1261
35.8.1SDMMC power control register (SDMMC_POWER) .....1261
35.8.2SDMMC clock control register (SDMMC_CLKCR) .....1261
35.8.3SDMMC argument register (SDMMC_ARG) .....1264
35.8.4SDMMC command register (SDMMC_CMD) .....1264
35.8.5SDMMC command response register (SDMMC_RESPCMD) .....1265
35.8.6SDMMC response 1..4 register (SDMMC_RESPx) .....1265
35.8.7SDMMC data timer register (SDMMC_DTIMER) .....1266
35.8.8SDMMC data length register (SDMMC_DLEN) .....1267
35.8.9SDMMC data control register (SDMMC_DCTRL) .....1267
35.8.10SDMMC data counter register (SDMMC_DCOUNT) .....1270
35.8.11SDMMC status register (SDMMC_STA) .....1270
35.8.12SDMMC interrupt clear register (SDMMC_ICR) .....1271
35.8.13SDMMC mask register (SDMMC_MASK) .....1273
35.8.14SDMMC FIFO counter register (SDMMC_FIFOCNT) .....1275
35.8.15SDMMC data FIFO register (SDMMC_FIFO) .....1276
35.8.16SDMMC register map .....1277
36Controller area network (bxCAN) .....1279
36.1Introduction .....1279
36.2bxCAN main features .....1279
36.3bxCAN general description .....1280
36.3.1CAN 2.0B active core .....1280
37.4OTG_FS/OTG_HS functional description . . . . .1328
37.4.1OTG_FS/OTG_HS block diagram . . . . .1328
37.4.2OTG_FS/OTG_HS pin and internal signals . . . . .1329
37.4.3OTG_FS/OTG_HS core . . . . .1330
37.4.4Embedded full-speed OTG PHY connected to OTG_FS . . . . .1330
37.4.5Embedded full-speed OTG PHY connected to OTG_HS . . . . .1331
37.4.6OTG detections . . . . .1331
37.4.7High-speed OTG PHY connected to OTG_HS . . . . .1331
37.5OTG_FS/OTG_HS dual role device (DRD) . . . . .1332
37.5.1ID line detection . . . . .1332
37.5.2HNP dual role device . . . . .1332
37.5.3SRP dual role device . . . . .1333
37.6OTG_FS/OTG_HS as a USB peripheral . . . . .1333
37.6.1SRP-capable peripheral . . . . .1334
37.6.2Peripheral states . . . . .1334
37.6.3Peripheral endpoints . . . . .1335
37.7OTG_FS/OTG_HS as a USB host . . . . .1337
37.7.1SRP-capable host . . . . .1338
37.7.2USB host states . . . . .1338
37.7.3Host channels . . . . .1340
37.7.4Host scheduler . . . . .1341
37.8OTG_FS/OTG_HS SOF trigger . . . . .1342
37.8.1Host SOFs . . . . .1342
37.8.2Peripheral SOFs . . . . .1342
37.9OTG_FS/OTG_HS low-power modes . . . . .1343
37.10OTG_FS/OTG_HS Dynamic update of the OTG_HFIR register . . . . .1344
37.11OTG_FS/OTG_HS data FIFOs . . . . .1344
37.11.1Peripheral FIFO architecture . . . . .1345
37.11.2Host FIFO architecture . . . . .1346
37.11.3FIFO RAM allocation . . . . .1347
37.12OTG_FS system performance . . . . .1349
37.13OTG_FS/OTG_HS interrupts . . . . .1349
37.14OTG_FS/OTG_HS control and status registers . . . . .1351
37.14.1CSR memory map . . . . .1351
37.15OTG_FS/OTG_HS registers . . . . .1357
37.15.1OTG control and status register (OTG_GOTGCTL) . . . . .1357
37.15.2OTG interrupt register (OTG_GOTGINT) . . . . .1360
37.15.3OTG AHB configuration register (OTG_GAHBCFG) . . . . .1362
37.15.4OTG USB configuration register (OTG_GUSBCFG) . . . . .1364
37.15.5OTG reset register (OTG_GRSTCTL) . . . . .1367
37.15.6OTG core interrupt register (OTG_GINTSTS) . . . . .1370
37.15.7OTG interrupt mask register (OTG_GINTMSK) . . . . .1375
37.15.8OTG receive status debug read register (OTG_GRXSTSR) . . . . .1378
37.15.9OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . .1379
37.15.10OTG status read and pop registers (OTG_GRXSTSP) . . . . .1380
37.15.11OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . . . .1381
37.15.12OTG receive FIFO size register (OTG_GRXFSIZ) . . . . .1382
37.15.13OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0) . . . . .		1383
37.15.14OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . .		1384
37.15.15OTG general core configuration register (OTG_GCCFG) . . . . .1385
37.15.16OTG core ID register (OTG_CID) . . . . .1386
37.15.17OTG core LPM configuration register (OTG_GLPMCFG) . . . . .1386
37.15.18OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . .		1390
37.15.19OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFn) . . . . .		1390
37.15.20Host-mode registers . . . . .1391
37.15.21OTG host configuration register (OTG_HCFG) . . . . .1391
37.15.22OTG host frame interval register (OTG_HFIR) . . . . .1392
37.15.23OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . .		1393
37.15.24OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . .		1393
37.15.25OTG host all channels interrupt register (OTG_HAINT) . . . . .1394
37.15.26OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . .		1395
37.15.27OTG host port control and status register (OTG_HPRT) . . . . .1396
37.15.28OTG host channel x characteristics register (OTG_HCCHARx) . . . . .1398
37.15.29OTG host channel x split control register (OTG_HCSPLTx) . . . . .1399
37.15.30OTG host channel x interrupt register (OTG_HCINTx) . . . . .1400
37.15.31OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . . . .1402
37.15.32OTG host channel x transfer size register (OTG_HCTSIZx) . . . . .1403
37.15.33OTG host channel x DMA address register (OTG_HCDMAx) . . . . .1404
37.15.34Device-mode registers . . . . .1405
37.15.35OTG device configuration register (OTG_DCFG) . . . . .1405
37.15.36OTG device control register (OTG_DCTL) . . . . .1407
37.15.37OTG device status register (OTG_DSTS) . . . . .1409
37.15.38OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . .		1410
37.15.39OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . .		1411
37.15.40OTG device all endpoints interrupt register (OTG_DAINT) . . . . .1413
37.15.41OTG all endpoints interrupt mask register
(OTG_DAINTEMSK) . . . . .		1413
37.15.42OTG device V BUS discharge time register
(OTG_DVBUSDIS) . . . . .		1414
37.15.43OTG device V BUS pulsing time register
(OTG_DVBUSPULSE) . . . . .		1414
37.15.44OTG device threshold control register (OTG_DTHRCTL) . . . . .1415
37.15.45OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK) . . . . .		1416
37.15.46OTG device each endpoint interrupt register (OTG_DEACHINT) . . . . .1417
37.15.47OTG device each endpoint interrupt mask register
(OTG_DEACHINTMSK) . . . . .		1417
37.15.48OTG device each IN endpoint-1 interrupt mask register
(OTG_HS_DIEPEACHMSK1) . . . . .		1418
37.15.49OTG device each OUT endpoint-1 interrupt mask register
(OTG_HS_DOEPEACHMSK1) . . . . .		1419
37.15.50OTG device control IN endpoint 0 control register
(OTG_DIEPCTL0) . . . . .		1420
37.15.51OTG device IN endpoint x control register (OTG_DIEPCTLx) . . . . .1422
37.15.52OTG device IN endpoint x interrupt register (OTG_DIEPINTx) . . . . .1424
37.15.53OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0) . . . . .		1426
37.15.54OTG device IN endpoint x DMA address register
(OTG_DIEPDMAx) . . . . .		1427
37.15.55OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) . . . . .		1427
37.15.56OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) . . . . .1428
37.15.57OTG device control OUT endpoint 0 control register
(OTG_DOEPCTL0) . . . . .		1429
37.15.58OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . . . . .1430
38.5.5MAC filtering . . . . .1545
38.5.6MAC loopback mode . . . . .1548
38.5.7MAC management counters: MMC . . . . .1548
38.5.8Power management: PMT . . . . .1549
38.5.9Precision time protocol (IEEE1588 PTP) . . . . .1552
38.6Ethernet functional description: DMA controller operation . . . . .1558
38.6.1Initialization of a transfer using DMA . . . . .1559
38.6.2Host bus burst access . . . . .1559
38.6.3Host data buffer alignment . . . . .1560
38.6.4Buffer size calculations . . . . .1560
38.6.5DMA arbiter . . . . .1561
38.6.6Error response to DMA . . . . .1561
38.6.7Tx DMA configuration . . . . .1561
38.6.8Rx DMA configuration . . . . .1573
38.6.9DMA interrupts . . . . .1584
38.7Ethernet interrupts . . . . .1585
38.8Ethernet registers . . . . .1586
38.8.1MAC register description . . . . .1586
38.8.2MMC register description . . . . .1606
38.8.3IEEE 1588 time stamp registers . . . . .1611
38.8.4DMA register description . . . . .1619
38.8.5Ethernet register maps . . . . .1634
39HDMI-CEC controller (CEC) . . . . .1638
39.1HDMI-CEC introduction . . . . .1638
39.2HDMI-CEC controller main features . . . . .1638
39.3HDMI-CEC functional description . . . . .1639
39.3.1HDMI-CEC pin . . . . .1639
39.3.2HDMI-CEC block diagram . . . . .1639
39.3.3Message description . . . . .1639
39.3.4Bit timing . . . . .1640
39.4Arbitration . . . . .1641
39.4.1SFT option bit . . . . .1642
39.5Error handling . . . . .1643
39.5.1Bit error . . . . .1643
39.5.2Message error . . . . .1643
39.5.3Bit rising error (BRE) . . . . .1643
39.5.4Short bit period error (SBPE) . . . . .1644
39.5.5Long bit period error (LBPE) . . . . .1644
39.5.6Transmission error detection (TXERR) . . . . .1645
39.6HDMI-CEC interrupts . . . . .1647
39.7HDMI-CEC registers . . . . .1648
39.7.1CEC control register (CEC_CR) . . . . .1648
39.7.2CEC configuration register (CEC_CFGR) . . . . .1649
39.7.3CEC Tx data register (CEC_TXDR) . . . . .1651
39.7.4CEC Rx data register (CEC_RXDR) . . . . .1651
39.7.5CEC interrupt and status register (CEC_ISR) . . . . .1651
39.7.6CEC interrupt enable register (CEC_IER) . . . . .1653
39.7.7HDMI-CEC register map . . . . .1655
40Debug support (DBG) . . . . .1656
40.1Overview . . . . .1656
40.2Reference Arm® documentation . . . . .1657
40.3SWJ debug port (serial wire and JTAG) . . . . .1657
40.3.1Mechanism to select the JTAG-DP or the SW-DP . . . . .1658
40.4Pinout and debug port pins . . . . .1658
40.4.1SWJ debug port pins . . . . .1659
40.4.2Flexible SWJ-DP pin assignment . . . . .1659
40.4.3Internal pull-up and pull-down on JTAG pins . . . . .1659
40.4.4Using serial wire and releasing the unused debug pins as GPIOs . . . . .1661
40.5STM32F75xxx and STM32F74xxx JTAG Debug Port connection . . . . .1661
40.6ID codes and locking mechanism . . . . .1663
40.6.1MCU device ID code . . . . .1663
40.6.2Boundary scan Debug Port . . . . .1663
40.6.3Cortex®-M7 with FPU Debug Port . . . . .1663
40.6.4Cortex®-M7 with FPU JEDEC-106 ID code . . . . .1664
40.7JTAG debug port . . . . .1664
40.8SW debug port . . . . .1666
40.8.1SW protocol introduction . . . . .1666
40.8.2SW protocol sequence . . . . .1666
40.8.3SW-DP state machine (reset, idle states, ID code) . . . . .1667
40.8.4DP and AP read/write accesses . . . . .1668
40.8.5SW-DP registers . . . . .1668
40.8.6SW-AP registers . . . . .1669
40.9AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP . . . . .		1670
40.10Core debug . . . . .1671
40.11Capability of the debugger host to connect under system reset . . . . .1672
40.12FPB (Flash patch breakpoint) . . . . .1672
40.13DWT (data watchpoint trigger) . . . . .1673
40.14ITM (instrumentation trace macrocell) . . . . .1673
40.14.1General description . . . . .1673
40.14.2Time stamp packets, synchronization and overflow packets . . . . .1673
40.15ETM (Embedded trace macrocell) . . . . .1675
40.15.1General description . . . . .1675
40.15.2Signal protocol, packet types . . . . .1675
40.15.3Main ETM registers . . . . .1676
40.15.4Configuration example . . . . .1676
40.16MCU debug component (DBGMCU) . . . . .1676
40.16.1Debug support for low-power modes . . . . .1676
40.16.2Debug support for timers, watchdog, bxCAN and I 2 C . . . . .1677
40.16.3Debug MCU configuration register . . . . .1677
40.16.4DBGMCU_CR register . . . . .1678
40.16.5Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . .1679
40.16.6Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ) . . . . .1681
40.17Pelican TPIU (trace port interface unit) . . . . .1682
40.17.1Introduction . . . . .1682
40.17.2TRACE pin assignment . . . . .1683
40.17.3TPIU formatter . . . . .1685
40.17.4TPIU frame synchronization packets . . . . .1685
40.17.5Transmission of the synchronization frame packet . . . . .1685
40.17.6Synchronous mode . . . . .1686
40.17.7Asynchronous mode . . . . .1686
40.17.8TRACECLKIN connection inside the
STM32F75xxx and STM32F74xxx . . . . .		1686
40.17.9TPIU registers . . . . .1687
40.17.10Example of configuration . . . . .1687
40.18DBG register map . . . . .1688

41 Device electronic signature . . . . . 1689

41.1 Unique device ID register (96 bits) . . . . . 1689

41.2 Flash size . . . . . 1690

41.3 Package data register . . . . . 1691

42 Important security notice . . . . . 1692

43 Revision history . . . . . 1693

List of tables

Table 1.STM32F75xxx and STM32F74xxx register boundary addresses . . . . .71
Table 2.Boot modes . . . . .75
Table 3.STM32F756xx and STM32F74xxx Flash memory organization . . . . .79
Table 4.STM32F750xx Flash memory organization . . . . .79
Table 5.Number of wait states according to CPU clock (HCLK) frequency . . . . .80
Table 6.Maximum program/erase parallelism . . . . .82
Table 7.Flash interrupt request . . . . .85
Table 8.Option byte organization . . . . .85
Table 9.Access versus read protection level . . . . .90
Table 10.OTP area organization . . . . .91
Table 11.Flash register map and reset values . . . . .99
Table 12.Voltage regulator configuration mode versus device operating mode . . . . .106
Table 13.Low-power mode summary . . . . .111
Table 14.Features over all modes . . . . .112
Table 15.Sleep-now entry and exit . . . . .116
Table 16.Sleep-on-exit entry and exit . . . . .117
Table 17.Stop operating modes . . . . .117
Table 18.Stop mode entry and exit (STM32F75xxx and STM32F74xxx) . . . . .119
Table 19.Standby mode entry and exit . . . . .121
Table 20.PWR - register map and reset values . . . . .132
Table 21.RCC register map and reset values . . . . .198
Table 22.Port bit configuration table . . . . .203
Table 23.GPIO register map and reset values . . . . .218
Table 24.SYSCFG register map and reset values . . . . .225
Table 25.DMA1 request mapping . . . . .230
Table 26.DMA2 request mapping . . . . .230
Table 27.Source and destination address . . . . .232
Table 28.Source and destination address registers in double-buffer mode (DBM = 1) . . . . .237
Table 29.Packing/unpacking and endian behavior (bit PINC = MINC = 1) . . . . .238
Table 30.Restriction on NDT versus PSIZE and MSIZE . . . . .238
Table 31.FIFO threshold configurations . . . . .241
Table 32.Possible DMA configurations . . . . .245
Table 33.DMA interrupt requests . . . . .247
Table 34.DMA register map and reset values . . . . .257
Table 35.Supported color mode in input . . . . .263
Table 36.Data order in memory . . . . .264
Table 37.Alpha mode configuration . . . . .265
Table 38.Supported CLUT color mode . . . . .266
Table 39.CLUT data order in system memory . . . . .266
Table 40.Supported color mode in output . . . . .267
Table 41.Data order in memory . . . . .267
Table 42.DMA2D interrupt requests . . . . .272
Table 43.DMA2D register map and reset values . . . . .288
Table 44.STM32F75xxx and STM32F74xxx vector table . . . . .290
Table 45.External interrupt/event controller register map and reset values . . . . .301
Table 46.CRC internal input/output signals . . . . .303
Table 47.CRC register map and reset values . . . . .308
Table 48.NOR/PSRAM bank selection . . . . .313
Table 49.NOR/PSRAM External memory address . . . . .314
Table 50.NAND memory mapping and timing registers. . . . .314
Table 51.NAND bank selection . . . . .314
Table 52.SDRAM bank selection. . . . .315
Table 53.SDRAM address mapping . . . . .315
Table 54.SDRAM address mapping with 8-bit data bus width. . . . .316
Table 55.SDRAM address mapping with 16-bit data bus width. . . . .316
Table 56.SDRAM address mapping with 32-bit data bus width. . . . .317
Table 57.Programmable NOR/PSRAM access parameters . . . . .319
Table 58.Non-multiplexed I/O NOR flash memory. . . . .320
Table 59.16-bit multiplexed I/O NOR flash memory . . . . .320
Table 60.Non-multiplexed I/Os PSRAM/SRAM . . . . .320
Table 61.16-Bit multiplexed I/O PSRAM . . . . .321
Table 62.NOR flash/PSRAM: example of supported memories
and transactions . . . . .		322
Table 63.FMC_BCRx bitfields (mode 1) . . . . .325
Table 64.FMC_BTRx bitfields (mode 1) . . . . .325
Table 65.FMC_BCRx bitfields (mode A) . . . . .327
Table 66.FMC_BTRx bitfields (mode A) . . . . .327
Table 67.FMC_BWTRx bitfields (mode A). . . . .328
Table 68.FMC_BCRx bitfields (mode 2/B). . . . .330
Table 69.FMC_BTRx bitfields (mode 2/B). . . . .330
Table 70.FMC_BWTRx bitfields (mode 2/B) . . . . .331
Table 71.FMC_BCRx bitfields (mode C) . . . . .332
Table 72.FMC_BTRx bitfields (mode C) . . . . .333
Table 73.FMC_BWTRx bitfields (mode C). . . . .333
Table 74.FMC_BCRx bitfields (mode D) . . . . .335
Table 75.FMC_BTRx bitfields (mode D) . . . . .335
Table 76.FMC_BWTRx bitfields (mode D). . . . .336
Table 77.FMC_BCRx bitfields (Muxed mode). . . . .337
Table 78.FMC_BTRx bitfields (Muxed mode) . . . . .338
Table 79.FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .343
Table 80.FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .344
Table 81.FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .345
Table 82.FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .346
Table 83.Programmable NAND flash access parameters . . . . .354
Table 84.8-bit NAND flash . . . . .354
Table 85.16-bit NAND flash . . . . .355
Table 86.Supported memories and transactions . . . . .355
Table 87.ECC result relevant bits . . . . .364
Table 88.SDRAM signals. . . . .365
Table 89.FMC register map and reset values . . . . .382
Table 90.QUADSPI pins . . . . .386
Table 91.QUADSPI interrupt requests. . . . .400
Table 92.QUADSPI register map and reset values . . . . .411
Table 93.ADC pins. . . . .415
Table 94.Analog watchdog channel selection . . . . .421
Table 95.Configuring the trigger polarity . . . . .426
Table 96.External trigger for regular channels. . . . .426
Table 97.External trigger for injected channels . . . . .427
Table 98.ADC interrupts . . . . .442
Table 99.ADC global register map. . . . .457
Table 100.ADC register map and reset values for each ADC . . . . .457
Table 101.ADC register map and reset values (common ADC registers) . . . . .459
Table 102.DAC pins . . . . .461
Table 103.External triggers . . . . .464
Table 104.DAC register map . . . . .481
Table 105.DCMI input/output pins . . . . .483
Table 106.Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .485
Table 107.Positioning of captured data bytes in 32-bit words (10-bit width) . . . . .485
Table 108.Positioning of captured data bytes in 32-bit words (12-bit width) . . . . .485
Table 109.Positioning of captured data bytes in 32-bit words (14-bit width) . . . . .486
Table 110.Data storage in monochrome progressive video format . . . . .491
Table 111.Data storage in RGB progressive video format . . . . .492
Table 112.Data storage in YCbCr progressive video format . . . . .492
Table 113.Data storage in YCbCr progressive video format - Y extraction mode . . . . .492
Table 114.DCMI interrupts . . . . .493
Table 115.DCMI register map and reset values . . . . .503
Table 116.LTDC pins and signal interface . . . . .505
Table 117.Clock domain for each register . . . . .506
Table 118.Pixel data mapping versus color format . . . . .511
Table 119.LTDC interrupt requests . . . . .515
Table 120.LTDC register map and reset values . . . . .534
Table 121.RNG internal input/output signals . . . . .538
Table 122.RNG interrupt requests . . . . .543
Table 123.RNG configurations . . . . .544
Table 124.RNG register map and reset map . . . . .547
Table 125.CRYP internal input/output signals . . . . .550
Table 126.Counter mode initialization vector . . . . .576
Table 127.GCM last block definition . . . . .579
Table 128.GCM mode IV registers initialization . . . . .579
Table 129.CCM mode IV registers initialization . . . . .586
Table 130.DES/TDES data swapping example . . . . .590
Table 131.AES data swapping example . . . . .591
Table 132.Key endianness in CRYP_KxR/LR registers (AES 128/192/256-bit keys) . . . . .593
Table 133.Key endianness in CRYP_KxR/LR registers (DES K1 and TDES K1/2/3) . . . . .593
Table 134.Initialization vector endianness in CRYP_IVx(L/R)R registers (AES) . . . . .594
Table 135.Initialization vector endianness in CRYP_IVx(L/R)R registers (DES/TDES) . . . . .594
Table 136.Cryptographic processor configuration for memory-to-peripheral DMA transfers . . . . .594
Table 137.Cryptographic processor configuration for peripheral-to-memory DMA transfers . . . . .595
Table 138.CRYP interrupt requests . . . . .597
Table 139.Processing latency for ECB, CBC and CTR . . . . .598
Table 140.Processing time (in clock cycle) for GCM and CCM per 128-bit block . . . . .598
Table 141.CRYP register map and reset values . . . . .611
Table 142.HASH internal input/output signals . . . . .615
Table 143.Hash processor outputs . . . . .618
Table 144.Processing time (in clock cycle) . . . . .624
Table 145.HASH interrupt requests . . . . .625
Table 146.HASH register map and reset values . . . . .633
Table 147.Behavior of timer outputs versus BRK/BRK2 inputs . . . . .676
Table 148.Counting direction versus encoder signals . . . . .683
Table 149.TIMx internal trigger connection . . . . .700
Table 150.Output control bits for complementary OCx and OCxN channels with break feature . . . . .714
Table 151.TIM1 register map and reset values . . . . .726
Table 152.TIM8 register map and reset values . . . . .728
Table 153.Counting direction versus encoder signals . . . . .765
Table 154.TIMx internal trigger connection . . . . .783
Table 155.Output control bit for standard OCx channels . . . . .793
Table 156.TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . .800
Table 157.TIMx internal trigger connection . . . . .830
Table 158.Output control bit for standard OCx channels . . . . .837
Table 159.TIM9/TIM12 register map and reset values . . . . .840
Table 160.Output control bit for standard OCx channels . . . . .849
Table 161.TIM10/TIM11/TIM13/TIM14 register map and reset values . . . . .851
Table 162.TIMx register map and reset values . . . . .865
Table 163.STM32F75xxx and STM32F74xxx LPTIM features . . . . .867
Table 164.LPTIM1 external trigger connection . . . . .868
Table 165.Prescaler division ratios . . . . .869
Table 166.Encoder counting scenarios . . . . .875
Table 167.Effect of low-power modes on the LPTIM . . . . .876
Table 168.Interrupt events . . . . .877
Table 169.LPTIM register map and reset values . . . . .886
Table 170.IWDG register map and reset values . . . . .895
Table 171.WWDG register map and reset values . . . . .901
Table 172.RTC pin PC13 configuration . . . . .905
Table 173.RTC pin PI8 configuration . . . . .906
Table 174.RTC pin PC2 configuration . . . . .907
Table 175.RTC functions over modes . . . . .907
Table 176.Effect of low-power modes on RTC . . . . .919
Table 177.Interrupt control bits . . . . .920
Table 178.RTC register map and reset values . . . . .945
Table 179.I2C implementation . . . . .948
Table 180.I2C input/output pins . . . . .949
Table 181.I2C internal input/output signals . . . . .949
Table 182.Comparison of analog and digital filters . . . . .951
Table 183.I 2 C-bus and SMBus specification data setup and hold times . . . . .954
Table 184.I2C configuration . . . . .957
Table 185.I 2 C-bus and SMBus specification clock timings . . . . .968
Table 186.Timing settings for f I2CCLK of 8 MHz . . . . .978
Table 187.Timing settings for f I2CCLK of 16 MHz . . . . .978
Table 188.Timing settings for f I2CCLK of 48 MHz . . . . .979
Table 189.SMBus timeout specifications . . . . .981
Table 190.SMBus with PEC configuration . . . . .983
Table 191.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms . . . . .984
Table 192.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .984
Table 193.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .984
Table 194.Effect of low-power modes to I2C . . . . .993
Table 195.I2C interrupt requests . . . . .993
Table 196.I2C register map and reset values . . . . .1009
Table 197.STM32F75xxx and STM32F74xxx USART features . . . . .1012
Table 198.Noise detection from sampled data . . . . .1024
Table 199.Error calculation for programmed baud rates at f CK = 216 MHz
in both cases of oversampling by 8 (OVER8 = 1) . . . . .		1027
Table 200.Error calculation for programmed baud rates at f CK = 216 MHz
in both cases of oversampling by 16 (OVER8 = 0) . . . . .1027
Table 201. Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .1028
Table 202. Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . .1028
Table 203. Frame formats . . . . .1033
Table 204. Effect of low-power modes on the USART . . . . .1050
Table 205. USART interrupt requests. . . . .1051
Table 206. USART register map and reset values . . . . .1072
Table 207. STM32F75xxx and STM32F74xxx SPI and SPI/I2S implementation . . . . .1075
Table 208. SPI interrupt requests . . . . .1100
Table 209. Audio-frequency precision using 48 MHz clock derived from HSE. . . . .1114
Table 210. I2S interrupt requests . . . . .1120
Table 211. SPI/I2S register map and reset values . . . . .1132
Table 212. SAI internal input/output signals . . . . .1136
Table 213. SAI input/output pins. . . . .1136
Table 214. External synchronization selection . . . . .1138
Table 215. Example of possible audio frequency sampling range . . . . .1145
Table 216. SOPD pattern . . . . .1151
Table 217. Parity bit calculation . . . . .1151
Table 218. Audio sampling frequency versus symbol rates . . . . .1152
Table 219. SAI interrupt sources . . . . .1161
Table 220. SAI register map and reset values . . . . .1186
Table 221. Transition sequence for preamble . . . . .1194
Table 222. Minimum SPDIFRX_CLK frequency versus audio sampling rate. . . . .1204
Table 223. Bit field property versus SPDIFRX state. . . . .1206
Table 224. SPDIFRX interface register map and reset values . . . . .1218
Table 225. SDMMC I/O definitions . . . . .1222
Table 226. Command format . . . . .1227
Table 227. Short response format . . . . .1228
Table 228. Long response format. . . . .1228
Table 229. Command path status flags . . . . .1228
Table 230. Data token format . . . . .1231
Table 231. DPSM flags . . . . .1232
Table 232. Transmit FIFO status flags . . . . .1233
Table 233. Receive FIFO status flags . . . . .1233
Table 234. Card status . . . . .1244
Table 235. SD status . . . . .1247
Table 236. Speed class code field . . . . .1248
Table 237. Performance move field . . . . .1249
Table 238. AU_SIZE field . . . . .1249
Table 239. Maximum AU size. . . . .1249
Table 240. Erase size field . . . . .1250
Table 241. Erase timeout field . . . . .1250
Table 242. Erase offset field . . . . .1250
Table 243. Block-oriented write commands . . . . .1253
Table 244. Block-oriented write protection commands. . . . .1254
Table 245. Erase commands . . . . .1254
Table 246. I/O mode commands . . . . .1254
Table 247. Lock card . . . . .1255
Table 248. Application-specific commands . . . . .1255
Table 249. R1 response . . . . .1256
Table 250. R2 response . . . . .1256
Table 251. R3 response . . . . .1257
Table 252.R4 response . . . . .1257
Table 253.R4b response . . . . .1257
Table 254.R5 response . . . . .1258
Table 255.R6 response . . . . .1259
Table 256.Response type and SDMMC_RESPx registers . . . . .1266
Table 257.SDMMC register map . . . . .1277
Table 258.Transmit mailbox mapping . . . . .1293
Table 259.Receive mailbox mapping . . . . .1293
Table 260.bxCAN register map and reset values . . . . .1319
Table 261.OTG_HS speeds supported . . . . .1324
Table 262.OTG_FS speeds supported . . . . .1324
Table 263.OTG_FS/OTG_HS implementation . . . . .1327
Table 264.OTG_FS input/output pins . . . . .1329
Table 265.OTG_HS input/output pins . . . . .1329
Table 266.OTG_FS/OTG_HS input/output signals . . . . .1330
Table 267.Compatibility of STM32 low power modes with the OTG . . . . .1343
Table 268.Core global control and status registers (CSRs). . . . .1351
Table 269.Host-mode control and status registers (CSRs) . . . . .1352
Table 270.Device-mode control and status registers . . . . .1354
Table 271.Data FIFO (DFIFO) access register map . . . . .1357
Table 272.Power and clock gating control and status registers . . . . .1357
Table 273.TRDT values (FS). . . . .1367
Table 274.TRDT values (HS) . . . . .1367
Table 275.Minimum duration for soft disconnect . . . . .1408
Table 276.OTG_FS/OTG_HS register map and reset values . . . . .1438
Table 277.Alternate function mapping . . . . .1519
Table 278.Management frame format . . . . .1521
Table 279.Clock range . . . . .1523
Table 280.TX interface signal encoding . . . . .1525
Table 281.RX interface signal encoding . . . . .1525
Table 282.Frame statuses . . . . .1541
Table 283.Destination address filtering . . . . .1547
Table 284.Source address filtering . . . . .1548
Table 285.Receive descriptor 0 - encoding for bits 7, 5 and 0 (normal descriptor format only, EDFE=0). . . . .1579
Table 286.Time stamp snapshot dependency on registers bits . . . . .1613
Table 287.Ethernet register map and reset values . . . . .1634
Table 288.HDMI pin . . . . .1639
Table 289.Error handling timing parameters . . . . .1645
Table 290.TXERR timing parameters . . . . .1646
Table 291.HDMI-CEC interrupts . . . . .1647
Table 292.HDMI-CEC register map and reset values . . . . .1655
Table 293.SWJ debug port pins . . . . .1659
Table 294.Flexible SWJ-DP pin assignment . . . . .1659
Table 295.JTAG debug port data registers . . . . .1664
Table 296.32-bit debug port registers addressed through the shifted value A[3:2] . . . . .1666
Table 297.Packet request (8-bits) . . . . .1667
Table 298.ACK response (3 bits). . . . .1667
Table 299.DATA transfer (33 bits). . . . .1667
Table 300.SW-DP registers . . . . .1668
Table 301.Cortex ® -M7 with FPU AHB-AP registers . . . . .1670
Table 302.Core debug registers . . . . .1671
Table 303. Main ITM registers . . . . .1674
Table 304. Asynchronous TRACE pin assignment. . . . .1683
Table 305. Synchronous TRACE pin assignment . . . . .1683
Table 306. Flexible TRACE pin assignment. . . . .1684
Table 307. Important TPIU registers. . . . .1687
Table 308. DBG register map and reset values . . . . .1688
Table 309. Document revision history . . . . .1693

List of figures

Figure 1.System architecture for STM32F75xxx and STM32F74xxx devices . . . . .65
Figure 2.Memory map . . . . .70
Figure 3.Flash memory interface connection inside system architecture
(STM32F75xxx and STM32F74xxx) . . . . .		77
Figure 4.RDP levels . . . . .90
Figure 5.Power supply overview . . . . .101
Figure 6.VDDUSB connected to VDD power supply . . . . .102
Figure 7.VDDUSB connected to external independent power supply . . . . .103
Figure 8.Backup domain . . . . .105
Figure 9.Power-on reset/power-down reset waveform . . . . .108
Figure 10.BOR thresholds . . . . .109
Figure 11.PVD thresholds . . . . .110
Figure 12.Simplified diagram of the reset circuit . . . . .134
Figure 13.Clock tree . . . . .135
Figure 14.HSE/ LSE clock sources . . . . .139
Figure 15.Frequency measurement with TIM5 in Input capture mode . . . . .144
Figure 16.Frequency measurement with TIM11 in Input capture mode . . . . .145
Figure 17.Basic structure of an I/O port bit . . . . .202
Figure 18.Basic structure of a 5-Volt tolerant I/O port bit . . . . .202
Figure 19.Input floating / pull up / pull down configurations . . . . .207
Figure 20.Output configuration . . . . .208
Figure 21.Alternate function configuration . . . . .209
Figure 22.High impedance-analog configuration . . . . .209
Figure 23.DMA block diagram . . . . .228
Figure 24.Channel selection . . . . .230
Figure 25.Peripheral-to-memory mode . . . . .233
Figure 26.Memory-to-peripheral mode . . . . .234
Figure 27.Memory-to-memory mode . . . . .235
Figure 28.FIFO structure . . . . .240
Figure 29.DMA2D block diagram . . . . .262
Figure 30.External interrupt/event controller block diagram . . . . .295
Figure 31.External interrupt/event GPIO mapping . . . . .297
Figure 32.CRC calculation unit block diagram . . . . .303
Figure 33.FMC block diagram . . . . .310
Figure 34.FMC memory banks . . . . .313
Figure 35.Mode 1 read access waveforms . . . . .324
Figure 36.Mode 1 write access waveforms . . . . .324
Figure 37.Mode A read access waveforms . . . . .326
Figure 38.Mode A write access waveforms . . . . .326
Figure 39.Mode 2 and mode B read access waveforms . . . . .328
Figure 40.Mode 2 write access waveforms . . . . .329
Figure 41.Mode B write access waveforms . . . . .329
Figure 42.Mode C read access waveforms . . . . .331
Figure 43.Mode C write access waveforms . . . . .332
Figure 44.Mode D read access waveforms . . . . .334
Figure 45.Mode D write access waveforms . . . . .334
Figure 46.Muxed read access waveforms . . . . .336
Figure 47.Muxed write access waveforms . . . . .337
Figure 48.Asynchronous wait during a read access waveforms . . . . .339
Figure 49.Asynchronous wait during a write access waveforms . . . . .340
Figure 50.Wait configuration waveforms . . . . .342
Figure 51.Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . .343
Figure 52.Synchronous multiplexed write mode waveforms - PSRAM (CRAM) . . . . .345
Figure 53.NAND flash controller waveforms for common memory access . . . . .356
Figure 54.Access to non 'CE don't care' NAND-flash . . . . .358
Figure 55.Burst write SDRAM access waveforms . . . . .367
Figure 56.Burst read SDRAM access . . . . .368
Figure 57.Logic diagram of Read access with RBURST bit set (CAS=1, RPIPE=0) . . . . .369
Figure 58.Read access crossing row boundary . . . . .371
Figure 59.Write access crossing row boundary . . . . .371
Figure 60.Self-refresh mode . . . . .374
Figure 61.Power-down mode . . . . .375
Figure 62.QUADSPI block diagram when dual-flash mode is disabled . . . . .385
Figure 63.QUADSPI block diagram when dual-flash mode is enabled . . . . .386
Figure 64.Example of read command in quad-SPI mode . . . . .387
Figure 65.Example of a DDR command in quad-SPI mode . . . . .390
Figure 66.NCS when CKMODE = 0 (T = CLK period) . . . . .398
Figure 67.NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .398
Figure 68.NCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . .399
Figure 69.NCS when CKMODE = 1 with an abort (T = CLK period) . . . . .399
Figure 70.Single ADC block diagram . . . . .414
Figure 71.ADC1 connectivity . . . . .416
Figure 72.ADC2 connectivity . . . . .417
Figure 73.ADC3 connectivity . . . . .418
Figure 74.Timing diagram . . . . .421
Figure 75.Analog watchdog's guarded area . . . . .421
Figure 76.Injected conversion latency . . . . .423
Figure 77.Right alignment of 12-bit data . . . . .425
Figure 78.Left alignment of 12-bit data . . . . .425
Figure 79.Left alignment of 6-bit data . . . . .425
Figure 80.Multi ADC block diagram (1) . . . . .430
Figure 81.Injected simultaneous mode on 4 channels: dual ADC mode . . . . .433
Figure 82.Injected simultaneous mode on 4 channels: triple ADC mode . . . . .433
Figure 83.Regular simultaneous mode on 16 channels: dual ADC mode . . . . .434
Figure 84.Regular simultaneous mode on 16 channels: triple ADC mode . . . . .434
Figure 85.Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode . . . . .435
Figure 86.Interleaved mode on 1 channel in continuous conversion mode: triple ADC mode . . . . .436
Figure 87.Alternate trigger: injected group of each ADC . . . . .437
Figure 88.Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . .437
Figure 89.Alternate trigger: injected group of each ADC . . . . .438
Figure 90.Alternate + regular simultaneous . . . . .439
Figure 91.Case of trigger occurring during injected conversion . . . . .439
Figure 92.Temperature sensor and VREFINT channel block diagram . . . . .440
Figure 93.DAC channel block diagram . . . . .461
Figure 94.DAC output buffer connection . . . . .462
Figure 95.Data registers in single DAC channel mode . . . . .463
Figure 96.Data registers in dual DAC channel mode . . . . .463
Figure 97.Timing diagram for conversion with trigger disabled TEN = 0 . . . . .464
Figure 98.DAC LFSR register calculation algorithm . . . . .466
Figure 99.DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .466
Figure 100. DAC triangle wave generation . . . . .467
Figure 101. DAC conversion (SW trigger enabled) with triangle wave generation . . . . .467
Figure 102. DCMI block diagram . . . . .483
Figure 103. Top-level block diagram . . . . .483
Figure 104. DCMI signal waveforms . . . . .484
Figure 105. Timing diagram . . . . .486
Figure 106. Frame capture waveforms in snapshot mode. . . . .488
Figure 107. Frame capture waveforms in continuous grab mode . . . . .489
Figure 108. Coordinates and size of the window after cropping . . . . .489
Figure 109. Data capture waveforms. . . . .490
Figure 110. Pixel raster scan order . . . . .491
Figure 111. LTDC block diagram . . . . .505
Figure 112. LCD-TFT synchronous timings . . . . .508
Figure 113. Layer window programmable parameters . . . . .511
Figure 114. Blending two layers with background . . . . .514
Figure 115. Interrupt events. . . . .515
Figure 116. RNG block diagram . . . . .538
Figure 117. Entropy source model. . . . .539
Figure 118. CRYPT block diagram . . . . .550
Figure 119. AES-ECB mode overview. . . . .553
Figure 120. AES-CBC mode overview. . . . .554
Figure 121. AES-CTR mode overview. . . . .555
Figure 122. AES-GCM mode overview . . . . .556
Figure 123. AES-GMAC mode overview . . . . .556
Figure 124. AES-CCM mode overview . . . . .557
Figure 125. Example of suspend mode management. . . . .563
Figure 126. DES/TDES-ECB mode encryption . . . . .564
Figure 127. DES/TDES-ECB mode decryption . . . . .565
Figure 128. DES/TDES-CBC mode encryption . . . . .566
Figure 129. DES/TDES-CBC mode decryption . . . . .567
Figure 130. AES-ECB mode encryption . . . . .569
Figure 131. AES-ECB mode decryption . . . . .570
Figure 132. AES-CBC mode encryption . . . . .571
Figure 133. AES-CBC mode decryption . . . . .572
Figure 134. Message construction for the Counter mode . . . . .574
Figure 135. AES-CTR mode encryption . . . . .575
Figure 136. AES-CTR mode decryption . . . . .576
Figure 137. Message construction for the Galois/counter mode . . . . .578
Figure 138. Message construction for the Galois Message Authentication Code mode . . . . .583
Figure 139. Message construction for the Counter with CBC-MAC mode. . . . .584
Figure 140. 64-bit block construction according to the data type (IN FIFO). . . . .591
Figure 141. 128-bit block construction according to the data type. . . . .592
Figure 142. HASH block diagram . . . . .614
Figure 143. Message data swapping feature. . . . .616
Figure 144. HASH suspend/resume mechanism. . . . .622
Figure 145. Advanced-control timer block diagram . . . . .636
Figure 146. Counter timing diagram with prescaler division change from 1 to 2 . . . . .638
Figure 147. Counter timing diagram with prescaler division change from 1 to 4 . . . . .638
Figure 148. Counter timing diagram, internal clock divided by 1 . . . . .640
Figure 149. Counter timing diagram, internal clock divided by 2 . . . . .640
Figure 150. Counter timing diagram, internal clock divided by 4 . . . . .641
Figure 151. Counter timing diagram, internal clock divided by N. . . . .641
Figure 152. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .642
Figure 153. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .642
Figure 154. Counter timing diagram, internal clock divided by 1 . . . . .644
Figure 155. Counter timing diagram, internal clock divided by 2 . . . . .644
Figure 156. Counter timing diagram, internal clock divided by 4 . . . . .645
Figure 157. Counter timing diagram, internal clock divided by N . . . . .645
Figure 158. Counter timing diagram, update event when repetition counter is not used. . . . .646
Figure 159. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .647
Figure 160. Counter timing diagram, internal clock divided by 2 . . . . .648
Figure 161. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .648
Figure 162. Counter timing diagram, internal clock divided by N . . . . .649
Figure 163. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .649
Figure 164. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .650
Figure 165. Update rate examples depending on mode and TIMx_RCR register settings . . . . .651
Figure 166. External trigger input block . . . . .652
Figure 167. Control circuit in normal mode, internal clock divided by 1 . . . . .653
Figure 168. TI2 external clock connection example. . . . .654
Figure 169. Control circuit in external clock mode 1 . . . . .655
Figure 170. External trigger input block . . . . .655
Figure 171. Control circuit in external clock mode 2 . . . . .656
Figure 172. Capture/compare channel (example: channel 1 input stage) . . . . .657
Figure 173. Capture/compare channel 1 main circuit . . . . .658
Figure 174. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .658
Figure 175. Output stage of capture/compare channel (channel 4). . . . .659
Figure 176. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .659
Figure 177. PWM input mode timing . . . . .661
Figure 178. Output compare mode, toggle on OC1 . . . . .663
Figure 179. Edge-aligned PWM waveforms (ARR=8) . . . . .664
Figure 180. Center-aligned PWM waveforms (ARR=8). . . . .665
Figure 181. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .667
Figure 182. Combined PWM mode on channel 1 and 3 . . . . .668
Figure 183. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .669
Figure 184. Complementary output with dead-time insertion . . . . .670
Figure 185. Dead-time waveforms with delay greater than the negative pulse . . . . .670
Figure 186. Dead-time waveforms with delay greater than the positive pulse. . . . .671
Figure 187. Break and Break2 circuitry overview . . . . .673
Figure 188. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .675
Figure 189. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .676
Figure 190. PWM output state following BRK assertion (OSSI=0) . . . . .677
Figure 191. Clearing TIMx_OCxREF . . . . .678
Figure 192. 6-step generation, COM example (OSSR=1) . . . . .679
Figure 193. Example of one pulse mode. . . . .680
Figure 194. Retriggerable one pulse mode . . . . .682
Figure 195. Example of counter operation in encoder interface mode. . . . .683
Figure 196. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .684
Figure 197. Measuring time interval between edges on 3 signals . . . . .685
Figure 198. Example of Hall sensor interface . . . . .687
Figure 199. Control circuit in reset mode . . . . .688
Figure 200. Control circuit in Gated mode . . . . .689
Figure 201. Control circuit in trigger mode . . . . .690
Figure 202. Control circuit in external clock mode 2 + trigger mode . . . . .691
Figure 203. General-purpose timer block diagram . . . . .732
Figure 204. Counter timing diagram with prescaler division change from 1 to 2 . . . . .734
Figure 205. Counter timing diagram with prescaler division change from 1 to 4 . . . . .734
Figure 206. Counter timing diagram, internal clock divided by 1 . . . . .735
Figure 207. Counter timing diagram, internal clock divided by 2 . . . . .736
Figure 208. Counter timing diagram, internal clock divided by 4 . . . . .736
Figure 209. Counter timing diagram, internal clock divided by N . . . . .737
Figure 210. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .737
Figure 211. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .738
Figure 212. Counter timing diagram, internal clock divided by 1 . . . . .739
Figure 213. Counter timing diagram, internal clock divided by 2 . . . . .739
Figure 214. Counter timing diagram, internal clock divided by 4 . . . . .740
Figure 215. Counter timing diagram, internal clock divided by N . . . . .740
Figure 216. Counter timing diagram, Update event . . . . .741
Figure 217. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .742
Figure 218. Counter timing diagram, internal clock divided by 2 . . . . .743
Figure 219. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .743
Figure 220. Counter timing diagram, internal clock divided by N . . . . .744
Figure 221. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .744
Figure 222. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .745
Figure 223. Control circuit in normal mode, internal clock divided by 1 . . . . .746
Figure 224. TI2 external clock connection example. . . . .746
Figure 225. Control circuit in external clock mode 1 . . . . .747
Figure 226. External trigger input block . . . . .748
Figure 227. Control circuit in external clock mode 2 . . . . .749
Figure 228. Capture/Compare channel (example: channel 1 input stage) . . . . .750
Figure 229. Capture/Compare channel 1 main circuit . . . . .750
Figure 230. Output stage of Capture/Compare channel (channel 1). . . . .751
Figure 231. PWM input mode timing . . . . .753
Figure 232. Output compare mode, toggle on OC1 . . . . .755
Figure 233. Edge-aligned PWM waveforms (ARR=8). . . . .756
Figure 234. Center-aligned PWM waveforms (ARR=8). . . . .757
Figure 235. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .758
Figure 236. Combined PWM mode on channels 1 and 3 . . . . .760
Figure 237. Clearing TIMx_OCxREF . . . . .761
Figure 238. Example of one-pulse mode. . . . .762
Figure 239. Retriggerable one-pulse mode . . . . .764
Figure 240. Example of counter operation in encoder interface mode . . . . .765
Figure 241. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .766
Figure 242. Control circuit in reset mode . . . . .767
Figure 243. Control circuit in gated mode . . . . .768
Figure 244. Control circuit in trigger mode. . . . .769
Figure 245. Control circuit in external clock mode 2 + trigger mode . . . . .770
Figure 246. Master/Slave timer example . . . . .771
Figure 247. Master/slave connection example with 1 channel only timers . . . . .771
Figure 248. Gating TIM with OC1REF of TIM3 . . . . .772
Figure 249. Gating TIM with Enable of TIM3 . . . . .773
Figure 250. Triggering TIM with update of TIM3 . . . . .774
Figure 251. Triggering TIM with Enable of TIM3 . . . . .774
Figure 252. Triggering TIM3 and TIM2 with TIM3 TI1 input. . . . .775
Figure 253. General-purpose timer block diagram (TIM9/TIM12) . . . . .804
Figure 254. General-purpose timer block diagram (TIM10/TIM11/TIM13/TIM14) . . . . .805
Figure 255. Counter timing diagram with prescaler division change from 1 to 2 . . . . .807
Figure 256. Counter timing diagram with prescaler division change from 1 to 4 . . . . .807
Figure 257. Counter timing diagram, internal clock divided by 1 . . . . .808
Figure 258. Counter timing diagram, internal clock divided by 2 . . . . .809
Figure 259. Counter timing diagram, internal clock divided by 4 . . . . .809
Figure 260. Counter timing diagram, internal clock divided by N . . . . .810
Figure 261. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .810
Figure 262. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .811
Figure 263. Control circuit in normal mode, internal clock divided by 1 . . . . .812
Figure 264. TI2 external clock connection example. . . . .812
Figure 265. Control circuit in external clock mode 1 . . . . .813
Figure 266. Capture/compare channel (example: channel 1 input stage). . . . .814
Figure 267. Capture/compare channel 1 main circuit . . . . .814
Figure 268. Output stage of capture/compare channel (channel 1). . . . .815
Figure 269. PWM input mode timing . . . . .817
Figure 270. Output compare mode, toggle on OC1. . . . .818
Figure 271. Edge-aligned PWM waveforms (ARR=8). . . . .819
Figure 272. Combined PWM mode on channel 1 and 2 . . . . .820
Figure 273. Example of one pulse mode. . . . .821
Figure 274. Retriggerable one pulse mode . . . . .823
Figure 275. Control circuit in reset mode . . . . .824
Figure 276. Control circuit in gated mode . . . . .825
Figure 277. Control circuit in trigger mode. . . . .825
Figure 278. Basic timer block diagram. . . . .853
Figure 279. Counter timing diagram with prescaler division change from 1 to 2 . . . . .855
Figure 280. Counter timing diagram with prescaler division change from 1 to 4 . . . . .855
Figure 281. Counter timing diagram, internal clock divided by 1 . . . . .856
Figure 282. Counter timing diagram, internal clock divided by 2 . . . . .857
Figure 283. Counter timing diagram, internal clock divided by 4 . . . . .857
Figure 284. Counter timing diagram, internal clock divided by N . . . . .858
Figure 285. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .858
Figure 286. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .859
Figure 287. Control circuit in normal mode, internal clock divided by 1 . . . . .860
Figure 288. Low-power timer block diagram . . . . .867
Figure 289. Glitch filter timing diagram . . . . .869
Figure 290. LPTIM output waveform, single counting mode configuration . . . . .871
Figure 291. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set). . . . .871
Figure 292. LPTIM output waveform, Continuous counting mode configuration . . . . .872
Figure 293. Waveform generation . . . . .873
Figure 294. Encoder mode counting sequence . . . . .876
Figure 295. Independent watchdog block diagram . . . . .887
Figure 296. Watchdog block diagram . . . . .897
Figure 297. Window watchdog timing diagram . . . . .898
Figure 298. RTC block diagram . . . . .904
Figure 299. Block diagram . . . . .949
Figure 300. I 2 C-bus protocol . . . . .951
Figure 301. Setup and hold timings . . . . .952
Figure 302. I2C initialization flow . . . . .955
Figure 303. Data reception . . . . .956
Figure 304. Data transmission . . . . .956
Figure 305. Target initialization flow . . . . .960
Figure 306. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .961
Figure 307. Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .962
Figure 308. Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .963
Figure 309. Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .964
Figure 310. Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .965
Figure 311. Transfer bus diagrams for I2C target receiver
(mandatory events only) . . . . .		965
Figure 312. Controller clock generation . . . . .967
Figure 313. Controller initialization flow . . . . .969
Figure 314. 10-bit address read access with HEAD10R = 0 . . . . .969
Figure 315. 10-bit address read access with HEAD10R = 1 . . . . .970
Figure 316. Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .971
Figure 317. Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .972
Figure 318. Transfer bus diagrams for I2C controller transmitter
(mandatory events only) . . . . .		973
Figure 319. Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .975
Figure 320. Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .976
Figure 321. Transfer bus diagrams for I2C controller receiver
(mandatory events only) . . . . .		977
Figure 322. Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . .981
Figure 323. Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .985
Figure 324. Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . .985
Figure 325. Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .987
Figure 326. Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .988
Figure 327. Bus transfer diagrams for SMBus controller transmitter . . . . .989
Figure 328. Bus transfer diagrams for SMBus controller receiver . . . . .991
Figure 329. USART block diagram . . . . .1014
Figure 330. Word length programming . . . . .1016
Figure 331. Configurable stop bits . . . . .1018
Figure 332. TC/TXE behavior when transmitting . . . . .1019
Figure 333. Start bit detection when oversampling by 16 or 8. . . . .1020
Figure 334. Data sampling when oversampling by 16. . . . .1023
Figure 335. Data sampling when oversampling by 8. . . . .1024
Figure 336. Mute mode using Idle line detection . . . . .1031
Figure 337. Mute mode using address mark detection . . . . .1032
Figure 338. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .1035
Figure 339. Break detection in LIN mode vs. Framing error detection. . . . .1036
Figure 340. USART example of synchronous transmission. . . . .1037
Figure 341. USART data clock timing diagram (M bits = 00). . . . .1037
Figure 342. USART data clock timing diagram (M bits = 01) . . . . .1038
Figure 343. RX data setup/hold time . . . . .1038
Figure 344. ISO 7816-3 asynchronous protocol . . . . .1040
Figure 345. Parity error detection using the 1.5 stop bits . . . . .1041
Figure 346. IrDA SIR ENDEC- block diagram . . . . .1045
Figure 347. IrDA data modulation (3/16) - normal mode . . . . .1045
Figure 348. Transmission using DMA . . . . .1047
Figure 349. Reception using DMA . . . . .1048
Figure 350. Hardware flow control between 2 USARTs . . . . .1048
Figure 351. RS232 RTS flow control . . . . .1049
Figure 352. RS232 CTS flow control . . . . .1050
Figure 353. USART interrupt mapping diagram . . . . .1052
Figure 354. SPI block diagram. . . . .1076
Figure 355. Full-duplex single master/ single slave application. . . . .1077
Figure 356. Half-duplex single master/ single slave application . . . . .1078
Figure 357. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		1079
Figure 358. Master and three independent slaves. . . . .1080
Figure 359. Multimaster application. . . . .1081
Figure 360. Hardware/software slave select management . . . . .1082
Figure 361. Data clock timing diagram . . . . .1083
Figure 362. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .1084
Figure 363. Packing data in FIFO for transmission and reception. . . . .1088
Figure 364. Master full-duplex communication . . . . .1091
Figure 365. Slave full-duplex communication . . . . .1092
Figure 366. Master full-duplex communication with CRC . . . . .1093
Figure 367. Master full-duplex communication in packed mode . . . . .1094
Figure 368. NSSP pulse generation in Motorola SPI master mode. . . . .1097
Figure 369. TI mode transfer . . . . .1098
Figure 370. I2S block diagram . . . . .1101
Figure 371. Full-duplex communication. . . . .1103
Figure 372. I 2 S Philips protocol waveforms (16/32-bit full accuracy). . . . .1104
Figure 373. I 2 S Philips standard waveforms (24-bit frame) . . . . .1104
Figure 374. Transmitting 0x8EAA33 . . . . .1105
Figure 375. Receiving 0x8EAA33 . . . . .1105
Figure 376. I 2 S Philips standard (16-bit extended to 32-bit packet frame) . . . . .1105
Figure 377. Example of 16-bit data frame extended to 32-bit channel frame . . . . .1105
Figure 378. MSB Justified 16-bit or 32-bit full-accuracy length . . . . .1106
Figure 379. MSB justified 24-bit frame length . . . . .1106
Figure 380. MSB justified 16-bit extended to 32-bit packet frame . . . . .1107
Figure 381. LSB justified 16-bit or 32-bit full-accuracy . . . . .1107
Figure 382. LSB justified 24-bit frame length. . . . .1107
Figure 383. Operations required to transmit 0x3478AE. . . . .1108
Figure 384. Operations required to receive 0x3478AE . . . . .1108
Figure 385. LSB justified 16-bit extended to 32-bit packet frame . . . . .1108
Figure 386. Example of 16-bit data frame extended to 32-bit channel frame . . . . .1109
Figure 387. PCM standard waveforms (16-bit) . . . . .1109
Figure 388. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .1110
Figure 389. Start sequence in master mode . . . . .1111
Figure 390. Audio sampling frequency definition . . . . .1112
Figure 391. I 2 S clock generator architecture . . . . .1112
Figure 392. SAI functional block diagram . . . . .1135
Figure 393. Audio frame . . . . .1139
Figure 394. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .1141
Figure 395. FS role is start of frame (FSDEF = 0). . . . .1142
Figure 396. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .1143
Figure 397. First bit offset . . . . .1143
Figure 398. Audio block clock generator overview . . . . .1144
Figure 399. AC'97 audio frame . . . . .1148
Figure 400. Example of typical AC'97 configuration on devices featuring at least
two embedded SAIs (three external AC'97 decoders) . . . . .		1149
Figure 401. SPDIF format . . . . .1150
Figure 402. SAI_xDR register ordering . . . . .1151
Figure 403. Data companding hardware in an audio block in the SAI . . . . .1154
Figure 404. Tristate strategy on SD output line on an inactive slot . . . . .1156
Figure 405. Tristate on output data line in a protocol like I2S . . . . .1157
Figure 406. Overrun detection error . . . . .1158
Figure 407. FIFO underrun event . . . . .1158
Figure 408. SPDIFRX block diagram . . . . .1189
Figure 409. S/PDIF sub-frame format . . . . .1190
Figure 410. S/PDIF block format . . . . .1190
Figure 411. S/PDIF Preambles . . . . .1191
Figure 412. Channel coding example . . . . .1191
Figure 413. SPDIFRX decoder . . . . .1192
Figure 414. Noise filtering and edge detection . . . . .1193
Figure 415. Thresholds . . . . .1194
Figure 416. Synchronization flowchart . . . . .1196
Figure 417. Synchronization process scheduling . . . . .1197
Figure 418. SPDIFRX States . . . . .1198
Figure 419. SPDIFRX_FMTx_DR register format . . . . .1200
Figure 420. Channel/user data format . . . . .1201
Figure 421. S/PDIF overrun error when RXSTEO = 0 . . . . .1203
Figure 422. S/PDIF overrun error when RXSTEO = 1 . . . . .1204
Figure 423. SPDIFRX interface interrupt mapping diagram . . . . .1205
Figure 424. “No response” and “no data” operations . . . . .1220
Figure 425. (Multiple) block read operation . . . . .1220
Figure 426. (Multiple) block write operation . . . . .1220
Figure 427. Sequential read operation . . . . .1221
Figure 428. Sequential write operation . . . . .1221
Figure 429. SDMMC block diagram . . . . .1221
Figure 430. SDMMC adapter . . . . .1223
Figure 431. Control unit . . . . .1224
Figure 432. SDMMC_CK clock dephasing (BYPASS = 0) . . . . .1225
Figure 433. SDMMC adapter command path . . . . .1225
Figure 434. Command path state machine (SDMMC) . . . . .1226
Figure 435. SDMMC command transfer . . . . .1227
Figure 436. Data path . . . . .1229
Figure 437. Data path state machine (DPSM) . . . . .1230
Figure 438. CAN network topology . . . . .1280
Figure 439. Dual-CAN block diagram . . . . .1281
Figure 440. bxCAN operating modes . . . . .1283
Figure 441. bxCAN in silent mode . . . . .1284
Figure 442. bxCAN in Loop back mode . . . . .1284
Figure 443. bxCAN in combined mode . . . . .1285
Figure 444. Transmit mailbox states . . . . .1287
Figure 445. Receive FIFO states . . . . .1288
Figure 446. Filter bank scale configuration - Register organization . . . . .1290
Figure 447. Example of filter numbering . . . . .1291
Figure 448. Filtering mechanism example . . . . .1292
Figure 449. CAN error state diagram . . . . .1294
Figure 450. Bit timing . . . . .1296
Figure 451. CAN frames . . . . .1297
Figure 452. Event flags and interrupt generation . . . . .1298
Figure 453. CAN mailbox registers . . . . .1310
Figure 454. OTG_FS full-speed block diagram . . . . .1328
Figure 455. OTG_HS high-speed block diagram . . . . .1329
Figure 456. OTG_FS/OTG_HS A-B device connection . . . . .1332
Figure 457. OTG_FS/OTG_HS peripheral-only connection . . . . .1334
Figure 458. OTG_FS/OTG_HS host-only connection . . . . .1338
Figure 459. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . .1342
Figure 460. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .1344
Figure 461. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .1345
Figure 462. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . .1346
Figure 463. Interrupt hierarchy . . . . .1350
Figure 464. Transmit FIFO write task . . . . .1456
Figure 465. Receive FIFO read task . . . . .1457
Figure 466. Normal bulk/control OUT/SETUP . . . . .1459
Figure 467. Bulk/control IN transactions . . . . .1463
Figure 468. Normal interrupt OUT . . . . .1466
Figure 469. Normal interrupt IN . . . . .1471
Figure 470. Isochronous OUT transactions . . . . .1473
Figure 471. Isochronous IN transactions . . . . .1476
Figure 472. Normal bulk/control OUT/SETUP transactions - DMA . . . . .1478
Figure 473. Normal bulk/control IN transaction - DMA . . . . .1480
Figure 474. Normal interrupt OUT transactions - DMA mode . . . . .1481
Figure 475. Normal interrupt IN transactions - DMA mode . . . . .1482
Figure 476. Normal isochronous OUT transaction - DMA mode . . . . .1483
Figure 477. Normal isochronous IN transactions - DMA mode . . . . .1484
Figure 478. Receive FIFO packet read . . . . .1490
Figure 479. Processing a SETUP packet . . . . .1492
Figure 480. Bulk OUT transaction . . . . .1499
Figure 481. TRDT max timing case . . . . .1509
Figure 482. A-device SRP . . . . .1510
Figure 483. B-device SRP . . . . .1511
Figure 484. A-device HNP . . . . .1512
Figure 485. B-device HNP . . . . .1514
Figure 486. ETH block diagram . . . . .1520
Figure 487. SMI interface signals . . . . .1521
Figure 488. MDIO timing and frame structure - Write cycle . . . . .1522
Figure 489. MDIO timing and frame structure - Read cycle . . . . .1523
Figure 490. Media independent interface signals . . . . .1524
Figure 491. MII clock sources . . . . .1526
Figure 492. Reduced media-independent interface signals . . . . .1526
Figure 493. RMII clock sources- . . . . .1527
Figure 494. Clock scheme . . . . .1527
Figure 495. Address field format . . . . .1529
Figure 496. MAC frame format . . . . .1531
Figure 497. Tagged MAC frame format . . . . .1531
Figure 498. Transmission bit order . . . . .1538
Figure 499. Transmission with no collision . . . . .1538
Figure 500. Transmission with collision . . . . .1539
Figure 501. Frame transmission in MMI and RMII modes . . . . .1539
Figure 502. Receive bit order . . . . .1543
Figure 503. Reception with no error . . . . .1544
Figure 504. Reception with errors . . . . .1544
Figure 505. Reception with false carrier indication . . . . .1544
Figure 506. MAC core interrupt masking scheme . . . . .1545
Figure 507. Wakeup frame filter register . . . . .1550
Figure 508. Networked time synchronization . . . . .1553
Figure 509. System time update using the Fine correction method. . . . .1555
Figure 510. PTP trigger output to TIM2 ITR1 connection . . . . .1557
Figure 511. PPS output . . . . .1558
Figure 512. Descriptor ring and chain structure. . . . .1559
Figure 513. TxDMA operation in default mode . . . . .1563
Figure 514. TxDMA operation in OSF mode . . . . .1565
Figure 515. Normal transmit descriptor . . . . .1566
Figure 516. Enhanced transmit descriptor . . . . .1572
Figure 517. Receive DMA operation . . . . .1574
Figure 518. Normal Rx DMA descriptor structure . . . . .1576
Figure 519. Enhanced receive descriptor field format with IEEE1588 time stamp enabled. . . . .1582
Figure 520. Interrupt scheme. . . . .1585
Figure 521. Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR). . . . .1596
Figure 522. HDMI-CEC block diagram . . . . .1639
Figure 523. Message structure . . . . .1640
Figure 524. Blocks . . . . .1640
Figure 525. Bit timings . . . . .1641
Figure 526. Signal free time. . . . .1641
Figure 527. Arbitration phase. . . . .1642
Figure 528. SFT of three nominal bit periods. . . . .1642
Figure 529. Error bit timing . . . . .1643
Figure 530. Error handling . . . . .1644
Figure 531. TXERR detection . . . . .1646
Figure 532. Block diagram of STM32 MCU and Cortex ® -M7 with FPU -level
debug support . . . . .		1656
Figure 533. SWJ debug port . . . . .1658
Figure 534. JTAG Debug Port connections . . . . .1662
Figure 535. TPIU block diagram . . . . .1682

Chapters