26. Revision history

Table 152. Document revision history

DateVersionChanges
24-July-20141Initial version
15-Sep-20172Added:
– Section 5.3: Low-power modes
– Exiting low-power mode
– Table 63: Minimum and maximum timeout values at 30 MHz (fPCLK1)
– Table 132: TRDT values
Updated:
– Table 8: Option byte organization
– Table 14: Low-power mode summary
– Section 4.2: CRC main features
– Section 5.4.1: PWR power control register (PWR_CR)
– Entering Sleep mode, Exiting Sleep mode
– Table 15: Sleep-now entry and exit
– Table 16: Sleep-on-exit entry and exit
– Entering Stop mode
– Exiting Stop mode
– Entering Standby mode, Exiting Standby mode
– Section 8.3.6: GPIO locking mechanism
– Section 8.4.1: GPIO port mode register (GPIOx_MODER) (x = A..E and H)
– Section 11.12.7: ADC watchdog higher threshold register (ADC_HTR)
– Section 11.12.8: ADC watchdog lower threshold register (ADC_LTR)
– Section 12.4.12: TIM1 auto-reload register (TIMx_ARR)
– Section 13.4.10: TIMx counter (TIMx_CNT)
– Section 13.4.10: TIMx counter (TIMx_CNT)
– Section 13.4.11: TIMx prescaler (TIMx_PSC)
– Section 13.4.12: TIMx auto-reload register (TIMx_ARR)
– Section 13.4.15: TIMx capture/compare register 3 (TIMx_CCR3)
– Section 14.4.5: TIM9 event generation register (TIMx_EGR)
– Section 16.4: How to program the watchdog timeout
– Section 23.15.4: ETM configuration example
– Section 23.16.2: Debug support for timers, watchdog and I2C
– Table 18: Stop mode entry and exit
– Table 19: Standby mode entry and exit
– Table 53: TIMx internal trigger connection
– Table 53: TIMx internal trigger connection
– Figure 157: Watchdog block diagram
30-Nov-20183Updated:
– Section 9.3.4: Arbiter
– Section 22: USB on-the-go full-speed (OTG_FS)

Table 152. Document revision history (continued)

DateVersionChanges
13-May-20254

Cover page:
Updated Section : Related documents .

Memory and bus architecture:
Updated Table 3: Memory mapping vs. Boot mode/physical remap in STM32F411xC/E .
Updated Section : Related documents .

Embedded Flash memory interface:
Updated Table 6: Maximum program/erase parallelism .
Updated Section 3.6.3: Read protection (RDP) .

PWR:
Updated Section 5.1.2: Battery backup domain .
Updated Bits DBP for Section 5.4.1: PWR power control register (PWR_CR) .
Updated Bits BRE and BRR for Section 5.4.2: PWR power control/status register (PWR_CSR) .

RCC:
Updated Section 6.1.1: System reset .
Updated Section 6.1.3: Backup domain reset .
Updated Bit ADC1EN for Section 6.3.12: RCC APB2 peripheral clock enable register (RCC_APB2ENR) .
Updated Bit LSEBYP for Section 6.3.17: RCC Backup domain control register (RCC_BDCR) .

GPIO:
Updated Section 8.3.2: I/O pin multiplexer and mapping .
Updated Table 25: RTC additional functions .

GPIO:
Updated address offset for Section 9.5.10: DMA stream x FIFO control register (DMA_SxFCCR) (x = 0..7) .

Interrupts and events:
Updated reset value for Section 10.3.6: Pending register (EXTI_PR) .

ADC:
Updated Section 11.3.3: Channel selection .
Updated Section 11.9: Temperature sensor .

TIM1:
Updated Section 12.3.7: PWM input mode .
Updated Bits SMS for Section 12.4.3: TIM1 slave mode control register (TIMx_SMCR) .
Updated Bit OC1PE for Section 12.4.7: TIM1 capture/compare mode register 1 (TIMx_CCMR1) .
Added Bit CC4NP for Section 12.4.9: TIM1 capture/compare enable register (TIMx_CCER) .

TIM2 to TIM5:
Updated Section 13.3.6: PWM input mode .
Updated Bits SMS for Section 13.4.3: TIMx slave mode control register (TIMx_SMCR) .
Updated Bit OC1PE for Section 13.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1) .

TIM9 to TIM11:
Updated Section 14.3.6: PWM input mode (only for TIM9) .
Updated Bit OC1PE for Section 14.4.6: TIM9 capture/compare mode register 1 (TIMx_CCMR1) .

Table 152. Document revision history (continued)

DateVersionChanges
13-May-2025
(continued)		4TIM9 to TIM11:
Updated Bit 0C1PE for Section 14.5.5: TIM10/11 capture/compare mode register 1 (TIMx_CCMR1) .
RTC:
Updated Section 17.3.6: Reading the calendar .
I2C:
Master and slave terms in Section 18: Inter-integrated circuit (I2C) interface replaced with controller and target, respectively.
Updated Section 18.6.2: I 2 C Control register 2 (I2C_CR2) .
Updated Section 18.6.8: I 2 C Clock control register (I2C_CCR) .
USART:
Updated Figure 179: USART data clock timing diagram (M=0) .
SPI:
Updated Figure 179: USART data clock timing diagram (M=0) .
Updated Section 20.1: SPI introduction .
Updated Figure 200: TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in case of continuous transfers .
SDIO:
Updated Section 21.9.2: SDI clock control register (SDIO_CLKCR) .
OTG_FS:
Updated Figure 248: Device-mode FIFO address mapping and AHB FIFO access mapping .
Updated Figure 249: Host-mode FIFO address mapping and AHB FIFO access mapping .
Updated Table 129: Device-mode control and status registers .
DBG:
Updated Section 23.4.2: Flexible SWJ-DP pin assignment .
Updated Section 23.15.4: ETM configuration example .
Important security notice:
Added Section 25: Important security notice .