2. System and memory overview

2.1 System architecture

The main system consists of:

• • Two masters:
  • – Cortex ^® -M0+ core (AHB-lite bus)
  • – GP-DMA (general-purpose DMA)
• • Three slaves:
  • – Internal SRAM
  • – Internal Non-volatile memory
  • – AHB to APB, which connects all the APB peripherals

These are interconnected using a multilayer AHB bus architecture as shown in Figure 1 :

Figure 1. System architecture

1. 1. Refer to Table 1: STM32L0x1 memory density , to Table 2: Overview of features per category and to the device datasheets for the GPIO ports and peripherals available on your device.

2.1.1 S0: Cortex ^® -bus

This bus connects the DCode/ICode bus of the Cortex ^® -M0+ core to the BusMatrix. This bus is used by the core to fetch instructions, get data and access the AHB/APB resources.

2.1.2 S1: DMA-bus

This bus connects the AHB master interface of the DMA to the BusMatrix which manages the access of the different masters to Flash memory and data EEPROM, the SRAM and the AHB/APB peripherals.

2.1.3 BusMatrix

The BusMatrix manages the access arbitration between masters. The arbitration uses a Round Robin algorithm. The BusMatrix is composed of two masters (CPU, DMA) and three slaves (NVM interface, SRAM, AHB2APB1/2 bridges).

AHB/APB bridges

The AHB/APB bridge provide full synchronous connections between the AHB and the 2 APB buses. APB1 and APB2 operate at a maximum frequency of 32 MHz.

Refer to Section 2.2.2: Memory map and register boundary addresses on page 52 for the address mapping of the peripherals connected to this bridge.

After each device reset, all peripheral clocks are disabled (except for the SRAM and MIF). Before using a peripheral you have to enable its clock in the RCC_AHBENR, RCC_APB2ENR, RCC_APB1ENR or RCC_IOPENR register.

Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

2.2 Memory organization

2.2.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant.

The addressable memory space is divided into eight main blocks, of 512 Mbytes each.

2.2.2 Memory map and register boundary addresses

Figure 2. Memory map

All the memory map areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to the following table.

The following table gives the boundary addresses of the peripherals available in the devices.

Table 3. STM32L0x1 peripheral register boundary addresses ⁽¹⁾

1. 1. Refer to Table 1: STM32L0x1 memory density , to Table 2: Overview of features per category and to the device datasheets for the GPIO ports and peripherals available on your device. The memory area corresponding to unavailable GPIO ports or peripherals are reserved.

2.3 Embedded SRAM

STM32L0x1 devices feature up to 20 Kbytes of static SRAM.

This RAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). This memory can be addressed at maximum system clock frequency without wait state and thus by both CPU and DMA.

The SRAM start address is 0x2000 0000.

The CPU can access the SRAM from address 0x0000 0000 when physical remap is selected through boot pin or MEM_MODE (see Section 9.2.1: SYSCFG memory remap register (SYSCFG_CFGR1) ).

2.4 Boot configuration

In the STM32L0x1, three different boot modes can be selected through the BOOT0 pin and boot configuration bits in the User option byte, as shown in the following table.

1. 1. Grayed options are available on category 1 devices only.

The boot mode configuration is latched on the 2nd rising edge of SYSCLK after reset. For category 1 devices, the value present on BOOT0 pin is latched on NRST rising edge. It is up to the user to set nBOOT1 and BOOT0 to select the required boot mode.

The boot mode configuration is also re-sampled when exiting from Standby mode, except for category 1 devices where BOOT0 pin is latched on NRST rising edge. Consequently the boot mode configuration must not be modified in Standby mode (except for category 1 devices). After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.

Depending on the selected boot mode, Flash program memory, system memory or SRAM is accessible as follows:

• • Boot from Flash program memory: the Flash program memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x0800 0000). In other words, the Flash memory contents can be accessed starting from address 0x0000 0000 or 0x0800 0000.
• • Boot from system memory: the system memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x1FF0 0000).
• • Boot from the embedded SRAM: the SRAM is aliased in the boot memory space (0x0000 0000), but it is still accessible from its original memory space (0x2000 0000).

BOOT0/GPIO pin sharing (category 1 devices only)

On category 1 devices, the BOOT0 pin is shared with a GPIO pin. The pin state is latched on NRST rising edge as BOOT0 state. The pin logic level can then be read as an input value on the shared GPIO pin. This pin feature specific input voltage characteristics (refer to the corresponding datasheets for details).

Empty check (category 1 devices only)

On category 1 devices, an internal empty check flag is implemented to allow easy programming of virgin devices by the bootloader. This flag is used when BOOT0 pin is configured to select Flash program memory as target boot area. When this flag is set, the device is considered as unprogrammed and the system memory (bootloader) is selected as boot area instead of the Flash program memory to allow the application to program the Flash memory.

The empty check flag is updated only when the option bytes are loaded: it is set when the content of address 0x0800 0000 is read as 0x0000 0000 and cleared otherwise. As a result, only a power-on reset or setting OBL_LAUNCH bit in FLASH_CR register can clear this flag after programming a virgin device to execute user code after system reset.

Note: If the device is programmed for the first time but the option bytes are not reloaded, the system memory will still be selected as boot area after system reset. In this case, the bootloader code switches the boot memory mapping to Flash program memory and performs a jump to the user code it hosts.

Bank swapping (category 5 devices only)

For devices featuring two banks, the bank swapping mechanism allows the CPU to point either to bank1 or to bank 2 in the boot memory space (0x0000 0000). Either Flash program and data EEPROM address are changed (see Table 10: NVM organization for UFB = 0 (128 Kbyte category 5 devices) , Table 12: NVM organization for UFB = 0 (64 Kbyte category 5 devices) ).

Physical remap

Once the boot pin and bit are selected, the application software can modify the memory accessible in the code area. This modification is performed by programming the MEM_MODE bits in the SYSCFG memory remap register (SYSCFG_CFGR1).

Embedded bootloader

The embedded bootloader is located in the System memory, programmed by ST during production. It is used to reprogram the Flash memory using one of the following serial interfaces:

• • For category 1 devices: USART2 or SPI1.
• • For category 2 devices: USART2 or SPI1.
• • For category 3 devices: USART1, USART2, SPI1 or SPI2
• • For category 5 devices: USART1, USART2, SPI1, SPI2, I2C1 or I2C2.

For details concerning the bootloader serial interface corresponding I/O, refer to your device datasheet.

For further details on STM32 bootloader, please refer to AN2606.