RM0377-STM32L0x1

Introduction

This reference manual targets application developers. It provides complete information on how to use the STM32L0x1 microcontroller memory and peripherals.

The STM32L0x1 is a line of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the corresponding datasheets.

For information on the Arm ® Cortex ® -M0+ core, refer to the Cortex ® -M0+ Technical Reference Manual .

The STM32L0x1 microcontrollers include state-of-the-art patented technology.

Contents

3.3.4Writing/erasing the NVM . . . . .75
Write/erase protocol . . . . .75
Unlocking/locking operations . . . . .76
Detailed description of NVM write/erase operations. . . . .79
Parallel write half-page Flash program memory. . . . .85
Status register . . . . .89
3.4Memory protection . . . . .90
3.4.1RDP (Read Out Protection) . . . . .91
3.4.2PcROP (Proprietary Code Read-Out Protection) . . . . .92
3.4.3Protections against unwanted write/erase operations . . . . .94
3.4.4Write/erase protection management . . . . .95
3.4.5Protection errors . . . . .96
Write protection error flag (WRPERR) . . . . .96
Read error (RDERR) . . . . .96
3.5NVM interrupts . . . . .96
3.5.1Hard fault . . . . .97
3.6Memory interface management . . . . .97
3.6.1Operation priority and evolution . . . . .97
Read . . . . .97
Write/erase . . . . .97
Option byte loading. . . . .98
3.6.2Sequence of operations . . . . .98
Read as data while write . . . . .98
Fetch while write. . . . .98
Write while another write operation is ongoing. . . . .99
3.6.3Change the number of wait states while reading . . . . .99
3.6.4Power-down . . . . .99
3.7Flash register description . . . . .100
Read registers . . . . .100
Write to registers . . . . .100
3.7.1Access control register (FLASH_ACR) . . . . .101
3.7.2Program and erase control register (FLASH_PECR) . . . . .102
3.7.3Power-down key register (FLASH_PDKEYR) . . . . .106
3.7.4PECR unlock key register (FLASH_PEKEYR) . . . . .106
3.7.5Program and erase key register (FLASH_PRGKEYR) . . . . .106
3.7.6Option bytes unlock key register (FLASH_OPTKEYR) . . . . .107
3.7.7Status register (FLASH_SR) . . . . .108
3.7.8Option bytes register (FLASH_OPTR) . . . . .110

4 Cyclic redundancy check calculation unit (CRC) . . . . . 117

5 Firewall (FW) . . . . . 124

5.3.4Segment accesses and properties . . . . .127
Segment access depending on the Firewall state . . . . .127
Segments properties . . . . .128
5.3.5Firewall initialization . . . . .128
5.3.6Firewall states . . . . .129
Opening the Firewall . . . . .130
Closing the Firewall . . . . .130
5.4Firewall registers . . . . .131
5.4.1Code segment start address (FW_CSSA) . . . . .131
5.4.2Code segment length (FW_CSL) . . . . .131
5.4.3Non-volatile data segment start address (FW_NVDSSA) . . . . .132
5.4.4Non-volatile data segment length (FW_NVDLSL) . . . . .132
5.4.5Volatile data segment start address (FW_VDSSA) . . . . .133
5.4.6Volatile data segment length (FW_VDSL) . . . . .133
5.4.7Configuration register (FW_CR) . . . . .134
5.4.8Firewall register map . . . . .135
6Power control (PWR) . . . . .136
6.1Power supplies . . . . .136
6.1.1Independent A/D converter supply and reference voltage . . . . .137
On packages with V REF+ pin . . . . .137
On packages without V REF+ pin . . . . .137
6.1.2RTC and RTC backup registers . . . . .138
RTC registers access . . . . .138
6.1.3Voltage regulator . . . . .138
6.1.4Dynamic voltage scaling management . . . . .138
Range 1 . . . . .139
Range 2 and 3 . . . . .139
6.1.5Dynamic voltage scaling configuration . . . . .140
6.1.6Voltage regulator and clock management when VDD drops
below 1.71 V . . . . .		140
6.1.7Voltage regulator and clock management when modifying the
VCORE range . . . . .		141
6.1.8Voltage range and limitations when VDD ranges from 1.71 V to 2.0 V141
6.2Power supply supervisor . . . . .142
6.2.1Power-on reset (POR)/power-down reset (PDR) . . . . .144
6.2.2Brown out reset (BOR) . . . . .144
6.2.3Programmable voltage detector (PVD) . . . . .145

7 Reset and clock control (RCC) . . . . . 167

7.1Reset . . . . .167
7.1.1System reset . . . . .167
Software reset . . . . .167
Low-power management reset . . . . .167
Option byte loader reset . . . . .167
7.1.2Power reset . . . . .168
7.1.3RTC and backup registers reset . . . . .168
7.2Clocks . . . . .169
7.2.1HSE clock . . . . .172
External source (HSE bypass) . . . . .173
External crystal/ceramic resonator (HSE crystal) . . . . .173
7.2.2HSI16 clock . . . . .174
Calibration . . . . .174
7.2.3MSI clock . . . . .174
Calibration . . . . .175
7.2.4PLL . . . . .175
7.2.5LSE clock . . . . .176
External source (LSE bypass) . . . . .176
7.2.6LSI clock . . . . .176
LSI measurement . . . . .176
7.2.7System clock (SYSCLK) selection . . . . .177
7.2.8System clock source frequency versus voltage range . . . . .177
7.2.9HSE clock security system (CSS) . . . . .177
7.2.10LSE Clock Security System . . . . .178
7.2.11RTC clock . . . . .178
7.2.12Watchdog clock . . . . .179
7.2.13Clock-out capability . . . . .179
7.2.14Internal/external clock measurement using TIM21 . . . . .179
7.2.15Clock-independent system clock sources for TIM2/TIM21/TIM22 . . . . .180
7.3RCC registers . . . . .181
7.3.1Clock control register (RCC_CR) . . . . .181
7.3.2Internal clock sources calibration register (RCC_ICSCR) . . . . .184
7.3.3Clock configuration register (RCC_CFGR) . . . . .185
7.3.4Clock interrupt enable register (RCC_CIER) . . . . .187
7.3.5Clock interrupt flag register (RCC_CIFR) . . . . .189
7.3.6Clock interrupt clear register (RCC_CICR) . . . . .190
7.3.7GPIO reset register (RCC_IOPRSTR) . . . . .191
7.3.8AHB peripheral reset register (RCC_AHBRSTR) . . . . .192
7.3.9APB2 peripheral reset register (RCC_APB2RSTR) . . . . .193
7.3.10APB1 peripheral reset register (RCC_APB1RSTR) . . . . .194
7.3.11GPIO clock enable register (RCC_IOPENR) . . . . .196
7.3.12AHB peripheral clock enable register (RCC_AHBENR) . . . . .198
7.3.13APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .199
7.3.14APB1 peripheral clock enable register (RCC_APB1ENR) . . . . .201
7.3.15GPIO clock enable in Sleep mode register (RCC_IOPSMENR) . . . . .203
7.3.16AHB peripheral clock enable in Sleep mode register (RCC_AHBSMENR) . . . . .204
7.3.17APB2 peripheral clock enable in Sleep mode register (RCC_APB2SMENR) . . . . .205
7.3.18APB1 peripheral clock enable in Sleep mode register (RCC_APB1SMENR) . . . . .206
7.3.19Clock configuration register (RCC_CCIPR) . . . . .208
7.3.20Control/status register (RCC_CSR) . . . . .209
7.3.21RCC register map . . . . .213
8General-purpose I/Os (GPIO) . . . . .216
8.1Introduction . . . . .216
8.2GPIO main features . . . . .216
8.3GPIO functional description . . . . .216
8.3.1General-purpose I/O (GPIO) . . . . .218
8.3.2I/O pin alternate function multiplexer and mapping . . . . .219
8.3.3I/O port control registers . . . . .220
8.3.4I/O port data registers . . . . .220
8.3.5I/O data bitwise handling . . . . .220
8.3.6GPIO locking mechanism . . . . .220
8.3.7I/O alternate function input/output . . . . .221
8.3.8External interrupt/wakeup lines . . . . .221
8.3.9Input configuration . . . . .221
8.3.10Output configuration . . . . .222
8.3.11Alternate function configuration . . . . .223
8.3.12Analog configuration . . . . .224
8.3.13Using the HSE or LSE oscillator pins as GPIOs . . . . .224
8.3.14Using the GPIO pins in the RTC supply domain . . . . .224
8.3.15BOOT0/GPIO pin sharing . . . . .225
8.4GPIO registers . . . . .225
8.4.1GPIO port mode register (GPIOx_MODER)
(x = A to E and H) . . . . .		225
8.4.2GPIO port output type register (GPIOx_OTYPER)
(x = A to E and H) . . . . .		225
8.4.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to E and H) . . . . .		226
8.4.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to E and H) . . . . .		226
8.4.5GPIO port input data register (GPIOx_IDR)
(x = A to E and H) . . . . .		227
8.4.6GPIO port output data register (GPIOx_ODR)
(x = A to E and H) . . . . .		227
8.4.7GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to E and H) . . . . .		228
8.4.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to E and H) . . . . .		228
8.4.9GPIO alternate function low register (GPIOx_AFRL)
(x = A to E and H) . . . . .		229
8.4.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to E and H) . . . . .		230
8.4.11GPIO port bit reset register (GPIOx_BRR) (x = A to E and H) . . . . .230
8.4.12GPIO register map . . . . .231
9System configuration controller (SYSCFG) . . . . .233
9.1Introduction . . . . .233
9.2SYSCFG registers . . . . .234
9.2.1SYSCFG memory remap register (SYSCFG_CFGR1) . . . . .234
9.2.2SYSCFG peripheral mode configuration register (SYSCFG_CFGR2) . . . . .235
9.2.3Reference control and status register (SYSCFG_CFGR3) . . . . .236
9.2.4SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . .		237
9.2.5SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . .		238
9.2.6SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . .		238
9.2.7SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . .		239
9.2.8SYSCFG register map . . . . .239
10Direct memory access controller (DMA) . . . . .241
10.1Introduction . . . . .241
12.1Introduction . . . . .268
12.2EXTI main features . . . . .268
12.3EXTI functional description . . . . .268
12.3.1EXTI block diagram . . . . .269
12.3.2Wakeup event management . . . . .269
12.3.3Peripherals asynchronous interrupts . . . . .270
12.3.4Hardware interrupt selection . . . . .270
12.3.5Hardware event selection . . . . .270
12.3.6Software interrupt/event selection . . . . .270
12.4EXTI interrupt/event line mapping . . . . .271
12.5EXTI registers . . . . .273
12.5.1EXTI interrupt mask register (EXTI_IMR) . . . . .273
12.5.2EXTI event mask register (EXTI_EMR) . . . . .273
12.5.3EXTI rising edge trigger selection register (EXTI_RTSR) . . . . .274
12.5.4Falling edge trigger selection register (EXTI_FTSR) . . . . .275
12.5.5EXTI software interrupt event register (EXTI_SWIER) . . . . .275
12.5.6EXTI pending register (EXTI_PR) . . . . .276
12.5.7EXTI register map . . . . .277
13Analog-to-digital converter (ADC) . . . . .278
13.1Introduction . . . . .278
13.2ADC main features . . . . .279
13.3ADC functional description . . . . .280
13.3.1ADC pins and internal signals . . . . .280
13.3.2ADC voltage regulator (ADVREGEN) . . . . .281
Analog reference for the ADC internal voltage regulator . . . . .281
ADVREG enable sequence . . . . .282
ADVREG disable sequence . . . . .282
13.3.3Calibration (ADCAL) . . . . .282
Calibration factor forcing software procedure . . . . .284
13.3.4ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .284
13.3.5ADC clock (CKMODE, PRESC[3:0], LFMEN) . . . . .285
Low frequency . . . . .286
13.3.6ADC connectivity . . . . .287
13.3.7Configuring the ADC . . . . .288
13.3.8Channel selection (CHSEL, SCANDIR) . . . . .288
Temperature sensor, V REFINT internal channels . . . . .288
13.3.9Programmable sampling time (SMP) . . . . .289
13.3.10Single conversion mode (CONT = 0) . . . . .289
13.3.11Continuous conversion mode (CONT = 1) . . . . .290
13.3.12Starting conversions (ADSTART) . . . . .290
13.3.13Timings . . . . .291
13.3.14Stopping an ongoing conversion (ADSTP) . . . . .292
13.4Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . . . . .292
13.4.1Discontinuous mode (DISCEN) . . . . .293
13.4.2Programmable resolution (RES) - Fast conversion mode . . . . .293
13.4.3End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . .294
13.4.4End of conversion sequence (EOS flag) . . . . .294
13.4.5Example timing diagrams (single/continuous modes
hardware/software triggers) . . . . .		295
13.5Data management . . . . .297
13.5.1Data register and data alignment (ADC_DR, ALIGN) . . . . .297
13.5.2ADC overrun (OVR, OVRMOD) . . . . .297
13.5.3Managing a sequence of data converted without using the DMA . . . . .298
13.5.4Managing converted data without using the DMA without overrun . . . . .298
13.5.5Managing converted data using the DMA . . . . .298
DMA one shot mode (DMACFG = 0) . . . . .299
DMA circular mode (DMACFG = 1) . . . . .299
13.6Low-power features . . . . .300
13.6.1Wait mode conversion . . . . .300
13.6.2Auto-off mode (AUTOFF) . . . . .301
13.7Analog window watchdog (AWDEN, AWDSGL, AWDCH,
ADC_TR) . . . . .		302
13.7.1Description of the analog watchdog . . . . .302
13.7.2ADC_AWD1_OUT output signal generation . . . . .303
13.7.3Analog watchdog threshold control . . . . .305
13.8Oversampler . . . . .306
13.8.1ADC operating modes supported when oversampling . . . . .308
13.8.2Analog watchdog . . . . .308
13.8.3Triggered mode . . . . .308
13.9Temperature sensor and internal reference voltage . . . . .309
Main features . . . . .310
Reading the temperature . . . . .310
Calculating the actual V DDA voltage using the internal reference voltage . . . . .311
Converting a supply-relative ADC measurement to an absolute voltage value . . . . .311
13.10ADC interrupts . . . . .312
13.11ADC registers . . . . .313
13.11.1ADC interrupt and status register (ADC_ISR) . . . . .313
13.11.2ADC interrupt enable register (ADC_IER) . . . . .314
13.11.3ADC control register (ADC_CR) . . . . .316
13.11.4ADC configuration register 1 (ADC_CFGR1) . . . . .318
13.11.5ADC configuration register 2 (ADC_CFGR2) . . . . .322
13.11.6ADC sampling time register (ADC_SMPR) . . . . .323
13.11.7ADC watchdog threshold register (ADC_TR) . . . . .324
13.11.8ADC channel selection register (ADC_CHSELR) . . . . .324
13.11.9ADC data register (ADC_DR) . . . . .325
13.11.10ADC Calibration factor (ADC_CALFACT) . . . . .325
13.11.11ADC common configuration register (ADC_CCR) . . . . .326
13.12ADC register map . . . . .327
14Comparator (COMP) . . . . .329
14.1Introduction . . . . .329
14.2COMP main features . . . . .329
14.3COMP functional description . . . . .330
14.3.1COMP block diagram . . . . .330
14.3.2COMP pins and internal signals . . . . .330
14.3.3COMP reset and clocks . . . . .331
14.3.4Comparator LOCK mechanism . . . . .331
14.3.5Power mode . . . . .331
14.4COMP interrupts . . . . .331
14.5COMP registers . . . . .331
14.5.1Comparator 1 control and status register (COMP1_CSR) . . . . .331
14.5.2Comparator 2 control and status register (COMP2_CSR) . . . . .333
14.5.3COMP register map . . . . .336
15AES hardware accelerator (AES) . . . . .337
15.1Introduction . . . . .337
15.2AES main features . . . . .337
15.3AES implementation . . . . .338
15.4AES functional description . . . . .338
15.4.1AES block diagram . . . . .338
15.4.2AES internal signals . . . . .338
15.4.3AES cryptographic core . . . . .339
Overview. . . . .339
Typical data processing . . . . .339
Chaining modes . . . . .339
Electronic codebook (ECB) mode . . . . .340
Cipher block chaining (CBC) mode . . . . .341
Counter (CTR) mode . . . . .342
15.4.4AES procedure to perform a cipher operation . . . . .342
Introduction. . . . .342
Initialization of AES. . . . .343
Data append . . . . .343
15.4.5AES decryption key preparation . . . . .345
15.4.6AES ciphertext stealing and data padding . . . . .346
15.4.7AES task suspend and resume . . . . .346
15.4.8AES basic chaining modes (ECB, CBC) . . . . .347
Overview. . . . .347
ECB/CBC encryption sequence . . . . .350
ECB/CBC decryption sequence . . . . .350
Suspend/resume operations in ECB/CBC modes . . . . .351
Alternative single ECB/CBC decryption using Mode 4 . . . . .352
15.4.9AES counter (CTR) mode . . . . .352
Overview. . . . .352
CTR encryption and decryption . . . . .353
Suspend/resume operations in CTR mode . . . . .355
15.4.10AES data registers and data swapping . . . . .355
Data input and output . . . . .355
Data swapping . . . . .355
Data padding . . . . .357
15.4.11AES key registers . . . . .357
15.4.12AES initialization vector registers . . . . .357
15.4.13AES DMA interface . . . . .357
Data input using DMA. . . . .358
Data output using DMA . . . . .358
DMA operation in different operating modes . . . . .359
15.4.14AES error management . . . . .360
Read error flag (RDERR) . . . . .360
Write error flag (WDERR). . . . .360
15.5AES interrupts . . . . .360
15.6AES processing latency . . . . .361
15.7AES registers . . . . .362
15.7.1AES control register (AES_CR) . . . . .362
15.7.2AES status register (AES_SR) . . . . .364
15.7.3AES data input register (AES_DINR) . . . . .365
15.7.4AES data output register (AES_DOUTR) . . . . .365
15.7.5AES key register 0 (AES_KEYR0) . . . . .366
15.7.6AES key register 1 (AES_KEYR1) . . . . .367
15.7.7AES key register 2 (AES_KEYR2) . . . . .367
15.7.8AES key register 3 (AES_KEYR3) . . . . .367
15.7.9AES initialization vector register 0 (AES_IVR0) . . . . .368
15.7.10AES initialization vector register 1 (AES_IVR1) . . . . .368
15.7.11AES initialization vector register 2 (AES_IVR2) . . . . .369
15.7.12AES initialization vector register 3 (AES_IVR3) . . . . .369
15.7.13AES register map . . . . .369
16General-purpose timers (TIM2/TIM3) . . . . .371
16.1TIM2/TIM3 introduction . . . . .371
16.2TIM2/TIM3 main features . . . . .371
16.3TIM2/TIM3 functional description . . . . .373
16.3.1Time-base unit . . . . .373
Prescaler description . . . . .373
16.3.2Counter modes . . . . .375
Upcounting mode . . . . .375
Downcounting mode . . . . .378
Center-aligned mode (up/down counting) . . . . .381
16.3.3Clock selection . . . . .385
Internal clock source (CK_INT) . . . . .385
External clock source mode 1 . . . . .386
External clock source mode 2 . . . . .388
16.3.4Capture/compare channels . . . . .389
16.3.5Input capture mode . . . . .391
16.3.6PWM input mode . . . . .393
16.3.7Forced output mode . . . . .394
16.3.8Output compare mode . . . . .394
16.3.9PWM mode . . . . .395
PWM edge-aligned mode . . . . .396
Downcounting configuration . . . . .397
PWM center-aligned mode . . . . .397
16.3.10One-pulse mode . . . . .399
Particular case: OCx fast enable: . . . . .400
16.3.11Clearing the OCxREF signal on an external event . . . . .400
16.3.12Encoder interface mode . . . . .401
16.3.13Timer input XOR function . . . . .403
16.3.14Timers and external trigger synchronization . . . . .404
Slave mode: Reset mode . . . . .404
Slave mode: Gated mode . . . . .405
Slave mode: Trigger mode . . . . .406
Slave mode: External Clock mode 2 + trigger mode . . . . .407
16.3.15Timer synchronization . . . . .408
Using one timer as prescaler for another timer . . . . .408
Using one timer to enable another timer . . . . .409
Using one timer to start another timer . . . . .411
Starting 2 timers synchronously in response to an external trigger . . . . .413
16.3.16Debug mode . . . . .414
16.4TIM2/TIM3 registers . . . . .415
16.4.1TIMx control register 1 (TIMx_CR1) . . . . .415
16.4.2TIMx control register 2 (TIMx_CR2) . . . . .417
16.4.3TIMx slave mode control register (TIMx_SMCR) . . . . .418
16.4.4TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . .420
16.4.5TIMx status register (TIMx_SR) . . . . .421
16.4.6TIMx event generation register (TIMx_EGR) . . . . .423
16.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . .424
Output compare mode . . . . .424
Input capture mode. . . . .425
16.4.8TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . .427
Output compare mode . . . . .427
Input capture mode. . . . .428
16.4.9TIMx capture/compare enable register (TIMx_CCER) . . . . .428
16.4.10TIMx counter (TIMx_CNT) . . . . .430
16.4.11TIMx prescaler (TIMx_PSC) . . . . .430
16.4.12TIMx auto-reload register (TIMx_ARR) . . . . .430
16.4.13TIMx capture/compare register 1 (TIMx_CCR1) . . . . .431
16.4.14TIMx capture/compare register 2 (TIMx_CCR2) . . . . .431
16.4.15TIMx capture/compare register 3 (TIMx_CCR3) . . . . .432
16.4.16TIMx capture/compare register 4 (TIMx_CCR4) . . . . .432
16.4.17TIMx DMA control register (TIMx_DCR) . . . . .433
16.4.18TIMx DMA address for full transfer (TIMx_DMAR) . . . . .433
Example of how to use the DMA burst feature . . . . .434
16.4.19TIM2 option register (TIM2_OR) . . . . .435
16.4.20TIM3 option register (TIM3_OR) . . . . .436
16.5TIMx register map . . . . .437
17General-purpose timers (TIM21/22) . . . . .439
17.1Introduction . . . . .439
17.2TIM21/22 main features . . . . .439
17.2.1TIM21/22 main features . . . . .439
17.3TIM21/22 functional description . . . . .441
17.3.1Timebase unit . . . . .441
Prescaler description . . . . .441
17.3.2Counter modes . . . . .443
Upcounting mode . . . . .443
Downcounting mode . . . . .447
Center-aligned mode (up/down counting) . . . . .450
17.3.3Clock selection . . . . .454
Internal clock source (CK_INT) . . . . .454
External clock source mode 2 . . . . .456
17.3.4Capture/compare channels . . . . .457
17.3.5Input capture mode . . . . .459
17.3.6PWM input mode . . . . .461
17.3.7Forced output mode . . . . .462
17.3.8Output compare mode . . . . .462
17.3.9PWM mode . . . . .463
PWM center-aligned mode . . . . .465
Hints on using center-aligned mode . . . . .466
17.3.10Clearing the OCxREF signal on an external event . . . . .466
17.3.11One-pulse mode . . . . .467
Particular case: OCx fast enable . . . . .469
17.3.12Encoder interface mode . . . . .469
17.3.13TIM21/22 external trigger synchronization . . . . .471
Slave mode: Reset mode . . . . .471
Slave mode: Gated mode . . . . .472
Slave mode: Trigger mode . . . . .473
17.3.14Timer synchronization (TIM21/22) . . . . .474
17.3.15Debug mode . . . . .474
17.4TIM21/22 registers . . . . .475
17.4.1TIM21/22 control register 1 (TIMx_CR1) . . . . .475
17.4.2TIM21/22 control register 2 (TIMx_CR2) . . . . .477
17.4.3TIM21/22 slave mode control register (TIMx_SMCR) . . . . .478
17.4.4TIM21/22 Interrupt enable register (TIMx_DIER) . . . . .481
17.4.5TIM21/22 status register (TIMx_SR) . . . . .481
17.4.6TIM21/22 event generation register (TIMx_EGR) . . . . .483
17.4.7TIM21/22 capture/compare mode register 1 (TIMx_CCMR1) . . . . .484
Output compare mode . . . . .484
Input capture mode . . . . .486
17.4.8TIM21/22 capture/compare enable register (TIMx_CCER) . . . . .487
17.4.9TIM21/22 counter (TIMx_CNT) . . . . .488
17.4.10TIM21/22 prescaler (TIMx_PSC) . . . . .488
17.4.11TIM21/22 auto-reload register (TIMx_ARR) . . . . .488
17.4.12TIM21/22 capture/compare register 1 (TIMx_CCR1) . . . . .489
17.4.13TIM21/22 capture/compare register 2 (TIMx_CCR2) . . . . .489
17.4.14TIM21 option register (TIM21_OR) . . . . .490
17.4.15TIM22 option register (TIM22_OR) . . . . .491
17.4.16TIM21/22 register map . . . . .492
18Basic timers (TIM6/7) . . . . .494
18.1Introduction . . . . .494
18.2TIM6/7 main features . . . . .494
18.3TIM6/7 functional description . . . . .495
18.3.1Time-base unit . . . . .495
Prescaler description . . . . .495
18.3.2Counting mode . . . . .497
18.3.3Clock source . . . . .500
18.3.4Debug mode . . . . .501
18.4TIM6/7 registers . . . . .502
18.4.1TIM6/7 control register 1 (TIMx_CR1) . . . . .502
18.4.2TIM6/7 control register 2 (TIMx_CR2) . . . . .503
18.4.3TIM6/7 DMA/Interrupt enable register (TIMx_DIER) . . . . .503
18.4.4TIM6/7 status register (TIMx_SR) . . . . .504
18.4.5TIM6/7 event generation register (TIMx_EGR) . . . . .504
18.4.6TIM6/7 counter (TIMx_CNT) . . . . .504
18.4.7TIM6/7 prescaler (TIMx_PSC) . . . . .505
18.4.8TIM6/7 auto-reload register (TIMx_ARR) . . . . .505
18.4.9TIM6/7 register map . . . . .506
19Low-power timer (LPTIM) . . . . .507
19.1Introduction . . . . .507
19.2LPTIM main features . . . . .507
19.3LPTIM implementation . . . . .508
19.4LPTIM functional description . . . . .508
19.4.1LPTIM block diagram . . . . .508
19.4.2LPTIM trigger mapping . . . . .509
19.4.3LPTIM reset and clocks . . . . .509
19.4.4Glitch filter . . . . .509
19.4.5Prescaler . . . . .510
19.4.6Trigger multiplexer . . . . .511
19.4.7Operating mode . . . . .511
One-shot mode . . . . .511
Continous mode . . . . .512
19.4.8Timeout function . . . . .513
19.4.9Waveform generation . . . . .513
19.4.10Register update . . . . .514
19.4.11Counter mode . . . . .515
19.4.12Timer enable . . . . .516
19.4.13Encoder mode . . . . .516
19.4.14Debug mode . . . . .517
19.5LPTIM low-power modes . . . . .517
19.6LPTIM interrupts . . . . .518
19.7LPTIM registers . . . . .518
19.7.1LPTIM interrupt and status register (LPTIM_ISR) . . . . .519
19.7.2LPTIM interrupt clear register (LPTIM_ICR) . . . . .520
19.7.3LPTIM interrupt enable register (LPTIM_IER) . . . . .520
19.7.4LPTIM configuration register (LPTIM_CFGGR) . . . . .521
19.7.5LPTIM control register (LPTIM_CR) . . . . .524
19.7.6LPTIM compare register (LPTIM_CMP) . . . . .525
19.7.7LPTIM autoreload register (LPTIM_ARR) . . . . .526
19.7.8LPTIM counter register (LPTIM_CNT) . . . . .526
19.7.9LPTIM register map . . . . .527

20 Independent watchdog (IWDG) . . . . . 528

20.1 Introduction . . . . . 528

20.2 IWDG main features . . . . . 528

20.3 IWDG functional description . . . . . 528

20.3.1 IWDG block diagram . . . . . 528

20.3.2 Window option . . . . . 529

Configuring the IWDG when the window option is enabled . . . . . 529

Configuring the IWDG when the window option is disabled . . . . . 529

20.3.3 Hardware watchdog . . . . . 530

20.3.4 Register access protection . . . . . 530

20.3.5 Debug mode . . . . . 530

20.4 IWDG registers . . . . . 531

20.4.1 IWDG key register (IWDG_KR) . . . . . 531

20.4.2 IWDG prescaler register (IWDG_PR) . . . . . 532

20.4.3 IWDG reload register (IWDG_RLR) . . . . . 533

20.4.4 IWDG status register (IWDG_SR) . . . . . 534

20.4.5 IWDG window register (IWDG_WINR) . . . . . 535

20.4.6 IWDG register map . . . . . 536

21 System window watchdog (WWDG) . . . . . 537

21.1 Introduction . . . . . 537

21.2 WWDG main features . . . . . 537

21.3 WWDG functional description . . . . . 537

21.3.1 WWDG block diagram . . . . . 538

21.3.2 Enabling the watchdog . . . . . 538

21.3.3 Controlling the down-counter . . . . . 538

21.3.4 How to program the watchdog timeout . . . . . 538

21.3.5 Debug mode . . . . . 540

21.4 WWDG interrupts . . . . . 540

21.5 WWDG registers . . . . . 540

21.5.1 WWDG control register (WWDG_CR) . . . . . 540

21.5.2 WWDG configuration register (WWDG_CFR) . . . . . 541

21.5.3 WWDG status register (WWDG_SR) . . . . . 541

21.5.4 WWDG register map . . . . . 542

22 Real-time clock (RTC) . . . . . 543

22.1Introduction . . . . .543
22.2RTC main features . . . . .544
22.3RTC implementation . . . . .544
22.4RTC functional description . . . . .545
22.4.1RTC block diagram . . . . .545
22.4.2GPIOs controlled by the RTC . . . . .546
22.4.3Clock and prescalers . . . . .547
22.4.4Real-time clock and calendar . . . . .548
22.4.5Programmable alarms . . . . .549
22.4.6Periodic auto-wakeup . . . . .549
22.4.7RTC initialization and configuration . . . . .550
RTC register access . . . . .550
RTC register write protection . . . . .550
Calendar initialization and configuration . . . . .550
Daylight saving time . . . . .551
Programming the alarm . . . . .551
Programming the wakeup timer . . . . .551
22.4.8Reading the calendar . . . . .551
When BYPSHAD control bit is cleared in the RTC_CR register . . . . .551
When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow registers) . . . . .552
22.4.9Resetting the RTC . . . . .552
22.4.10RTC synchronization . . . . .553
22.4.11RTC reference clock detection . . . . .553
22.4.12RTC smooth digital calibration . . . . .554
Calibration when PREDIV_A<3 . . . . .555
Verifying the RTC calibration . . . . .555
Re-calibration on-the-fly . . . . .556
22.4.13Time-stamp function . . . . .556
22.4.14Tamper detection . . . . .557
RTC backup registers . . . . .557
Tamper detection initialization . . . . .557
Trigger output generation on tamper event . . . . .558
Timestamp on tamper event . . . . .558
Edge detection on tamper inputs . . . . .558
Level detection with filtering on RTC_TAMPx inputs . . . . .558
22.4.15Calibration clock output . . . . .559
22.4.16Alarm output . . . . .559
Alarm output . . . . .559
23.4.6I2C initialization . . . . .593
Enabling and disabling the peripheral . . . . .593
Noise filters . . . . .593
I2C timings . . . . .595
23.4.7Software reset . . . . .598
23.4.8Data transfer . . . . .599
Reception . . . . .599
Transmission . . . . .600
Hardware transfer management. . . . .600
23.4.9I2C slave mode . . . . .601
I2C slave initialization. . . . .601
Slave clock stretching (NOSTRETCH = 0). . . . .602
Slave without clock stretching (NOSTRETCH = 1). . . . .602
Slave byte control mode. . . . .603
Slave transmitter. . . . .604
Slave receiver. . . . .608
23.4.10I2C master mode . . . . .610
I2C master initialization . . . . .610
Master communication initialization (address phase). . . . .612
Initialization of a master receiver addressing a 10-bit address slave . . . . .613
Master transmitter. . . . .614
Master receiver. . . . .618
23.4.11I2C_TIMINGR register configuration examples . . . . .622
23.4.12SMBus specific features . . . . .623
Introduction. . . . .623
Bus protocols . . . . .623
Address resolution protocol (ARP). . . . .623
Received command and data acknowledge control. . . . .624
Host notify protocol. . . . .624
SMBus alert . . . . .624
Packet error checking. . . . .624
Timeouts. . . . .624
Bus idle detection. . . . .626
23.4.13SMBus initialization . . . . .626
Received command and data acknowledge control (Slave mode). . . . .626
Specific address (Slave mode). . . . .626
Packet error checking. . . . .626
Timeout detection. . . . .627
Bus idle detection. . . . .627
23.4.14SMBus: I2C_TIMEOUTR register configuration examples . . . . .628
23.4.15SMBus slave mode . . . . .628

SMBus slave transmitter . . . . . 628

SMBus Slave receiver . . . . . 630

SMBus master transmitter . . . . . 632

SMBus master receiver . . . . . 634

23.4.16 Wakeup from Stop mode on address match . . . . . 636

23.4.17 Error conditions . . . . . 636

Bus error (BERR) . . . . . 636

Arbitration lost (ARLO) . . . . . 637

Overrun/underrun error (OVR) . . . . . 637

Packet error checking error (PECERR) . . . . . 637

Timeout Error (TIMEOUT) . . . . . 637

Alert (ALERT) . . . . . 638

23.4.18 DMA requests . . . . . 638

Transmission using DMA . . . . . 638

Reception using DMA . . . . . 639

23.4.19 Debug mode . . . . . 639

23.5 I2C low-power modes . . . . . 639

23.6 I2C interrupts . . . . . 640

23.7 I2C registers . . . . . 641

23.7.1 I2C control register 1 (I2C_CR1) . . . . . 641

23.7.2 I2C control register 2 (I2C_CR2) . . . . . 644

23.7.3 I2C own address 1 register (I2C_OAR1) . . . . . 646

23.7.4 I2C own address 2 register (I2C_OAR2) . . . . . 647

23.7.5 I2C timing register (I2C_TIMINGR) . . . . . 648

23.7.6 I2C timeout register (I2C_TIMEOUTR) . . . . . 649

23.7.7 I2C interrupt and status register (I2C_ISR) . . . . . 650

23.7.8 I2C interrupt clear register (I2C_ICR) . . . . . 652

23.7.9 I2C PEC register (I2C_PECR) . . . . . 653

23.7.10 I2C receive data register (I2C_RXDR) . . . . . 654

23.7.11 I2C transmit data register (I2C_TXDR) . . . . . 654

23.7.12 I2C register map . . . . . 655

24 Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . . 657

24.1 Introduction . . . . . 657

24.2 USART main features . . . . . 657

24.3 USART extended features . . . . . 658

24.4 USART implementation . . . . . 659

24.5USART functional description . . . . .659
24.5.1USART character description . . . . .662
24.5.2USART transmitter . . . . .664
Character transmission. . . . .664
Single byte communication. . . . .665
Break characters . . . . .666
Idle characters . . . . .666
24.5.3USART receiver . . . . .667
Start bit detection . . . . .667
Character reception . . . . .668
Break character . . . . .668
Idle character . . . . .668
Overrun error . . . . .669
Selecting the proper oversampling method . . . . .669
Framing error . . . . .671
Configurable stop bits during reception . . . . .672
24.5.4USART baud rate generation . . . . .672
How to derive USARTDIV from USART_BRR register values . . . . .673
24.5.5Tolerance of the USART receiver to clock deviation . . . . .674
24.5.6USART auto baud rate detection . . . . .676
24.5.7Multiprocessor communication using USART . . . . .677
Idle line detection (WAKE=0) . . . . .678
4-bit/7-bit address mark detection (WAKE=1) . . . . .678
24.5.8Modbus communication using USART . . . . .679
Modbus/RTU . . . . .679
Modbus/ASCII . . . . .679
24.5.9USART parity control . . . . .680
Even parity . . . . .680
Odd parity . . . . .680
Parity checking in reception . . . . .680
Parity generation in transmission . . . . .680
24.5.10USART LIN (local interconnection network) mode . . . . .681
LIN transmission. . . . .681
LIN reception . . . . .681
24.5.11USART synchronous mode . . . . .683
24.5.12USART Single-wire Half-duplex communication . . . . .686
24.5.13USART Smartcard mode . . . . .686
Block mode (T=1). . . . .689
Direct and inverse convention . . . . .690
24.5.14USART IrDA SIR ENDEC block . . . . .691

25 Low-power universal asynchronous receiver transmitter (LPUART) . . . . . 725

Character transmission . . . . .732
Single byte communication . . . . .733
Break characters . . . . .734
Idle characters . . . . .734
25.4.3 LPUART receiver . . . . .734
Start bit detection . . . . .734
Character reception . . . . .735
Break character . . . . .735
Idle character . . . . .735
Overrun error . . . . .736
Selecting the clock source . . . . .736
Framing error . . . . .737
Configurable stop bits during reception . . . . .737
25.4.4 LPUART baud rate generation . . . . .737
25.4.5 Tolerance of the LPUART receiver to clock deviation . . . . .739
25.4.6 Multiprocessor communication using LPUART . . . . .740
Idle line detection (WAKE=0) . . . . .740
4-bit/7-bit address mark detection (WAKE=1) . . . . .741
25.4.7 LPUART parity control . . . . .742
Even parity . . . . .742
Odd parity . . . . .742
Parity checking in reception . . . . .743
Parity generation in transmission . . . . .743
25.4.8 Single-wire Half-duplex communication using LPUART . . . . .743
25.4.9 Continuous communication in DMA mode using LPUART . . . . .743
Transmission using DMA . . . . .744
Reception using DMA . . . . .745
Error flagging and interrupt generation in multibuffer communication . . . . .746
25.4.10 RS232 Hardware flow control and RS485 Driver Enable using LPUART . . . . .746
RS232 RTS flow control . . . . .747
RS232 CTS flow control . . . . .747
RS485 Driver Enable . . . . .748
25.4.11 Wakeup from Stop mode using LPUART . . . . .749
Using Mute mode with Stop mode . . . . .750
Determining the maximum LPUART baud rate allowing to wakeup correctly from Stop mode when the LPUART clock source is the HSI clock . . . . .750
25.5 LPUART in low-power mode . . . . .751
25.6 LPUART interrupts . . . . .751
25.7 LPUART registers . . . . .753

26 Serial peripheral interface/ inter-IC sound (SPI/I2S) . . . . . 768

26.3.12SPI status flags . . . . .785
Tx buffer empty flag (TXE) . . . . .785
Rx buffer not empty (RXNE) . . . . .785
Busy flag (BSY) . . . . .785
26.3.13SPI error flags . . . . .786
Overrun flag (OVR) . . . . .786
Mode fault (MODF) . . . . .786
CRC error (CRCERR) . . . . .787
TI mode frame format error (FRE) . . . . .787
26.4SPI special features . . . . .787
26.4.1TI mode . . . . .787
TI protocol in master mode . . . . .787
26.4.2CRC calculation . . . . .788
CRC principle . . . . .788
CRC transfer managed by CPU . . . . .788
CRC transfer managed by DMA . . . . .789
Resetting the SPIx_TXCRC and SPIx_RXCRC values . . . . .789
26.5SPI interrupts . . . . .790
26.6I 2 S functional description . . . . .791
26.6.1I 2 S general description . . . . .791
26.6.2I 2 S full-duplex . . . . .792
26.6.3Supported audio protocols . . . . .793
I 2 S Philips standard . . . . .794
MSB justified standard . . . . .796
LSB justified standard . . . . .797
PCM standard . . . . .799
26.6.4Clock generator . . . . .800
26.6.5I 2 S master mode . . . . .802
Procedure . . . . .802
Transmission sequence . . . . .802
Reception sequence . . . . .803
26.6.6I 2 S slave mode . . . . .804
Transmission sequence . . . . .804
Reception sequence . . . . .805
26.6.7I 2 S status flags . . . . .805
Busy flag (BSY) . . . . .805
Tx buffer empty flag (TXE) . . . . .806
RX buffer not empty (RXNE) . . . . .806
Channel Side flag (CHSIDE) . . . . .806
26.6.8I 2 S error flags . . . . .806
Underrun flag (UDR) . . . . .806
Overrun flag (OVR) . . . . .807
Frame error flag (FRE) . . . . .807
26.6.9 I 2 S interrupts . . . . .807
26.6.10 DMA features . . . . .807
26.7 SPI and I 2 S registers . . . . .808
26.7.1 SPI control register 1 (SPI_CR1) (not used in I 2 S mode) . . . . .808
26.7.2 SPI control register 2 (SPI_CR2) . . . . .810
26.7.3 SPI status register (SPI_SR) . . . . .811
26.7.4 SPI data register (SPI_DR) . . . . .813
26.7.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I 2 S mode) . . . . .813
26.7.6 SPI RX CRC register (SPI_RXCRCR) (not used in I 2 S mode) . . . . .814
26.7.7 SPI TX CRC register (SPI_TXCRCR) (not used in I 2 S mode) . . . . .814
26.7.8 SPI_I 2 S configuration register (SPI_I2SCFGGR) . . . . .815
26.7.9 SPI_I 2 S prescaler register (SPI_I2SPR) . . . . .816
26.7.10 SPI register map . . . . .817
27 Debug support (DBG) . . . . .818
27.1 Overview . . . . .818
27.2 Reference Arm® documentation . . . . .819
27.3 Pinout and debug port pins . . . . .819
27.3.1 SWD port pins . . . . .819
27.3.2 SW-DP pin assignment . . . . .819
27.3.3 Internal pull-up & pull-down on SWD pins . . . . .820
27.4 ID codes and locking mechanism . . . . .820
27.4.1 MCU device ID code . . . . .820
DBG_IDCODE . . . . .820
27.5 SWD port . . . . .821
27.5.1 SWD protocol introduction . . . . .821
27.5.2 SWD protocol sequence . . . . .821
27.5.3 SW-DP state machine (reset, idle states, ID code) . . . . .822
27.5.4 DP and AP read/write accesses . . . . .823
27.5.5 SW-DP registers . . . . .823
27.5.6 SW-AP registers . . . . .824
27.6 Core debug . . . . .825
27.7 BPU (Break Point Unit) . . . . .825
27.7.1BPU functionality . . . . .825
27.8DWT (Data Watchpoint) . . . . .826
27.8.1DWT functionality . . . . .826
27.8.2DWT Program Counter Sample Register . . . . .826
27.9MCU debug component (DBG) . . . . .826
27.9.1Debug support for low-power modes . . . . .826
27.9.2Debug support for timers, watchdog and I 2 C . . . . .827
27.9.3Debug MCU configuration register (DBG_CR) . . . . .827
27.9.4Debug MCU APB1 freeze register (DBG_APB1_FZ) . . . . .829
27.9.5Debug MCU APB2 freeze register (DBG_APB2_FZ) . . . . .831
27.10DBG register map . . . . .832
28Device electronic signature . . . . .833
28.1Memory size register . . . . .833
28.1.1Flash size register . . . . .833
28.2Unique device ID registers (96 bits) . . . . .833
Appendix ACode examples. . . . .835
A.1Introduction . . . . .835
A.2NVM/RCC Operation code example . . . . .835
A.2.1Increasing the CPU frequency preparation sequence code . . . . .835
A.2.2Decreasing the CPU frequency preparation sequence code . . . . .835
A.2.3Switch from PLL to HSI16 sequence code . . . . .836
A.2.4Switch to PLL sequence code. . . . .836
A.3NVM Operation code example . . . . .837
A.3.1Unlocking the data EEPROM and FLASH_PECR register code example . . . . .837
A.3.2Locking data EEPROM and FLASH_PECR register code example . . . . .837
A.3.3Unlocking the NVM program memory code example . . . . .837
A.3.4Unlocking the option bytes area code example . . . . .838
A.3.5Write to data EEPROM code example . . . . .838
A.3.6Erase to data EEPROM code example . . . . .838
A.3.7Program Option byte code example . . . . .839
A.3.8Erase Option byte code example . . . . .839
A.3.9Program a single word to Flash program memory code example . . . . .840
A.3.10Program half-page to Flash program memory code example . . . . .841
A.3.11Erase a page in Flash program memory code example . . . . .842
A.3.12Mass erase code example . . . . .843
A.4Clock Controller. . . . .844
A.4.1HSE start sequence code example . . . . .844
A.4.2PLL configuration modification code example . . . . .845
A.4.3MCO selection code example. . . . .846
A.5GPIOs . . . . .846
A.5.1Locking mechanism code example. . . . .846
A.5.2Alternate function selection sequence code example. . . . .846
A.5.3Analog GPIO configuration code example . . . . .846
A.6DMA . . . . .847
A.6.1DMA Channel Configuration sequence code example . . . . .847
A.7Interrupts and event . . . . .847
A.7.1NVIC initialization example. . . . .847
A.7.2Extended interrupt selection code example . . . . .847
A.8ADC. . . . .848
A.8.1Calibration code example . . . . .848
A.8.2ADC enable sequence code example . . . . .848
A.8.3ADC disable sequence code example . . . . .849
A.8.4ADC clock selection code example . . . . .849
A.8.5Single conversion sequence code example - Software trigger. . . . .849
A.8.6Continuous conversion sequence code example - Software trigger. . . . .850
A.8.7Single conversion sequence code example - Hardware trigger . . . . .850
A.8.8Continuous conversion sequence code example - Hardware trigger . . . . .851
A.8.9DMA one shot mode sequence code example . . . . .851
A.8.10DMA circular mode sequence code example . . . . .852
A.8.11Wait mode sequence code example. . . . .852
A.8.12Auto off and no wait mode sequence code example . . . . .852
A.8.13Auto off and wait mode sequence code example . . . . .853
A.8.14Analog watchdog code example. . . . .853
A.8.15Oversampling code example . . . . .854
A.8.16Temperature configuration code example. . . . .854
A.8.17Temperature computation code example . . . . .854
A.9Timers . . . . .855
A.9.1Upcounter on TI2 rising edge code example . . . . .855
A.9.2Up counter on each 2 ETR rising edges code example . . . . .855
A.9.3Input capture configuration code example . . . . .856
A.9.4Input capture data management code example . . . . .856
A.9.5PWM input configuration code example . . . . .857
A.9.6PWM input with DMA configuration code example . . . . .857
A.9.7Output compare configuration code example . . . . .858
A.9.8Edge-aligned PWM configuration example. . . . .858
A.9.9Center-aligned PWM configuration example . . . . .859
A.9.10ETR configuration to clear OCxREF code example . . . . .859
A.9.11Encoder interface code example . . . . .860
A.9.12Reset mode code example . . . . .860
A.9.13Gated mode code example. . . . .861
A.9.14Trigger mode code example . . . . .861
A.9.15External clock mode 2 + trigger mode code example. . . . .862
A.9.16One-Pulse mode code example . . . . .862
A.9.17Timer prescaling another timer code example . . . . .863
A.9.18Timer enabling another timer code example. . . . .863
A.9.19Master and slave synchronization code example . . . . .864
A.9.20Two timers synchronized by an external trigger code example . . . . .866
A.9.21DMA burst feature code example . . . . .867
A.10Low-power timer (LPTIM) . . . . .868
A.10.1Pulse counter configuration code example. . . . .868
A.11IWDG code example . . . . .868
A.11.1IWDG configuration code example . . . . .868
A.11.2IWDG configuration with window code example. . . . .868
A.12WWDG code example. . . . .869
A.12.1WWDG configuration code example. . . . .869
A.13RTC code example . . . . .869
A.13.1RTC calendar configuration code example. . . . .869
A.13.2RTC alarm configuration code example . . . . .870
A.13.3RTC WUT configuration code example . . . . .870
A.13.4RTC read calendar code example . . . . .870
A.13.5RTC calibration code example . . . . .871
A.13.6RTC tamper and time stamp configuration code example . . . . .871
A.13.7RTC tamper and time stamp code example . . . . .872
A.13.8RTC clock output code example . . . . .872
A.14I2C code example . . . . .872
A.14.1I2C configured in slave mode code example . . . . .872
A.14.2I2C slave transmitter code example . . . . .873
A.14.3I2C slave receiver code example . . . . .873
A.14.4I2C configured in master mode to receive code example. . . . .873
A.14.5I2C configured in master mode to transmit code example . . . . .874
A.14.6I2C master transmitter code example. . . . .874
A.14.7I2C master receiver code example . . . . .874
A.14.8I2C configured in master mode to transmit with DMA code example . .874
A.14.9I2C configured in slave mode to receive with DMA code example . . . .875
A.15USART code example. . . . .875
A.15.1USART transmitter configuration code example. . . . .875
A.15.2USART transmit byte code example. . . . .875
A.15.3USART transfer complete code example . . . . .875
A.15.4USART receiver configuration code example. . . . .875
A.15.5USART receive byte code example . . . . .876
A.15.6USART LIN mode code example . . . . .876
A.15.7USART synchronous mode code example. . . . .876
A.15.8USART single-wire half-duplex code example . . . . .877
A.15.9USART smartcard mode code example . . . . .877
A.15.10USART IrDA mode code example . . . . .877
A.15.11USART DMA code example . . . . .878
A.15.12USART hardware flow control code example. . . . .878
A.16LPUART code example. . . . .879
A.16.1LPUART receiver configuration code example. . . . .879
A.16.2LPUART receive byte code example . . . . .879
A.17SPI code example . . . . .879
A.17.1SPI master configuration code example. . . . .879
A.17.2SPI slave configuration code example . . . . .879
A.17.3SPI full duplex communication code example . . . . .879
A.17.4SPI master configuration with DMA code example. . . . .880
A.17.5SPI slave configuration with DMA code example . . . . .880
A.17.6SPI interrupt code example . . . . .880
A.18DBG code example . . . . .880
A.18.1DBG read device Id code example. . . . .880
A.18.2DBG debug in LPM code example . . . . .880
Revision history. . . . .881

List of tables

Table 1.STM32L0x1 memory density . . . . .47
Table 2.Overview of features per category . . . . .47
Table 3.STM32L0x1 peripheral register boundary addresses . . . . .53
Table 4.Boot modes . . . . .56
Table 5.NVM organization (category 1 devices) . . . . .60
Table 6.NVM organization (category 2 devices) . . . . .61
Table 7.NVM organization (category 3 devices) . . . . .61
Table 8.NVM organization for UFB = 0 (192 Kbyte category 5 devices) . . . . .62
Table 9.Flash memory and data EEPROM remapping
(192 Kbyte category 5 devices) . . . . .		63
Table 10.NVM organization for UFB = 0 (128 Kbyte category 5 devices) . . . . .63
Table 11.Flash memory and data EEPROM remapping (128 Kbyte category 5 devices) . . . . .64
Table 12.NVM organization for UFB = 0 (64 Kbyte category 5 devices) . . . . .64
Table 13.Boot pin and BFB2 bit configuration . . . . .65
Table 14.Link between master clock power range and frequencies . . . . .67
Table 15.Delays to memory access and number of wait states . . . . .67
Table 16.Internal buffer management . . . . .70
Table 17.Configurations for buffers and speculative reading . . . . .73
Table 18.Dhrystone performances in all memory interface configurations . . . . .74
Table 19.NVM write/erase timings . . . . .88
Table 20.NVM write/erase duration . . . . .88
Table 21.Protection level and content of RDP Option bytes . . . . .92
Table 22.Link between protection bits of FLASH_WRPROTx register
and protected address in Flash program memory . . . . .		93
Table 23.Memory access vs mode, protection and Flash program memory sectors . . . . .94
Table 24.Flash interrupt request . . . . .97
Table 25.Flash interface - register map and reset values . . . . .114
Table 26.Option byte format . . . . .115
Table 27.Option byte organization . . . . .115
Table 28.CRC internal input/output signals . . . . .118
Table 29.CRC register map and reset values . . . . .123
Table 30.Segment accesses according to the Firewall state . . . . .127
Table 31.Segment granularity and area ranges . . . . .128
Table 32.Firewall register map and reset values . . . . .135
Table 33.Performance versus VCORE ranges . . . . .139
Table 34.Summary of low-power modes . . . . .147
Table 35.Sleep-now . . . . .151
Table 36.Sleep-on-exit . . . . .152
Table 37.Sleep-now (Low-power sleep) . . . . .153
Table 38.Sleep-on-exit (Low-power sleep) . . . . .154
Table 39.Stop mode . . . . .156
Table 40.Standby mode . . . . .158
Table 41.PWR - register map and reset values . . . . .166
Table 42.HSE/LSE clock sources . . . . .172
Table 43.System clock source frequency . . . . .177
Table 44.RCC register map and reset values . . . . .213
Table 45.Port bit configuration table . . . . .218
Table 46.GPIO register map and reset values . . . . .231
Table 47.SYSCFG register map and reset values . . . . .239
Table 48.DMA implementation . . . . .242
Table 49.DMA requests for each channel . . . . .243
Table 50.Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .251
Table 51.DMA interrupt requests . . . . .252
Table 52.DMA register map and reset values . . . . .262
Table 53.List of vectors . . . . .265
Table 54.EXTI lines connections . . . . .272
Table 55.Extended interrupt/event controller register map and reset values . . . . .277
Table 56.ADC input/output pins . . . . .280
Table 57.ADC internal input/output signals . . . . .281
Table 58.External triggers . . . . .281
Table 59.Latency between trigger and start of conversion . . . . .286
Table 60.Configuring the trigger polarity . . . . .292
Table 61.tSAR timings depending on resolution . . . . .294
Table 62.Analog watchdog comparison . . . . .303
Table 63.Analog watchdog channel selection . . . . .303
Table 64.Maximum output results vs N and M. Grayed values indicates truncation . . . . .307
Table 65.ADC interrupts . . . . .312
Table 66.ADC register map and reset values . . . . .327
Table 67.COMP register map and reset values . . . . .336
Table 68.AES internal input/output signals . . . . .338
Table 69.CTR mode initialization vector definition . . . . .354
Table 70.Key endianness in AES_KEYRx registers . . . . .357
Table 71.DMA channel configuration for memory-to-AES data transfer . . . . .358
Table 72.DMA channel configuration for AES-to-memory data transfer . . . . .359
Table 73.AES interrupt requests . . . . .361
Table 74.Processing latency (in clock cycle) . . . . .361
Table 75.AES register map and reset values . . . . .369
Table 76.Counting direction versus encoder signals . . . . .402
Table 77.TIM2/TIM3 internal trigger connection . . . . .419
Table 78.Output control bit for standard OCx channels . . . . .429
Table 79.TIM2/3 register map and reset values . . . . .437
Table 80.Counting direction versus encoder signals . . . . .470
Table 81.TIMx Internal trigger connection . . . . .480
Table 82.Output control bit for standard OCx channels . . . . .488
Table 83.TIM21/22 register map and reset values . . . . .492
Table 84.TIM6/7 register map and reset values . . . . .506
Table 85.STM32L0x1 LPTIM features . . . . .508
Table 86.LPTIM1 external trigger connection . . . . .509
Table 87.Prescaler division ratios . . . . .510
Table 88.Encoder counting scenarios . . . . .516
Table 89.Effect of low-power modes on the LPTIM . . . . .517
Table 90.Interrupt events . . . . .518
Table 91.LPTIM register map and reset values . . . . .527
Table 92.IWDG register map and reset values . . . . .536
Table 93.WWDG register map and reset values . . . . .542
Table 94.RTC implementation . . . . .544
Table 95.RTC pin PC13 configuration . . . . .546
Table 96.RTC_OUT mapping . . . . .547
Table 97.Effect of low-power modes on RTC . . . . .560
Table 98.Interrupt control bits . . . . .560
Table 99.RTC register map and reset values . . . . .585
Table 100.STM32L0x1 I2C features . . . . .589
Table 101.I2C input/output pins . . . . .592
Table 102.I2C internal input/output signals . . . . .592
Table 103.Comparison of analog vs. digital filters . . . . .594
Table 104.I2C-SMBus specification data setup and hold times . . . . .597
Table 105.I2C configuration . . . . .601
Table 106.I2C-SMBus specification clock timings . . . . .612
Table 107.Examples of timing settings for f I2CCLK = 8 MHz . . . . .622
Table 108.Examples of timings settings for f I2CCLK = 16 MHz . . . . .622
Table 109.SMBus timeout specifications . . . . .624
Table 110.SMBus with PEC configuration . . . . .627
Table 111.Examples of TIMEOUTA settings for various I2CCLK frequencies
(max t TIMEOUT = 25 ms) . . . . .		628
Table 112.Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . .628
Table 113.Examples of TIMEOUTA settings for various I2CCLK frequencies
(max t IDLE = 50 µs) . . . . .		628
Table 114.Effect of low-power modes on the I2C . . . . .639
Table 115.I2C Interrupt requests . . . . .640
Table 116.I2C register map and reset values . . . . .655
Table 117.STM32L0x1 USART/LPUART features . . . . .659
Table 118.Noise detection from sampled data . . . . .671
Table 119.Error calculation for programmed baud rates at f CK = 32 MHz in both cases of
oversampling by 16 or by 8 . . . . .		674
Table 120.Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . .675
Table 121.Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . .675
Table 122.Frame formats . . . . .680
Table 123.Effect of low-power modes on the USART . . . . .699
Table 124.USART interrupt requests . . . . .699
Table 125.USART register map and reset values . . . . .723
Table 126.STM32L0x1 USART/LPUART features . . . . .727
Table 127.Error calculation for programmed baud rates at f ck = 32.768 kHz . . . . .738
Table 128.Error calculation for programmed baud rates at f ck = 32 MHz . . . . .738
Table 129.Tolerance of the LPUART receiver . . . . .739
Table 130.Frame formats . . . . .742
Table 131.Effect of low-power modes on the LPUART . . . . .751
Table 132.LPUART interrupt requests . . . . .751
Table 133.LPUART register map and reset values . . . . .767
Table 134.STM32L0x1 SPI implementation . . . . .769
Table 135.SPI interrupt requests . . . . .790
Table 136.Audio-frequency precision using standard 8 MHz HSE . . . . .801
Table 137.I 2 S interrupt requests . . . . .807
Table 138.SPI register map and reset values . . . . .817
Table 139.SW debug port pins . . . . .819
Table 140.REV_ID values . . . . .821
Table 141.Packet request (8-bits) . . . . .821
Table 142.ACK response (3 bits) . . . . .822
Table 143.DATA transfer (33 bits) . . . . .822
Table 144.SW-DP registers . . . . .823
Table 145.32-bit debug port registers addressed through the shifted value A[3:2] . . . . .824
Table 146.Core debug registers . . . . .825
Table 147.DBG register map and reset values . . . . .832

Table 148. Document revision history ..... 881

List of figures

Figure 1.System architecture . . . . .49
Figure 2.Memory map . . . . .52
Figure 3.Structure of one internal buffer . . . . .69
Figure 4.Timing to fetch and execute instructions with prefetch disabled. . . . .71
Figure 5.Timing to fetch and execute instructions with prefetch enabled . . . . .73
Figure 6.RDP levels . . . . .92
Figure 7.CRC calculation unit block diagram . . . . .118
Figure 8.STM32L0x1 firewall connection schematics. . . . .125
Figure 9.Firewall functional states . . . . .129
Figure 10.Power supply overview . . . . .137
Figure 11.Performance versus VDD and VCORE range . . . . .140
Figure 12.Power supply supervisors . . . . .143
Figure 13.Power-on reset/power-down reset waveform . . . . .144
Figure 14.BOR thresholds . . . . .145
Figure 15.PVD thresholds . . . . .146
Figure 16.Simplified diagram of the reset circuit. . . . .168
Figure 17.Clock tree . . . . .171
Figure 18.Using TIM21 channel 1 input capture to measure frequencies . . . . .179
Figure 19.Basic structure of an I/O port bit . . . . .217
Figure 20.Basic structure of a 5-Volt tolerant I/O port bit . . . . .217
Figure 21.Input floating / pull up / pull down configurations . . . . .222
Figure 22.Output configuration . . . . .223
Figure 23.Alternate function configuration . . . . .223
Figure 24.High impedance-analog configuration . . . . .224
Figure 25.DMA request mapping . . . . .243
Figure 26.DMA block diagram . . . . .245
Figure 27.Extended interrupts and events controller (EXTI) block diagram . . . . .269
Figure 28.Extended interrupt/event GPIO mapping . . . . .271
Figure 29.ADC block diagram . . . . .280
Figure 30.ADC calibration. . . . .283
Figure 31.Calibration factor forcing . . . . .284
Figure 32.Enabling/disabling the ADC . . . . .285
Figure 33.ADC clock scheme . . . . .285
Figure 34.ADC connectivity . . . . .287
Figure 35.Analog to digital conversion time . . . . .291
Figure 36.ADC conversion timings . . . . .291
Figure 37.Stopping an ongoing conversion . . . . .292
Figure 38.Single conversions of a sequence, software trigger . . . . .295
Figure 39.Continuous conversion of a sequence, software trigger. . . . .295
Figure 40.Single conversions of a sequence, hardware trigger . . . . .296
Figure 41.Continuous conversions of a sequence, hardware trigger . . . . .296
Figure 42.Data alignment and resolution (oversampling disabled: OVSE = 0). . . . .297
Figure 43.Example of overrun (OVR) . . . . .298
Figure 44.Wait mode conversion (continuous mode, software trigger). . . . .300
Figure 45.Behavior with WAIT = 0, AUTOFF = 1 . . . . .301
Figure 46.Behavior with WAIT = 1, AUTOFF = 1 . . . . .302
Figure 47.Analog watchdog guarded area . . . . .303
Figure 48.ADC_AWD1_OUT signal generation . . . . .304
Figure 49.ADC_AWD1_OUT signal generation (AWD flag not cleared by software) . . . . .305
Figure 50.ADC1_AWD_OUT signal generation (on a single channel) . . . . .305
Figure 51.Analog watchdog threshold update . . . . .306
Figure 52.20-bit to 16-bit result truncation . . . . .307
Figure 53.Numerical example with 5-bits shift and rounding . . . . .307
Figure 54.Triggered oversampling mode (TOVS bit = 1) . . . . .309
Figure 55.Temperature sensor and VREFINT channel block diagram . . . . .310
Figure 56.Comparator 1 and 2 block diagrams . . . . .330
Figure 57.AES block diagram . . . . .338
Figure 58.ECB encryption and decryption principle . . . . .340
Figure 59.CBC encryption and decryption principle . . . . .341
Figure 60.CTR encryption and decryption principle . . . . .342
Figure 61.STM32 cryptolib AES flowchart example . . . . .343
Figure 62.Encryption key derivation for ECB/CBC decryption (Mode 2). . . . .346
Figure 63.Example of suspend mode management . . . . .347
Figure 64.ECB encryption . . . . .347
Figure 65.ECB decryption . . . . .348
Figure 66.CBC encryption . . . . .348
Figure 67.CBC decryption . . . . .349
Figure 68.ECB/CBC encryption (Mode 1) . . . . .350
Figure 69.ECB/CBC decryption (Mode 3) . . . . .351
Figure 70.Message construction in CTR mode . . . . .353
Figure 71.CTR encryption . . . . .353
Figure 72.CTR decryption . . . . .354
Figure 73.128-bit block construction with respect to data swap . . . . .356
Figure 74.DMA transfer of a 128-bit data block during input phase . . . . .358
Figure 75.DMA transfer of a 128-bit data block during output phase . . . . .359
Figure 76.AES interrupt signal generation . . . . .361
Figure 77.General-purpose timer block diagram . . . . .372
Figure 78.Counter timing diagram with prescaler division change from 1 to 2 . . . . .374
Figure 79.Counter timing diagram with prescaler division change from 1 to 4 . . . . .374
Figure 80.Counter timing diagram, internal clock divided by 1 . . . . .375
Figure 81.Counter timing diagram, internal clock divided by 2 . . . . .376
Figure 82.Counter timing diagram, internal clock divided by 4 . . . . .376
Figure 83.Counter timing diagram, internal clock divided by N . . . . .377
Figure 84.Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .377
Figure 85.Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .378
Figure 86.Counter timing diagram, internal clock divided by 1 . . . . .379
Figure 87.Counter timing diagram, internal clock divided by 2 . . . . .379
Figure 88.Counter timing diagram, internal clock divided by 4 . . . . .380
Figure 89.Counter timing diagram, internal clock divided by N . . . . .380
Figure 90.Counter timing diagram, Update event when repetition counter
is not used . . . . .		381
Figure 91.Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .382
Figure 92.Counter timing diagram, internal clock divided by 2 . . . . .383
Figure 93.Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .383
Figure 94.Counter timing diagram, internal clock divided by N . . . . .384
Figure 95.Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .384
Figure 96.Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .385
Figure 97.Control circuit in normal mode, internal clock divided by 1 . . . . .386
Figure 98.TI2 external clock connection example . . . . .386
Figure 99.Control circuit in external clock mode 1 . . . . .387
Figure 100.External trigger input block . . . . .388
Figure 101.Control circuit in external clock mode 2 . . . . .389
Figure 102.Capture/compare channel (example: channel 1 input stage) . . . . .390
Figure 103.Capture/compare channel 1 main circuit . . . . .390
Figure 104.Output stage of capture/compare channel (channel 1). . . . .391
Figure 105.PWM input mode timing . . . . .393
Figure 106.Output compare mode, toggle on OC1. . . . .395
Figure 107.Edge-aligned PWM waveforms (ARR=8) . . . . .396
Figure 108.Center-aligned PWM waveforms (ARR=8). . . . .398
Figure 109.Example of one-pulse mode. . . . .399
Figure 110.Clearing TIMx_OCxREF . . . . .401
Figure 111.Example of counter operation in encoder interface mode . . . . .403
Figure 112.Example of encoder interface mode with TI1FP1 polarity inverted . . . . .403
Figure 113.Control circuit in reset mode . . . . .404
Figure 114.Control circuit in gated mode . . . . .405
Figure 115.Control circuit in trigger mode . . . . .406
Figure 116.Control circuit in external clock mode 2 + trigger mode . . . . .408
Figure 117.Master/Slave timer example . . . . .408
Figure 118.Gating timer y with OC1REF of timer x. . . . .410
Figure 119.Gating timer y with Enable of timer x . . . . .411
Figure 120.Triggering timer y with update of timer x. . . . .412
Figure 121.Triggering timer y with Enable of timer x . . . . .412
Figure 122.Triggering timer x and y with timer x TI1 input . . . . .413
Figure 123.General-purpose timer block diagram (TIM21/22) . . . . .440
Figure 124.Counter timing diagram with prescaler division change from 1 to 2 . . . . .442
Figure 125.Counter timing diagram with prescaler division change from 1 to 4 . . . . .443
Figure 126.Counter timing diagram, internal clock divided by 1 . . . . .444
Figure 127.Counter timing diagram, internal clock divided by 2 . . . . .445
Figure 128.Counter timing diagram, internal clock divided by 4 . . . . .445
Figure 129.Counter timing diagram, internal clock divided by N. . . . .446
Figure 130.Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . .		446
Figure 131.Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . .		447
Figure 132.Counter timing diagram, internal clock divided by 1 . . . . .448
Figure 133.Counter timing diagram, internal clock divided by 2 . . . . .448
Figure 134.Counter timing diagram, internal clock divided by 4 . . . . .449
Figure 135.Counter timing diagram, internal clock divided by N. . . . .449
Figure 136.Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .451
Figure 137.Counter timing diagram, internal clock divided by 2 . . . . .451
Figure 138.Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .452
Figure 139.Counter timing diagram, internal clock divided by N. . . . .452
Figure 140.Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .453
Figure 141.Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .453
Figure 142.Control circuit in normal mode, internal clock divided by 1 . . . . .454
Figure 143.TI2 external clock connection example. . . . .455
Figure 144.Control circuit in external clock mode 1 . . . . .456
Figure 145.External trigger input block . . . . .456
Figure 146.Control circuit in external clock mode 2 . . . . .457
Figure 147.Capture/compare channel (example: channel 1 input stage) . . . . .458
Figure 148.Capture/compare channel 1 main circuit . . . . .458
Figure 149. Output stage of capture/compare channel (channel 1 and 2) . . . . .459
Figure 150. PWM input mode timing . . . . .461
Figure 151. Output compare mode, toggle on OC1 . . . . .463
Figure 152. Edge-aligned PWM waveforms (ARR=8) . . . . .464
Figure 153. Center-aligned PWM waveforms (ARR=8) . . . . .465
Figure 154. Clearing TIMx_OCxREF . . . . .467
Figure 155. Example of one pulse mode . . . . .468
Figure 156. Example of counter operation in encoder interface mode . . . . .470
Figure 157. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .471
Figure 158. Control circuit in reset mode . . . . .472
Figure 159. Control circuit in gated mode . . . . .473
Figure 160. Control circuit in trigger mode . . . . .474
Figure 161. Basic timer block diagram . . . . .494
Figure 162. Counter timing diagram with prescaler division change from 1 to 2 . . . . .496
Figure 163. Counter timing diagram with prescaler division change from 1 to 4 . . . . .496
Figure 164. Counter timing diagram, internal clock divided by 1 . . . . .497
Figure 165. Counter timing diagram, internal clock divided by 2 . . . . .498
Figure 166. Counter timing diagram, internal clock divided by 4 . . . . .498
Figure 167. Counter timing diagram, internal clock divided by N . . . . .499
Figure 168. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) . . . . .499
Figure 169. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .500
Figure 170. Control circuit in normal mode, internal clock divided by 1 . . . . .501
Figure 171. Low-power timer block diagram . . . . .508
Figure 172. Glitch filter timing diagram . . . . .510
Figure 173. LPTIM output waveform, single counting mode configuration . . . . .512
Figure 174. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set) . . . . .512
Figure 175. LPTIM output waveform, Continuous counting mode configuration . . . . .513
Figure 176. Waveform generation . . . . .514
Figure 177. Encoder mode counting sequence . . . . .517
Figure 178. Independent watchdog block diagram . . . . .528
Figure 179. Watchdog block diagram . . . . .538
Figure 180. Window watchdog timing diagram . . . . .539
Figure 181. RTC block diagram . . . . .545
Figure 182. I2C1/3 block diagram . . . . .590
Figure 183. I2C2 block diagram . . . . .591
Figure 184. I2C bus protocol . . . . .593
Figure 185. Setup and hold timings . . . . .595
Figure 186. I2C initialization flow . . . . .598
Figure 187. Data reception . . . . .599
Figure 188. Data transmission . . . . .600
Figure 189. Slave initialization flow . . . . .603
Figure 190. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0 . . . . .605
Figure 191. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1 . . . . .606
Figure 192. Transfer bus diagrams for I2C slave transmitter . . . . .607
Figure 193. Transfer sequence flow for slave receiver with NOSTRETCH = 0 . . . . .608
Figure 194. Transfer sequence flow for slave receiver with NOSTRETCH = 1 . . . . .609
Figure 195. Transfer bus diagrams for I2C slave receiver . . . . .609
Figure 196. Master clock generation . . . . .611
Figure 197. Master initialization flow . . . . .613
Figure 198. 10-bit address read access with HEAD10R = 0 . . . . .613
Figure 199. 10-bit address read access with HEAD10R = 1 . . . . .614
Figure 200. Transfer sequence flow for I2C master transmitter for N≤255 bytes . . . . .615
Figure 201. Transfer sequence flow for I2C master transmitter for N>255 bytes . . . . .616
Figure 202. Transfer bus diagrams for I2C master transmitter . . . . .617
Figure 203. Transfer sequence flow for I2C master receiver for N≤255 bytes . . . . .619
Figure 204. Transfer sequence flow for I2C master receiver for N >255 bytes . . . . .620
Figure 205. Transfer bus diagrams for I2C master receiver . . . . .621
Figure 206. Timeout intervals for t LOW:SEXT , t LOW:MEXT . . . . .625
Figure 207. Transfer sequence flow for SMBus slave transmitter N bytes + PEC . . . . .629
Figure 208. Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . .630
Figure 209. Transfer sequence flow for SMBus slave receiver N Bytes + PEC . . . . .631
Figure 210. Bus transfer diagrams for SMBus slave receiver (SBC=1) . . . . .632
Figure 211. Bus transfer diagrams for SMBus master transmitter . . . . .633
Figure 212. Bus transfer diagrams for SMBus master receiver . . . . .635
Figure 213. USART block diagram . . . . .661
Figure 214. Word length programming . . . . .663
Figure 215. Configurable stop bits . . . . .665
Figure 216. TC/TXE behavior when transmitting . . . . .666
Figure 217. Start bit detection when oversampling by 16 or 8 . . . . .667
Figure 218. Data sampling when oversampling by 16 . . . . .670
Figure 219. Data sampling when oversampling by 8 . . . . .671
Figure 220. Mute mode using Idle line detection . . . . .678
Figure 221. Mute mode using address mark detection . . . . .679
Figure 222. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .682
Figure 223. Break detection in LIN mode vs. Framing error detection. . . . .683
Figure 224. USART example of synchronous transmission. . . . .684
Figure 225. USART data clock timing diagram (M bits = 00) . . . . .684
Figure 226. USART data clock timing diagram (M bits = 01) . . . . .685
Figure 227. RX data setup/hold time . . . . .685
Figure 228. ISO 7816-3 asynchronous protocol . . . . .687
Figure 229. Parity error detection using the 1.5 stop bits . . . . .688
Figure 230. IrDA SIR ENDEC- block diagram . . . . .692
Figure 231. IrDA data modulation (3/16) -Normal Mode . . . . .693
Figure 232. Transmission using DMA . . . . .694
Figure 233. Reception using DMA . . . . .695
Figure 234. Hardware flow control between 2 USARTs . . . . .695
Figure 235. RS232 RTS flow control . . . . .696
Figure 236. RS232 CTS flow control . . . . .697
Figure 237. USART interrupt mapping diagram . . . . .700
Figure 238. LPUART block diagram . . . . .729
Figure 239. Word length programming . . . . .731
Figure 240. Configurable stop bits . . . . .732
Figure 241. TC/TXE behavior when transmitting . . . . .734
Figure 242. Mute mode using Idle line detection . . . . .741
Figure 243. Mute mode using address mark detection . . . . .742
Figure 244. Transmission using DMA . . . . .745
Figure 245. Reception using DMA . . . . .746
Figure 246. Hardware flow control between 2 LPUARTs . . . . .746
Figure 247. RS232 RTS flow control . . . . .747
Figure 248. RS232 CTS flow control . . . . .748
Figure 249. LPUART interrupt mapping diagram . . . . .752
Figure 250.SPI block diagram. . . . .770
Figure 251.Full-duplex single master/ single slave application. . . . .771
Figure 252.Half-duplex single master/ single slave application . . . . .772
Figure 253.Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		773
Figure 254.Master and three independent slaves. . . . .774
Figure 255.Multi-master application . . . . .775
Figure 256.Hardware/software slave select management . . . . .776
Figure 257.Data clock timing diagram . . . . .778
Figure 258.TXE/RXNE/BSY behavior in master / full-duplex mode (BIDIMODE=0,
RXONLY=0) in the case of continuous transfers . . . . .		781
Figure 259.TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0,
RXONLY=0) in the case of continuous transfers . . . . .		782
Figure 260.Transmission using DMA . . . . .784
Figure 261.Reception using DMA. . . . .785
Figure 262.TI mode transfer . . . . .788
Figure 263.I 2 S block diagram . . . . .791
Figure 264.Full-duplex communication. . . . .793
Figure 265.I 2 S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . .794
Figure 266.I 2 S Philips standard waveforms (24-bit frame with CPOL = 0). . . . .794
Figure 267.Transmitting 0x8EAA33 . . . . .795
Figure 268.Receiving 0x8EAA33 . . . . .795
Figure 269.I 2 S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . .795
Figure 270.Example of 16-bit data frame extended to 32-bit channel frame . . . . .796
Figure 271.MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . .796
Figure 272.MSB justified 24-bit frame length with CPOL = 0 . . . . .796
Figure 273.MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .797
Figure 274.LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . .797
Figure 275.LSB justified 24-bit frame length with CPOL = 0. . . . .797
Figure 276.Operations required to transmit 0x3478AE. . . . .798
Figure 277.Operations required to receive 0x3478AE . . . . .798
Figure 278.LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .798
Figure 279.Example of 16-bit data frame extended to 32-bit channel frame . . . . .799
Figure 280.PCM standard waveforms (16-bit) . . . . .799
Figure 281.PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .799
Figure 282.Audio sampling frequency definition. . . . .800
Figure 283.I 2 S clock generator architecture . . . . .800
Figure 284.Block diagram of STM32L0x1 MCU and Cortex ® -M0+-level debug support . . . . .818

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