22. Basic timers (TIM6/7)
22.1 Introduction
The basic timers TIM6, TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler.
They can be used as generic timers for timebase generation but they are also specifically used to drive the digital-to-analog converter (DAC). In fact, the timers are internally connected to the DAC and are able to drive it through their trigger outputs.
The timers are completely independent, and do not share any resources.
22.2 TIM6/7 main features
Basic timer (TIM6/TIM7) features include:
- • 16-bit auto-reload upcounter
- • 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536
- • Synchronization circuit to trigger the DAC
- • Interrupt/DMA generation on the update event: counter overflow
Figure 178. Basic timer block diagram
The block diagram illustrates the internal architecture of the TIM6/7 basic timer. At the top, a 'Trigger controller' block receives an 'Internal clock (CK_INT)' from the 'TIMxCLK from RCC' input. It has a 'Control' sub-block and outputs a 'TRGO' signal 'to DAC'. Below the trigger controller, a 'PSC prescaler' block receives 'CK_PSC' and outputs 'CK_CNT' to a 'CNT counter' (labeled with a '+'). The 'CNT counter' is connected to an 'Auto-reload register' (labeled 'U'). The 'Auto-reload register' has a 'Stop, clear or up' input and outputs 'UI' and 'U' signals. The 'Trigger controller' also provides 'Reset, enable, Count' signals to the 'Auto-reload register' and 'CNT counter'.
Notes:
Reg
Preload registers transferred to active registers on U event according to control bit
→ Event
↗ Interrupt & DMA output
MS33142V1
22.3 TIM6/7 functional description
22.3.1 Time-base unit
The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.
The time-base unit includes:
- • Counter Register (TIMx_CNT)
- • Prescaler Register (TIMx_PSC)
- • Auto-Reload Register (TIMx_ARR)
The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to write or read the auto-reload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set.
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event.
Figure 179 and Figure 180 give some examples of the counter behavior when the prescaler ratio is changed on the fly.
Figure 179. Counter timing diagram with prescaler division change from 1 to 2
This timing diagram illustrates the operation of a basic timer when the prescaler division is changed from 1 to 2. The signals shown are:
- CK_PSC : Prescaler input clock signal.
- CEN : Counter Enable signal, which goes high to start the counter.
- Timerclock = CK_CNT : The clock signal for the counter, which is derived from CK_PSC divided by the prescaler value.
- Counter register : Shows the counter values. It starts at F7 and increments through F8, F9, FA, FB, and FC. Upon reaching FC, an Update event (UEV) occurs, and the counter resets to 00. The counter then continues to increment: 00, 01, 02, 03.
- Update event (UEV) : A pulse generated when the counter reaches its maximum value (FC) and resets to 00.
- Prescaler control register : Initially set to 0 (division by 1). At the time of the update event, a new value of 1 (division by 2) is written to this register.
- Write a new value in TIMx_PSC : An arrow indicates the write operation to the prescaler control register at the UEV.
- Prescaler buffer : A buffer that latches the value from the prescaler control register. It initially holds 0 and updates to 1 at the UEV.
- Prescaler counter : A counter that divides the CK_PSC frequency. It counts from 0 to 1 when the division is 2. The sequence shown is 0, 1, 0, 1, 0, 1, 0, 1.
Vertical dashed lines indicate the timing relationships between the update event, the register updates, and the counter increments. The diagram is labeled MS31076V2.
Figure 180. Counter timing diagram with prescaler division change from 1 to 4
This timing diagram illustrates the operation of a basic timer when the prescaler division is changed from 1 to 4. The signals shown are:
- CK_PSC : Prescaler input clock signal.
- CEN : Counter Enable signal, which goes high to start the counter.
- Timerclock = CK_CNT : The clock signal for the counter, which is derived from CK_PSC divided by the prescaler value.
- Counter register : Shows the counter values. It starts at F7 and increments through F8, F9, FA, FB, and FC. Upon reaching FC, an Update event (UEV) occurs, and the counter resets to 00. The counter then continues to increment: 00, 01.
- Update event (UEV) : A pulse generated when the counter reaches its maximum value (FC) and resets to 00.
- Prescaler control register : Initially set to 0 (division by 1). At the time of the update event, a new value of 3 (division by 4) is written to this register.
- Write a new value in TIMx_PSC : An arrow indicates the write operation to the prescaler control register at the UEV.
- Prescaler buffer : A buffer that latches the value from the prescaler control register. It initially holds 0 and updates to 3 at the UEV.
- Prescaler counter : A counter that divides the CK_PSC frequency. It counts from 0 to 3 when the division is 4. The sequence shown is 0, 1, 2, 3, 0, 1, 2, 3.
Vertical dashed lines indicate the timing relationships between the update event, the register updates, and the counter increments. The diagram is labeled MS31077V2.
22.3.2 Counting mode
The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
An update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent).
When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit):
- • The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register)
- • The auto-reload shadow register is updated with the preload value (TIMx_ARR)
The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36.
Figure 181. Counter timing diagram, internal clock divided by 1
The timing diagram illustrates the operation of a counter in counting mode. The signals shown are:
- CK_PSC : Prescaler clock signal, shown as a square wave.
- CNT_EN : Counter enable signal, which is high to enable counting.
- Timerclock = CK_CNT : Counter clock signal, which is the output of the prescaler.
- Counter register : Shows the sequence of values from 31 to 36, then 00 to 07, indicating a modulo-64 counter.
- Counter overflow : A pulse generated when the counter reaches the auto-reload value (36).
- Update event (UEV) : A pulse generated when the counter overflows.
- Update interrupt flag (UIF) : A pulse generated when the counter overflows.
The diagram shows that the counter counts from 31 to 36, then overflows to 00 and continues counting. The overflow event occurs at the transition from 36 to 00. The update event (UEV) and the update interrupt flag (UIF) are generated at the same time as the overflow.
MS31078V2
Figure 182. Counter timing diagram, internal clock divided by 2
This timing diagram illustrates the operation of a basic timer with the internal clock divided by 2. The signals shown are:
- CK_PSC : Prescaler clock signal, shown as a high-frequency square wave.
- CNT_EN : Counter enable signal, which goes high to start counting.
- Timerclock = CK_CNT : The clock signal for the counter, which is half the frequency of CK_PSC.
- Counter register : Shows the sequence of values: 0034, 0035, 0036, 0000, 0001, 0002, 0003. The values 0034, 0035, and 0036 are shown in separate segments, indicating they are captured at different clock edges.
- Counter overflow : A pulse that goes high when the counter reaches 0036 and resets to 0000.
- Update event (UEV) : A pulse that goes high when the counter overflows.
- Update interrupt flag (UIF) : A signal that goes high when the update event occurs and remains high until cleared.
Vertical dashed lines indicate the rising edges of the Timerclock (CK_CNT) that correspond to the counter value updates. The diagram is labeled MS31079V2 in the bottom right corner.
Figure 183. Counter timing diagram, internal clock divided by 4
This timing diagram illustrates the operation of a basic timer with the internal clock divided by 4. The signals shown are:
- CK_PSC : Prescaler clock signal, shown as a high-frequency square wave.
- CNT_EN : Counter enable signal, which goes high to start counting.
- Timerclock = CK_CNT : The clock signal for the counter, which is one-quarter the frequency of CK_PSC.
- Counter register : Shows the sequence of values: 0035, 0036, 0000, 0001. The values 0035 and 0036 are shown in separate segments, indicating they are captured at different clock edges.
- Counter overflow : A pulse that goes high when the counter reaches 0036 and resets to 0000.
- Update event (UEV) : A pulse that goes high when the counter overflows.
- Update interrupt flag (UIF) : A signal that goes high when the update event occurs and remains high until cleared.
Vertical dashed lines indicate the rising edges of the Timerclock (CK_CNT) that correspond to the counter value updates. The diagram is labeled MS31080V2 in the bottom right corner.
Figure 184. Counter timing diagram, internal clock divided by N
This timing diagram illustrates the operation of a timer with an internal clock divided by N. The top signal, CK_PSC, is a periodic square wave. Below it, the Timerclock = CK_CNT is shown as a series of pulses that are half the frequency of CK_PSC. The Counter register starts at value 1F, increments to 20, and then overflows to 00. The Counter overflow signal is a pulse that goes high when the counter reaches 00. The Update event (UEV) and Update interrupt flag (UIF) are also shown as pulses that go high at the overflow point. The diagram is labeled MS31081V2 in the bottom right corner.
Figure 185. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded)
This timing diagram shows the counter's behavior when ARPE = 0 and the auto-reload register is not preloaded. It includes signals for CK_PSC, CEN (Counter Enable), Timerclock = CK_CNT, Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), and the Auto-reload preload register. The counter starts at 31, increments through 32, 33, 34, 35, 36, overflows to 00, and continues through 01, 02, 03, 04, 05, 06, 07. The Counter overflow, UEV, and UIF signals are pulses that go high at the 36 to 00 transition. The Auto-reload preload register initially contains FF, and a note indicates that a new value (36) is written to TIMx_ARR at the overflow point. The diagram is labeled MS31082V2 in the bottom right corner.
Figure 186. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)
The timing diagram illustrates the operation of a basic timer when ARPE=1 and the ARR register is preloaded. The signals shown are:
- CK_PSC : Prescaler clock signal, shown as a square wave.
- CEN : Counter Enable signal. It is initially low and goes high at the first rising edge of CK_PSC.
- Timerclock = CK_CNT : Counter clock signal, which is the output of the prescaler. It starts at the second rising edge of CK_PSC.
- Counter register : Shows the counter values. It starts at F0 and increments by 1 at each rising edge of CK_CNT: F1, F2, F3, F4, F5. Upon reaching F5, it overflows to 00 and continues incrementing: 01, 02, 03, 04, 05, 06, 07.
- Counter overflow : A pulse that goes high when the counter register overflows from F5 to 00.
- Update event (UEV) : A pulse that goes high when the counter register overflows from F5 to 00.
- Update interrupt flag (UIF) : A pulse that goes high when the counter register overflows from F5 to 00.
- Auto-reload preload register : Shows the value F5 initially. When a new value (36) is written to TIMx_ARR, it updates to 36.
- Auto-reload shadow register : Shows the value F5 initially. It updates to 36 when the counter register overflows from F5 to 00.
An arrow indicates that writing a new value in TIMx_ARR updates the Auto-reload preload register. The diagram is labeled MS31083V2.
22.3.3 Clock source
The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 187 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.
Figure 187. Control circuit in normal mode, internal clock divided by 1
The timing diagram shows the following signals and their relationship:
- Internal clock: A continuous square wave.
- CEN=CNT_EN: Counter Enable. It is initially low, then goes high to start counting, and later goes low to stop counting.
- UG: Update Generation. It is initially low. When CEN goes high, UG goes high briefly to generate an update event, then returns low.
- CNT_INIT: Counter Initialization. It is initially low. When CEN goes high, CNT_INIT goes high briefly to initialize the counter, then returns low.
- Counter clock = CK_CNT = CK_PSC: The clock for the counter. It is initially low. When CEN goes high, it becomes a square wave derived from the internal clock.
- Counter register: Shows the sequence of values: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. The counter increments from 31 to 36, then overflows to 00 and continues to 07. Vertical dashed lines indicate the clock edges corresponding to these values.
MS31085V2
22.3.4 Debug mode
When the microcontroller enters the debug mode (Cortex ® -M0+ core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module. For more details, refer to Section 32.9.2: Debug support for timers, watchdog and I 2 C .
22.4 TIM6/7 registers
Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions.
The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).
22.4.1 TIM6/7 control register 1 (TIMx_CR1)
Address offset: 0x00
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ARPE | Res. | Res. | Res. | OPM | URS | UDIS | CEN |
| rw | rw | rw | rw | rw |
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 ARPE : Auto-reload preload enable
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM : One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit).
Bit 2 URS : Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generates an update interrupt or DMA request if enabled.
These events can be:
- – Counter overflow/underflow
- – Setting the UG bit
- – Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
Bit 1 UDIS : Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
- – Counter overflow/underflow
- – Setting the UG bit
- – Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN : Counter enable
0: Counter disabled
1: Counter enabled
Note: Gated mode can work only if the CEN bit has been previously set by software.
However trigger mode can set the CEN bit automatically by hardware.
CEN is cleared automatically in one-pulse mode, when an update event occurs.
22.4.2 TIM6/7 control register 2 (TIMx_CR2)
Address offset: 0x04
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MMS[2:0] | Res. | Res. | Res. | |||
| rw | rw | rw | |||||||||||||
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:4 MMS : Master mode selection
These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register).
010: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.
Bits 3:0 Reserved, must be kept at reset value.
22.4.3 TIM6/7 DMA/Interrupt enable register (TIMx_DIER)
Address offset: 0x0C
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | UDE | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UIE |
| rw | rw |
Bits 15:9 Reserved, must be kept at reset value.
Bit 8 UDE : Update DMA request enable
0: Update DMA request disabled.
1: Update DMA request enabled.
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 UIE : Update interrupt enable
0: Update interrupt disabled.
1: Update interrupt enabled.
22.4.4 TIM6/7 status register (TIMx_SR)
Address offset: 0x10
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UIF |
| rc_w0 |
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 UIF : Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
- – At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register.
- – When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register.
22.4.5 TIM6/7 event generation register (TIMx_EGR)
Address offset: 0x14
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UG |
| w |
Bits 15:1 Reserved, must be kept at reset value.
Bit 0 UG : Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected).
22.4.6 TIM6/7 counter (TIMx_CNT)
Address offset: 0x24
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| CNT[15:0] | |||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Bits 15:0 CNT[15:0] : Counter value
22.4.7 TIM6/7 prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PSC[15:0] | |||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Bits 15:0 PSC[15:0] : Prescaler value
The counter clock frequency (CK_CNT) is equal to \( f_{CK\_PSC} / (PSC[15:0] + 1) \) .
PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).
22.4.8 TIM6/7 auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0xFFFF
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ARR[15:0] | |||||||||||||||
| rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw | rw |
Bits 15:0 ARR[15:0] : Auto-reload value
ARR is the value to be loaded into the actual auto-reload register.
Refer to Section 22.3.1: Time-base unit on page 568 for more details about ARR update and behavior.
The counter is blocked while the auto-reload value is null.
22.4.9 TIM6/7 register map
TIMx registers are mapped as 16-bit addressable registers as described in the table below:
Table 98. TIM6/7 register map and reset values
| Offset | Register | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0x00 | TIMx_CR1 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | ARPE | Res. | Res. | Res. | OPM | URS | UDIS | CEN |
| Reset value | 0 | 0 | 0 | 0 | 0 | ||||||||||||
| 0x04 | TIMx_CR2 | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | MMS[2:0] | Res. | Res. | Res. | Res. | ||
| Reset value | 0 | 0 | 0 | ||||||||||||||
| 0x08 | Res. | ||||||||||||||||
| 0x0C | TIMx_DIER | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UDE | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UIE |
| Reset value | 0 | 0 | |||||||||||||||
| 0x10 | TIMx_SR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UIF |
| Reset value | 0 | ||||||||||||||||
| 0x14 | TIMx_EGR | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | Res. | UG |
| Reset value | 0 | ||||||||||||||||
| 0x18 | Res. | ||||||||||||||||
| 0x1C | Res. | ||||||||||||||||
| 0x20 | Res. | ||||||||||||||||
| 0x24 | TIMx_CNT | CNT[15:0] | |||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 0x28 | TIMx_PSC | PSC[15:0] | |||||||||||||||
| Reset value | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| 0x2C | TIMx_ARR | ARR[15:0] | |||||||||||||||
| Reset value | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Refer to Section 2.2 on page 57 for the register boundary addresses.