RM0376-STM32L0x2

Introduction

This reference manual targets application developers. It provides complete information on how to use the STM32L0x2 microcontroller memory and peripherals.

The STM32L0x2 is a line of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the corresponding datasheets.

For information on the Arm ® Cortex ® -M0+ core, refer to the Cortex ® -M0+ Technical Reference Manual .

The STM32L0x2 microcontrollers include state-of-the-art patented technology.

Contents

Unlocking/locking operations . . . . .81
Detailed description of NVM write/erase operations. . . . .84
Parallel write half-page Flash program memory. . . . .90
Status register . . . . .94
3.4    Memory protection . . . . .95
3.4.1    RDP (Read Out Protection) . . . . .96
3.4.2    PcROP (Proprietary Code Read-Out Protection) . . . . .97
3.4.3    Protections against unwanted write/erase operations . . . . .99
3.4.4    Write/erase protection management . . . . .100
3.4.5    Protection errors . . . . .101
Write protection error flag (WRPERR) . . . . .101
Read error (RDERR) . . . . .101
3.5    NVM interrupts . . . . .101
3.5.1    Hard fault . . . . .102
3.6    Memory interface management . . . . .102
3.6.1    Operation priority and evolution . . . . .102
Read . . . . .102
Write/erase . . . . .102
Option byte loading. . . . .103
3.6.2    Sequence of operations . . . . .103
Read as data while write . . . . .103
Fetch while write. . . . .103
Write while another write operation is ongoing. . . . .104
3.6.3    Change the number of wait states while reading . . . . .104
3.6.4    Power-down . . . . .104
3.7    Flash register description . . . . .105
Read registers . . . . .105
Write to registers . . . . .105
3.7.1    Access control register (FLASH_ACR) . . . . .106
3.7.2    Program and erase control register (FLASH_PECR) . . . . .107
3.7.3    Power-down key register (FLASH_PDKEYR) . . . . .111
3.7.4    PECR unlock key register (FLASH_PEKEYR) . . . . .111
3.7.5    Program and erase key register (FLASH_PRGKEYR) . . . . .111
3.7.6    Option bytes unlock key register (FLASH_OPTKEYR) . . . . .112
3.7.7    Status register (FLASH_SR) . . . . .113
3.7.8    Option bytes register (FLASH_OPTR) . . . . .115
3.7.9    Write protection register 1 (FLASH_WRPROT1) . . . . .117
3.7.10   Write protection register 2 (FLASH_WRPROT2) . . . . .118
3.7.11Flash register map . . . . .119
3.8Option bytes . . . . .120
3.8.1Option bytes description . . . . .120
3.8.2Mismatch when loading protection flags . . . . .121
3.8.3Reloading Option bytes by software . . . . .121
4Cyclic redundancy check calculation unit (CRC) . . . . .122
4.1Introduction . . . . .122
4.2CRC main features . . . . .122
4.3CRC functional description . . . . .123
4.3.1CRC block diagram . . . . .123
4.3.2CRC internal signals . . . . .123
4.3.3CRC operation . . . . .123
Polynomial programmability . . . . .124
4.4CRC registers . . . . .125
4.4.1CRC data register (CRC_DR) . . . . .125
4.4.2CRC independent data register (CRC_IDR) . . . . .125
4.4.3CRC control register (CRC_CR) . . . . .126
4.4.4CRC initial value (CRC_INIT) . . . . .127
4.4.5CRC polynomial (CRC_POL) . . . . .127
4.4.6CRC register map . . . . .128
5Firewall (FW) . . . . .129
5.1Introduction . . . . .129
5.2Firewall main features . . . . .129
5.3Firewall functional description . . . . .130
5.3.1Firewall AMBA bus snoop . . . . .130
5.3.2Functional requirements . . . . .130
Debug consideration . . . . .130
Write protection . . . . .131
Interrupts management . . . . .131
5.3.3Firewall segments . . . . .131
Code segment . . . . .131
Non-volatile data segment . . . . .131
Volatile data segment . . . . .132
5.3.4Segment accesses and properties . . . . .132
Segment access depending on the Firewall state . . . . .132
Segments properties133
5.3.5 Firewall initialization133
5.3.6 Firewall states134
Opening the Firewall135
Closing the Firewall135
5.4 Firewall registers136
5.4.1 Code segment start address (FW_CSSA)136
5.4.2 Code segment length (FW_CSL)136
5.4.3 Non-volatile data segment start address (FW_NVDSSA)137
5.4.4 Non-volatile data segment length (FW_NVDLSL)137
5.4.5 Volatile data segment start address (FW_VDSSA)138
5.4.6 Volatile data segment length (FW_VDSL)138
5.4.7 Configuration register (FW_CR)139
5.4.8 Firewall register map140
6 Power control (PWR)141
6.1 Power supplies141
6.1.1 Independent A/D and DAC converter supply and reference voltage142
On packages with V REF+ pin142
On packages without V REF+ pin142
6.1.2 RTC and RTC backup registers143
RTC registers access143
6.1.3 Voltage regulator143
6.1.4 Dynamic voltage scaling management143
Range 1144
Range 2 and 3144
6.1.5 Dynamic voltage scaling configuration145
6.1.6 Voltage regulator and clock management when VDD drops below 1.71 V145
6.1.7 Voltage regulator and clock management when modifying the VCORE range146
6.1.8 Voltage range and limitations when VDD ranges from 1.71 V to 2.0 V146
6.2 Power supply supervisor147
6.2.1 Power-on reset (POR)/power-down reset (PDR)149
6.2.2 Brown out reset (BOR)149
6.2.3 Programmable voltage detector (PVD)150
6.2.4 Internal voltage reference (VREFINT)151
6.3 Low-power modes152
6.3.1Behavior of clocks in low-power modes . . . . .153
Sleep and Low-power sleep modes . . . . .153
Stop and Standby modes . . . . .153
6.3.2Slowing down system clocks . . . . .154
6.3.3Peripheral clock gating . . . . .154
6.3.4Low-power run mode (LP run) . . . . .154
Entering Low-power run mode . . . . .154
Exiting Low-power run mode . . . . .155
6.3.5Entering low-power mode . . . . .155
6.3.6Exiting low-power mode . . . . .155
6.3.7Sleep mode . . . . .156
I/O states in Sleep mode . . . . .156
Entering Sleep mode . . . . .156
Exiting Sleep mode. . . . .156
6.3.8Low-power sleep mode (LP sleep) . . . . .157
I/O states in Low-power sleep mode . . . . .157
Entering Low-power sleep mode . . . . .157
Exiting Low-power sleep mode. . . . .158
6.3.9Stop mode . . . . .159
I/O states in Low-power sleep mode . . . . .159
Entering Stop mode . . . . .159
Exiting Stop mode . . . . .160
6.3.10Standby mode . . . . .162
I/O states in Standby mode . . . . .162
Entering Standby mode . . . . .162
Exiting Standby mode. . . . .162
Debug mode . . . . .163
6.3.11Waking up the device from Stop and Standby modes using the RTC and comparators . . . . .163
RTC auto-wakeup (AWU) from the Stop mode . . . . .164
RTC auto-wakeup (AWU) from the Standby mode. . . . .164
Comparator auto-wakeup (AWU) from the Stop mode. . . . .165
6.4Power control registers . . . . .166
6.4.1PWR power control register (PWR_CR) . . . . .166
6.4.2PWR power control/status register (PWR_CSR) . . . . .169
6.4.3PWR register map . . . . .171
7Reset and clock control (RCC) . . . . .172
7.1Reset . . . . .172
7.1.1System reset . . . . .172
Software reset . . . . .172
Low-power management reset . . . . .172
Option byte loader reset . . . . .172
7.1.2 Power reset . . . . .173
7.1.3 RTC and backup registers reset . . . . .173
7.2 Clocks . . . . .174
7.2.1 HSE clock . . . . .177
External source (HSE bypass) . . . . .178
External crystal/ceramic resonator (HSE crystal) . . . . .178
7.2.2 HSI16 clock . . . . .178
Calibration . . . . .178
7.2.3 MSI clock . . . . .179
Calibration . . . . .179
7.2.4 HSI48 clock . . . . .179
7.2.5 PLL . . . . .180
7.2.6 LSE clock . . . . .181
External source (LSE bypass) . . . . .181
7.2.7 LSI clock . . . . .181
LSI measurement . . . . .181
7.2.8 System clock (SYSCLK) selection . . . . .182
7.2.9 System clock source frequency versus voltage range . . . . .182
7.2.10 HSE clock security system (CSS) . . . . .182
7.2.11 LSE Clock Security System . . . . .183
7.2.12 RTC clock . . . . .183
7.2.13 Watchdog clock . . . . .184
7.2.14 Clock-out capability . . . . .184
7.2.15 Internal/external clock measurement using TIM21 . . . . .184
7.2.16 Clock-independent system clock sources for TIM2/TIM21/TIM22 . . . . .185
7.3 RCC registers . . . . .186
7.3.1 Clock control register (RCC_CR) . . . . .186
7.3.2 Internal clock sources calibration register (RCC_ICSCR) . . . . .189
7.3.3 Clock recovery RC register (RCC_CRRRCR) . . . . .190
7.3.4 Clock configuration register (RCC_CFGR) . . . . .191
7.3.5 Clock interrupt enable register (RCC_CIER) . . . . .193
7.3.6 Clock interrupt flag register (RCC_CIFR) . . . . .195
7.3.7 Clock interrupt clear register (RCC_CICR) . . . . .196
7.3.8 GPIO reset register (RCC_IOPRSTR) . . . . .197
7.3.9 AHB peripheral reset register (RCC_AHBRSTR) . . . . .198
7.3.10APB2 peripheral reset register (RCC_APB2RSTR) . . . . .199
7.3.11APB1 peripheral reset register (RCC_APB1RSTR) . . . . .200
7.3.12GPIO clock enable register (RCC_IOPENR) . . . . .203
7.3.13AHB peripheral clock enable register (RCC_AHBENR) . . . . .204
7.3.14APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .206
7.3.15APB1 peripheral clock enable register (RCC_APB1ENR) . . . . .208
7.3.16GPIO clock enable in Sleep mode register (RCC_IOPSMENR) . . . . .211
7.3.17AHB peripheral clock enable in Sleep mode register (RCC_AHBSMENR) . . . . .212
7.3.18APB2 peripheral clock enable in Sleep mode register (RCC_APB2SMENR) . . . . .213
7.3.19APB1 peripheral clock enable in Sleep mode register (RCC_APB1SMENR) . . . . .214
7.3.20Clock configuration register (RCC_CCIPR) . . . . .216
7.3.21Control/status register (RCC_CSR) . . . . .217
7.3.22RCC register map . . . . .221
8Clock recovery system (CRS) . . . . .224
8.1Introduction . . . . .224
8.2CRS main features . . . . .224
8.3CRS implementation . . . . .224
8.4CRS functional description . . . . .225
8.4.1CRS block diagram . . . . .225
8.4.2Synchronization input . . . . .225
8.4.3Frequency error measurement . . . . .226
8.4.4Frequency error evaluation and automatic trimming . . . . .226
8.4.5CRS initialization and configuration . . . . .227
RELOAD value . . . . .227
FELIM value . . . . .227
8.5CRS low-power modes . . . . .228
8.6CRS interrupts . . . . .228
8.7CRS registers . . . . .229
8.7.1CRS control register (CRS_CR) . . . . .229
8.7.2CRS configuration register (CRS_CFGR) . . . . .230
8.7.3CRS interrupt and status register (CRS_ISR) . . . . .231
8.7.4CRS interrupt flag clear register (CRS_ICR) . . . . .233
8.7.5CRS register map . . . . .233
9General-purpose I/Os (GPIO) . . . . .235
9.1Introduction . . . . .235
9.2GPIO main features . . . . .235
9.3GPIO functional description . . . . .235
9.3.1General-purpose I/O (GPIO) . . . . .237
9.3.2I/O pin alternate function multiplexer and mapping . . . . .238
9.3.3I/O port control registers . . . . .239
9.3.4I/O port data registers . . . . .239
9.3.5I/O data bitwise handling . . . . .239
9.3.6GPIO locking mechanism . . . . .239
9.3.7I/O alternate function input/output . . . . .240
9.3.8External interrupt/wakeup lines . . . . .240
9.3.9Input configuration . . . . .240
9.3.10Output configuration . . . . .241
9.3.11Alternate function configuration . . . . .242
9.3.12Analog configuration . . . . .243
9.3.13Using the HSE or LSE oscillator pins as GPIOs . . . . .243
9.3.14Using the GPIO pins in the RTC supply domain . . . . .243
9.4GPIO registers . . . . .244
9.4.1GPIO port mode register (GPIOx_MODER)
(x = A to E and H) . . . . .		244
9.4.2GPIO port output type register (GPIOx_OTYPER)
(x = A to E and H) . . . . .		244
9.4.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to E and H) . . . . .		245
9.4.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to E and H) . . . . .		245
9.4.5GPIO port input data register (GPIOx_IDR)
(x = A to E and H) . . . . .		246
9.4.6GPIO port output data register (GPIOx_ODR)
(x = A to E and H) . . . . .		246
9.4.7GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to E and H) . . . . .		247
9.4.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to E and H) . . . . .		247
9.4.9GPIO alternate function low register (GPIOx_AFRL)
(x = A to E and H) . . . . .		248
9.4.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to E and H) . . . . .		249
11.4.5DMA data width, alignment and endianness . . . . .270
Addressing AHB peripherals not supporting byte/half-word write transfers . . .271
11.4.6DMA error management . . . . .272
11.5DMA interrupts . . . . .272
11.6DMA registers . . . . .272
11.6.1DMA interrupt status register (DMA_ISR) . . . . .273
11.6.2DMA interrupt flag clear register (DMA_IFCR) . . . . .275
11.6.3DMA channel x configuration register (DMA_CCRx) . . . . .276
11.6.4DMA channel x number of data to transfer register (DMA_CNDTRx) . . . . .279
11.6.5DMA channel x peripheral address register (DMA_CPARx) . . . . .280
11.6.6DMA channel x memory address register (DMA_CMARx) . . . . .280
11.6.7DMA channel selection register (DMA_CSELR) . . . . .282
11.6.8DMA register map . . . . .282
12Nested vectored interrupt controller (NVIC) . . . . .285
12.1Main features . . . . .285
12.2SysTick calibration value register . . . . .285
12.3Interrupt and exception vectors . . . . .285
13Extended interrupt and event controller (EXTI) . . . . .288
13.1Introduction . . . . .288
13.2EXTI main features . . . . .288
13.3EXTI functional description . . . . .288
13.3.1EXTI block diagram . . . . .289
13.3.2Wakeup event management . . . . .289
13.3.3Peripherals asynchronous interrupts . . . . .290
13.3.4Hardware interrupt selection . . . . .290
13.3.5Hardware event selection . . . . .290
13.3.6Software interrupt/event selection . . . . .290
13.4EXTI interrupt/event line mapping . . . . .291
13.5EXTI registers . . . . .293
13.5.1EXTI interrupt mask register (EXTI_IMR) . . . . .293
13.5.2EXTI event mask register (EXTI_EMR) . . . . .293
13.5.3EXTI rising edge trigger selection register (EXTI_RTSR) . . . . .294
13.5.4Falling edge trigger selection register (EXTI_FTSR) . . . . .295
13.5.5EXTI software interrupt event register (EXTI_SWIER) . . . . .295
13.5.6EXTI pending register (EXTI_PR) . . . . .296
13.5.7EXTI register map . . . . .297
14Analog-to-digital converter (ADC) . . . . .298
14.1Introduction . . . . .298
14.2ADC main features . . . . .299
14.3ADC functional description . . . . .300
14.3.1ADC pins and internal signals . . . . .300
14.3.2ADC voltage regulator (ADVREGEN) . . . . .301
Analog reference for the ADC internal voltage regulator . . . . .301
ADVREG enable sequence . . . . .302
ADVREG disable sequence . . . . .302
14.3.3Calibration (ADCAL) . . . . .302
Calibration factor forcing software procedure . . . . .304
14.3.4ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .304
14.3.5ADC clock (CKMODE, PRESC[3:0], LFMEN) . . . . .305
Low frequency . . . . .306
14.3.6ADC connectivity . . . . .307
14.3.7Configuring the ADC . . . . .308
14.3.8Channel selection (CHSEL, SCANDIR) . . . . .308
Temperature sensor, V REFINT internal channels . . . . .308
14.3.9Programmable sampling time (SMP) . . . . .309
14.3.10Single conversion mode (CONT = 0) . . . . .309
14.3.11Continuous conversion mode (CONT = 1) . . . . .310
14.3.12Starting conversions (ADSTART) . . . . .310
14.3.13Timings . . . . .311
14.3.14Stopping an ongoing conversion (ADSTP) . . . . .312
14.4Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . . . . .312
14.4.1Discontinuous mode (DISCEN) . . . . .313
14.4.2Programmable resolution (RES) - Fast conversion mode . . . . .313
14.4.3End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . .314
14.4.4End of conversion sequence (EOS flag) . . . . .314
14.4.5Example timing diagrams (single/continuous modes
hardware/software triggers) . . . . .		315
14.5Data management . . . . .317
14.5.1Data register and data alignment (ADC_DR, ALIGN) . . . . .317
14.5.2ADC overrun (OVR, OVRMOD) . . . . .317
14.5.3Managing a sequence of data converted without using the DMA . . . . .318
14.5.4Managing converted data without using the DMA without overrun . . .318
14.5.5Managing converted data using the DMA . . . . .318
DMA one shot mode (DMACFG = 0) . . . . .319
DMA circular mode (DMACFG = 1) . . . . .319
14.6Low-power features . . . . .320
14.6.1Wait mode conversion . . . . .320
14.6.2Auto-off mode (AUTOFF) . . . . .321
14.7Analog window watchdog (AWDEN, AWDSGL, AWDCH,
ADC_TR) . . . . .		322
14.7.1Description of the analog watchdog . . . . .322
14.7.2ADC_AWD1_OUT output signal generation . . . . .323
14.7.3Analog watchdog threshold control . . . . .325
14.8Oversampler . . . . .326
14.8.1ADC operating modes supported when oversampling . . . . .328
14.8.2Analog watchdog . . . . .328
14.8.3Triggered mode . . . . .328
14.9Temperature sensor and internal reference voltage . . . . .329
Main features . . . . .330
Reading the temperature . . . . .330
Calculating the actual V DDA voltage using the internal reference voltage . . . . .331
Converting a supply-relative ADC measurement to an absolute voltage value . . . . .331
14.10ADC interrupts . . . . .332
14.11ADC registers . . . . .333
14.11.1ADC interrupt and status register (ADC_ISR) . . . . .333
14.11.2ADC interrupt enable register (ADC_IER) . . . . .334
14.11.3ADC control register (ADC_CR) . . . . .336
14.11.4ADC configuration register 1 (ADC_CFGR1) . . . . .338
14.11.5ADC configuration register 2 (ADC_CFGR2) . . . . .342
14.11.6ADC sampling time register (ADC_SMPR) . . . . .343
14.11.7ADC watchdog threshold register (ADC_TR) . . . . .344
14.11.8ADC channel selection register (ADC_CHSELR) . . . . .344
14.11.9ADC data register (ADC_DR) . . . . .345
14.11.10ADC Calibration factor (ADC_CALFACT) . . . . .345
14.11.11ADC common configuration register (ADC_CCR) . . . . .346
14.12ADC register map . . . . .347
15Digital-to-analog converter (DAC) . . . . .349
15.1Introduction . . . . .349
15.2DAC1 main features . . . . .349
15.3DAC output buffer enable . . . . .351
15.4DAC channel enable . . . . .351
15.5Single mode functional description . . . . .351
15.5.1DAC data format . . . . .351
15.5.2DAC channel conversion . . . . .351
Independent trigger with single LFSR generation . . . . .352
Independent trigger with single triangle generation . . . . .352
15.5.3DAC output voltage . . . . .353
15.5.4DAC trigger selection . . . . .353
15.6Dual-mode functional description . . . . .354
15.6.1DAC data format . . . . .354
15.6.2DAC channel conversion in dual mode . . . . .354
15.6.3Description of dual conversion modes . . . . .354
Independent trigger without wave generation. . . . .355
Independent trigger with single LFSR generation . . . . .355
Independent trigger with different LFSR generation. . . . .355
Independent trigger with single triangle generation . . . . .356
Independent trigger with different triangle generation . . . . .356
Simultaneous software start . . . . .356
Simultaneous trigger without wave generation. . . . .356
Simultaneous trigger with single LFSR generation. . . . .357
Simultaneous trigger with different LFSR generation . . . . .357
Simultaneous trigger with single triangle generation . . . . .357
Simultaneous trigger with different triangle generation . . . . .358
15.6.4DAC output voltage . . . . .358
15.6.5DAC trigger selection . . . . .358
15.7Noise generation . . . . .358
15.8Triangle-wave generation . . . . .359
15.9DMA request . . . . .360
DMA underrun . . . . .360
15.10DAC registers . . . . .361
15.10.1DAC control register (DAC_CR) . . . . .361
15.10.2DAC software trigger register (DAC_SWTRIGR) . . . . .365
15.10.3DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . .		365
15.10.4DAC channel1 12-bit left-aligned data holding register (DAC_DHR12L1) .....366
15.10.5DAC channel1 8-bit right-aligned data holding register (DAC_DHR8R1) .....366
15.10.6DAC channel2 12-bit right-aligned data holding register (DAC_DHR12R2) .....366
15.10.7DAC channel2 12-bit left-aligned data holding register (DAC_DHR12L2) .....367
15.10.8DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) .....367
15.10.9Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) .....368
15.10.10Dual DAC 12-bit left-aligned data holding register (DAC_DHR12LD) .....368
15.10.11Dual DAC 8-bit right-aligned data holding register (DAC_DHR8RD) .....368
15.10.12DAC channel1 data output register (DAC_DOR1) .....369
15.10.13DAC channel2 data output register (DAC_DOR2) .....369
15.10.14DAC status register (DAC_SR) .....369
15.10.15DAC register map .....371
16Comparator (COMP) .....373
16.1Introduction .....373
16.2COMP main features .....373
16.3COMP functional description .....374
16.3.1COMP block diagram .....374
16.3.2COMP pins and internal signals .....374
16.3.3COMP reset and clocks .....375
16.3.4Comparator LOCK mechanism .....375
16.3.5Power mode .....375
16.4COMP interrupts .....375
16.5COMP registers .....375
16.5.1Comparator 1 control and status register (COMP1_CSR) .....375
16.5.2Comparator 2 control and status register (COMP2_CSR) .....377
16.5.3COMP register map .....379
17Touch sensing controller (TSC) .....380
17.1Introduction .....380
17.2TSC main features .....380
17.3TSC functional description . . . . .381
17.3.1TSC block diagram . . . . .381
17.3.2Surface charge transfer acquisition overview . . . . .381
17.3.3Reset and clocks . . . . .383
17.3.4Charge transfer acquisition sequence . . . . .384
17.3.5Spread spectrum feature . . . . .385
17.3.6Max count error . . . . .385
17.3.7Sampling capacitor I/O and channel I/O mode selection . . . . .386
17.3.8Acquisition mode . . . . .387
17.3.9I/O hysteresis and analog switch control . . . . .387
17.4TSC low-power modes . . . . .388
17.5TSC interrupts . . . . .388
17.6TSC registers . . . . .389
17.6.1TSC control register (TSC_CR) . . . . .389
17.6.2TSC interrupt enable register (TSC_IER) . . . . .391
17.6.3TSC interrupt clear register (TSC_ICR) . . . . .392
17.6.4TSC interrupt status register (TSC_ISR) . . . . .393
17.6.5TSC I/O hysteresis control register (TSC_IOHCR) . . . . .393
17.6.6TSC I/O analog switch control register
(TSC_IOASCR) . . . . .		394
17.6.7TSC I/O sampling control register (TSC_IOSCR) . . . . .394
17.6.8TSC I/O channel control register (TSC_IOCCR) . . . . .395
17.6.9TSC I/O group control status register (TSC_IOGCSR) . . . . .395
17.6.10TSC I/O group x counter register (TSC_IOGxCR) . . . . .396
17.6.11TSC register map . . . . .397
18AES hardware accelerator (AES) . . . . .399
18.1Introduction . . . . .399
18.2AES main features . . . . .399
18.3AES implementation . . . . .400
18.4AES functional description . . . . .400
18.4.1AES block diagram . . . . .400
18.4.2AES internal signals . . . . .400
18.4.3AES cryptographic core . . . . .401
Overview. . . . .401
Typical data processing . . . . .401
Chaining modes . . . . .401
Electronic codebook (ECB) mode . . . . .402
Cipher block chaining (CBC) mode . . . . .403
Counter (CTR) mode . . . . .404
18.4.4 AES procedure to perform a cipher operation . . . . .404
Introduction. . . . .404
Initialization of AES. . . . .405
Data append . . . . .405
18.4.5 AES decryption key preparation . . . . .407
18.4.6 AES ciphertext stealing and data padding . . . . .408
18.4.7 AES task suspend and resume . . . . .408
18.4.8 AES basic chaining modes (ECB, CBC) . . . . .409
Overview. . . . .409
ECB/CBC encryption sequence . . . . .412
ECB/CBC decryption sequence . . . . .412
Suspend/resume operations in ECB/CBC modes . . . . .413
Alternative single ECB/CBC decryption using Mode 4 . . . . .414
18.4.9 AES counter (CTR) mode . . . . .414
Overview. . . . .414
CTR encryption and decryption . . . . .415
Suspend/resume operations in CTR mode . . . . .417
18.4.10 AES data registers and data swapping . . . . .417
Data input and output . . . . .417
Data swapping . . . . .417
Data padding . . . . .419
18.4.11 AES key registers . . . . .419
18.4.12 AES initialization vector registers . . . . .419
18.4.13 AES DMA interface . . . . .419
Data input using DMA. . . . .420
Data output using DMA . . . . .420
DMA operation in different operating modes . . . . .421
18.4.14 AES error management . . . . .422
Read error flag (RDERR) . . . . .422
Write error flag (WDERR). . . . .422
18.5 AES interrupts . . . . .422
18.6 AES processing latency . . . . .423
18.7 AES registers . . . . .424
18.7.1 AES control register (AES_CR) . . . . .424
18.7.2 AES status register (AES_SR) . . . . .426
18.7.3 AES data input register (AES_DINR) . . . . .427

19 True random number generator (RNG) . . . . . 433

19.6.3Data collection .....440
19.7RNG registers .....440
19.7.1RNG control register (RNG_CR) .....440
19.7.2RNG status register (RNG_SR) .....442
19.7.3RNG data register (RNG_DR) .....443
19.7.4RNG register map .....443
20General-purpose timers (TIM2/TIM3) .....444
20.1TIM2/TIM3 introduction .....444
20.2TIM2/TIM3 main features .....444
20.3TIM2/TIM3 functional description .....446
20.3.1Time-base unit .....446
Prescaler description .....446
20.3.2Counter modes .....448
Upcounting mode .....448
Downcounting mode .....451
Center-aligned mode (up/down counting) .....454
20.3.3Clock selection .....458
Internal clock source (CK_INT) .....458
External clock source mode 1 .....459
External clock source mode 2 .....461
20.3.4Capture/compare channels .....462
20.3.5Input capture mode .....464
20.3.6PWM input mode .....466
20.3.7Forced output mode .....467
20.3.8Output compare mode .....467
20.3.9PWM mode .....468
PWM edge-aligned mode .....469
Downcounting configuration .....470
PWM center-aligned mode .....470
20.3.10One-pulse mode .....472
Particular case: OCx fast enable: .....473
20.3.11Clearing the OCxREF signal on an external event .....473
20.3.12Encoder interface mode .....474
20.3.13Timer input XOR function .....476
20.3.14Timers and external trigger synchronization .....477
Slave mode: Reset mode .....477
Slave mode: Gated mode .....478

21 General-purpose timers (TIM21/22) . . . . . 512

21.2TIM21/22 main features . . . . .512
21.2.1TIM21/22 main features . . . . .512
21.3TIM21/22 functional description . . . . .514
21.3.1Timebase unit . . . . .514
Prescaler description . . . . .514
21.3.2Counter modes . . . . .516
Upcounting mode . . . . .516
Downcounting mode . . . . .520
Center-aligned mode (up/down counting) . . . . .523
21.3.3Clock selection . . . . .527
Internal clock source (CK_INT) . . . . .527
External clock source mode 2 . . . . .529
21.3.4Capture/compare channels . . . . .530
21.3.5Input capture mode . . . . .532
21.3.6PWM input mode . . . . .534
21.3.7Forced output mode . . . . .535
21.3.8Output compare mode . . . . .535
21.3.9PWM mode . . . . .536
PWM center-aligned mode . . . . .538
Hints on using center-aligned mode . . . . .539
21.3.10Clearing the OCxREF signal on an external event . . . . .539
21.3.11One-pulse mode . . . . .540
Particular case: OCx fast enable . . . . .542
21.3.12Encoder interface mode . . . . .542
21.3.13TIM21/22 external trigger synchronization . . . . .544
Slave mode: Reset mode . . . . .544
Slave mode: Gated mode . . . . .545
Slave mode: Trigger mode . . . . .546
21.3.14Timer synchronization (TIM21/22) . . . . .547
21.3.15Debug mode . . . . .547
21.4TIM21/22 registers . . . . .548
21.4.1TIM21/22 control register 1 (TIMx_CR1) . . . . .548
21.4.2TIM21/22 control register 2 (TIMx_CR2) . . . . .550
21.4.3TIM21/22 slave mode control register (TIMx_SMCR) . . . . .551
21.4.4TIM21/22 Interrupt enable register (TIMx_DIER) . . . . .554
21.4.5TIM21/22 status register (TIMx_SR) . . . . .554
21.4.6TIM21/22 event generation register (TIMx_EGR) . . . . .556
21.4.7TIM21/22 capture/compare mode register 1 (TIMx_CCMR1) . . . . .557
Output compare mode . . . . .557
Input capture mode. . . . .559
21.4.8 TIM21/22 capture/compare enable register (TIMx_CCER) . . . . .560
21.4.9 TIM21/22 counter (TIMx_CNT) . . . . .561
21.4.10 TIM21/22 prescaler (TIMx_PSC) . . . . .561
21.4.11 TIM21/22 auto-reload register (TIMx_ARR) . . . . .561
21.4.12 TIM21/22 capture/compare register 1 (TIMx_CCR1) . . . . .562
21.4.13 TIM21/22 capture/compare register 2 (TIMx_CCR2) . . . . .562
21.4.14 TIM21 option register (TIM21_OR) . . . . .563
21.4.15 TIM22 option register (TIM22_OR) . . . . .564
21.4.16 TIM21/22 register map . . . . .565
22 Basic timers (TIM6/7) . . . . .567
22.1 Introduction . . . . .567
22.2 TIM6/7 main features . . . . .567
22.3 TIM6/7 functional description . . . . .568
22.3.1 Time-base unit . . . . .568
Prescaler description . . . . .568
22.3.2 Counting mode . . . . .570
22.3.3 Clock source . . . . .573
22.3.4 Debug mode . . . . .574
22.4 TIM6/7 registers . . . . .575
22.4.1 TIM6/7 control register 1 (TIMx_CR1) . . . . .575
22.4.2 TIM6/7 control register 2 (TIMx_CR2) . . . . .576
22.4.3 TIM6/7 DMA/Interrupt enable register (TIMx_DIER) . . . . .576
22.4.4 TIM6/7 status register (TIMx_SR) . . . . .577
22.4.5 TIM6/7 event generation register (TIMx_EGR) . . . . .577
22.4.6 TIM6/7 counter (TIMx_CNT) . . . . .577
22.4.7 TIM6/7 prescaler (TIMx_PSC) . . . . .578
22.4.8 TIM6/7 auto-reload register (TIMx_ARR) . . . . .578
22.4.9 TIM6/7 register map . . . . .579
23 Low-power timer (LPTIM) . . . . .580
23.1 Introduction . . . . .580
23.2 LPTIM main features . . . . .580
23.3 LPTIM implementation . . . . .581
23.4 LPTIM functional description . . . . .581
23.4.1LPTIM block diagram . . . . .581
23.4.2LPTIM trigger mapping . . . . .582
23.4.3LPTIM reset and clocks . . . . .582
23.4.4Glitch filter . . . . .582
23.4.5Prescaler . . . . .583
23.4.6Trigger multiplexer . . . . .584
23.4.7Operating mode . . . . .584
One-shot mode . . . . .584
Continous mode . . . . .585
23.4.8Timeout function . . . . .586
23.4.9Waveform generation . . . . .586
23.4.10Register update . . . . .587
23.4.11Counter mode . . . . .588
23.4.12Timer enable . . . . .589
23.4.13Encoder mode . . . . .589
23.4.14Debug mode . . . . .590
23.5LPTIM low-power modes . . . . .590
23.6LPTIM interrupts . . . . .591
23.7LPTIM registers . . . . .591
23.7.1LPTIM interrupt and status register (LPTIM_ISR) . . . . .592
23.7.2LPTIM interrupt clear register (LPTIM_ICR) . . . . .593
23.7.3LPTIM interrupt enable register (LPTIM_IER) . . . . .593
23.7.4LPTIM configuration register (LPTIM_CFGGR) . . . . .594
23.7.5LPTIM control register (LPTIM_CR) . . . . .597
23.7.6LPTIM compare register (LPTIM_CMP) . . . . .598
23.7.7LPTIM autoreload register (LPTIM_ARR) . . . . .599
23.7.8LPTIM counter register (LPTIM_CNT) . . . . .599
23.7.9LPTIM register map . . . . .600
24Independent watchdog (IWDG) . . . . .601
24.1Introduction . . . . .601
24.2IWDG main features . . . . .601
24.3IWDG functional description . . . . .601
24.3.1IWDG block diagram . . . . .601
24.3.2Window option . . . . .602
Configuring the IWDG when the window option is enabled . . . . .602
Configuring the IWDG when the window option is disabled . . . . .602
24.3.3Hardware watchdog . . . . .603
24.3.4Register access protection . . . . .603
24.3.5Debug mode . . . . .603
24.4IWDG registers . . . . .604
24.4.1IWDG key register (IWDG_KR) . . . . .604
24.4.2IWDG prescaler register (IWDG_PR) . . . . .605
24.4.3IWDG reload register (IWDG_RLR) . . . . .606
24.4.4IWDG status register (IWDG_SR) . . . . .607
24.4.5IWDG window register (IWDG_WINR) . . . . .608
24.4.6IWDG register map . . . . .609
25System window watchdog (WWDG) . . . . .610
25.1Introduction . . . . .610
25.2WWDG main features . . . . .610
25.3WWDG functional description . . . . .610
25.3.1WWDG block diagram . . . . .611
25.3.2Enabling the watchdog . . . . .611
25.3.3Controlling the down-counter . . . . .611
25.3.4How to program the watchdog timeout . . . . .611
25.3.5Debug mode . . . . .613
25.4WWDG interrupts . . . . .613
25.5WWDG registers . . . . .613
25.5.1WWDG control register (WWDG_CR) . . . . .613
25.5.2WWDG configuration register (WWDG_CFR) . . . . .614
25.5.3WWDG status register (WWDG_SR) . . . . .614
25.5.4WWDG register map . . . . .615
26Real-time clock (RTC) . . . . .616
26.1Introduction . . . . .616
26.2RTC main features . . . . .617
26.3RTC implementation . . . . .617
26.4RTC functional description . . . . .618
26.4.1RTC block diagram . . . . .618
26.4.2GPIOs controlled by the RTC . . . . .619
26.4.3Clock and prescalers . . . . .620
26.4.4Real-time clock and calendar . . . . .621
26.4.5Programmable alarms . . . . .622
26.4.6Periodic auto-wakeup . . . . .622
26.4.7RTC initialization and configuration . . . . .623
RTC register access . . . . .623
RTC register write protection . . . . .623
Calendar initialization and configuration . . . . .623
Daylight saving time . . . . .624
Programming the alarm . . . . .624
Programming the wakeup timer . . . . .624
26.4.8Reading the calendar . . . . .624
When BYPSHAD control bit is cleared in the RTC_CR register. . . . .624
When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow registers) . . . . .625
26.4.9Resetting the RTC . . . . .625
26.4.10RTC synchronization . . . . .626
26.4.11RTC reference clock detection . . . . .626
26.4.12RTC smooth digital calibration . . . . .627
Calibration when PREDIV_A<3 . . . . .628
Verifying the RTC calibration . . . . .628
Re-calibration on-the-fly . . . . .629
26.4.13Time-stamp function . . . . .629
26.4.14Tamper detection . . . . .630
RTC backup registers . . . . .630
Tamper detection initialization . . . . .630
Trigger output generation on tamper event . . . . .631
Timestamp on tamper event . . . . .631
Edge detection on tamper inputs . . . . .631
Level detection with filtering on RTC_TAMPx inputs . . . . .631
26.4.15Calibration clock output . . . . .632
26.4.16Alarm output . . . . .632
Alarm output . . . . .632
26.5RTC low-power modes . . . . .633
26.6RTC interrupts . . . . .633
26.7RTC registers . . . . .634
26.7.1RTC time register (RTC_TR) . . . . .634
26.7.2RTC date register (RTC_DR) . . . . .635
26.7.3RTC control register (RTC_CR) . . . . .636
26.7.4RTC initialization and status register (RTC_ISR) . . . . .639
26.7.5RTC prescaler register (RTC_PRER) . . . . .642

27 Inter-integrated circuit (I2C) interface . . . . . 660

27.4.9I2C slave mode . . . . .673
I2C slave initialization . . . . .673
Slave clock stretching (NOSTRETCH = 0). . . . .674
Slave without clock stretching (NOSTRETCH = 1). . . . .674
Slave byte control mode . . . . .675
Slave transmitter . . . . .676
Slave receiver . . . . .680
27.4.10I2C master mode . . . . .682
I2C master initialization . . . . .682
Master communication initialization (address phase). . . . .684
Initialization of a master receiver addressing a 10-bit address slave . . . . .685
Master transmitter . . . . .686
Master receiver . . . . .690
27.4.11I2C_TIMINGR register configuration examples . . . . .694
27.4.12SMBus specific features . . . . .695
Introduction. . . . .695
Bus protocols . . . . .695
Address resolution protocol (ARP). . . . .695
Received command and data acknowledge control . . . . .696
Host notify protocol . . . . .696
SMBus alert . . . . .696
Packet error checking . . . . .696
Timeouts . . . . .696
Bus idle detection . . . . .698
27.4.13SMBus initialization . . . . .698
Received command and data acknowledge control (Slave mode). . . . .698
Specific address (Slave mode). . . . .698
Packet error checking . . . . .698
Timeout detection . . . . .699
Bus idle detection . . . . .699
27.4.14SMBus: I2C_TIMEOUTR register configuration examples . . . . .700
27.4.15SMBus slave mode . . . . .700
SMBus slave transmitter . . . . .700
SMBus Slave receiver . . . . .702
SMBus master transmitter . . . . .704
SMBus master receiver . . . . .706
27.4.16Wakeup from Stop mode on address match . . . . .708
27.4.17Error conditions . . . . .708
Bus error (BERR) . . . . .708
Arbitration lost (ARLO) . . . . .709
Overrun/underrun error (OVR) . . . . .709

28 Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . . 729

Start bit detection . . . . .739
Character reception . . . . .740
Break character . . . . .740
Idle character . . . . .740
Overrun error . . . . .741
Selecting the proper oversampling method . . . . .741
Framing error . . . . .743
Configurable stop bits during reception . . . . .744
28.5.4 USART baud rate generation . . . . .744
How to derive USARTDIV from USART_BRR register values . . . . .745
28.5.5 Tolerance of the USART receiver to clock deviation . . . . .746
28.5.6 USART auto baud rate detection . . . . .748
28.5.7 Multiprocessor communication using USART . . . . .749
Idle line detection (WAKE=0) . . . . .750
4-bit/7-bit address mark detection (WAKE=1) . . . . .750
28.5.8 Modbus communication using USART . . . . .751
Modbus/RTU . . . . .751
Modbus/ASCII . . . . .751
28.5.9 USART parity control . . . . .752
Even parity . . . . .752
Odd parity . . . . .752
Parity checking in reception . . . . .752
Parity generation in transmission . . . . .752
28.5.10 USART LIN (local interconnection network) mode . . . . .753
LIN transmission . . . . .753
LIN reception . . . . .753
28.5.11 USART synchronous mode . . . . .755
28.5.12 USART Single-wire Half-duplex communication . . . . .758
28.5.13 USART Smartcard mode . . . . .758
Block mode (T=1) . . . . .761
Direct and inverse convention . . . . .762
28.5.14 USART IrDA SIR ENDEC block . . . . .763
IrDA low-power mode . . . . .764
28.5.15 USART continuous communication in DMA mode . . . . .765
Transmission using DMA . . . . .765
Reception using DMA . . . . .766
Error flagging and interrupt generation in multibuffer communication . . . . .767
28.5.16 RS232 hardware flow control and RS485 driver enable using USART . . . . .767
RS232 RTS flow control . . . . .768
RS232 CTS flow control . . . . .768
RS485 Driver Enable . . . . .769
28.5.17 Wakeup from Stop mode using USART . . . . .769
Using Mute mode with Stop mode . . . . .770
Determining the maximum USART baud rate allowing to wakeup correctly from Stop mode when the USART clock source is the HSI clock. . . . .770
28.6 USART in low-power modes . . . . .771
28.7 USART interrupts . . . . .771
28.8 USART registers . . . . .773
28.8.1 USART control register 1 (USART_CR1) . . . . .773
28.8.2 USART control register 2 (USART_CR2) . . . . .776
28.8.3 USART control register 3 (USART_CR3) . . . . .780
28.8.4 USART baud rate register (USART_BRR) . . . . .784
28.8.5 USART guard time and prescaler register (USART_GTPR) . . . . .784
28.8.6 USART receiver timeout register (USART_RTOR) . . . . .785
28.8.7 USART request register (USART_RQR) . . . . .786
28.8.8 USART interrupt and status register (USART_ISR) . . . . .787
28.8.9 USART interrupt flag clear register (USART_ICR) . . . . .792
28.8.10 USART receive data register (USART_RDR) . . . . .793
28.8.11 USART transmit data register (USART_TDR) . . . . .793
28.8.12 USART register map . . . . .794
29 Low-power universal asynchronous receiver transmitter (LPUART) . . . . .796
29.1 Introduction . . . . .796
29.2 LPUART main features . . . . .797
29.3 LPUART implementation . . . . .797
29.4 LPUART functional description . . . . .798
29.4.1 LPUART character description . . . . .800
29.4.2 LPUART transmitter . . . . .802
Character transmission. . . . .802
Single byte communication. . . . .803
Break characters . . . . .804
Idle characters . . . . .804
29.4.3 LPUART receiver . . . . .804
Start bit detection . . . . .804
Character reception . . . . .805
Break character . . . . .805
Idle character . . . . .805
Overrun error . . . . .806
Selecting the clock source . . . . .806
Framing error . . . . .807
Configurable stop bits during reception . . . . .807
29.4.4 LPUART baud rate generation . . . . .807
29.4.5 Tolerance of the LPUART receiver to clock deviation . . . . .809
29.4.6 Multiprocessor communication using LPUART . . . . .810
Idle line detection (WAKE=0) . . . . .810
4-bit/7-bit address mark detection (WAKE=1) . . . . .811
29.4.7 LPUART parity control . . . . .812
Even parity . . . . .812
Odd parity . . . . .812
Parity checking in reception . . . . .813
Parity generation in transmission . . . . .813
29.4.8 Single-wire Half-duplex communication using LPUART . . . . .813
29.4.9 Continuous communication in DMA mode using LPUART . . . . .813
Transmission using DMA . . . . .814
Reception using DMA . . . . .815
Error flagging and interrupt generation in multibuffer communication . . . . .816
29.4.10 RS232 Hardware flow control and RS485 Driver Enable using LPUART . . . . .816
RS232 RTS flow control . . . . .817
RS232 CTS flow control . . . . .817
RS485 Driver Enable . . . . .818
29.4.11 Wakeup from Stop mode using LPUART . . . . .819
Using Mute mode with Stop mode . . . . .820
Determining the maximum LPUART baud rate allowing to wakeup correctly from Stop mode when the LPUART clock source is the HSI clock . . . . .820
29.5 LPUART in low-power mode . . . . .821
29.6 LPUART interrupts . . . . .821
29.7 LPUART registers . . . . .823
29.7.1 Control register 1 (LPUART_CR1) . . . . .823
29.7.2 Control register 2 (LPUART_CR2) . . . . .826
29.7.3 Control register 3 (LPUART_CR3) . . . . .828
29.7.4 Baud rate register (LPUART_BRR) . . . . .830
29.7.5 Request register (LPUART_RQR) . . . . .830
29.7.6 Interrupt & status register (LPUART_ISR) . . . . .831
29.7.7 Interrupt flag clear register (LPUART_ICR) . . . . .834

30 Serial peripheral interface/ inter-IC sound (SPI/I2S) . . . . . 838

TI mode frame format error (FRE) . . . . .857
30.4 SPI special features . . . . .857
30.4.1 TI mode . . . . .857
TI protocol in master mode. . . . .857
30.4.2 CRC calculation . . . . .858
CRC principle . . . . .858
CRC transfer managed by CPU . . . . .858
CRC transfer managed by DMA. . . . .859
Resetting the SPIx_TXCRC and SPIx_RXCRC values . . . . .859
30.5 SPI interrupts . . . . .860
30.6 I 2 S functional description . . . . .861
30.6.1 I 2 S general description . . . . .861
30.6.2 I 2 S full-duplex . . . . .862
30.6.3 Supported audio protocols . . . . .863
I 2 S Philips standard . . . . .864
MSB justified standard . . . . .866
LSB justified standard. . . . .867
PCM standard. . . . .869
30.6.4 Clock generator . . . . .870
30.6.5 I 2 S master mode . . . . .872
Procedure. . . . .872
Transmission sequence . . . . .872
Reception sequence . . . . .873
30.6.6 I 2 S slave mode . . . . .874
Transmission sequence . . . . .874
Reception sequence . . . . .875
30.6.7 I 2 S status flags . . . . .875
Busy flag (BSY) . . . . .875
Tx buffer empty flag (TXE) . . . . .876
RX buffer not empty (RXNE) . . . . .876
Channel Side flag (CHSIDE) . . . . .876
30.6.8 I 2 S error flags . . . . .876
Underrun flag (UDR) . . . . .876
Overrun flag (OVR). . . . .877
Frame error flag (FRE) . . . . .877
30.6.9 I 2 S interrupts . . . . .877
30.6.10 DMA features . . . . .877
30.7 SPI and I 2 S registers . . . . .878
30.7.1 SPI control register 1 (SPI_CR1) (not used in I 2 S mode) . . . . .878
30.7.2SPI control register 2 (SPI_CR2) . . . . .880
30.7.3SPI status register (SPI_SR) . . . . .881
30.7.4SPI data register (SPI_DR) . . . . .883
30.7.5SPI CRC polynomial register (SPI_CRCPR) (not used in I 2 S mode) . . . . .883
30.7.6SPI RX CRC register (SPI_RXCRCR) (not used in I 2 S mode) . . . . .884
30.7.7SPI TX CRC register (SPI_TXCRCR) (not used in I 2 S mode) . . . . .884
30.7.8SPI_I 2 S configuration register (SPI_I2SCFGGR) . . . . .885
30.7.9SPI_I 2 S prescaler register (SPI_I2SPR) . . . . .886
30.7.10SPI register map . . . . .887
31Universal serial bus full-speed device interface (USB) . . . . .888
31.1Introduction . . . . .888
31.2USB main features . . . . .888
31.3USB implementation . . . . .888
31.4USB functional description . . . . .889
31.4.1Description of USB blocks . . . . .890
31.5Programming considerations . . . . .891
31.5.1Generic USB device programming . . . . .891
31.5.2System and power-on reset . . . . .892
USB reset (RESET interrupt) . . . . .892
Structure and usage of packet buffers . . . . .892
Endpoint initialization . . . . .894
IN packets (data transmission) . . . . .894
OUT and SETUP packets (data reception) . . . . .895
Control transfers . . . . .896
31.5.3Double-buffered endpoints . . . . .897
31.5.4Isochronous transfers . . . . .899
31.5.5Suspend/Resume events . . . . .900
31.6USB and USB SRAM registers . . . . .903
31.6.1Common registers . . . . .903
USB control register (USB_CNTR) . . . . .903
USB interrupt status register (USB_ISTR) . . . . .905
USB frame number register (USB_FNR) . . . . .908
USB device address (USB_DADDR) . . . . .908
Buffer table address (USB_BTABLE) . . . . .909
LPM control and status register (USB_LPMCSR) . . . . .909
Battery charging detector (USB_BCDR) . . . . .910
Endpoint-specific registers . . . . .911
USB endpoint n register (USB_EPnR), n=[0..7] . . . . .911
31.6.2 Buffer descriptor table . . . . .916
Transmission buffer address n (USB_ADDRn_TX) . . . . .916
Transmission byte count n (USB_COUNTn_TX) . . . . .916
Reception buffer address n (USB_ADDRn_RX) . . . . .917
Reception byte count n (USB_COUNTn_RX) . . . . .917
31.6.3 USB register map . . . . .919
32 Debug support (DBG) . . . . .921
32.1 Overview . . . . .921
32.2 Reference Arm® documentation . . . . .922
32.3 Pinout and debug port pins . . . . .922
32.3.1 SWD port pins . . . . .922
32.3.2 SW-DP pin assignment . . . . .922
32.3.3 Internal pull-up & pull-down on SWD pins . . . . .923
32.4 ID codes and locking mechanism . . . . .923
32.4.1 MCU device ID code . . . . .923
DBG_IDCODE . . . . .923
32.5 SWD port . . . . .924
32.5.1 SWD protocol introduction . . . . .924
32.5.2 SWD protocol sequence . . . . .924
32.5.3 SW-DP state machine (reset, idle states, ID code) . . . . .925
32.5.4 DP and AP read/write accesses . . . . .926
32.5.5 SW-DP registers . . . . .926
32.5.6 SW-AP registers . . . . .927
32.6 Core debug . . . . .928
32.7 BPU (Break Point Unit) . . . . .928
32.7.1 BPU functionality . . . . .928
32.8 DWT (Data Watchpoint) . . . . .929
32.8.1 DWT functionality . . . . .929
32.8.2 DWT Program Counter Sample Register . . . . .929
32.9 MCU debug component (DBG) . . . . .929
32.9.1 Debug support for low-power modes . . . . .929
32.9.2 Debug support for timers, watchdog and I 2 C . . . . .930
32.9.3 Debug MCU configuration register (DBG_CR) . . . . .930
32.9.4 Debug MCU APB1 freeze register (DBG_APB1_FZ) . . . . .932

32.9.5 Debug MCU APB2 freeze register (DBG_APB2_FZ) . . . . . 934

32.10 DBG register map . . . . . 935

33 Device electronic signature . . . . . 936

33.1 Memory size register . . . . . 936

33.1.1 Flash size register . . . . . 936

33.2 Unique device ID registers (96 bits) . . . . . 936

Appendix A Code examples. . . . . 938

A.1 Introduction . . . . . 938

A.2 NVM/RCC Operation code example . . . . . 938

A.2.1 Increasing the CPU frequency preparation sequence code . . . . . 938

A.2.2 Decreasing the CPU frequency preparation sequence code . . . . . 938

A.2.3 Switch from PLL to HSI16 sequence code . . . . . 939

A.2.4 Switch to PLL sequence code. . . . . 939

A.3 NVM Operation code example . . . . . 940

A.3.1 Unlocking the data EEPROM and FLASH_PECR register code example . . . . . 940

A.3.2 Locking data EEPROM and FLASH_PECR register code example. . . . . 940

A.3.3 Unlocking the NVM program memory code example . . . . . 940

A.3.4 Unlocking the option bytes area code example . . . . . 941

A.3.5 Write to data EEPROM code example . . . . . 941

A.3.6 Erase to data EEPROM code example . . . . . 941

A.3.7 Program Option byte code example . . . . . 942

A.3.8 Erase Option byte code example . . . . . 942

A.3.9 Program a single word to Flash program memory code example . . . . . 943

A.3.10 Program half-page to Flash program memory code example . . . . . 944

A.3.11 Erase a page in Flash program memory code example. . . . . 945

A.3.12 Mass erase code example . . . . . 946

A.4 Clock Controller. . . . . 947

A.4.1 HSE start sequence code example . . . . . 947

A.4.2 PLL configuration modification code example . . . . . 948

A.4.3 MCO selection code example. . . . . 949

A.5 GPIOs . . . . . 949

A.5.1 Locking mechanism code example. . . . . 949

A.5.2 Alternate function selection sequence code example. . . . . 949

A.5.3 Analog GPIO configuration code example . . . . . 949

A.6DMA . . . . .950
A.6.1DMA Channel Configuration sequence code example . . . . .950
A.7Interrupts and event . . . . .950
A.7.1NVIC initialization example . . . . .950
A.7.2Extended interrupt selection code example . . . . .950
A.8ADC . . . . .951
A.8.1Calibration code example . . . . .951
A.8.2ADC enable sequence code example . . . . .951
A.8.3ADC disable sequence code example . . . . .952
A.8.4ADC clock selection code example . . . . .952
A.8.5Single conversion sequence code example - Software trigger . . . . .952
A.8.6Continuous conversion sequence code example - Software trigger . . . . .953
A.8.7Single conversion sequence code example - Hardware trigger . . . . .953
A.8.8Continuous conversion sequence code example - Hardware trigger . . . . .954
A.8.9DMA one shot mode sequence code example . . . . .954
A.8.10DMA circular mode sequence code example . . . . .955
A.8.11Wait mode sequence code example . . . . .955
A.8.12Auto off and no wait mode sequence code example . . . . .955
A.8.13Auto off and wait mode sequence code example . . . . .956
A.8.14Analog watchdog code example . . . . .956
A.8.15Oversampling code example . . . . .957
A.8.16Temperature configuration code example . . . . .957
A.8.17Temperature computation code example . . . . .957
A.9DAC . . . . .958
A.9.1Independent trigger without wave generation code example . . . . .958
A.9.2Independent trigger with single triangle generation code example . . . . .958
A.9.3DMA initialization code example . . . . .958
A.10TSC code example . . . . .959
A.10.1TSC configuration code example . . . . .959
A.10.2TSC interrupt code example . . . . .960
A.11Timers . . . . .960
A.11.1Upcounter on TI2 rising edge code example . . . . .960
A.11.2Up counter on each 2 ETR rising edges code example . . . . .960
A.11.3Input capture configuration code example . . . . .961
A.11.4Input capture data management code example . . . . .961
A.11.5PWM input configuration code example . . . . .962
A.11.6PWM input with DMA configuration code example . . . . .962
A.11.7Output compare configuration code example . . . . .963
A.11.8Edge-aligned PWM configuration example. . . . .963
A.11.9Center-aligned PWM configuration example . . . . .964
A.11.10ETR configuration to clear OCxREF code example . . . . .964
A.11.11Encoder interface code example . . . . .965
A.11.12Reset mode code example . . . . .965
A.11.13Gated mode code example. . . . .966
A.11.14Trigger mode code example . . . . .966
A.11.15External clock mode 2 + trigger mode code example. . . . .967
A.11.16One-Pulse mode code example . . . . .967
A.11.17Timer prescaling another timer code example . . . . .968
A.11.18Timer enabling another timer code example. . . . .968
A.11.19Master and slave synchronization code example . . . . .969
A.11.20Two timers synchronized by an external trigger code example . . . . .971
A.11.21DMA burst feature code example . . . . .972
A.12Low-power timer (LPTIM) . . . . .973
A.12.1Pulse counter configuration code example. . . . .973
A.13IWDG code example . . . . .973
A.13.1IWDG configuration code example . . . . .973
A.13.2IWDG configuration with window code example. . . . .973
A.14WWDG code example. . . . .974
A.14.1WWDG configuration code example. . . . .974
A.15RTC code example . . . . .974
A.15.1RTC calendar configuration code example. . . . .974
A.15.2RTC alarm configuration code example . . . . .975
A.15.3RTC WUT configuration code example . . . . .975
A.15.4RTC read calendar code example . . . . .976
A.15.5RTC calibration code example . . . . .976
A.15.6RTC tamper and time stamp configuration code example . . . . .976
A.15.7RTC tamper and time stamp code example . . . . .977
A.15.8RTC clock output code example . . . . .977
A.16I2C code example . . . . .977
A.16.1I2C configured in slave mode code example . . . . .977
A.16.2I2C slave transmitter code example . . . . .978
A.16.3I2C slave receiver code example . . . . .978
A.16.4I2C configured in master mode to receive code example . . . . .978
A.16.5I2C configured in master mode to transmit code example . . . . .979
A.16.6I2C master transmitter code example . . . . .979
A.16.7I2C master receiver code example . . . . .979
A.16.8I2C configured in master mode to transmit with DMA code example . .979
A.16.9I2C configured in slave mode to receive with DMA code example . . . .980
A.17USART code example . . . . .980
A.17.1USART transmitter configuration code example . . . . .980
A.17.2USART transmit byte code example . . . . .980
A.17.3USART transfer complete code example . . . . .980
A.17.4USART receiver configuration code example . . . . .980
A.17.5USART receive byte code example . . . . .981
A.17.6USART LIN mode code example . . . . .981
A.17.7USART synchronous mode code example . . . . .981
A.17.8USART single-wire half-duplex code example . . . . .982
A.17.9USART smartcard mode code example . . . . .982
A.17.10USART IrDA mode code example . . . . .982
A.17.11USART DMA code example . . . . .983
A.17.12USART hardware flow control code example . . . . .983
A.18LPUART code example . . . . .984
A.18.1LPUART receiver configuration code example . . . . .984
A.18.2LPUART receive byte code example . . . . .984
A.19SPI code example . . . . .984
A.19.1SPI master configuration code example . . . . .984
A.19.2SPI slave configuration code example . . . . .984
A.19.3SPI full duplex communication code example . . . . .984
A.19.4SPI master configuration with DMA code example . . . . .985
A.19.5SPI slave configuration with DMA code example . . . . .985
A.19.6SPI interrupt code example . . . . .985
A.20DBG code example . . . . .985
A.20.1DBG read device Id code example . . . . .985
A.20.2DBG debug in LPM code example . . . . .985
Revision history. . . . .986

List of tables

Table 1.STM32L0x2 memory density . . . . .53
Table 2.Overview of features per category . . . . .53
Table 3.STM32L0x2 peripheral register boundary addresses . . . . .59
Table 4.Boot modes . . . . .63
Table 5.NVM organization (category 3 devices) . . . . .66
Table 6.NVM organization for UFB = 0 (192 Kbyte category 5 devices) . . . . .67
Table 7.Flash memory and data EEPROM remapping
(192 Kbyte category 5 devices) . . . . .		68
Table 8.NVM organization for UFB = 0 (128 Kbyte category 5 devices) . . . . .68
Table 9.Flash memory and data EEPROM remapping (128 Kbyte category 5 devices) . . . . .69
Table 10.NVM organization for UFB = 0 (64 Kbyte category 5 devices) . . . . .69
Table 11.Boot pin and BFB2 bit configuration . . . . .70
Table 12.Link between master clock power range and frequencies . . . . .72
Table 13.Delays to memory access and number of wait states . . . . .72
Table 14.Internal buffer management . . . . .75
Table 15.Configurations for buffers and speculative reading . . . . .78
Table 16.Dhrystone performances in all memory interface configurations . . . . .79
Table 17.NVM write/erase timings . . . . .93
Table 18.NVM write/erase duration . . . . .93
Table 19.Protection level and content of RDP Option bytes . . . . .97
Table 20.Link between protection bits of FLASH_WRPROTx register
and protected address in Flash program memory . . . . .		98
Table 21.Memory access vs mode, protection and Flash program memory sectors . . . . .99
Table 22.Flash interrupt request . . . . .102
Table 23.Flash interface - register map and reset values . . . . .119
Table 24.Option byte format . . . . .120
Table 25.Option byte organization . . . . .120
Table 26.CRC internal input/output signals . . . . .123
Table 27.CRC register map and reset values . . . . .128
Table 28.Segment accesses according to the Firewall state . . . . .132
Table 29.Segment granularity and area ranges . . . . .133
Table 30.Firewall register map and reset values . . . . .140
Table 31.Performance versus VCORE ranges . . . . .144
Table 32.Summary of low-power modes . . . . .152
Table 33.Sleep-now . . . . .156
Table 34.Sleep-on-exit . . . . .157
Table 35.Sleep-now (Low-power sleep) . . . . .158
Table 36.Sleep-on-exit (Low-power sleep) . . . . .159
Table 37.Stop mode . . . . .161
Table 38.Standby mode . . . . .163
Table 39.PWR - register map and reset values . . . . .171
Table 40.HSE/LSE clock sources . . . . .177
Table 41.System clock source frequency . . . . .182
Table 42.RCC register map and reset values . . . . .221
Table 43.CRS features . . . . .224
Table 44.Effect of low-power modes on CRS . . . . .228
Table 45.Interrupt control bits . . . . .228
Table 46.CRS register map and reset values . . . . .233
Table 47.Port bit configuration table . . . . .237
Table 48.GPIO register map and reset values . . . . .250
Table 49.SYSCFG register map and reset values . . . . .259
Table 50.DMA implementation . . . . .262
Table 51.DMA requests for each channel . . . . .263
Table 52.Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .271
Table 53.DMA interrupt requests . . . . .272
Table 54.DMA register map and reset values . . . . .282
Table 55.List of vectors . . . . .285
Table 56.EXTI lines connections . . . . .292
Table 57.Extended interrupt/event controller register map and reset values . . . . .297
Table 58.ADC input/output pins . . . . .300
Table 59.ADC internal input/output signals . . . . .301
Table 60.External triggers . . . . .301
Table 61.Latency between trigger and start of conversion . . . . .306
Table 62.Configuring the trigger polarity . . . . .312
Table 63.tSAR timings depending on resolution . . . . .314
Table 64.Analog watchdog comparison . . . . .323
Table 65.Analog watchdog channel selection . . . . .323
Table 66.Maximum output results vs N and M. Grayed values indicates truncation . . . . .327
Table 67.ADC interrupts . . . . .332
Table 68.ADC register map and reset values . . . . .347
Table 69.DAC pins . . . . .350
Table 70.External triggers . . . . .353
Table 71.DAC register map and reset values . . . . .371
Table 72.COMP register map and reset values . . . . .379
Table 73.Acquisition sequence summary . . . . .383
Table 74.Spread spectrum deviation versus AHB clock frequency . . . . .385
Table 75.I/O state depending on its mode and IODEF bit value . . . . .386
Table 76.Effect of low-power modes on TSC . . . . .388
Table 77.Interrupt control bits . . . . .388
Table 78.TSC register map and reset values . . . . .397
Table 79.AES internal input/output signals . . . . .400
Table 80.CTR mode initialization vector definition . . . . .416
Table 81.Key endianness in AES_KEYRx registers . . . . .419
Table 82.DMA channel configuration for memory-to-AES data transfer . . . . .420
Table 83.DMA channel configuration for AES-to-memory data transfer . . . . .421
Table 84.AES interrupt requests . . . . .423
Table 85.Processing latency (in clock cycle) . . . . .423
Table 86.AES register map and reset values . . . . .431
Table 87.RNG internal input/output signals . . . . .434
Table 88.RNG interrupt requests . . . . .439
Table 89.RNG register map and reset map . . . . .443
Table 90.Counting direction versus encoder signals . . . . .475
Table 91.TIM2/TIM3 internal trigger connection . . . . .492
Table 92.Output control bit for standard OCx channels . . . . .502
Table 93.TIM2/3 register map and reset values . . . . .510
Table 94.Counting direction versus encoder signals . . . . .543
Table 95.TIMx Internal trigger connection . . . . .553
Table 96.Output control bit for standard OCx channels . . . . .561
Table 97.TIM21/22 register map and reset values . . . . .565
Table 98.TIM6/7 register map and reset values . . . . .579
Table 99.STM32L0x2 LPTIM features . . . . .581
Table 100.LPTIM1 external trigger connection . . . . .582
Table 101.Prescaler division ratios . . . . .583
Table 102.Encoder counting scenarios . . . . .589
Table 103.Effect of low-power modes on the LPTIM . . . . .590
Table 104.Interrupt events . . . . .591
Table 105.LPTIM register map and reset values . . . . .600
Table 106.IWDG register map and reset values . . . . .609
Table 107.WWDG register map and reset values . . . . .615
Table 108.RTC implementation . . . . .617
Table 109.RTC pin PC13 configuration . . . . .619
Table 110.RTC_OUT mapping . . . . .620
Table 111.Effect of low-power modes on RTC . . . . .633
Table 112.Interrupt control bits . . . . .633
Table 113.RTC register map and reset values . . . . .658
Table 114.STM32L0x2 I2C features . . . . .661
Table 115.I2C input/output pins . . . . .664
Table 116.I2C internal input/output signals . . . . .664
Table 117.Comparison of analog vs. digital filters . . . . .666
Table 118.I2C-SMBus specification data setup and hold times . . . . .669
Table 119.I2C configuration . . . . .673
Table 120.I2C-SMBus specification clock timings . . . . .684
Table 121.Examples of timing settings for f I2CCLK = 8 MHz . . . . .694
Table 122.Examples of timings settings for f I2CCLK = 16 MHz . . . . .694
Table 123.SMBus timeout specifications . . . . .696
Table 124.SMBus with PEC configuration . . . . .699
Table 125.Examples of TIMEOUTA settings for various I2CCLK frequencies
(max t TIMEOUT = 25 ms) . . . . .		700
Table 126.Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . .700
Table 127.Examples of TIMEOUTA settings for various I2CCLK frequencies
(max t IDLE = 50 µs) . . . . .		700
Table 128.Effect of low-power modes on the I2C . . . . .711
Table 129.I2C Interrupt requests . . . . .712
Table 130.I2C register map and reset values . . . . .727
Table 131.STM32L0x2 USART/LPUART features . . . . .731
Table 132.Noise detection from sampled data . . . . .743
Table 133.Error calculation for programmed baud rates at f CK = 32 MHz in both cases of
oversampling by 16 or by 8 . . . . .		746
Table 134.Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . .747
Table 135.Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . .747
Table 136.Frame formats . . . . .752
Table 137.Effect of low-power modes on the USART . . . . .771
Table 138.USART interrupt requests . . . . .771
Table 139.USART register map and reset values . . . . .794
Table 140.STM32L0x2 USART/LPUART features . . . . .798
Table 141.Error calculation for programmed baud rates at f ck = 32.768 kHz . . . . .808
Table 142.Error calculation for programmed baud rates at f ck = 32 MHz . . . . .808
Table 143.Tolerance of the LPUART receiver . . . . .809
Table 144.Frame formats . . . . .812
Table 145.Effect of low-power modes on the LPUART . . . . .821
Table 146.LPUART interrupt requests . . . . .821
Table 147.LPUART register map and reset values . . . . .837
Table 148.STM32L0x2 SPI implementation . . . . .839
Table 149.SPI interrupt requests . . . . .860
Table 150.Audio-frequency precision using standard 8 MHz HSE . . . . .871
Table 151.I 2 S interrupt requests . . . . .877
Table 152.SPI register map and reset values . . . . .887
Table 153.STM32L0x2 USB implementation. . . . .888
Table 154.Double-buffering buffer flag definition. . . . .898
Table 155.Bulk double-buffering memory buffers usage . . . . .898
Table 156.Isochronous memory buffers usage . . . . .900
Table 157.Resume event detection . . . . .901
Table 158.Reception status encoding . . . . .914
Table 159.Endpoint type encoding . . . . .914
Table 160.Endpoint kind meaning . . . . .914
Table 161.Transmission status encoding . . . . .915
Table 162.Definition of allocated buffer memory . . . . .918
Table 163.USB register map and reset values . . . . .919
Table 164.SW debug port pins . . . . .922
Table 165.REV_ID values . . . . .924
Table 166.Packet request (8-bits) . . . . .924
Table 167.ACK response (3 bits). . . . .925
Table 168.DATA transfer (33 bits). . . . .925
Table 169.SW-DP registers . . . . .926
Table 170.32-bit debug port registers addressed through the shifted value A[3:2] . . . . .927
Table 171.Core debug registers . . . . .928
Table 172.DBG register map and reset values . . . . .935
Table 173.Document revision history . . . . .986

List of figures

Figure 1. System architecture . . . . . 55

Figure 2. Memory map . . . . . 58

Figure 3. Structure of one internal buffer . . . . . 74

Figure 4. Timing to fetch and execute instructions with prefetch disabled. . . . . 76

Figure 5. Timing to fetch and execute instructions with prefetch enabled . . . . . 78

Figure 6. RDP levels . . . . . 97

Figure 7. CRC calculation unit block diagram . . . . . 123

Figure 8. STM32L0x2 firewall connection schematics. . . . . 130

Figure 9. Firewall functional states . . . . . 134

Figure 10. Power supply overview . . . . . 142

Figure 11. Performance versus VDD and VCORE range . . . . . 145

Figure 12. Power supply supervisors . . . . . 148

Figure 13. Power-on reset/power-down reset waveform . . . . . 149

Figure 14. BOR thresholds . . . . . 150

Figure 15. PVD thresholds . . . . . 151

Figure 16. Simplified diagram of the reset circuit. . . . . 173

Figure 17. Clock tree . . . . . 176

Figure 18. Using TIM21 channel 1 input capture to measure frequencies . . . . . 184

Figure 19. CRS block diagram. . . . . 225

Figure 20. CRS counter behavior . . . . . 226

Figure 21. Basic structure of an I/O port bit . . . . . 236

Figure 22. Basic structure of a 5-Volt tolerant I/O port bit . . . . . 236

Figure 23. Input floating / pull up / pull down configurations . . . . . 241

Figure 24. Output configuration . . . . . 242

Figure 25. Alternate function configuration . . . . . 242

Figure 26. High impedance-analog configuration . . . . . 243

Figure 27. DMA request mapping . . . . . 263

Figure 28. DMA block diagram . . . . . 265

Figure 29. Extended interrupts and events controller (EXTI) block diagram . . . . . 289

Figure 30. Extended interrupt/event GPIO mapping . . . . . 291

Figure 31. ADC block diagram . . . . . 300

Figure 32. ADC calibration. . . . . 303

Figure 33. Calibration factor forcing . . . . . 304

Figure 34. Enabling/disabling the ADC . . . . . 305

Figure 35. ADC clock scheme . . . . . 305

Figure 36. ADC connectivity . . . . . 307

Figure 37. Analog to digital conversion time . . . . . 311

Figure 38. ADC conversion timings . . . . . 311

Figure 39. Stopping an ongoing conversion . . . . . 312

Figure 40. Single conversions of a sequence, software trigger . . . . . 315

Figure 41. Continuous conversion of a sequence, software trigger. . . . . 315

Figure 42. Single conversions of a sequence, hardware trigger . . . . . 316

Figure 43. Continuous conversions of a sequence, hardware trigger . . . . . 316

Figure 44. Data alignment and resolution (oversampling disabled: OVSE = 0). . . . . 317

Figure 45. Example of overrun (OVR) . . . . . 318

Figure 46. Wait mode conversion (continuous mode, software trigger). . . . . 320

Figure 47. Behavior with WAIT = 0, AUTOFF = 1 . . . . . 321

Figure 48.Behavior with WAIT = 1, AUTOFF = 1 . . . . .322
Figure 49.Analog watchdog guarded area . . . . .323
Figure 50.ADC_AWD1_OUT signal generation . . . . .324
Figure 51.ADC_AWD1_OUT signal generation (AWD flag not cleared by software) . . . . .325
Figure 52.ADC1_AWD_OUT signal generation (on a single channel) . . . . .325
Figure 53.Analog watchdog threshold update . . . . .326
Figure 54.20-bit to 16-bit result truncation . . . . .327
Figure 55.Numerical example with 5-bits shift and rounding . . . . .327
Figure 56.Triggered oversampling mode (TOVS bit = 1) . . . . .329
Figure 57.Temperature sensor and VREFINT channel block diagram . . . . .330
Figure 58.DAC block diagram . . . . .350
Figure 59.Data registers in single DAC channel mode . . . . .351
Figure 60.Timing diagram for conversion with trigger disabled TEN = 0 . . . . .352
Figure 61.Data registers in dual DAC channel mode . . . . .354
Figure 62.DAC LFSR register calculation algorithm . . . . .358
Figure 63.DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .359
Figure 64.DAC triangle wave generation . . . . .359
Figure 65.DAC conversion (SW trigger enabled) with triangle wave generation . . . . .360
Figure 66.Comparator 1 and 2 block diagrams . . . . .374
Figure 67.TSC block diagram . . . . .381
Figure 68.Surface charge transfer analog I/O group structure . . . . .382
Figure 69.Sampling capacitor voltage variation . . . . .383
Figure 70.Charge transfer acquisition sequence . . . . .384
Figure 71.Spread spectrum variation principle . . . . .385
Figure 72.AES block diagram . . . . .400
Figure 73.ECB encryption and decryption principle . . . . .402
Figure 74.CBC encryption and decryption principle . . . . .403
Figure 75.CTR encryption and decryption principle . . . . .404
Figure 76.STM32 cryptolib AES flowchart example . . . . .405
Figure 77.Encryption key derivation for ECB/CBC decryption (Mode 2). . . . .408
Figure 78.Example of suspend mode management . . . . .409
Figure 79.ECB encryption . . . . .409
Figure 80.ECB decryption . . . . .410
Figure 81.CBC encryption . . . . .410
Figure 82.CBC decryption . . . . .411
Figure 83.ECB/CBC encryption (Mode 1) . . . . .412
Figure 84.ECB/CBC decryption (Mode 3) . . . . .413
Figure 85.Message construction in CTR mode . . . . .415
Figure 86.CTR encryption . . . . .415
Figure 87.CTR decryption . . . . .416
Figure 88.128-bit block construction with respect to data swap . . . . .418
Figure 89.DMA transfer of a 128-bit data block during input phase . . . . .420
Figure 90.DMA transfer of a 128-bit data block during output phase . . . . .421
Figure 91.AES interrupt signal generation . . . . .423
Figure 92.RNG block diagram . . . . .434
Figure 93.Entropy source model . . . . .435
Figure 94.General-purpose timer block diagram . . . . .445
Figure 95.Counter timing diagram with prescaler division change from 1 to 2 . . . . .447
Figure 96.Counter timing diagram with prescaler division change from 1 to 4 . . . . .447
Figure 97.Counter timing diagram, internal clock divided by 1 . . . . .448
Figure 98.Counter timing diagram, internal clock divided by 2 . . . . .449
Figure 99.Counter timing diagram, internal clock divided by 4 . . . . .449
Figure 100. Counter timing diagram, internal clock divided by N . . . . .450
Figure 101. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .450
Figure 102. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .451
Figure 103. Counter timing diagram, internal clock divided by 1 . . . . .452
Figure 104. Counter timing diagram, internal clock divided by 2 . . . . .452
Figure 105. Counter timing diagram, internal clock divided by 4 . . . . .453
Figure 106. Counter timing diagram, internal clock divided by N . . . . .453
Figure 107. Counter timing diagram, Update event when repetition counter is not used . . . . .454
Figure 108. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .455
Figure 109. Counter timing diagram, internal clock divided by 2 . . . . .456
Figure 110. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .456
Figure 111. Counter timing diagram, internal clock divided by N . . . . .457
Figure 112. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .457
Figure 113. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .458
Figure 114. Control circuit in normal mode, internal clock divided by 1 . . . . .459
Figure 115. TI2 external clock connection example. . . . .459
Figure 116. Control circuit in external clock mode 1 . . . . .460
Figure 117. External trigger input block . . . . .461
Figure 118. Control circuit in external clock mode 2 . . . . .462
Figure 119. Capture/compare channel (example: channel 1 input stage). . . . .463
Figure 120. Capture/compare channel 1 main circuit . . . . .463
Figure 121. Output stage of capture/compare channel (channel 1). . . . .464
Figure 122. PWM input mode timing . . . . .466
Figure 123. Output compare mode, toggle on OC1. . . . .468
Figure 124. Edge-aligned PWM waveforms (ARR=8). . . . .469
Figure 125. Center-aligned PWM waveforms (ARR=8). . . . .471
Figure 126. Example of one-pulse mode. . . . .472
Figure 127. Clearing TIMx_OCxREF . . . . .474
Figure 128. Example of counter operation in encoder interface mode . . . . .476
Figure 129. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .476
Figure 130. Control circuit in reset mode . . . . .477
Figure 131. Control circuit in gated mode . . . . .478
Figure 132. Control circuit in trigger mode . . . . .479
Figure 133. Control circuit in external clock mode 2 + trigger mode . . . . .481
Figure 134. Master/Slave timer example . . . . .481
Figure 135. Gating timer y with OC1REF of timer x. . . . .483
Figure 136. Gating timer y with Enable of timer x . . . . .484
Figure 137. Triggering timer y with update of timer x. . . . .485
Figure 138. Triggering timer y with Enable of timer x . . . . .485
Figure 139. Triggering timer x and y with timer x TI1 input . . . . .486
Figure 140. General-purpose timer block diagram (TIM21/22) . . . . .513
Figure 141. Counter timing diagram with prescaler division change from 1 to 2 . . . . .515
Figure 142. Counter timing diagram with prescaler division change from 1 to 4 . . . . .516
Figure 143. Counter timing diagram, internal clock divided by 1 . . . . .517
Figure 144. Counter timing diagram, internal clock divided by 2 . . . . .518
Figure 145. Counter timing diagram, internal clock divided by 4 . . . . .518
Figure 146. Counter timing diagram, internal clock divided by N. . . . .519
Figure 147. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .519
Figure 148. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .520
Figure 149. Counter timing diagram, internal clock divided by 1 . . . . .521
Figure 150. Counter timing diagram, internal clock divided by 2 . . . . .521
Figure 151. Counter timing diagram, internal clock divided by 4 . . . . .522
Figure 152. Counter timing diagram, internal clock divided by N . . . . .522
Figure 153. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .524
Figure 154. Counter timing diagram, internal clock divided by 2 . . . . .524
Figure 155. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .525
Figure 156. Counter timing diagram, internal clock divided by N . . . . .525
Figure 157. Counter timing diagram, Update event with ARPE=1 (counter underflow) . . . . .526
Figure 158. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .526
Figure 159. Control circuit in normal mode, internal clock divided by 1 . . . . .527
Figure 160. TI2 external clock connection example . . . . .528
Figure 161. Control circuit in external clock mode 1 . . . . .529
Figure 162. External trigger input block . . . . .529
Figure 163. Control circuit in external clock mode 2 . . . . .530
Figure 164. Capture/compare channel (example: channel 1 input stage) . . . . .531
Figure 165. Capture/compare channel 1 main circuit . . . . .531
Figure 166. Output stage of capture/compare channel (channel 1 and 2) . . . . .532
Figure 167. PWM input mode timing . . . . .534
Figure 168. Output compare mode, toggle on OC1 . . . . .536
Figure 169. Edge-aligned PWM waveforms (ARR=8) . . . . .537
Figure 170. Center-aligned PWM waveforms (ARR=8) . . . . .538
Figure 171. Clearing TIMx_OCxREF . . . . .540
Figure 172. Example of one pulse mode . . . . .541
Figure 173. Example of counter operation in encoder interface mode . . . . .543
Figure 174. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .544
Figure 175. Control circuit in reset mode . . . . .545
Figure 176. Control circuit in gated mode . . . . .546
Figure 177. Control circuit in trigger mode . . . . .547
Figure 178. Basic timer block diagram . . . . .567
Figure 179. Counter timing diagram with prescaler division change from 1 to 2 . . . . .569
Figure 180. Counter timing diagram with prescaler division change from 1 to 4 . . . . .569
Figure 181. Counter timing diagram, internal clock divided by 1 . . . . .570
Figure 182. Counter timing diagram, internal clock divided by 2 . . . . .571
Figure 183. Counter timing diagram, internal clock divided by 4 . . . . .571
Figure 184. Counter timing diagram, internal clock divided by N . . . . .572
Figure 185. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded) . . . . .		572
Figure 186. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded) . . . . .		573
Figure 187. Control circuit in normal mode, internal clock divided by 1 . . . . .574
Figure 188. Low-power timer block diagram . . . . .581
Figure 189. Glitch filter timing diagram . . . . .583
Figure 190. LPTIM output waveform, single counting mode configuration . . . . .585
Figure 191. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . .		585
Figure 192. LPTIM output waveform, Continuous counting mode configuration . . . . .586
Figure 193. Waveform generation . . . . .587
Figure 194. Encoder mode counting sequence . . . . .590
Figure 195. Independent watchdog block diagram . . . . .601
Figure 196. Watchdog block diagram . . . . .611
Figure 197. Window watchdog timing diagram . . . . .612
Figure 198. RTC block diagram . . . . .618
Figure 199. I2C1/3 block diagram . . . . .662
Figure 200. I2C2 block diagram . . . . .663
Figure 201. I2C bus protocol . . . . .665
Figure 202. Setup and hold timings . . . . .667
Figure 203. I2C initialization flow . . . . .670
Figure 204. Data reception . . . . .671
Figure 205. Data transmission . . . . .672
Figure 206. Slave initialization flow . . . . .675
Figure 207. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0 . . . . .677
Figure 208. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1 . . . . .678
Figure 209. Transfer bus diagrams for I2C slave transmitter . . . . .679
Figure 210. Transfer sequence flow for slave receiver with NOSTRETCH = 0 . . . . .680
Figure 211. Transfer sequence flow for slave receiver with NOSTRETCH = 1 . . . . .681
Figure 212. Transfer bus diagrams for I2C slave receiver . . . . .681
Figure 213. Master clock generation . . . . .683
Figure 214. Master initialization flow . . . . .685
Figure 215. 10-bit address read access with HEAD10R = 0 . . . . .685
Figure 216. 10-bit address read access with HEAD10R = 1 . . . . .686
Figure 217. Transfer sequence flow for I2C master transmitter for N≤255 bytes . . . . .687
Figure 218. Transfer sequence flow for I2C master transmitter for N>255 bytes . . . . .688
Figure 219. Transfer bus diagrams for I2C master transmitter . . . . .689
Figure 220. Transfer sequence flow for I2C master receiver for N≤255 bytes . . . . .691
Figure 221. Transfer sequence flow for I2C master receiver for N >255 bytes . . . . .692
Figure 222. Transfer bus diagrams for I2C master receiver . . . . .693
Figure 223. Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . .697
Figure 224. Transfer sequence flow for SMBus slave transmitter N bytes + PEC . . . . .701
Figure 225. Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . .702
Figure 226. Transfer sequence flow for SMBus slave receiver N Bytes + PEC . . . . .703
Figure 227. Bus transfer diagrams for SMBus slave receiver (SBC=1) . . . . .704
Figure 228. Bus transfer diagrams for SMBus master transmitter . . . . .705
Figure 229. Bus transfer diagrams for SMBus master receiver . . . . .707
Figure 230. USART block diagram . . . . .733
Figure 231. Word length programming . . . . .735
Figure 232. Configurable stop bits . . . . .737
Figure 233. TC/TXE behavior when transmitting . . . . .738
Figure 234. Start bit detection when oversampling by 16 or 8 . . . . .739
Figure 235. Data sampling when oversampling by 16 . . . . .742
Figure 236. Data sampling when oversampling by 8 . . . . .743
Figure 237. Mute mode using Idle line detection . . . . .750
Figure 238. Mute mode using address mark detection . . . . .751
Figure 239. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .754
Figure 240. Break detection in LIN mode vs. Framing error detection. . . . .755
Figure 241. USART example of synchronous transmission. . . . .756
Figure 242. USART data clock timing diagram (M bits = 00) . . . . .756
Figure 243. USART data clock timing diagram (M bits = 01) . . . . .757
Figure 244. RX data setup/hold time . . . . .757
Figure 245. ISO 7816-3 asynchronous protocol . . . . .759
Figure 246. Parity error detection using the 1.5 stop bits . . . . .760
Figure 247. IrDA SIR ENDEC- block diagram . . . . .764
Figure 248. IrDA data modulation (3/16) -Normal Mode . . . . .765
Figure 249. Transmission using DMA . . . . .766
Figure 250. Reception using DMA . . . . .767
Figure 251. Hardware flow control between 2 USARTs . . . . .767
Figure 252. RS232 RTS flow control . . . . .768
Figure 253. RS232 CTS flow control . . . . .769
Figure 254. USART interrupt mapping diagram . . . . .772
Figure 255. LPUART block diagram . . . . .799
Figure 256. Word length programming . . . . .801
Figure 257. Configurable stop bits . . . . .802
Figure 258. TC/TXE behavior when transmitting . . . . .804
Figure 259. Mute mode using Idle line detection . . . . .811
Figure 260. Mute mode using address mark detection . . . . .812
Figure 261. Transmission using DMA . . . . .815
Figure 262. Reception using DMA . . . . .816
Figure 263. Hardware flow control between 2 LPUARTs . . . . .816
Figure 264. RS232 RTS flow control . . . . .817
Figure 265. RS232 CTS flow control . . . . .818
Figure 266. LPUART interrupt mapping diagram . . . . .822
Figure 267. SPI block diagram. . . . .840
Figure 268. Full-duplex single master/ single slave application. . . . .841
Figure 269. Half-duplex single master/ single slave application . . . . .842
Figure 270. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		843
Figure 271. Master and three independent slaves. . . . .844
Figure 272. Multi-master application . . . . .845
Figure 273. Hardware/software slave select management . . . . .846
Figure 274. Data clock timing diagram . . . . .848
Figure 275. TXE/RXNE/BSY behavior in master / full-duplex mode (BIDIMODE=0,
RXONLY=0) in the case of continuous transfers . . . . .		851
Figure 276. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0,
RXONLY=0) in the case of continuous transfers . . . . .		852
Figure 277. Transmission using DMA . . . . .854
Figure 278. Reception using DMA . . . . .855
Figure 279. TI mode transfer . . . . .858
Figure 280. I 2 S block diagram . . . . .861
Figure 281. Full-duplex communication. . . . .863
Figure 282. I 2 S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . .864
Figure 283. I 2 S Philips standard waveforms (24-bit frame with CPOL = 0). . . . .864
Figure 284. Transmitting 0x8EAA33 . . . . .865
Figure 285. Receiving 0x8EAA33 . . . . .865
Figure 286. I 2 S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . .865
Figure 287. Example of 16-bit data frame extended to 32-bit channel frame . . . . .866
Figure 288. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . .866
Figure 289. MSB justified 24-bit frame length with CPOL = 0 . . . . .866
Figure 290. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .867
Figure 291. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . .867
Figure 292. LSB justified 24-bit frame length with CPOL = 0 . . . . .867
Figure 293. Operations required to transmit 0x3478AE. . . . .868
Figure 294. Operations required to receive 0x3478AE . . . . .868
Figure 295. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .868
Figure 296. Example of 16-bit data frame extended to 32-bit channel frame . . . . .869
Figure 297. PCM standard waveforms (16-bit) . . . . .869
Figure 298. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .869
Figure 299. Audio sampling frequency definition . . . . .870
Figure 300. I 2 S clock generator architecture . . . . .870
Figure 301. USB peripheral block diagram . . . . .889
Figure 302. Packet buffer areas with examples of buffer description table locations . . . . .893
Figure 303. Block diagram of STM32L0x2 MCU and Cortex ® -M0+-level debug support . . . . .921

Chapters