26. Revision history

PWR:
Updated Table 15: Low-power mode summary to add Return from ISR as entry condition.
Added Section : Entering low-power mode and Section : Exiting low-power mode.
Updated Section : Entering Sleep mode, Section : Exiting Sleep mode, Table 16: Sleep-now entry and exit and Table 17: Sleep-on-exit entry and exit.
Updated Section : Entering Stop mode, Section : Exiting Stop mode and Table 19: Stop mode entry and exit.
Updated Section : Entering Standby mode, Section : Exiting Standby mode and Table 20: Standby mode entry and exit.
Standby mode entry sequence updated in Table 20: Standby mode entry and exit to change WUF bit (PWR_CSR) to CWUF (PWR_CR).

RCC:
Changed access type for bits 24 and 25:31 of Section 6.3.18: RCC clock control & status register (RCC_CSR).

DMA:
Updated description of FTH[1:0] bits in Section 9.5.10: DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7).

TIM1:
Updated Table 50: TIMx Internal trigger connection.
Added note related to slave clock in MMS bits of Section 12.4.2: TIM1 control register 2 (TIMx_CR2).
Updated SMS bit description in Section 12.4.3: TIM1 slave mode control register (TIMx_SMCR) and added note related to slave clock.

TIM2/5:
Updated Table 54: TIMx internal trigger connection.
Added note related to the slave timer clock in Section 13.3.15: Timer synchronization.
Added note related to slave clock in MMS bits of Section 13.4.2: TIMx control register 2 (TIMx_CR2).
Updated SMS bit description in Section 13.4.3: TIMx slave mode control register (TIMx_SMCR) and added note related to slave clock.
Register format changed to 32 bits instead of 16 in Section 13.4.10: TIMx counter (TIMx_CNT) and Section 13.4.12: TIMx auto-reload register (TIMx_ARR).

TIM10/11:
Updated Table 57: TIMx internal trigger connection.
Added Section 14.5.2: TIM10/11 Interrupt enable register (TIMx_DIER).

WWDG

Updated Figure 157: Watchdog block diagram and Section 16.4: How to program the watchdog timeout.

WDGLS:

Updated note in 1. in Table 62: Min/max IWDG timeout period (in ms) at 32 kHz (LSI).

I2C:

Updated FREQ[5:0] bitfield description in Section 18.6.2: I2C Control register 2 (I2C_CR2)

USART:

Removed note related to RXNEIE in Section : Reception using DMA.

USB_OTG:

Updated description of TRDT bits in Section : OTG_FS USB configuration register (OTG_FS_GUSBCFG) and added Table 133: TRDT values..

DEBUG:

Updated REV_ID bits in Section : DBGMCU_IDCODE.

Removed DB bit G_TIM8_STOP in Section 23.16.5: Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ)

Updated:

• – Section 11.12.1: ADC status register (ADC_SR)
• – Section 11.12.8: ADC watchdog lower threshold register (ADC_LTR)
• – Section 11.12.9: ADC regular sequence register 1 (ADC_SQR1)
• – Section 11.12.11: ADC regular sequence register 3 (ADC_SQR3)
• – Section 11.12.15: ADC common control register (ADC_CCR)
• – Section 12.3.21: Debug mode
• – Table 51: Output control bits for complementary OCx and OCxN channels with break feature
• – Section 14.4.6: TIM9 capture/compare mode register 1 (TIMx_CCMR1)
• – Section 14.4.9: TIM9 prescaler (TIMx_PSC)
• – Section 14.4.10: TIM9 auto-reload register (TIMx_ARR)
• – Section 14.5.1: TIM10/11 control register 1 (TIMx_CR1)
• – Section 14.5.5: TIM10/11 capture/compare mode register 1 (TIMx_CCMR1)
• – Section 22: USB on-the-go full-speed (OTG_FS)

Updated Section 1: Documentation conventions to remove reference to Cortex-M7 core.

Updated Introduction

Updated Table 4: Memory mapping vs. Boot mode/physical remap in STM32F401xD/E

Updated Table 7: Maximum program/erase parallelism

Updated Section 3.6.3: Read protection (RDP)

PWR:

Updated Figure 8: Power-on reset/power-down reset waveform

Updated Section 5.1.2: Battery backup domain

Updated Section 5.4.1: PWR power control register (PWR_CR)

Updated Section 5.4.2: PWR power control/status register (PWR_CSR)

RCC:

Updated Section 6.1.1: System reset

Updated Section 6.1.3: Backup domain reset

Updated Section 6.3.4: RCC clock interrupt register (RCC_CIR)

Updated Section 6.3.12: RCC APB2 peripheral clock enable register (RCC_APB2ENR)

GPIO:

Updated Section 8.3.2: I/O pin multiplexer and mapping

Updated Section 8.4.1: GPIO port mode register (GPIOx_MODER) (x = A..E and H)

DMA:

Updated Section 9.5.10: DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7)

EXTI:

Updated Section 10.3.6: Pending register (EXTI_PR)

ADC:

Updated Section 11.3.3: Channel selection

Updated Section 11.3.5: Continuous conversion mode

Updated Section 11.8.1: Using the DMA

Updated Section 11.9: Temperature sensor

TIM1:

Updated Figure 39: Advanced-control timer block diagram

Updated Section 12.3.7: PWM input mode

Updated Section 12.3.16: Encoder interface mode

Updated Section 12.4.3: TIM1 slave mode control register (TIMx_SMCR)

Updated Section 12.4.7: TIM1 capture/compare mode register 1 (TIMx_CCMR1)

Updated Section 12.4.9: TIM1 capture/compare enable register (TIMx_CCER)

TIM2 to TIM5:

Updated Section 13.3.12: Encoder interface mode

Updated Section 13.4.3: TIMx slave mode control register (TIMx_SMCR)

Updated Section 13.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1)

TIM9 to TIM11:

Updated Section 14.3.6: PWM input mode (only for TIM9)

Updated Section 14.4.6: TIM9 capture/compare mode register 1 (TIMx_CCMR1)

Updated Section 14.5.5: TIM10/11 capture/compare mode register 1 (TIMx_CCMR1)

WWDG:

Updated \( t_{WWDG} \) +
in Section 16.4: How to program the watchdog timeout

RTC:

Updated Section 17.3.6: Reading the calendar

I2C:

Master and slave terms in Section 18: Inter-integrated circuit (I2C) interface replaced with controller and target, respectively.

Updated Section 18.6.2: I ² C Control register 2 (I2C_CR2)

Updated Section 18.6.8: I ² C Clock control register (I2C_CCR)

USART:

Updated Figure 179: USART data clock timing diagram (M=0)

SPI:

Updated Section 20.1: SPI introduction

Updated Figure 200: TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in case of continuous transfers

SDIO:

Updated Section 21.9.2: SDI clock control register (SDIO_CLKCR)

OTG_FS:

Updated Figure 248: Device-mode FIFO address mapping and AHB FIFO access mapping

Updated Figure 249: Host-mode FIFO address mapping and AHB FIFO access mapping

Updated Table 130: Device-mode control and status registers

Updated Section 22.17.6: Operational model

DBG:

Updated Section 23.4.2: Flexible SWJ-DP pin assignment

Updated Section : DBGMCU_IDCODE

Device electronic signature:

Updated Section 24.1: Unique device ID register (96 bits)

Important security notice:

Added Section 25: Important security notice