RM0368-STM32F401xB-C-401xD-E

Introduction

This Reference manual targets application developers. It provides complete information on how to use the memory and the peripherals of the STM32F401xB/C and STM32F401xD/E microcontrollers.

STM32F401xB/C and STM32F401xD/E are part of the STM32F401xx family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics refer to the datasheets.

For information on the Arm ^®Cortex ^®-M4 with FPU core, refer to the Cortex ^®-M4 with FPU Technical Reference Manual .

STM32F401xx microcontrollers include ST state-of-the-art patented technology.

Available from STMicroelectronics web site ( http://www.st.com ):

• STM32F401xB/C datasheet (DS9716)
• STM32F401xD/E datasheet (DS10086)
• STM32F401xB/C errata sheet (ES0222)
• STM32F401xD/E errata sheet (ES0299)
• For information on the Arm ^®-M4 core with FPU, refer to the STM32F3xx/F4xxx Cortex ^®-M4 with FPU-M4 programming manual (PM0214)

1 Documentation conventions . . . . . 34
- 1.1 List of abbreviations for registers . . . . . 34
- 1.2 Glossary . . . . . 35
- 1.3 Peripheral availability . . . . . 35
2 Memory and bus architecture . . . . . 36
- 2.1 System architecture . . . . . 36
  - 2.1.1 I-bus . . . . . 37
  - 2.1.2 D-bus . . . . . 37
  - 2.1.3 S-bus . . . . . 37
  - 2.1.4 DMA memory bus . . . . . 37
  - 2.1.5 DMA peripheral bus . . . . . 37
  - 2.1.6 BusMatrix . . . . . 37
  - 2.1.7 AHB/APB bridges (APB) . . . . . 37
- 2.2 Memory organization . . . . . 38
- 2.3 Memory map . . . . . 38
  - 2.3.1 Embedded SRAM . . . . . 40
  - 2.3.2 Flash memory overview . . . . . 40
  - 2.3.3 Bit banding . . . . . 40
- 2.4 Boot configuration . . . . . 41
3 Embedded flash memory interface . . . . . 44
- 3.1 Introduction . . . . . 44
- 3.2 Main features . . . . . 44
- 3.3 Embedded Flash memory in STM32F401xB/C and STM32F401xD/E . . . . . 45
- 3.4 Read interface . . . . . 46
  - 3.4.1 Relation between CPU clock frequency and flash memory read time . . 46
  - 3.4.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . 47
- 3.5 Erase and program operations . . . . . 49
  - 3.5.1 Unlocking the Flash control register . . . . . 49
  - 3.5.2 Program/erase parallelism . . . . . 50
  - 3.5.3 Erase . . . . . 50

3.5.4	Programming . . . . .	51
3.5.5	Interrupts . . . . .	52
3.6	Option bytes . . . . .	52
3.6.1	Description of user option bytes . . . . .	52
3.6.2	Programming user option bytes . . . . .	54
3.6.3	Read protection (RDP) . . . . .	54
3.6.4	Write protections . . . . .	56
3.6.5	Proprietary code readout protection (PCROP) . . . . .	57
3.7	One-time programmable bytes . . . . .	59
3.8	Flash interface registers . . . . .	60
3.8.1	Flash access control register (FLASH_ACR) . . . . .	60
3.8.2	Flash key register (FLASH_KEYR) . . . . .	61
3.8.3	Flash option key register (FLASH_OPTKEYR) . . . . .	61
3.8.4	Flash status register (FLASH_SR) . . . . .	62
3.8.5	Flash control register (FLASH_CR) . . . . .	63
3.8.6	Flash option control register (FLASH_OPTCR) . . . . .	64
3.8.7	Flash interface register map . . . . .	67
4	CRC calculation unit . . . . .	68
4.1	CRC introduction . . . . .	68
4.2	CRC main features . . . . .	68
4.3	CRC functional description . . . . .	68
4.4	CRC registers . . . . .	69
4.4.1	Data register (CRC_DR) . . . . .	69
4.4.2	Independent data register (CRC_IDR) . . . . .	69
4.4.3	Control register (CRC_CR) . . . . .	70
4.4.4	CRC register map . . . . .	70
5	Power controller (PWR) . . . . .	71
5.1	Power supplies . . . . .	71
5.1.1	Independent A/D converter supply and reference voltage . . . . .	72
5.1.2	Battery backup domain . . . . .	72
5.1.3	Voltage regulator . . . . .	73
5.2	Power supply supervisor . . . . .	74
5.2.1	Power-on reset (POR)/power-down reset (PDR) . . . . .	74
5.2.2	Brownout reset (BOR) . . . . .	75

5.2.3	Programmable voltage detector (PVD) .....	76
5.3	Low-power modes .....	76
5.3.1	Slowing down system clocks .....	78
5.3.2	Peripheral clock gating .....	78
5.3.3	Sleep mode .....	79
5.3.4	Stop mode .....	80
5.3.5	Standby mode .....	83
5.3.6	Programming the RTC alternate functions to wake up the device from the Stop and Standby modes .....	84
5.4	Power control registers .....	87
5.4.1	PWR power control register (PWR_CR) .....	87
5.4.2	PWR power control/status register (PWR_CSR) .....	89
5.5	PWR register map .....	90
6	Reset and clock control (RCC) for STM32F401xB/C and STM32F401xD/E .....	91
6.1	Reset .....	91
6.1.1	System reset .....	91
6.1.2	Power reset .....	92
6.1.3	Backup domain reset .....	93
6.2	Clocks .....	93
6.2.1	HSE clock .....	96
6.2.2	HSI clock .....	97
6.2.3	PLL configuration .....	97
6.2.4	LSE clock .....	98
6.2.5	LSI clock .....	98
6.2.6	System clock (SYSCLK) selection .....	98
6.2.7	Clock security system (CSS) .....	99
6.2.8	RTC/AWU clock .....	99
6.2.9	Watchdog clock .....	100
6.2.10	Clock-out capability .....	100
6.2.11	Internal/external clock measurement using TIM5/TIM11 .....	100
6.3	RCC registers .....	103
6.3.1	RCC clock control register (RCC_CR) .....	103
6.3.2	RCC PLL configuration register (RCC_PLLCFGR) .....	105
6.3.3	RCC clock configuration register (RCC_CFGR) .....	107
6.3.4	RCC clock interrupt register (RCC_CIR) .....	110

6.3.5	RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . .	112
6.3.6	RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .	114
6.3.7	RCC APB1 peripheral reset register for (RCC_APB1RSTR) . . . . .	114
6.3.8	RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . .	116
6.3.9	RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . .	118
6.3.10	RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . .	119
6.3.11	RCC APB1 peripheral clock enable register (RCC_APB1ENR) . . . . .	119
6.3.12	RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .	122
6.3.13	RCC AHB1 peripheral clock enable in low power mode register (RCC_AHB1LPENR) . . . . .	124
6.3.14	RCC AHB2 peripheral clock enable in low power mode register (RCC_AHB2LPENR) . . . . .	125
6.3.15	RCC APB1 peripheral clock enable in low power mode register (RCC_APB1LPENR) . . . . .	126
6.3.16	RCC APB2 peripheral clock enabled in low power mode register (RCC_APB2LPENR) . . . . .	128
6.3.17	RCC Backup domain control register (RCC_BDCR) . . . . .	130
6.3.18	RCC clock control & status register (RCC_CSR) . . . . .	131
6.3.19	RCC spread spectrum clock generation register (RCC_SSCGR) . . . . .	133
6.3.20	RCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . .	134
6.3.21	RCC Dedicated Clocks Configuration Register (RCC_DCKCFGR) . . . . .	136
6.3.22	RCC register map . . . . .	137
7	System configuration controller (SYSCFG) . . . . .	140
7.1	I/O compensation cell . . . . .	140
7.2	SYSCFG registers . . . . .	140
7.2.1	SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .	140
7.2.2	SYSCFG peripheral mode configuration register (SYSCFG_PMC) . . . . .	141
7.2.3	SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . .	142
7.2.4	SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) . . . . .	142
7.2.5	SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) . . . . .	143
7.2.6	SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) . . . . .	143
7.2.7	Compensation cell control register (SYSCFG_CMPCR) . . . . .	144
7.2.8	SYSCFG register map . . . . .	145

8	General-purpose I/Os (GPIO) . . . . .	146
8.1	GPIO introduction . . . . .	146
8.2	GPIO main features . . . . .	146
8.3	GPIO functional description . . . . .	146
8.3.1	General-purpose I/O (GPIO) . . . . .	148
8.3.2	I/O pin multiplexer and mapping . . . . .	149
8.3.3	I/O port control registers . . . . .	152
8.3.4	I/O port data registers . . . . .	152
8.3.5	I/O data bitwise handling . . . . .	152
8.3.6	GPIO locking mechanism . . . . .	152
8.3.7	I/O alternate function input/output . . . . .	153
8.3.8	External interrupt/wake-up lines . . . . .	153
8.3.9	Input configuration . . . . .	153
8.3.10	Output configuration . . . . .	154
8.3.11	Alternate function configuration . . . . .	155
8.3.12	Analog configuration . . . . .	156
8.3.13	Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins . . . . .	156
8.3.14	Using the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins . . . . .	156
8.3.15	Selection of RTC functions . . . . .	157
8.4	GPIO registers . . . . .	158
8.4.1	GPIO port mode register (GPIOx_MODER) (x = A..E and H) . . . . .	158
8.4.2	GPIO port output type register (GPIOx_OTYPER) (x = A..E and H) . . . . .	158
8.4.3	GPIO port output speed register (GPIOx_OSPEEDR) (x = A..E and H) . . . . .	159
8.4.4	GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..E and H) . . . . .	159
8.4.5	GPIO port input data register (GPIOx_IDR) (x = A..E and H) . . . . .	160
8.4.6	GPIO port output data register (GPIOx_ODR) (x = A..E and H) . . . . .	160
8.4.7	GPIO port bit set/reset register (GPIOx_BSRR) (x = A..E and H) . . . . .	161
8.4.8	GPIO port configuration lock register (GPIOx_LCKR) (x = A..E and H) . . . . .	161
8.4.9	GPIO alternate function low register (GPIOx_AFRL) (x = A..E and H) . . . . .	162
8.4.10	GPIO alternate function high register (GPIOx_AFRH) (x = A..E and H) . . . . .	163
8.4.11	GPIO register map . . . . .	164

9	DMA controller (DMA) . . . . .	166
9.1	DMA introduction . . . . .	166
9.2	DMA main features . . . . .	166
9.3	DMA functional description . . . . .	168
9.3.1	General description . . . . .	168
9.3.2	DMA transactions . . . . .	169
9.3.3	Channel selection . . . . .	170
9.3.4	Arbiter . . . . .	171
9.3.5	DMA streams . . . . .	172
9.3.6	Source, destination and transfer modes . . . . .	172
9.3.7	Pointer incrementation . . . . .	175
9.3.8	Circular mode . . . . .	176
9.3.9	Double buffer mode . . . . .	176
9.3.10	Programmable data width, packing/unpacking, endianness . . . . .	177
9.3.11	Single and burst transfers . . . . .	179
9.3.12	FIFO . . . . .	180
9.3.13	DMA transfer completion . . . . .	182
9.3.14	DMA transfer suspension . . . . .	183
9.3.15	Flow controller . . . . .	184
9.3.16	Summary of the possible DMA configurations . . . . .	185
9.3.17	Stream configuration procedure . . . . .	185
9.3.18	Error management . . . . .	186
9.4	DMA interrupts . . . . .	187
9.5	DMA registers . . . . .	188
9.5.1	DMA low interrupt status register (DMA_LISR) . . . . .	188
9.5.2	DMA high interrupt status register (DMA_HISR) . . . . .	189
9.5.3	DMA low interrupt flag clear register (DMA_LIFCR) . . . . .	190
9.5.4	DMA high interrupt flag clear register (DMA_HIFCR) . . . . .	190
9.5.5	DMA stream x configuration register (DMA_SxCR) (x = 0..7) . . . . .	191
9.5.6	DMA stream x number of data register (DMA_SxNDTR) (x = 0..7) . . . . .	194
9.5.7	DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7) . . . . .	195
9.5.8	DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7) . . . . .	195
9.5.9	DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7) . . . . .	195
9.5.10	DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7) . . . . .	196
9.5.11	DMA register map . . . . .	198

10 Interrupts and events . . . . . 202
- 10.1 Nested vectored interrupt controller (NVIC) . . . . . 202
  - 10.1.1 NVIC features . . . . . 202
  - 10.1.2 SysTick calibration value register . . . . . 202
  - 10.1.3 Interrupt and exception vectors . . . . . 202
- 10.2 External interrupt/event controller (EXTI) . . . . . 202
  - 10.2.1 EXTI main features . . . . . 205
  - 10.2.2 EXTI block diagram . . . . . 206
  - 10.2.3 Wake-up event management . . . . . 206
  - 10.2.4 Functional description . . . . . 206
  - 10.2.5 External interrupt/event line mapping . . . . . 208
- 10.3 EXTI registers . . . . . 209
  - 10.3.1 Interrupt mask register (EXTI_IMR) . . . . . 209
  - 10.3.2 Event mask register (EXTI_EMR) . . . . . 209
  - 10.3.3 Rising trigger selection register (EXTI_RTSR) . . . . . 210
  - 10.3.4 Falling trigger selection register (EXTI_FTSR) . . . . . 210
  - 10.3.5 Software interrupt event register (EXTI_SWIER) . . . . . 211
  - 10.3.6 Pending register (EXTI_PR) . . . . . 211
  - 10.3.7 EXTI register map . . . . . 212

11 Analog-to-digital converter (ADC) . . . . . 213
- 11.1 ADC introduction . . . . . 213
- 11.2 ADC main features . . . . . 213
- 11.3 ADC functional description . . . . . 214
  - 11.3.1 ADC on-off control . . . . . 215
  - 11.3.2 ADC clock . . . . . 215
  - 11.3.3 Channel selection . . . . . 215
  - 11.3.4 Single conversion mode . . . . . 216
  - 11.3.5 Continuous conversion mode . . . . . 216
  - 11.3.6 Timing diagram . . . . . 217
  - 11.3.7 Analog watchdog . . . . . 217
  - 11.3.8 Scan mode . . . . . 218
  - 11.3.9 Injected channel management . . . . . 218
  - 11.3.10 Discontinuous mode . . . . . 219
- 11.4 Data alignment . . . . . 221
- 11.5 Channel-wise programmable sampling time . . . . . 222

11.6	Conversion on external trigger and trigger polarity . . . . .	222
11.7	Fast conversion mode . . . . .	224
11.8	Data management . . . . .	225
11.8.1	Using the DMA . . . . .	225
11.8.2	Managing a sequence of conversions without using the DMA . . . . .	225
11.8.3	Conversions without DMA and without overrun detection . . . . .	226
11.9	Temperature sensor . . . . .	226
11.10	Battery charge monitoring . . . . .	227
11.11	ADC interrupts . . . . .	228
11.12	ADC registers . . . . .	229
11.12.1	ADC status register (ADC_SR) . . . . .	229
11.12.2	ADC control register 1 (ADC_CR1) . . . . .	230
11.12.3	ADC control register 2 (ADC_CR2) . . . . .	232
11.12.4	ADC sample time register 1 (ADC_SMPR1) . . . . .	234
11.12.5	ADC sample time register 2 (ADC_SMPR2) . . . . .	234
11.12.6	ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) . . . . .	235
11.12.7	ADC watchdog higher threshold register (ADC_HTR) . . . . .	235
11.12.8	ADC watchdog lower threshold register (ADC_LTR) . . . . .	236
11.12.9	ADC regular sequence register 1 (ADC_SQR1) . . . . .	236
11.12.10	ADC regular sequence register 2 (ADC_SQR2) . . . . .	237
11.12.11	ADC regular sequence register 3 (ADC_SQR3) . . . . .	237
11.12.12	ADC injected sequence register (ADC_JSQR) . . . . .	238
11.12.13	ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . .	239
11.12.14	ADC regular data register (ADC_DR) . . . . .	239
11.12.15	ADC common control register (ADC_CCR) . . . . .	239
11.12.16	ADC register map . . . . .	240
12	Advanced-control timer (TIM1) . . . . .	243
12.1	TIM1 introduction . . . . .	243
12.2	TIM1 main features . . . . .	244
12.3	TIM1 functional description . . . . .	246
12.3.1	Time-base unit . . . . .	246
12.3.2	Counter modes . . . . .	248
12.3.3	Repetition counter . . . . .	257
12.3.4	Clock selection . . . . .	259
12.3.5	Capture/compare channels . . . . .	262

12.3.6	Input capture mode . . . . .	265
12.3.7	PWM input mode . . . . .	266
12.3.8	Forced output mode . . . . .	266
12.3.9	Output compare mode . . . . .	267
12.3.10	PWM mode . . . . .	268
12.3.11	Complementary outputs and dead-time insertion . . . . .	271
12.3.12	Using the break function . . . . .	273
12.3.13	Clearing the OCxREF signal on an external event . . . . .	276
12.3.14	6-step PWM generation . . . . .	277
12.3.15	One-pulse mode . . . . .	278
12.3.16	Encoder interface mode . . . . .	279
12.3.17	Timer input XOR function . . . . .	282
12.3.18	Interfacing with Hall sensors . . . . .	282
12.3.19	TIMx and external trigger synchronization . . . . .	284
12.3.20	Timer synchronization . . . . .	287
12.3.21	Debug mode . . . . .	287
12.4	TIM1 registers . . . . .	288
12.4.1	TIM1 control register 1 (TIMx_CR1) . . . . .	288
12.4.2	TIM1 control register 2 (TIMx_CR2) . . . . .	289
12.4.3	TIM1 slave mode control register (TIMx_SMCR) . . . . .	292
12.4.4	TIM1 DMA/interrupt enable register (TIMx_DIER) . . . . .	294
12.4.5	TIM1 status register (TIMx_SR) . . . . .	296
12.4.6	TIM1 event generation register (TIMx_EGR) . . . . .	297
12.4.7	TIM1 capture/compare mode register 1 (TIMx_CCMR1) . . . . .	299
12.4.8	TIM1 capture/compare mode register 2 (TIMx_CCMR2) . . . . .	301
12.4.9	TIM1 capture/compare enable register (TIMx_CCER) . . . . .	303
12.4.10	TIM1 counter (TIMx_CNT) . . . . .	307
12.4.11	TIM1 prescaler (TIMx_PSC) . . . . .	307
12.4.12	TIM1 auto-reload register (TIMx_ARR) . . . . .	307
12.4.13	TIM1 repetition counter register (TIMx_RCR) . . . . .	308
12.4.14	TIM1 capture/compare register 1 (TIMx_CCR1) . . . . .	308
12.4.15	TIM1 capture/compare register 2 (TIMx_CCR2) . . . . .	309
12.4.16	TIM1 capture/compare register 3 (TIMx_CCR3) . . . . .	309
12.4.17	TIM1 capture/compare register 4 (TIMx_CCR4) . . . . .	310
12.4.18	TIM1 break and dead-time register (TIMx_BDTR) . . . . .	310
12.4.19	TIM1 DMA control register (TIMx_DCR) . . . . .	312
12.4.20	TIM1 DMA address for full transfer (TIMx_DMAR) . . . . .	313

12.4.21	TIM1 register map .....	314
13	General-purpose timers (TIM2 to TIM5) .....	316
13.1	TIM2 to TIM5 introduction .....	316
13.2	TIM2 to TIM5 main features .....	316
13.3	TIM2 to TIM5 functional description .....	317
13.3.1	Time-base unit .....	317
13.3.2	Counter modes .....	319
13.3.3	Clock selection .....	328
13.3.4	Capture/compare channels .....	331
13.3.5	Input capture mode .....	333
13.3.6	PWM input mode .....	334
13.3.7	Forced output mode .....	335
13.3.8	Output compare mode .....	335
13.3.9	PWM mode .....	336
13.3.10	One-pulse mode .....	339
13.3.11	Clearing the OCxREF signal on an external event .....	340
13.3.12	Encoder interface mode .....	341
13.3.13	Timer input XOR function .....	344
13.3.14	Timers and external trigger synchronization .....	344
13.3.15	Timer synchronization .....	347
13.3.16	Debug mode .....	352
13.4	TIM2 to TIM5 registers .....	353
13.4.1	TIMx control register 1 (TIMx_CR1) .....	353
13.4.2	TIMx control register 2 (TIMx_CR2) .....	355
13.4.3	TIMx slave mode control register (TIMx_SMCR) .....	356
13.4.4	TIMx DMA/Interrupt enable register (TIMx_DIER) .....	358
13.4.5	TIMx status register (TIMx_SR) .....	359
13.4.6	TIMx event generation register (TIMx_EGR) .....	361
13.4.7	TIMx capture/compare mode register 1 (TIMx_CCMR1) .....	362
13.4.8	TIMx capture/compare mode register 2 (TIMx_CCMR2) .....	365
13.4.9	TIMx capture/compare enable register (TIMx_CCER) .....	366
13.4.10	TIMx counter (TIMx_CNT) .....	368
13.4.11	TIMx prescaler (TIMx_PSC) .....	368
13.4.12	TIMx auto-reload register (TIMx_ARR) .....	368
13.4.13	TIMx capture/compare register 1 (TIMx_CCR1) .....	369
13.4.14	TIMx capture/compare register 2 (TIMx_CCR2) .....	369

13.4.15	TIMx capture/compare register 3 (TIMx_CCR3) . . . . .	370
13.4.16	TIMx capture/compare register 4 (TIMx_CCR4) . . . . .	370
13.4.17	TIMx DMA control register (TIMx_DCR) . . . . .	371
13.4.18	TIMx DMA address for full transfer (TIMx_DMAR) . . . . .	372
13.4.19	TIM2 option register (TIM2_OR) . . . . .	372
13.4.20	TIM5 option register (TIM5_OR) . . . . .	373
13.4.21	TIMx register map . . . . .	374
14	General-purpose timers (TIM9 to TIM11) . . . . .	376
14.1	TIM9/10/11 introduction . . . . .	376
14.2	TIM9/10/11 main features . . . . .	376
14.2.1	TIM9 main features . . . . .	376
14.2.2	TIM10/TIM11 main features . . . . .	377
14.3	TIM9 to TIM11 functional description . . . . .	379
14.3.1	Time-base unit . . . . .	379
14.3.2	Counter modes . . . . .	381
14.3.3	Clock selection . . . . .	384
14.3.4	Capture/compare channels . . . . .	386
14.3.5	Input capture mode . . . . .	387
14.3.6	PWM input mode (only for TIM9) . . . . .	389
14.3.7	Forced output mode . . . . .	390
14.3.8	Output compare mode . . . . .	390
14.3.9	PWM mode . . . . .	391
14.3.10	One-pulse mode . . . . .	392
14.3.11	TIM9 external trigger synchronization . . . . .	394
14.3.12	Timer synchronization (TIM9) . . . . .	397
14.3.13	Debug mode . . . . .	397
14.4	TIM9 registers . . . . .	398
14.4.1	TIM9 control register 1 (TIMx_CR1) . . . . .	398
14.4.2	TIM9 slave mode control register (TIMx_SMCR) . . . . .	399
14.4.3	TIM9 Interrupt enable register (TIMx_DIER) . . . . .	400
14.4.4	TIM9 status register (TIMx_SR) . . . . .	402
14.4.5	TIM9 event generation register (TIMx_EGR) . . . . .	403
14.4.6	TIM9 capture/compare mode register 1 (TIMx_CCMR1) . . . . .	404
14.4.7	TIM9 capture/compare enable register (TIMx_CCER) . . . . .	407
14.4.8	TIM9 counter (TIMx_CNT) . . . . .	408
14.4.9	TIM9 prescaler (TIMx_PSC) . . . . .	408

14.4.10	TIM9 auto-reload register (TIMx_ARR) . . . . .	408
14.4.11	TIM9 capture/compare register 1 (TIMx_CCR1) . . . . .	409
14.4.12	TIM9 capture/compare register 2 (TIMx_CCR2) . . . . .	409
14.4.13	TIM9 register map . . . . .	410
14.5	TIM10/11 registers . . . . .	412
14.5.1	TIM10/11 control register 1 (TIMx_CR1) . . . . .	412
14.5.2	TIM10/11 Interrupt enable register (TIMx_DIER) . . . . .	413
14.5.3	TIM status register (TIMx_SR) . . . . .	413
14.5.4	TIM event generation register (TIMx_EGR) . . . . .	414
14.5.5	TIM10/11 capture/compare mode register 1 (TIMx_CCMR1) . . . . .	414
14.5.6	TIM10/11 capture/compare enable register (TIMx_CCER) . . . . .	417
14.5.7	TIM10/11 counter (TIMx_CNT) . . . . .	418
14.5.8	TIM10/11 prescaler (TIMx_PSC) . . . . .	418
14.5.9	TIM10/11 auto-reload register (TIMx_ARR) . . . . .	418
14.5.10	TIM10/11 capture/compare register 1 (TIMx_CCR1) . . . . .	419
14.5.11	TIM11 option register 1 (TIM11_OR) . . . . .	419
14.5.12	TIM10/11 register map . . . . .	420
15	Independent watchdog (IWDG) . . . . .	422
15.1	IWDG introduction . . . . .	422
15.2	IWDG main features . . . . .	422
15.3	IWDG functional description . . . . .	422
15.3.1	Hardware watchdog . . . . .	422
15.3.2	Register access protection . . . . .	422
15.3.3	Debug mode . . . . .	423
15.4	IWDG registers . . . . .	424
15.4.1	Key register (IWDG_KR) . . . . .	424
15.4.2	Prescaler register (IWDG_PR) . . . . .	424
15.4.3	Reload register (IWDG_RLR) . . . . .	425
15.4.4	Status register (IWDG_SR) . . . . .	425
15.4.5	IWDG register map . . . . .	426
16	Window watchdog (WWDG) . . . . .	427
16.1	WWDG introduction . . . . .	427
16.2	WWDG main features . . . . .	427
16.3	WWDG functional description . . . . .	427

16.4	How to program the watchdog timeout . . . . .	429
16.5	Debug mode . . . . .	430
16.6	WWDG registers . . . . .	431
16.6.1	Control register (WWDG_CR) . . . . .	431
16.6.2	Configuration register (WWDG_CFR) . . . . .	432
16.6.3	Status register (WWDG_SR) . . . . .	432
16.6.4	WWDG register map . . . . .	433
17	Real-time clock (RTC) . . . . .	434
17.1	Introduction . . . . .	434
17.2	RTC main features . . . . .	435
17.3	RTC functional description . . . . .	436
17.3.1	Clock and prescalers . . . . .	436
17.3.2	Real-time clock and calendar . . . . .	437
17.3.3	Programmable alarms . . . . .	437
17.3.4	Periodic auto-wakeup . . . . .	438
17.3.5	RTC initialization and configuration . . . . .	439
17.3.6	Reading the calendar . . . . .	440
17.3.7	Resetting the RTC . . . . .	441
17.3.8	RTC synchronization . . . . .	442
17.3.9	RTC reference clock detection . . . . .	442
17.3.10	RTC coarse digital calibration . . . . .	443
17.3.11	RTC smooth digital calibration . . . . .	444
17.3.12	Timestamp function . . . . .	446
17.3.13	Tamper detection . . . . .	447
17.3.14	Calibration clock output . . . . .	448
17.3.15	Alarm output . . . . .	449
17.4	RTC and low-power modes . . . . .	449
17.5	RTC interrupts . . . . .	449
17.6	RTC registers . . . . .	451
17.6.1	RTC time register (RTC_TR) . . . . .	451
17.6.2	RTC date register (RTC_DR) . . . . .	452
17.6.3	RTC control register (RTC_CR) . . . . .	453
17.6.4	RTC initialization and status register (RTC_ISR) . . . . .	455
17.6.5	RTC prescaler register (RTC_PRER) . . . . .	457
17.6.6	RTC wake-up timer register (RTC_WUTR) . . . . .	458

17.6.7	RTC calibration register (RTC_CALIBR) . . . . .	459
17.6.8	RTC alarm A register (RTC_ALRMAR) . . . . .	460
17.6.9	RTC alarm B register (RTC_ALRMBR) . . . . .	461
17.6.10	RTC write protection register (RTC_WPR) . . . . .	462
17.6.11	RTC sub second register (RTC_SSR) . . . . .	462
17.6.12	RTC shift control register (RTC_SHIFTR) . . . . .	463
17.6.13	RTC time stamp time register (RTC_TSTR) . . . . .	463
17.6.14	RTC time stamp date register (RTC_TSDR) . . . . .	464
17.6.15	RTC timestamp sub second register (RTC_TSSSR) . . . . .	465
17.6.16	RTC calibration register (RTC_CALR) . . . . .	465
17.6.17	RTC tamper and alternate function configuration register (RTC_TAFCR) . . . . .	467
17.6.18	RTC alarm A sub second register (RTC_ALRMASSR) . . . . .	468
17.6.19	RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .	469
17.6.20	RTC backup registers (RTC_BKPxR) . . . . .	471
17.6.21	RTC register map . . . . .	471
18	Inter-integrated circuit (I2C) interface . . . . .	474
18.1	I ²C introduction . . . . .	474
18.2	I ²C main features . . . . .	474
18.3	I ²C functional description . . . . .	475
18.3.1	Mode selection . . . . .	475
18.3.2	I2C target mode . . . . .	477
18.3.3	I2C controller mode . . . . .	479
18.3.4	Error conditions . . . . .	484
18.3.5	Programmable noise filter . . . . .	485
18.3.6	SDA/SCL line control . . . . .	486
18.3.7	SMBus . . . . .	486
18.3.8	DMA requests . . . . .	489
18.3.9	Packet error checking . . . . .	490
18.4	I ²C interrupts . . . . .	491
18.5	I ²C debug mode . . . . .	493
18.6	I ²C registers . . . . .	493
18.6.1	I ²C Control register 1 (I2C_CR1) . . . . .	493
18.6.2	I ²C Control register 2 (I2C_CR2) . . . . .	495
18.6.3	I ²C Own address register 1 (I2C_OAR1) . . . . .	497
18.6.4	I ²C Own address register 2 (I2C_OAR2) . . . . .	497

18.6.5	I ²C Data register (I2C_DR) .....	498
18.6.6	I ²C Status register 1 (I2C_SR1) .....	498
18.6.7	I ²C Status register 2 (I2C_SR2) .....	501
18.6.8	I ²C Clock control register (I2C_CCR) .....	503
18.6.9	I ²C TRISE register (I2C_TRISE) .....	504
18.6.10	I ²C FLTR register (I2C_FLTR) .....	504
18.6.11	I2C register map .....	505
19	Universal synchronous asynchronous receiver transmitter (USART) .....	506
19.1	USART introduction .....	506
19.2	USART main features .....	506
19.3	USART functional description .....	507
19.3.1	USART character description .....	510
19.3.2	Transmitter .....	511
19.3.3	Receiver .....	514
19.3.4	Fractional baud rate generation .....	519
19.3.5	USART receiver tolerance to clock deviation .....	529
19.3.6	Multiprocessor communication .....	530
19.3.7	Parity control .....	532
19.3.8	LIN (local interconnection network) mode .....	533
19.3.9	USART synchronous mode .....	535
19.3.10	Single-wire half-duplex communication .....	537
19.3.11	Smartcard .....	538
19.3.12	IrDA SIR ENDEC block .....	540
19.3.13	Continuous communication using DMA .....	542
19.3.14	Hardware flow control .....	544
19.4	USART interrupts .....	547
19.5	USART mode configuration .....	548
19.6	USART registers .....	548
19.6.1	Status register (USART_SR) .....	548
19.6.2	Data register (USART_DR) .....	551
19.6.3	Baud rate register (USART_BRR) .....	551
19.6.4	Control register 1 (USART_CR1) .....	551
19.6.5	Control register 2 (USART_CR2) .....	554
19.6.6	Control register 3 (USART_CR3) .....	555
19.6.7	Guard time and prescaler register (USART_GTPR) .....	557

19.6.8	USART register map . . . . .	558
20	Serial peripheral interface (SPI) . . . . .	559
20.1	SPI introduction . . . . .	559
20.2	SPI and I ²S main features . . . . .	560
20.2.1	SPI features . . . . .	560
20.2.2	I ²S features . . . . .	561
20.3	SPI functional description . . . . .	562
20.3.1	General description . . . . .	562
20.3.2	Configuring the SPI in slave mode . . . . .	566
20.3.3	Configuring the SPI in master mode . . . . .	568
20.3.4	Configuring the SPI for half-duplex communication . . . . .	570
20.3.5	Data transmission and reception procedures . . . . .	571
20.3.6	CRC calculation . . . . .	577
20.3.7	Status flags . . . . .	579
20.3.8	Disabling the SPI . . . . .	580
20.3.9	SPI communication using DMA (direct memory addressing) . . . . .	581
20.3.10	Error flags . . . . .	583
20.3.11	SPI interrupts . . . . .	584
20.4	I ²S functional description . . . . .	585
20.4.1	I ²S general description . . . . .	585
20.4.2	I ²S full duplex . . . . .	586
20.4.3	Supported audio protocols . . . . .	587
20.4.4	Clock generator . . . . .	593
20.4.5	I ²S master mode . . . . .	595
20.4.6	I ²S slave mode . . . . .	597
20.4.7	Status flags . . . . .	599
20.4.8	Error flags . . . . .	600
20.4.9	I ²S interrupts . . . . .	601
20.4.10	DMA features . . . . .	601
20.5	SPI and I ²S registers . . . . .	602
20.5.1	SPI control register 1 (SPI_CR1)(not used in I ²S mode) . . . . .	602
20.5.2	SPI control register 2 (SPI_CR2) . . . . .	604
20.5.3	SPI status register (SPI_SR) . . . . .	605
20.5.4	SPI data register (SPI_DR) . . . . .	606
20.5.5	SPI CRC polynomial register (SPI_CRCPR)(not used in I ²S mode) . . . . .	607

20.5.6	SPI RX CRC register (SPI_RXCRCR)(not used in I ²S mode) . . . . .	607
20.5.7	SPI TX CRC register (SPI_TXCRCR)(not used in I ²S mode) . . . . .	608
20.5.8	SPI_I ²S configuration register (SPI_I2SCFGR) . . . . .	608
20.5.9	SPI_I ²S prescaler register (SPI_I2SPR) . . . . .	610
20.5.10	SPI register map . . . . .	611
21	Secure digital input/output interface (SDIO) . . . . .	612
21.1	SDIO main features . . . . .	612
21.2	SDIO bus topology . . . . .	612
21.3	SDIO functional description . . . . .	614
21.3.1	SDIO adapter . . . . .	616
21.3.2	SDIO APB2 interface . . . . .	626
21.4	Card functional description . . . . .	627
21.4.1	Card identification mode . . . . .	627
21.4.2	Card reset . . . . .	627
21.4.3	Operating voltage range validation . . . . .	627
21.4.4	Card identification process . . . . .	628
21.4.5	Block write . . . . .	629
21.4.6	Block read . . . . .	630
21.4.7	Stream access, stream write and stream read (MultiMediaCard only) . . . . .	630
21.4.8	Erase: group erase and sector erase . . . . .	632
21.4.9	Wide bus selection or deselection . . . . .	632
21.4.10	Protection management . . . . .	632
21.4.11	Card status register . . . . .	635
21.4.12	SD status register . . . . .	638
21.4.13	SD I/O mode . . . . .	642
21.4.14	Commands and responses . . . . .	643
21.5	Response formats . . . . .	647
21.5.1	R1 (normal response command) . . . . .	647
21.5.2	R1b . . . . .	647
21.5.3	R2 (CID, CSD register) . . . . .	647
21.5.4	R3 (OCR register) . . . . .	648
21.5.5	R4 (Fast I/O) . . . . .	648
21.5.6	R4b . . . . .	649
21.5.7	R5 (interrupt request) . . . . .	649
21.5.8	R6 . . . . .	650

21.6	SDIO I/O card-specific operations . . . . .	650
21.6.1	SDIO I/O read wait operation by SDIO_D2 signaling . . . . .	651
21.6.2	SDIO read wait operation by stopping SDIO_CK . . . . .	651
21.6.3	SDIO suspend/resume operation . . . . .	651
21.6.4	SDIO interrupts . . . . .	651
21.7	CE-ATA specific operations . . . . .	652
21.7.1	Command completion signal disable . . . . .	652
21.7.2	Command completion signal enable . . . . .	652
21.7.3	CE-ATA interrupt . . . . .	652
21.7.4	Aborting CMD61 . . . . .	652
21.8	HW flow control . . . . .	653
21.9	SDIO registers . . . . .	653
21.9.1	SDIO power control register (SDIO_POWER) . . . . .	653
21.9.2	SDI clock control register (SDIO_CLKCR) . . . . .	654
21.9.3	SDIO argument register (SDIO_ARG) . . . . .	655
21.9.4	SDIO command register (SDIO_CMD) . . . . .	655
21.9.5	SDIO command response register (SDIO_RESPCMD) . . . . .	656
21.9.6	SDIO response 1..4 register (SDIO_RESPx) . . . . .	657
21.9.7	SDIO data timer register (SDIO_DTIMER) . . . . .	657
21.9.8	SDIO data length register (SDIO_DLEN) . . . . .	658
21.9.9	SDIO data control register (SDIO_DCTRL) . . . . .	659
21.9.10	SDIO data counter register (SDIO_DCOUNT) . . . . .	660
21.9.11	SDIO status register (SDIO_STA) . . . . .	661
21.9.12	SDIO interrupt clear register (SDIO_ICR) . . . . .	662
21.9.13	SDIO mask register (SDIO_MASK) . . . . .	664
21.9.14	SDIO FIFO counter register (SDIO_FIFOCNT) . . . . .	666
21.9.15	SDIO data FIFO register (SDIO_FIFO) . . . . .	667
21.9.16	SDIO register map . . . . .	667
22	USB on-the-go full-speed (OTG_FS) . . . . .	669
22.1	OTG_FS introduction . . . . .	669
22.2	OTG_FS main features . . . . .	670
22.2.1	General features . . . . .	670
22.2.2	Host-mode features . . . . .	671
22.2.3	Peripheral-mode features . . . . .	671
22.3	OTG_FS functional description . . . . .	672

22.3.1	OTG pins . . . . .	672
22.3.2	OTG full-speed core . . . . .	672
22.3.3	Full-speed OTG PHY . . . . .	673
22.4	OTG dual role device (DRD) . . . . .	674
22.4.1	ID line detection . . . . .	674
22.4.2	HNP dual role device . . . . .	674
22.4.3	SRP dual role device . . . . .	675
22.5	USB peripheral . . . . .	675
22.5.1	SRP-capable peripheral . . . . .	676
22.5.2	Peripheral states . . . . .	676
22.5.3	Peripheral endpoints . . . . .	677
22.6	USB host . . . . .	679
22.6.1	SRP-capable host . . . . .	680
22.6.2	USB host states . . . . .	680
22.6.3	Host channels . . . . .	682
22.6.4	Host scheduler . . . . .	683
22.7	SOF trigger . . . . .	684
22.7.1	Host SOFs . . . . .	684
22.7.2	Peripheral SOFs . . . . .	685
22.8	OTG low-power modes . . . . .	685
22.9	Dynamic update of the OTG_FS_HFIR register . . . . .	686
22.10	USB data FIFOs . . . . .	687
22.11	Peripheral FIFO architecture . . . . .	688
22.11.1	Peripheral Rx FIFO . . . . .	688
22.11.2	Peripheral Tx FIFOs . . . . .	689
22.12	Host FIFO architecture . . . . .	689
22.12.1	Host Rx FIFO . . . . .	689
22.12.2	Host Tx FIFOs . . . . .	690
22.13	FIFO RAM allocation . . . . .	690
22.13.1	Device mode . . . . .	690
22.13.2	Host mode . . . . .	691
22.14	USB system performance . . . . .	691
22.15	OTG_FS interrupts . . . . .	692
22.16	OTG_FS control and status registers . . . . .	694
22.16.1	CSR memory map . . . . .	695

22.16.2	OTG_FS global registers . . . . .	700
22.16.3	Host-mode registers . . . . .	721
22.16.4	Device-mode registers . . . . .	731
22.16.5	OTG_FS power and clock gating control register (OTG_FS_PCGCCTL) . . . . .	754
22.16.6	OTG_FS register map . . . . .	755
22.17	OTG_FS programming model . . . . .	764
22.17.1	Core initialization . . . . .	764
22.17.2	Host initialization . . . . .	765
22.17.3	Device initialization . . . . .	765
22.17.4	Host programming model . . . . .	766
22.17.5	Device programming model . . . . .	782
22.17.6	Operational model . . . . .	784
22.17.7	Worst case response time . . . . .	802
22.17.8	OTG programming model . . . . .	803
23	Debug support (DBG) . . . . .	810
23.1	Overview . . . . .	810
23.2	Reference Arm® documentation . . . . .	811
23.3	SWJ debug port (serial wire and JTAG) . . . . .	811
23.3.1	Mechanism to select the JTAG-DP or the SW-DP . . . . .	812
23.4	Pinout and debug port pins . . . . .	812
23.4.1	SWJ debug port pins . . . . .	813
23.4.2	Flexible SWJ-DP pin assignment . . . . .	813
23.4.3	Internal pull-up and pull-down on JTAG pins . . . . .	813
23.4.4	Using serial wire and releasing the unused debug pins as GPIOs . . . . .	815
23.5	STM32F401xB/C and STM32F401xD/E JTAG TAP connection . . . . .	815
23.6	ID codes and locking mechanism . . . . .	817
23.6.1	MCU device ID code . . . . .	817
23.6.2	Boundary scan TAP . . . . .	817
23.6.3	Cortex®-M4 with FPU TAP . . . . .	818
23.6.4	Cortex®-M4 with FPU JEDEC-106 ID code . . . . .	818
23.7	JTAG debug port . . . . .	818
23.8	SW debug port . . . . .	820
23.8.1	SW protocol introduction . . . . .	820
23.8.2	SW protocol sequence . . . . .	820

23.8.3	SW-DP state machine (reset, idle states, ID code) . . . . .	821
23.8.4	DP and AP read/write accesses . . . . .	821
23.8.5	SW-DP registers . . . . .	822
23.8.6	SW-AP registers . . . . .	822
23.9	AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP . . . . .	823
23.10	Core debug . . . . .	824
23.11	Capability of the debugger host to connect under system reset . . . . .	825
23.12	FPB (Flash patch breakpoint) . . . . .	825
23.13	DWT (data watchpoint trigger) . . . . .	826
23.14	ITM (instrumentation trace macrocell) . . . . .	826
23.14.1	General description . . . . .	826
23.14.2	Time stamp packets, synchronization and overflow packets . . . . .	826
23.15	ETM (Embedded Trace Macrocell™) . . . . .	828
23.15.1	ETM general description . . . . .	828
23.15.2	ETM signal protocol and packet types . . . . .	828
23.15.3	Main ETM registers . . . . .	829
23.15.4	ETM configuration example . . . . .	829
23.16	MCU debug component (DBGMCU) . . . . .	829
23.16.1	Debug support for low-power modes . . . . .	829
23.16.2	Debug support for timers, watchdog and I ²C . . . . .	830
23.16.3	Debug MCU configuration register . . . . .	830
23.16.4	Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . .	832
23.16.5	Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ) . . . . .	833
23.17	TPIU (trace port interface unit) . . . . .	834
23.17.1	Introduction . . . . .	834
23.17.2	TRACE pin assignment . . . . .	835
23.17.3	TPUI formatter . . . . .	837
23.17.4	TPUI frame synchronization packets . . . . .	837
23.17.5	Transmission of the synchronization frame packet . . . . .	837
23.17.6	Synchronous mode . . . . .	838
23.17.7	Asynchronous mode . . . . .	838
23.17.8	TRACECLKIN connection inside the STM32F401xB/C and STM32F401xD/E . . . . .	838
23.17.9	TPIU registers . . . . .	839
23.17.10	Example of configuration . . . . .	839

23.18 DBG register map . . . . . 840

24 Device electronic signature . . . . . 841

24.1 Unique device ID register (96 bits) . . . . . 841

24.2 Flash size . . . . . 842

25 Important security notice . . . . . 843

26 Revision history . . . . . 844

List of tables

Table 1.	STM32F401xB/C and STM32F401xD/E register boundary addresses . . . . .	38
Table 2.	Boot modes. . . . .	41
Table 3.	Memory mapping vs. Boot mode/physical remap in STM32F401xB/C. . . . .	42
Table 4.	Memory mapping vs. Boot mode/physical remap in STM32F401xD/E. . . . .	43
Table 5.	Flash module organization (STM32F401xB/C and STM32F401xD/E) . . . . .	45
Table 6.	Number of wait states according to CPU clock (HCLK) frequency. . . . .	46
Table 7.	Maximum program/erase parallelism . . . . .	50
Table 8.	Flash interrupt request . . . . .	52
Table 9.	Option byte organization. . . . .	52
Table 10.	Description of the option bytes . . . . .	53
Table 11.	Access versus read protection level . . . . .	56
Table 12.	OTP area organization . . . . .	59
Table 13.	Flash register map and reset values . . . . .	67
Table 14.	CRC calculation unit register map and reset values. . . . .	70
Table 15.	Low-power mode summary . . . . .	78
Table 16.	Sleep-now entry and exit . . . . .	79
Table 17.	Sleep-on-exit entry and exit . . . . .	80
Table 18.	Stop operating modes. . . . .	81
Table 19.	Stop mode entry and exit . . . . .	82
Table 20.	Standby mode entry and exit . . . . .	84
Table 21.	PWR - register map and reset values. . . . .	90
Table 22.	RCC register map and reset values for STM32F401xB/C and STM32F401xD/E . . . . .	137
Table 23.	SYSCFG register map and reset values . . . . .	145
Table 24.	Port bit configuration table . . . . .	147
Table 25.	Flexible SWJ-DP pin assignment . . . . .	150
Table 26.	RTC additional functions. . . . .	157
Table 27.	GPIO register map and reset values . . . . .	164
Table 28.	DMA1 request mapping (STM32F401xB/C and STM32F401xD/E) . . . . .	170
Table 29.	DMA2 request mapping (STM32F401xB/C and STM32F401xD/E) . . . . .	171
Table 30.	Source and destination address . . . . .	172
Table 31.	Source and destination address registers in Double buffer mode (DBM=1). . . . .	177
Table 32.	Packing/unpacking & endian behavior (bit PINC = MINC = 1) . . . . .	178
Table 33.	Restriction on NDT versus PSIZE and MSIZE . . . . .	179
Table 34.	FIFO threshold configurations . . . . .	181
Table 35.	Possible DMA configurations . . . . .	185
Table 36.	DMA interrupt requests. . . . .	187
Table 37.	DMA register map and reset values . . . . .	198
Table 38.	Vector table for STM32F401xB/CSTM32F401xD/E . . . . .	203
Table 39.	External interrupt/event controller register map and reset values. . . . .	212
Table 40.	ADC pins. . . . .	215
Table 41.	Analog watchdog channel selection . . . . .	218
Table 42.	Configuring the trigger polarity . . . . .	222
Table 43.	External trigger for regular channels. . . . .	223
Table 44.	External trigger for injected channels . . . . .	224
Table 45.	ADC interrupts . . . . .	228
Table 46.	ADC global register map. . . . .	240
Table 47.	ADC register map and reset values for each ADC . . . . .	241

Table 48.	ADC register map and reset values (common ADC registers) . . . . .	242
Table 49.	Counting direction versus encoder signals . . . . .	280
Table 50.	TIMx Internal trigger connection . . . . .	294
Table 51.	Output control bits for complementary OCx and OCxN channels with break feature . . . . .	306
Table 52.	TIM1 register map and reset values . . . . .	314
Table 53.	Counting direction versus encoder signals . . . . .	342
Table 54.	TIMx internal trigger connection . . . . .	358
Table 55.	Output control bit for standard OCx channels . . . . .	367
Table 56.	TIM2 to TIM5 register map and reset values . . . . .	374
Table 57.	TIMx internal trigger connection . . . . .	400
Table 58.	Output control bit for standard OCx channels . . . . .	408
Table 59.	TIM9 register map and reset values . . . . .	410
Table 60.	Output control bit for standard OCx channels . . . . .	417
Table 61.	TIM10/11 register map and reset values . . . . .	420
Table 62.	Min/max IWDG timeout period (in ms) at 32 kHz (LSI) . . . . .	423
Table 63.	IWDG register map and reset values . . . . .	426
Table 64.	Minimum and maximum timeout values at 30 MHz ( $f_{PCLK1}$ ) . . . . .	430
Table 65.	WWDG register map and reset values . . . . .	433
Table 66.	Effect of low-power modes on RTC . . . . .	449
Table 67.	Interrupt control bits . . . . .	450
Table 68.	RTC register map and reset values . . . . .	471
Table 69.	Maximum DNF[3:0] value to be compliant with Thd:dat(max) . . . . .	485
Table 70.	SMBus vs. I2C . . . . .	487
Table 71.	I2C Interrupt requests . . . . .	491
Table 72.	I2C register map and reset values . . . . .	505
Table 73.	Noise detection from sampled data . . . . .	518
Table 74.	Error calculation for programmed baud rates at $f_{PCLK} = 8$ MHz or $f_{PCLK} = 12$ MHz, oversampling by 16. . . . .	521
Table 75.	Error calculation for programmed baud rates at $f_{PCLK} = 8$ MHz or $f_{PCLK} = 12$ MHz, oversampling by 8. . . . .	522
Table 76.	Error calculation for programmed baud rates at $f_{PCLK} = 16$ MHz or $f_{PCLK} = 24$ MHz, oversampling by 16. . . . .	522
Table 77.	Error calculation for programmed baud rates at $f_{PCLK} = 16$ MHz or $f_{PCLK} = 24$ MHz, oversampling by 8. . . . .	523
Table 78.	Error calculation for programmed baud rates at $f_{PCLK} = 8$ MHz or $f_{PCLK} = 16$ MHz, oversampling by 16. . . . .	524
Table 79.	Error calculation for programmed baud rates at $f_{PCLK} = 8$ MHz or $f_{PCLK} = 16$ MHz, oversampling by 8. . . . .	524
Table 80.	Error calculation for programmed baud rates at $f_{PCLK} = 30$ MHz or $f_{PCLK} = 60$ MHz, oversampling by 16. . . . .	525
Table 81.	Error calculation for programmed baud rates at $f_{PCLK} = 30$ MHz or $f_{PCLK} = 60$ MHz, oversampling by 8. . . . .	526
Table 82.	Error calculation for programmed baud rates at $f_{PCLK} = 42$ MHz or $f_{PCLK} = 84$ MHz, oversampling by 16. . . . .	527
Table 83.	Error calculation for programmed baud rates at $f_{PCLK} = 42$ MHz or $f_{PCLK} = 84$ MHz, oversampling by 8. . . . .	528
Table 84.	USART receiver's tolerance when DIV fraction is 0 . . . . .	529
Table 85.	USART receiver tolerance when DIV_Fraction is different from 0 . . . . .	530
Table 86.	Frame formats . . . . .	532
Table 87.	USART interrupt requests. . . . .	547
Table 88.	USART mode configuration . . . . .	548

Table 89.	USART register map and reset values . . . . .	558
Table 90.	SPI interrupt requests . . . . .	584
Table 91.	Audio frequency precision (for PLLM VCO = 1 MHz or 2 MHz) . . . . .	595
Table 92.	I ²S interrupt requests . . . . .	601
Table 93.	SPI register map and reset values . . . . .	611
Table 94.	SDIO I/O definitions . . . . .	615
Table 95.	Command format . . . . .	620
Table 96.	Short response format . . . . .	621
Table 97.	Long response format . . . . .	621
Table 98.	Command path status flags . . . . .	621
Table 99.	Data token format . . . . .	624
Table 100.	Transmit FIFO status flags . . . . .	625
Table 101.	Receive FIFO status flags . . . . .	626
Table 102.	Card status . . . . .	636
Table 103.	SD status . . . . .	639
Table 104.	Speed class code field . . . . .	640
Table 105.	Performance move field . . . . .	640
Table 106.	AU_SIZE field . . . . .	641
Table 107.	Maximum AU size . . . . .	641
Table 108.	Erase size field . . . . .	641
Table 109.	Erase timeout field . . . . .	642
Table 110.	Erase offset field . . . . .	642
Table 111.	Block-oriented write commands . . . . .	644
Table 112.	Block-oriented write protection commands . . . . .	645
Table 113.	Erase commands . . . . .	645
Table 114.	I/O mode commands . . . . .	646
Table 115.	Lock card . . . . .	646
Table 116.	Application-specific commands . . . . .	646
Table 117.	R1 response . . . . .	647
Table 118.	R2 response . . . . .	648
Table 119.	R3 response . . . . .	648
Table 120.	R4 response . . . . .	648
Table 121.	R4b response . . . . .	649
Table 122.	R5 response . . . . .	649
Table 123.	R6 response . . . . .	650
Table 124.	Response type and SDIO_RESPx registers . . . . .	657
Table 125.	SDIO register map . . . . .	667
Table 126.	OTG_FS input/output pins . . . . .	672
Table 127.	Compatibility of STM32 low power modes with the OTG . . . . .	685
Table 128.	Core global control and status registers (CSRs) . . . . .	695
Table 129.	Host-mode control and status registers (CSRs) . . . . .	696
Table 130.	Device-mode control and status registers . . . . .	697
Table 131.	Data FIFO (DFIFO) access register map . . . . .	698
Table 132.	Power and clock gating control and status registers . . . . .	699
Table 133.	TRDT values . . . . .	705
Table 134.	Minimum duration for soft disconnect . . . . .	733
Table 135.	OTG_FS register map and reset values . . . . .	755
Table 136.	SWJ debug port pins . . . . .	813
Table 137.	Flexible SWJ-DP pin assignment . . . . .	813
Table 138.	JTAG debug port data registers . . . . .	818
Table 139.	32-bit debug port registers addressed through the shifted value A[3:2] . . . . .	819
Table 140.	Packet request (8-bits) . . . . .	820

Table 141.	ACK response (3 bits) . . . . .	821
Table 142.	DATA transfer (33 bits) . . . . .	821
Table 143.	SW-DP registers . . . . .	822
Table 144.	Cortex®-M4 with FPU AHB-AP registers . . . . .	823
Table 145.	Core debug registers . . . . .	824
Table 146.	Main ITM registers . . . . .	827
Table 147.	Main ETM registers . . . . .	829
Table 148.	Asynchronous TRACE pin assignment . . . . .	835
Table 149.	Synchronous TRACE pin assignment . . . . .	835
Table 150.	Flexible TRACE pin assignment . . . . .	836
Table 151.	Important TPIU registers . . . . .	839
Table 152.	DBG register map and reset values . . . . .	840
Table 153.	Document revision history . . . . .	844

List of figures

Figure 1. System architecture . . . . . 36

Figure 2. Flash memory interface connection inside system architecture (STM32F401xB/C and STM32F401xD/E) . . . . . 44

Figure 3. Sequential 32-bit instruction execution . . . . . 48

Figure 4. RDP levels . . . . . 56

Figure 5. PCROP levels . . . . . 58

Figure 6. CRC calculation unit block diagram . . . . . 68

Figure 7. Power supply overview . . . . . 71

Figure 8. Power-on reset/power-down reset waveform . . . . . 74

Figure 9. BOR thresholds . . . . . 75

Figure 10. PVD thresholds . . . . . 76

Figure 11. Simplified diagram of the reset circuit . . . . . 92

Figure 12. Clock tree . . . . . 94

Figure 13. HSE/ LSE clock sources . . . . . 96

Figure 14. Frequency measurement with TIM5 in Input capture mode . . . . . 101

Figure 15. Frequency measurement with TIM11 in Input capture mode . . . . . 102

Figure 16. Basic structure of a five-volt tolerant I/O port bit . . . . . 147

Figure 17. Selecting an alternate function on STM32F401xB/C and STM32F401xD/E . . . . . 151

Figure 18. Input floating/pull up/pull down configurations . . . . . 154

Figure 19. Output configuration . . . . . 155

Figure 20. Alternate function configuration . . . . . 155

Figure 21. High impedance-analog configuration . . . . . 156

Figure 22. DMA block diagram . . . . . 168

Figure 23. System implementation of the two DMA controllers (STM32F401xB/C and STM32F401xD/E) . . . . . 169

Figure 24. Channel selection . . . . . 170

Figure 25. Peripheral-to-memory mode . . . . . 173

Figure 26. Memory-to-peripheral mode . . . . . 174

Figure 27. Memory-to-memory mode . . . . . 175

Figure 28. FIFO structure . . . . . 180

Figure 29. External interrupt/event controller block diagram . . . . . 206

Figure 30. External interrupt/event GPIO mapping . . . . . 208

Figure 31. Single ADC block diagram . . . . . 214

Figure 32. Timing diagram . . . . . 217

Figure 33. Analog watchdog's guarded area . . . . . 217

Figure 34. Injected conversion latency . . . . . 219

Figure 35. Right alignment of 12-bit data . . . . . 221

Figure 36. Left alignment of 12-bit data . . . . . 221

Figure 37. Left alignment of 6-bit data . . . . . 221

Figure 38. Temperature sensor and VREFINT channel block diagram . . . . . 226

Figure 39. Advanced-control timer block diagram . . . . . 245

Figure 40. Counter timing diagram with prescaler division change from 1 to 2 . . . . . 247

Figure 41. Counter timing diagram with prescaler division change from 1 to 4 . . . . . 247

Figure 42. Counter timing diagram, internal clock divided by 1 . . . . . 248

Figure 43. Counter timing diagram, internal clock divided by 2 . . . . . 249

Figure 44. Counter timing diagram, internal clock divided by 4 . . . . . 249

Figure 45. Counter timing diagram, internal clock divided by N . . . . . 249

Figure 46. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 250

Figure 47.	Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	250
Figure 48.	Counter timing diagram, internal clock divided by 1 . . . . .	252
Figure 49.	Counter timing diagram, internal clock divided by 2 . . . . .	252
Figure 50.	Counter timing diagram, internal clock divided by 4 . . . . .	253
Figure 51.	Counter timing diagram, internal clock divided by N . . . . .	253
Figure 52.	Counter timing diagram, update event when repetition counter is not used . . . . .	254
Figure 53.	Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .	255
Figure 54.	Counter timing diagram, internal clock divided by 2 . . . . .	255
Figure 55.	Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	256
Figure 56.	Counter timing diagram, internal clock divided by N . . . . .	256
Figure 57.	Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .	257
Figure 58.	Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .	257
Figure 59.	Update rate examples depending on mode and TIMx_RCR register settings . . . . .	258
Figure 60.	Control circuit in normal mode, internal clock divided by 1 . . . . .	259
Figure 61.	TI2 external clock connection example . . . . .	260
Figure 62.	Control circuit in external clock mode 1 . . . . .	261
Figure 63.	External trigger input block . . . . .	261
Figure 64.	Control circuit in external clock mode 2 . . . . .	262
Figure 65.	Capture/compare channel (example: channel 1 input stage) . . . . .	263
Figure 66.	Capture/compare channel 1 main circuit . . . . .	263
Figure 67.	Output stage of capture/compare channel (channel 1 to 3) . . . . .	264
Figure 68.	Output stage of capture/compare channel (channel 4) . . . . .	264
Figure 69.	PWM input mode timing . . . . .	266
Figure 70.	Output compare mode, toggle on OC1 . . . . .	268
Figure 71.	Edge-aligned PWM waveforms (ARR=8) . . . . .	269
Figure 72.	Center-aligned PWM waveforms (ARR=8) . . . . .	270
Figure 73.	Complementary output with dead-time insertion . . . . .	272
Figure 74.	Dead-time waveforms with delay greater than the negative pulse . . . . .	272
Figure 75.	Dead-time waveforms with delay greater than the positive pulse . . . . .	272
Figure 76.	Output behavior in response to a break . . . . .	275
Figure 77.	Clearing TIMx_OCxREF . . . . .	276
Figure 78.	6-step generation, COM example (OSSR=1) . . . . .	277
Figure 79.	Example of one pulse mode . . . . .	278
Figure 80.	Example of counter operation in encoder interface mode . . . . .	281
Figure 81.	Example of encoder interface mode with TI1FP1 polarity inverted . . . . .	281
Figure 82.	Example of Hall sensor interface . . . . .	283
Figure 83.	Control circuit in reset mode . . . . .	284
Figure 84.	Control circuit in gated mode . . . . .	285
Figure 85.	Control circuit in trigger mode . . . . .	286
Figure 86.	Control circuit in external clock mode 2 + trigger mode . . . . .	287
Figure 87.	General-purpose timer block diagram . . . . .	317
Figure 88.	Counter timing diagram with prescaler division change from 1 to 2 . . . . .	318
Figure 89.	Counter timing diagram with prescaler division change from 1 to 4 . . . . .	319
Figure 90.	Counter timing diagram, internal clock divided by 1 . . . . .	320
Figure 91.	Counter timing diagram, internal clock divided by 2 . . . . .	320
Figure 92.	Counter timing diagram, internal clock divided by 4 . . . . .	320
Figure 93.	Counter timing diagram, internal clock divided by N . . . . .	321
Figure 94.	Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	321
Figure 95.	Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	322
Figure 96.	Counter timing diagram, internal clock divided by 1 . . . . .	323
Figure 97.	Counter timing diagram, internal clock divided by 2 . . . . .	323
Figure 98.	Counter timing diagram, internal clock divided by 4 . . . . .	323

Figure 99.	Counter timing diagram, internal clock divided by N . . . . .	324
Figure 100.	Counter timing diagram, Update event . . . . .	324
Figure 101.	Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .	325
Figure 102.	Counter timing diagram, internal clock divided by 2 . . . . .	326
Figure 103.	Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	326
Figure 104.	Counter timing diagram, internal clock divided by N . . . . .	326
Figure 105.	Counter timing diagram, Update event with ARPE=1 (counter underflow) . . . . .	327
Figure 106.	Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .	327
Figure 107.	Control circuit in normal mode, internal clock divided by 1 . . . . .	328
Figure 108.	TI2 external clock connection example . . . . .	329
Figure 109.	Control circuit in external clock mode 1 . . . . .	330
Figure 110.	External trigger input block . . . . .	330
Figure 111.	Control circuit in external clock mode 2 . . . . .	331
Figure 112.	Capture/compare channel (example: channel 1 input stage) . . . . .	331
Figure 113.	Capture/compare channel 1 main circuit . . . . .	332
Figure 114.	Output stage of capture/compare channel (channel 1) . . . . .	332
Figure 115.	PWM input mode timing . . . . .	334
Figure 116.	Output compare mode, toggle on OC1 . . . . .	336
Figure 117.	Edge-aligned PWM waveforms (ARR=8) . . . . .	337
Figure 118.	Center-aligned PWM waveforms (ARR=8) . . . . .	338
Figure 119.	Example of one-pulse mode . . . . .	339
Figure 120.	Clearing TIMx_OCxREF . . . . .	341
Figure 121.	Example of counter operation in encoder interface mode . . . . .	343
Figure 122.	Example of encoder interface mode with TI1FP1 polarity inverted . . . . .	343
Figure 123.	Control circuit in reset mode . . . . .	344
Figure 124.	Control circuit in gated mode . . . . .	345
Figure 125.	Control circuit in trigger mode . . . . .	346
Figure 126.	Control circuit in external clock mode 2 + trigger mode . . . . .	347
Figure 127.	Master/Slave timer example . . . . .	347
Figure 128.	Gating timer 2 with OC1REF of timer 1 . . . . .	348
Figure 129.	Gating timer 2 with Enable of timer 1 . . . . .	349
Figure 130.	Triggering timer 2 with update of timer 1 . . . . .	350
Figure 131.	Triggering timer 2 with Enable of timer 1 . . . . .	351
Figure 132.	Triggering timer 1 and 2 with timer 1 TI1 input . . . . .	352
Figure 133.	General-purpose timer block diagram (TIM9) . . . . .	377
Figure 134.	General-purpose timer block diagram (TIM10/11) . . . . .	378
Figure 135.	Counter timing diagram with prescaler division change from 1 to 2 . . . . .	380
Figure 136.	Counter timing diagram with prescaler division change from 1 to 4 . . . . .	380
Figure 137.	Counter timing diagram, internal clock divided by 1 . . . . .	381
Figure 138.	Counter timing diagram, internal clock divided by 2 . . . . .	382
Figure 139.	Counter timing diagram, internal clock divided by 4 . . . . .	382
Figure 140.	Counter timing diagram, internal clock divided by N . . . . .	382
Figure 141.	Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	383
Figure 142.	Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	383
Figure 143.	Control circuit in normal mode, internal clock divided by 1 . . . . .	384
Figure 144.	TI2 external clock connection example . . . . .	385
Figure 145.	Control circuit in external clock mode 1 . . . . .	385
Figure 146.	Capture/compare channel (example: channel 1 input stage) . . . . .	386
Figure 147.	Capture/compare channel 1 main circuit . . . . .	387
Figure 148.	Output stage of capture/compare channel (channel 1) . . . . .	387
Figure 149.	PWM input mode timing . . . . .	389
Figure 150.	Output compare mode, toggle on OC1 . . . . .	391

Figure 151. Edge-aligned PWM waveforms (ARR=8) . . . . .	392
Figure 152. Example of one pulse mode. . . . .	393
Figure 153. Control circuit in reset mode . . . . .	395
Figure 154. Control circuit in gated mode . . . . .	396
Figure 155. Control circuit in trigger mode . . . . .	396
Figure 156. Independent watchdog block diagram . . . . .	423
Figure 157. Watchdog block diagram . . . . .	428
Figure 158. Window watchdog timing diagram . . . . .	429
Figure 159. RTC block diagram . . . . .	436
Figure 160. I2C bus protocol . . . . .	476
Figure 161. I2C block diagram . . . . .	477
Figure 162. Transfer sequence diagram for target transmitter . . . . .	478
Figure 163. Transfer sequence diagram for target receiver. . . . .	479
Figure 164. Transfer sequence diagram for controller transmitter . . . . .	482
Figure 165. Transfer sequence diagram for controller receiver . . . . .	483
Figure 166. I2C interrupt mapping diagram . . . . .	492
Figure 167. USART block diagram . . . . .	509
Figure 168. Word length programming . . . . .	510
Figure 169. Configurable stop bits . . . . .	512
Figure 170. TC/TXE behavior when transmitting . . . . .	513
Figure 171. Start bit detection when oversampling by 16 or 8. . . . .	514
Figure 172. Data sampling when oversampling by 16 . . . . .	517
Figure 173. Data sampling when oversampling by 8 . . . . .	518
Figure 174. Mute mode using Idle line detection . . . . .	531
Figure 175. Mute mode using address mark detection . . . . .	531
Figure 176. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .	534
Figure 177. Break detection in LIN mode vs. Framing error detection. . . . .	535
Figure 178. USART example of synchronous transmission. . . . .	536
Figure 179. USART data clock timing diagram (M=0) . . . . .	536
Figure 180. USART data clock timing diagram (M=1) . . . . .	537
Figure 181. RX data setup/hold time . . . . .	537
Figure 182. ISO 7816-3 asynchronous protocol . . . . .	538
Figure 183. Parity error detection using the 1.5 stop bits . . . . .	539
Figure 184. IrDA SIR ENDEC- block diagram . . . . .	541
Figure 185. IrDA data modulation (3/16) -Normal mode . . . . .	541
Figure 186. Transmission using DMA . . . . .	543
Figure 187. Reception using DMA . . . . .	544
Figure 188. Hardware flow control between 2 USARTs . . . . .	544
Figure 189. RTS flow control . . . . .	545
Figure 190. CTS flow control . . . . .	546
Figure 191. USART interrupt mapping diagram . . . . .	547
Figure 192. SPI block diagram. . . . .	562
Figure 193. Single master/ single slave application. . . . .	563
Figure 194. Data clock timing diagram . . . . .	565
Figure 195. TI mode - Slave mode, single transfer . . . . .	567
Figure 196. TI mode - Slave mode, continuous transfer . . . . .	568
Figure 197. TI mode - master mode, single transfer . . . . .	569
Figure 198. TI mode - master mode, continuous transfer . . . . .	570
Figure 199. TXE/RXNE/BSY behavior in Master / full-duplex mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . .	573
Figure 200. TXE/RXNE/BSY behavior in Slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in case of continuous transfers . . . . .	574

Figure 201. TXE/BSY behavior in Master transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . .	575
Figure 202. TXE/BSY in Slave transmit-only mode (BIDIMODE=0 and RXONLY=0) in case of continuous transfers . . . . .	575
Figure 203. RXNE behavior in receive-only mode (BIDIRMODE=0 and RXONLY=1) in case of continuous transfers . . . . .	576
Figure 204. TXE/BSY behavior when transmitting (BIDIRMODE=0 and RXONLY=0) in case of discontinuous transfers . . . . .	577
Figure 205. Transmission using DMA . . . . .	582
Figure 206. Reception using DMA . . . . .	582
Figure 207. TI mode frame format error detection . . . . .	584
Figure 208. I ²S block diagram . . . . .	585
Figure 209. I2S full duplex block diagram . . . . .	586
Figure 210. I ²S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0) . . . . .	588
Figure 211. I ²S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . .	588
Figure 212. Transmitting 0x8EAA33 . . . . .	588
Figure 213. Receiving 0x8EAA33 . . . . .	589
Figure 214. I ²S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . .	589
Figure 215. Example . . . . .	589
Figure 216. MSB justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . .	590
Figure 217. MSB justified 24-bit frame length with CPOL = 0 . . . . .	590
Figure 218. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .	590
Figure 219. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . .	591
Figure 220. LSB justified 24-bit frame length with CPOL = 0 . . . . .	591
Figure 221. Operations required to transmit 0x3478AE . . . . .	591
Figure 222. Operations required to receive 0x3478AE . . . . .	592
Figure 223. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .	592
Figure 224. Example of LSB justified 16-bit extended to 32-bit packet frame . . . . .	592
Figure 225. PCM standard waveforms (16-bit) . . . . .	593
Figure 226. PCM standard waveforms (16-bit extended to 32-bit packet frame) . . . . .	593
Figure 227. Audio sampling frequency definition . . . . .	594
Figure 228. I ²S clock generator architecture . . . . .	594
Figure 229. SDIO “no response” and “no data” operations . . . . .	613
Figure 230. SDIO (multiple) block read operation . . . . .	613
Figure 231. SDIO (multiple) block write operation . . . . .	613
Figure 232. SDIO sequential read operation . . . . .	614
Figure 233. SDIO sequential write operation . . . . .	614
Figure 234. SDIO block diagram . . . . .	614
Figure 235. SDIO adapter . . . . .	616
Figure 236. Control unit . . . . .	617
Figure 237. SDIO adapter command path . . . . .	618
Figure 238. Command path state machine (CPSM) . . . . .	619
Figure 239. SDIO command transfer . . . . .	620
Figure 240. Data path . . . . .	622
Figure 241. Data path state machine (DPSM) . . . . .	623
Figure 242. OTG full-speed block diagram . . . . .	672
Figure 243. OTG A-B device connection . . . . .	674
Figure 244. USB peripheral-only connection . . . . .	676
Figure 245. USB host-only connection . . . . .	680
Figure 246. SOF connectivity . . . . .	684
Figure 247. Updating OTG_FS_HFIR dynamically . . . . .	687
Figure 248. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .	688

Figure 249. Host-mode FIFO address mapping and AHB FIFO access mapping . . . . .	689
Figure 250. Interrupt hierarchy. . . . .	693
Figure 251. CSR memory map . . . . .	695
Figure 252. Transmit FIFO write task . . . . .	767
Figure 253. Receive FIFO read task . . . . .	768
Figure 254. Normal bulk/control OUT/SETUP and bulk/control IN transactions . . . . .	769
Figure 255. Bulk/control IN transactions . . . . .	772
Figure 256. Normal interrupt OUT/IN transactions . . . . .	774
Figure 257. Normal isochronous OUT/IN transactions . . . . .	779
Figure 258. Receive FIFO packet read . . . . .	785
Figure 259. Processing a SETUP packet . . . . .	787
Figure 260. Bulk OUT transaction . . . . .	794
Figure 261. TRDT max timing case . . . . .	803
Figure 262. A-device SRP . . . . .	804
Figure 263. B-device SRP . . . . .	805
Figure 264. A-device HNP . . . . .	806
Figure 265. B-device HNP . . . . .	808
Figure 266. Block diagram of STM32 MCU and Cortex ^®-M4 with FPU-level debug support . . . . .	810
Figure 267. SWJ debug port . . . . .	812
Figure 268. JTAG TAP connections . . . . .	816
Figure 269. TPIU block diagram . . . . .	834

RM0368-STM32F401xB-C-401xD-E

Introduction

Contents

List of tables

List of figures

Chapters

RM0368-STM32F401xB-C-401xD-E

Introduction

Related documents

Contents

List of tables

List of figures

Chapters