17. Liquid crystal display controller (LCD)

17.1 Introduction

The LCD controller is a digital controller/driver for monochrome passive liquid crystal display (LCD) with up to 8 common terminals and up to 52 ^(a) segment terminals to drive 208 (4x52) or 384 (8x48) LCD picture elements (pixels). The exact number of terminals depends on the device pinout as described in the datasheet.

The LCD is made up of several segments (pixels or complete symbols) that can be turned visible or invisible. Each segment consists of a layer of liquid crystal molecules aligned between two electrodes. When a voltage greater than a threshold voltage is applied across the liquid crystal, the segment becomes visible. The segment voltage must be alternated to avoid an electrophoresis effect in the liquid crystal (which degrades the display). The waveform across a segment must then be generated so as to avoid having a direct current (DC).

Glossary

Bias: Number of voltage levels used when driving an LCD. It is defined as \( 1/(\text{number of voltage levels used to drive an LCD display} - 1) \) .

Boost circuit: Contrast controller circuit

Common: Electrical connection terminal connected to several segments (52 segments).

Duty ratio: Number defined as \( 1/(\text{number of common terminals on a given LCD display}) \) .

Frame: One period of the waveform written to a segment.

Frame rate: Number of frames per second, that is, the number of times the LCD segments are energized per second.

LCD: (liquid crystal display) a passive display panel with terminals leading directly to a segment.

Segment: The smallest viewing element (a single bar or dot that is used to help create a character on an LCD display).

a. Refer to Table 73: Implementation , showing the product configurations.

17.2 LCD main features

• • Highly flexible frame rate control.
• • Supports Static, 1/2, 1/3, 1/4 and 1/8 duty.
• • Supports Static, 1/2, 1/3 and 1/4 bias.
• • Double buffered memory allows data in LCD_RAM registers to be updated at any time by the application firmware without affecting the integrity of the data displayed.
  • – LCD data RAM of up to 16 x 32-bit registers which contain pixel information (active/inactive)
• • Software selectable LCD output voltage (contrast) from \( V_{LCDmin} \) to \( V_{LCDmax} \) .
• • No need for external analog components:
  • – A step-up converter is embedded to generate an internal \( V_{LCD} \) voltage higher than \( V_{DD} \)
  • – Software selection between external and internal \( V_{LCD} \) voltage source. In case of an external source, the internal boost circuit is disabled to reduce power consumption
  • – A resistive network is embedded to generate intermediate \( V_{LCD} \) voltages
  • – The structure of the resistive network is configurable by software to adapt the power consumption to match the capacitive charge required by the LCD panel.
• • The contrast can be adjusted using two different methods:
  • – When using the internal step-up converter, the software can adjust \( V_{LCD} \) between \( V_{LCDmin} \) and \( V_{LCDmax} \) .
  • – Programmable dead time (up to 8 phase periods) between frames.
• • Full support of low-power modes: the LCD controller can be displayed in Sleep, Low-power run, Low-power sleep and Stop modes or can be fully disabled to reduce power consumption.
• • Built in phase inversion for reduced power consumption and EMI (electromagnetic interference).
• • Start of frame interrupt to synchronize the software when updating the LCD data RAM.
• • Blink capability:
  • – Up to 1, 2, 3, 4, 8 or all pixels which can be programmed to blink at a configurable frequency
  • – Software adjustable blink frequency to achieve around 0.5 Hz, 1 Hz, 2 Hz or 4 Hz.
• • Used LCD segment and common pins should be configured as GPIO alternate functions and unused segment and common pins can be used for general purpose I/O or for another peripheral alternate function.
• • \( V_{LCD} \) rails decoupling capability

Note: When the LCD relies on the internal step-up converter, the VLCD pin should be connected to \( V_{SS} \) with a capacitor. Its typical value is 1 \( \mu F \) (see \( C_{EXT} \) value in the product datasheets for further information).

Note: The VLCD pin should be connected to \( V_{DDA} \) if the LCD peripheral is not used.

17.3 LCD implementation

Table 73. Implementation

17.4 LCD functional description

17.4.1 General description

The LCD controller has five main blocks (see Figure 67 ):

Figure 67. LCD controller block diagram

Note: LCDCLK is the same as RTCCLK. Refer to the RTC/LCD clock description in the RCC section of this manual.

The frequency generator allows you to achieve various LCD frame rates starting from an LCD input clock frequency (LCDCLK) which can vary from 32 kHz up to 1 MHz.

3 different clock sources can be used to provide the LCD clock (LCDCLK/RTCCLK):

• • 32 kHz Low speed external RC (LSE)
• • 32 kHz Low speed internal RC (LSI)
• • High speed external (HSE) divided by 2, 4, 8 or 16 to obtain a 1 MHz clock

17.4.2 Frequency generator

This clock source must be stable in order to obtain accurate LCD timing and hence minimize DC voltage offset across LCD segments. The input clock LCDCLK can be divided by any value from 1 to \( 2^{15} \times 31 \) (see Section 17.7.2: LCD frame control register (LCD_FCR) on page 406 ). The frequency generator consists of a prescaler (16-bit ripple counter) and a 16 to 31 clock divider. The PS[3:0] bits, in the LCD_FCR register, select LCDCLK divided by \( 2^{\text{PS}[3:0]} \) . If a finer resolution rate is required, the DIV[3:0] bits, in the LCD_FCR register, can be used to divide the clock further by 16 to 31. In this way you can roughly scale the frequency, and then fine-tune it by linearly scaling the clock with the counter. The output of the frequency generator block is \( f_{\text{ck\_div}} \) which constitutes the time base for the entire LCD controller. The ck_div frequency is equivalent to the LCD phase frequency, rather than the frame frequency (they are equal only in case of static duty). The frame frequency ( \( f_{\text{frame}} \) ) is obtained from \( f_{\text{ck\_div}} \) by dividing it by the number of active common terminals (or by multiplying it for the duty). Thus the relation between the input clock frequency ( \( f_{\text{LCDCLK}} \) ) of the frequency generator and its output clock frequency \( f_{\text{ck\_div}} \) is:

This makes the frequency generator very flexible. An example of frame rate calculation is shown in Table 74 .

Table 74. Example of frame rate calculation

The frame frequency must be selected to be within a range of around ~30 Hz to ~100 Hz and is a compromise between power consumption and the acceptable refresh rate. In addition, a dedicated blink prescaler selects the blink frequency. This frequency is defined as:

with BLINKF[2:0] = 0, 1, 2, ... ,7

The blink frequency achieved is in the range of 0.5 Hz, 1 Hz, 2 Hz or 4 Hz.

17.4.3 Common driver

Common signals are generated by the common driver block (see Figure 67 ).

COM signal bias

Each COM signal has identical waveforms, but different phases. It has its max amplitude \( V_{\text{LCD}} \) or \( V_{\text{SS}} \) only in the corresponding phase of a frame cycle, while during the other phases, the signal amplitude is:

• • 1/4 \( V_{\text{LCD}} \) or 3/4 \( V_{\text{LCD}} \) in case of 1/4 bias
• • 1/3 \( V_{\text{LCD}} \) or 2/3 \( V_{\text{LCD}} \) in case of 1/3 bias
• • and 1/2 \( V_{\text{LCD}} \) in case of 1/2 bias.

Selection between 1/2, 1/3 and 1/4 bias mode can be done through the BIAS bits in the LCD_CR register.

A pixel is activated when both of its corresponding common and segment lines are active during the same phase, it means when the voltage difference between common and segment is maximum during this phase. Common signals are phase inverted in order to reduce EMI. As shown in Figure 68 , with phase inversion, there is a mean voltage of 1/2 \( V_{\text{LCD}} \) at the end of every odd cycle.

Figure 68. 1/3 bias, 1/4 duty

In case of 1/2 bias (BIAS = 01) the V _LCD pin generates an intermediate voltage equal to 1/2 V _LCD on node b for odd and even frames (see Figure 71).

COM signal duty

Depending on the DUTY[2:0] bits in the LCD_CR register, the COM signals are generated with static duty (see Figure 70), 1/2 duty (see Figure 71), 1/3 duty (see Figure 72), 1/4 duty (see Figure 73) or 1/8 duty (see Figure 74).

COM[n] n[0 to 7] is active during phase n in the odd frame, so the COM pin is driven to V _LCD .

During phase n of the even frame the COM pin is driven to V _SS .

In the case of 1/3 or 1/4 bias:

• • COM[n] is inactive during phases other than n so the COM pin is driven to 1/3 (1/4) V _LCD during odd frames and to 2/3 (3/4) V _LCD during even frames

In the case of 1/2 bias:

• • If COM[n] is inactive during phases other than n, the COM pin is always driven (odd and even frame) to 1/2 V _LCD .

When static duty is selected, the segment lines are not multiplexed, which means that each segment output corresponds to one pixel. In this way only up to 51 pixels can be driven. COM[0] is always active while COM[7:1] are not used and are driven to V _SS .

When the LCDEN bit in the LCD_CR register is reset, all common lines are pulled down to V _SS and the ENS flag in the LCD_SR register becomes 0. Static duty means that COM[0] is always active and only two voltage levels are used for the segment and common lines: V _LCD and V _SS . A pixel is active if the corresponding SEG line has a voltage opposite to that of the COM, and inactive when the voltages are equal. In this way the LCD has maximum contrast (see Figure 69, Figure 70). In the Figure 69 pixel 0 is active while pixel 1 is inactive.

Figure 69. Static duty case 1

In each frame there is only one phase, this is why \( f_{frame} \) is equal to \( f_{LCD} \) . If 1/4 duty is selected there are four phases in a frame in which COM[0] is active during phase 0, COM[1] is active during phase 1, COM[2] is active during phase 2, and COM[3] is active during phase 3.

Figure 70. Static duty case 2

In this mode, the segment terminals are multiplexed and each of them control four pixels. A pixel is activated only when both of its corresponding SEG and COM lines are active in the same phase. In case of 1/4 duty, to deactivate pixel 0 connected to COM[0] the SEG[0] needs to be inactive during the phase 0 when COM[0] is active. To activate pixel 0 connected to COM[1], the SEG[0] needs to be active during phase 1 when COM[1] is active (see Figure 73). To activate pixels from 0 to 51 connected to COM[0], SEG[0:51] need to be active during phase 0 when COM[0] is active. These considerations can be extended to the other pixels.

8 to 1 Mux

When COM[0] is active the common driver block, also drives the 8 to 1 mux shown in Figure 67 in order to select the content of first two RAM register locations. When COM[7] is active, the output of the 8 to 1 mux is the content of the last two RAM locations.

Figure 71. 1/2 duty, 1/2 bias

17.4.4 Segment driver

The segment driver block controls the SEG lines according to the pixel data coming from the 8 to 1 mux driven in each phase by the common driver block.

In the case of 1/4 or 1/8 duty

When COM[0] is active, the pixel information (active/inactive) related to the pixel connected to COM[0] (content of the first two LCD_RAM locations) goes through the 8 to 1 mux.

The SEG[n] pin n [0 to 51] is driven to V _SS (indicating pixel n is active when COM[0] is active) in phase 0 of the odd frame.

The SEG[n] pin is driven to \( V_{LCD} \) in phase 0 of the even frame. If pixel \( n \) is inactive then the SEG[n] pin is driven to \( 2/3 \) ( \( 2/4 \) ) \( V_{LCD} \) in the odd frame or \( 1/3 \) ( \( 2/4 \) ) \( V_{LCD} \) in the even frame (current inversion in \( V_{LCD} \) pad) (see Figure 68).

In case of \( 1/2 \) bias, if the pixel is inactive the SEG[n] pin is driven to \( V_{LCD} \) in the odd and to \( V_{SS} \) in the even frame.

When the LCD controller is disabled (LCDEN bit cleared in the LCD_CR register) then the SEG lines are pulled down to \( V_{SS} \) .

Figure 72. \( 1/3 \) duty, \( 1/3 \) bias

Figure 73. 1/4 duty, 1/3 bias

Figure 74. 1/8 duty, 1/4 bias

Blink

The segment driver also implements a programmable blink feature to allow some pixels to continuously switch on at a specific frequency. The blink mode can be configured by the BLINK[1:0] bits in the LCD_FCR register, making possible to blink up to 1, 2, 4, 8 or all pixels (see Section 17.7.2: LCD frame control register (LCD_FCR) ). The blink frequency can be selected from eight different values using the BLINKF[2:0] bits in the LCD_FCR register.

Table 75 gives examples of different blink frequencies (as a function of ck_div frequency).

Table 75. Blink frequency

17.4.5 Voltage generator and contrast control

LCD supply source

The LCD power supply source may come from either the internal step-up converter or from an external voltage applied on the VLCD pin. Internal or external voltage source can be selected using the VSEL bit in the LCD_CR register. In case of external source selected, the internal boost circuit (step-up converter) is disabled to reduce power consumption.

When the step-up converter is selected as \( V_{LCD} \) source, the \( V_{LCD} \) value can be chosen among a wide set of values from \( V_{LCDmin} \) to \( V_{LCDmax} \) by means of CC[2:0] (Contrast Control) bits inside LCD_FCR (see Section 17.7.2 ) register. New values of \( V_{LCD} \) takes effect every beginning of a new frame.

When external power source is selected as \( V_{LCD} \) source, the \( V_{LCD} \) voltage must be chosen in the range of \( V_{LCDmin} \) to \( V_{LCDmax} \) (see datasheets). The contrast can then be controlled by programming a dead time between frames (see Deadtime on page 397 ).

LCD intermediate voltages

The LCD intermediate voltage levels are generated through an internal resistor divider network as shown in Figure 75 .

The LCD voltage generator issues intermediate voltage levels between \( V_{SS} \) and \( V_{LCD} \) :

• • \( 1/3 V_{LCD} \) and \( 2/3 V_{LCD} \) in case of 1/3 bias
• • \( 1/4 V_{LCD} \) , \( 2/4 V_{LCD} \) and \( 3/4 V_{LCD} \) in case of 1/4 bias
• • only \( 1/2 V_{LCD} \) in case of 1/2 bias.

LCD drive selection

Two resistive networks, one with low value resistors ( \( R_L \) ) and one with high value resistors ( \( R_H \) ) are respectively used to increase the current during transitions and reduce power consumption in static state.

The EN switch follows the rules described below (see Figure 75 ):

• • If LCDEN bit in the LCD_CR register is set, the EN switch is closed.
• • When clearing the LCDEN bit in the LCD_CR register, the EN switch is open at the end of the even frame in order to avoid a medium voltage level different from 0 considering the entire frame odd plus even.

The PON[2:0] (Pulse ON duration) bits in the LCD_FCR register configure the time during which \( R_L \) is enabled through the HD (high drive) switch when the levels of the common and segment lines change (see Figure 75 ). A short drive time will lead to lower power consumption, but displays with high internal resistance may need a longer drive time to achieve satisfactory contrast.

Figure 75. LCD voltage control

1. \( R_{LN} \) and \( R_{HN} \) are the low value resistance network and the high value resistance network, respectively.

The \( R_{LN} \) divider can be always switched on using the HD bit in the LCD_FCR configuration register (see Section 17.7.2 ).

The HD switch follows the rules described below:

• • If the HD bit and the PON[2:0] bits in the LCD_FCR register are reset, then HD switch is open.
• • If the HD bit in the LCD_FCR register is reset and the PON[2:0] bits in the LCD_FCR are different from 00 then, the HD switch is closed during the number of pulses defined in the PON[2:0] bits.
• • If HD bit in the LCD_FCR register is 1 then HD switch is always closed.

After the LCDEN bit is activated, the RDY bit is set in the LCD_SR register to indicate that voltage levels are stable and the LCD controller can start to work.

External decoupling

Devices with \( V_{LCD} \) rails decoupling capability (see device datasheets) allow adding decoupling capacitors on the VLCD intermediate voltage rails that available on LCD_VLCD1, LCD_VLCD2 and LCD_VLCD3 for stabilization purpose (see Figure 75 ). Spikes might be observed when the voltage applied to the pixel is alternating. In this case, these decoupling capacitors will help to get a steady voltage resulting in a higher contrast.

This capability is particularly useful for consumption reason as it allow to select lower PON[2:0] values in the LCD_FCR register.

To connect the \( V_{LCD} \) rails as described in Table 76 to the dedicated GPIOs, configure the LCD_CAPA[4:0] bits of the SYSCFG_CFGR2 register (see Section 10.2.2: SYSCFG peripheral mode configuration register (SYSCFG_CFGR2) ).

Table 76. VLCD rail connections to GPIO pins

In order to be effective, the values of these decoupling capacitors must be tuned according to the LCD glass and the PCB capacitances. As a guideline the user can set the decoupling capacitor values to approximately 10 times the LCD capacitance.

Deadtime

In addition to using the CC[2:0] bits, the contrast can be controlled by programming a dead time between each frame. During the dead time the COM and SEG values are put to \( V_{SS} \) . The DEAD[2:0] bits in the LCD_FCR register can be used to program a time of up to eight phase periods. This dead time reduces the contrast without modifying the frame rate.

Figure 76. Deadtime

17.4.6 Double buffer memory

Using its double buffer memory the LCD controller ensures the coherency of the displayed information without having to use interrupts to control LCD_RAM modification.

The application software can access the first buffer level (LCD_RAM) through the APB interface. Once it has modified the LCD_RAM, it sets the UDR flag in the LCD_SR register. This UDR flag (update display request) requests the updated information to be moved into the second buffer level (LCD_DISPLAY).

This operation is done synchronously with the frame (at the beginning of the next frame), until the update is completed, the LCD_RAM is write protected and the UDR flag stays high. Once the update is completed another flag (UDD - Update Display Done) is set and generates an interrupt if the UDDIE bit in the LCD_FCR register is set.

The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one even frame.

The update will not occur (UDR = 1 and UDD = 0) until the display is enabled (LCDEN = 1)

17.4.7 COM and SEG multiplexing

Output pins versus duty modes

The output pins consists of up to:

• • SEG[51:0]
• • COM[3:0]

Depending on the duty configuration, the COM and SEG output pins may have different functions:

• • In static, 1/2, 1/3 and 1/4 duty modes there are up to 52 SEG pins and respectively 1, 2, 3 and 4 COM pins
• • In 1/8 duty mode (DUTY[2:0] = 100), COM[7:4] outputs are available on the SEG[51:48] and SEG[31:28] pins on category 5 and category 3 devices, respectively. This allows reducing the number of available segments.

Remapping capability for small packages

Additionally, it is possible to remap 4 segments by setting the MUX_SEG bit in the LCD_CR register. This is particularly useful when using smaller device types with fewer external pins. When MUX_SEG is set, output pins SEG[51:48] have the same function as SEG[31:28].

This feature is available only on category 5 devices.

Summary of COM and SEG functions versus duty and remap

All the possible ways of multiplexing the COM and SEG functions are described in Table 77 . Figure 77 gives examples showing the signal connections to the external pins.

Table 77. Remapping capability ⁽¹⁾

Table 77. Remapping capability ⁽¹⁾ (continued)

1. This table applies only to category 5 devices.

2. SEG21 is not available on BGA64.

Figure 77. SEG/COM mux feature example

1. This table applies only to category 5 devices.

17.4.8 Flowchart

Figure 78. Flowchart example

graph TD; START([START]) --> INIT["INIT<br/>- Enable the GPIO port clocks<br/>- Configure the LCD GPIO pins as alternate functions<br/>- Configure LCD controller according to the Display to be driven:"]; INIT --> LoadData["- Load the initial data to be displayed into<br/>LCD_RAM and set the UDR bit in the LCD_SR register"]; LoadData --> ProgramFrameRate["- Program the desired frame rate (PS and DIV bits in LCD_FCR)<br/>- Program the contrast (CC bits in LCD_FCR register)"]; ProgramFrameRate --> EnableDisplay["Enable the display (LCDEN bit in LCD_CR register)"]; EnableDisplay --> AdjustContrast{Adjust contrast?}; AdjustContrast -- Yes --> ChangePS["Change PS, DIV, CC, PON, DEAD or HD in LCD_FCR"]; AdjustContrast -- No --> ModifyData{Modify data?}; ModifyData -- Yes --> UDR1{UDR = 1?}; UDR1 -- Yes --> AdjustContrast; UDR1 -- No --> ModifyRAM["Modify the LCD_RAM"]; ModifyRAM --> SetUDR["Set UDR bit in LCD_SR"]; SetUDR --> AdjustContrast; ModifyData -- No --> ChangeBlink{Change blink?}; ChangeBlink -- Yes --> ChangeBlinkF["Change BLINK or BLINKF in LCD_FCR"]; ChangeBlinkF --> AdjustContrast; ChangeBlink -- No --> DisableLCD{Disable LCD?}; DisableLCD -- Yes --> DisableDisplay["Disable the display (LCDEN bit in LCD_CR register)"]; DisableDisplay --> ENS0{ENS = 0?}; ENS0 -- No --> AdjustContrast; ENS0 -- Yes --> END([END]);

MS33450V1

17.5 LCD low-power modes

the LCD controller can be displayed in Stop mode or can be fully disabled to reduce power consumption.

Table 78. LCD behavior in low-power modes

17.6 LCD interrupts

The table below gives the list of LCD interrupt requests.

Table 79. LCD interrupt requests

Start of frame (SOF)

The LCD start of frame interrupt is executed if the SOFIE (start of frame interrupt enable) bit is set (see Section 17.7.2: LCD frame control register (LCD_FCR) ). SOF is cleared by writing the SOFC bit to 1 in the LCD_CLR register when executing the corresponding interrupt handling vector.

Update display done (UDD)

The LCD update display interrupt is executed if the UDDIE (update display done interrupt enable) bit is set (see Section 17.7.2: LCD frame control register (LCD_FCR) ). UDD is cleared by writing the UDDC bit to 1 in the LCD_CLR register when executing the corresponding interrupt handling vector.

Depending on the product implementation, all these interrupts events can either share the same interrupt vector (LCD global interrupt), or be grouped into 2 interrupt vectors (LCD SOF interrupt and LCD UDD interrupt). Refer to the Table 55: List of vectors for details.

To enable the LCD interrupts, the following sequence is required:

1. 1. Configure and enable the LCD IRQ channel in the NVIC
2. 2. Configure the LCD to generate interrupts

17.7 LCD registers

The peripheral registers have to be accessed by words (32-bit).

17.7.1 LCD control register (LCD_CR)

Address offset: 0x00

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value

Bit 7 MUX_SEG : Mux segment enable

This bit is used to enable SEG pin remapping. Four SEG pins can be multiplexed with SEG[31:28]. See Section 17.4.7 .

0: SEG pin multiplexing disabled

1: SEG[31:28] are multiplexed with SEG[43:40]

Bits 6:5 BIAS[1:0] : Bias selector

These bits determine the bias used. Value 11 is forbidden.

00: Bias 1/4

01: Bias 1/2

10: Bias 1/3

11: Reserved

Bits 4:2 DUTY[2:0] : Duty selection

These bits determine the duty cycle. Values 101, 110 and 111 are forbidden.

000: Static duty

001: 1/2 duty

010: 1/3 duty

011: 1/4 duty

100: 1/8 duty

101: Reserved

110: Reserved

111: Reserved

Bit 1 VSEL : Voltage source selection

The VSEL bit determines the voltage source for the LCD.

0: Internal source (voltage step-up converter)

1: External source (VLCD pin)

Bit 0 LCDEN : LCD controller enable

This bit is set by software to enable the LCD Controller/Driver. It is cleared by software to turn off the LCD at the beginning of the next frame. When the LCD is disabled all COM and SEG pins are driven to V _SS . When this bit is set, the ULP bit must be reset in PWR_CR.

0: LCD Controller disabled

1: LCD Controller enabled

Note: The VSEL, MUX_SEG, BIAS, and DUTY bits are write-protected when the LCD is enabled (ENS bit in LCD_SR to 1).

17.7.2 LCD frame control register (LCD_FCR)

Address offset: 0x04

Reset value: 0x0000 0000

Bits 31:26 Reserved, must be kept at reset value

Bits 25:22 PS[3:0] : PS 16-bit prescaler

These bits are written by software to define the division factor of the PS 16-bit prescaler.
\( ck\_ps = LCDCLK/(2) \) . See Section 17.4.2 .

0000: \( ck\_ps = LCDCLK \)

0001: \( ck\_ps = LCDCLK/2 \)

0002: \( ck\_ps = LCDCLK/4 \)

...

1111: \( ck\_ps = LCDCLK/32768 \)

Bits 21:18 DIV[3:0] : DIV clock divider

These bits are written by software to define the division factor of the DIV divider. See Section 17.4.2 .

0000: \( ck\_div = ck\_ps/16 \)

0001: \( ck\_div = ck\_ps/17 \)

0002: \( ck\_div = ck\_ps/18 \)

...

1111: \( ck\_div = ck\_ps/31 \)

Bits 17:16 BLINK[1:0] : Blink mode selection

00: Blink disabled

01: Blink enabled on SEG[0], COM[0] (1 pixel)

10: Blink enabled on SEG[0], all COMs (up to 8 pixels depending on the programmed duty)

11: Blink enabled on all SEGs and all COMs (all pixels)

Bits 15:13 BLINKF[2:0] : Blink frequency selection

000: \( f_{LCD}/8 \)

001: \( f_{LCD}/16 \)

010: \( f_{LCD}/32 \)

011: \( f_{LCD}/64 \)

100: \( f_{LCD}/128 \)

101: \( f_{LCD}/256 \)

110: \( f_{LCD}/512 \)

111: \( f_{LCD}/1024 \)

These bits specify one of the \( V_{LCD} \) maximum voltages (independent of \( V_{DD} \) ). It ranges from 2.60 V to 3.51V.

• 000: \( V_{LCD0} \)
• 001: \( V_{LCD1} \)
• 010: \( V_{LCD2} \)
• 011: \( V_{LCD3} \)
• 100: \( V_{LCD4} \)
• 101: \( V_{LCD5} \)
• 110: \( V_{LCD6} \)
• 111: \( V_{LCD7} \)

Refer to the product datasheet for the \( V_{LCDx} \) values.

These bits are written by software to configure the length of the dead time between frames. During the dead time the COM and SEG voltage levels are held at 0 V to reduce the contrast without modifying the frame rate.

• 000: No dead time
• 001: 1 phase period dead time
• 010: 2 phase period dead time
• .....
• 111: 7 phase period dead time

These bits are written by software to define the pulse duration in terms of \( ck\_ps \) pulses. A short pulse will lead to lower power consumption, but displays with high internal resistance may need a longer pulse to achieve satisfactory contrast.

Note that the pulse will never be longer than one half prescaled LCD clock period.

• 000: 0
• 001: \( 1/ck\_ps \)
• 010: \( 2/ck\_ps \)
• 011: \( 3/ck\_ps \)
• 100: \( 4/ck\_ps \)
• 101: \( 5/ck\_ps \)
• 110: \( 6/ck\_ps \)
• 111: \( 7/ck\_ps \)

PON duration example with LCDCLK = 32.768 kHz and PS=0x03:

• 000: 0 \( \mu s \)
• 001: 244 \( \mu s \)
• 010: 488 \( \mu s \)
• 011: 782 \( \mu s \)
• 100: 976 \( \mu s \)
• 101: 1.22 ms
• 110: 1.46 ms
• 111: 1.71 ms

This bit is set and cleared by software.

• 0: LCD Update Display Done interrupt disabled
• 1: LCD Update Display Done interrupt enabled

Bit 2 Reserved, must be kept at reset value

Bit 1 SOFIE : Start of frame interrupt enable

This bit is set and cleared by software.

0: LCD Start of Frame interrupt disabled

1: LCD Start of Frame interrupt enabled

Bit 0 HD : High drive enable

This bit is written by software to enable a low resistance divider. Displays with high internal resistance may need a longer drive time to achieve satisfactory contrast. This bit is useful in this case if some additional power consumption can be tolerated.

0: Permanent high drive disabled

1: Permanent high drive enabled. When HD=1, then the PON bits have to be programmed to 001.

Note: The data in this register can be updated any time, however the new values are applied only at the beginning of the next frame (except for UDDIE, SOFIE that affect the device behavior immediately).

The new value of CC[2:0] bits is also applied immediately but its effect on device is delayed at the beginning of next frame by the voltage generator.

Reading this register obtains the last value written in the register and not the configuration used to display the current frame.

17.7.3 LCD status register (LCD_SR)

Address offset: 0x08

Reset value: 0x0000 0020

Bits 31:6 Reserved, must be kept at reset value

Bit 5 FCRSF : LCD Frame Control Register Synchronization flag

This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK domain. It is cleared by hardware when writing to the LCD_FCR register.

0: LCD Frame Control Register not yet synchronized

1: LCD Frame Control Register synchronized

Bit 4 RDY : Ready flag

This bit is set and cleared by hardware. It indicates the status of the step-up converter.

0: Not ready

1: Step-up converter is enabled and ready to provide the correct voltage.

Bit 3 UDD: Update Display Done

This bit is set by hardware. It is cleared by writing 1 to the UDDC bit in the LCD_CLR register. The bit set has priority over the clear.

0: No event

1: Update Display Request done. A UDD interrupt is generated if the UDDIE bit in the LCD_FCR register is set.

Note: If the device is in Stop mode (PCLK not provided) UDD will not generate an interrupt even if UDDIE = 1.

If the display is not enabled the UDD interrupt will never occur.

Bit 2 UDR: Update display request

Each time software modifies the LCD_RAM it must set the UDR bit to transfer the updated data to the second level buffer. The UDR bit stays set until the end of the update and during this time the LCD_RAM is write protected.

0: No effect

1: Update Display request

Note: When the display is disabled, the update is performed for all LCD_DISPLAY locations. When the display is enabled, the update is performed only for locations for which commons are active (depending on DUTY). For example if DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated.

Note: Writing 0 on this bit or writing 1 when it is already 1 has no effect. This bit can be cleared by hardware only. It can be cleared only when LCDEN = 1

Bit 1 SOF: Start of frame flag

This bit is set by hardware at the beginning of a new frame, at the same time as the display data is updated. It is cleared by writing a 1 to the SOFC bit in the LCD_CLR register. The bit clear has priority over the set.

0: No event

1: Start of Frame event occurred. An LCD Start of Frame Interrupt is generated if the SOFIE bit is set.

ENS: LCD enabled status

Bit 0 This bit is set and cleared by hardware. It indicates the LCD controller status.

0: LCD Controller disabled.

1: LCD Controller enabled

Note: The ENS bit is set immediately when the LCDEN bit in the LCD_CR goes from 0 to 1. On deactivation it reflects the real status of LCD so it becomes 0 at the end of the last displayed frame.

17.7.4 LCD clear register (LCD_CLR)

Address offset: 0x0C

Reset value: 0x0000 0000

Bits 31:4 Reserved, must be kept at reset value

Bit 3 UDDC : Update display done clear

This bit is written by software to clear the UDD flag in the LCD_SR register.

0: No effect

1: Clear UDD flag

Bit 2 Reserved, must be kept at reset value

Bit 1 SOF : Start of frame flag clear

This bit is written by software to clear the SOF flag in the LCD_SR register.

0: No effect

1: Clear SOF flag

Bit 0 Reserved, must be kept at reset value

17.7.5 LCD display memory (LCD_RAM)

Address offset: 0x14 to 0x50

Reset value: 0x0000 0000

Bits 31:0 SEGMENT_DATA[31:0]

Each bit corresponds to one pixel of the LCD display.

0: Pixel inactive

1: Pixel active

17.7.6 LCD register map

The following table summarizes the LCD registers.

Table 80. LCD register map and reset values

Table 80. LCD register map and reset values (continued)

Refer to Section 2.2 on page 58 for the Register boundary addresses table.