12. Nested vectored interrupt controller (NVIC)

12.1 Main features

• • Up to 39 maskable interrupt channels (see Table 55 ). These do not include the 16 interrupt lines of Cortex ^® -M0+.
• • 4 programmable priority levels (2 bits of interrupt priority are used)
• • Low-latency exception and interrupt handling
• • Power management control
• • Implementation of system control registers

The NVIC and the processor core interface are closely coupled, which enables low-latency interrupt processing and efficient processing of late arriving interrupts.

All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to the STM32L0 Series Cortex ^® -M0+ programming manual (PM0223).

For code example, refer to A.7.1: NVIC initialization example .

12.2 SysTick calibration value register

The SysTick calibration value is fixed to 4000, which gives a reference time base of 1 ms with the SysTick clock set to 4 MHz (max HCLK/8).

12.3 Interrupt and exception vectors

Table 55 is the vector table for STM32L0x3 devices.

Table 55. List of vectors ⁽¹⁾⁽²⁾

1. 1. The grayed cells correspond to the Cortex®-M0+ interrupts.
2. 2. Refer to Table 1: STM32L0x3 memory density , to Table 2: Overview of features per category and to the device datasheets for the GPIO ports and peripherals available on your device. The memory area corresponding to unavailable GPIO ports or peripherals are reserved.