6. Power control (PWR)

6.1 Power supplies

The device requires a 1.8-to-3.6 V \( V_{DD} \) operating voltage supply (down to 1.65 V at power-down) when the BOR is available. The device requires a 1.65-to-3.6 V \( V_{DD} \) operating voltage supply when the BOR is not available.

An embedded linear voltage regulator is used to supply the internal digital power, ranging from 1.2 to 1.8 V.

• • \( V_{DD} = 1.8 \) V (at power-on) or 1.65 V (at power-down) to 3.6 V when the BOR is available. \( V_{DD} = 1.65 \) V to 3.6 V, when BOR is not available

\( V_{DD} \) is the external power supply for I/Os and internal regulator. It is provided externally through \( V_{DD} \) pins

• • \( V_{CORE} = 1.2 \) to 1.8 V

\( V_{CORE} \) is the power supply for digital peripherals, SRAM and Flash memory. It is generated by a internal voltage regulator. Three \( V_{CORE} \) ranges can be selected by software depending on \( V_{DD} \) (refer Figure 11 ).

• • \( V_{SSA}, V_{DDA} = 1.8 \) V (at power-on) or 1.65 V (at power-down) to 3.6 V, when BOR is available and \( V_{SSA}, V_{DDA} = 1.65 \) to 3.6 V, when BOR is not available.

\( V_{DDA} \) is the external analog power supply for ADC, DAC, reset blocks, RC oscillators and PLL. The minimum voltage to be applied to \( V_{DDA} \) is 1.8 V when the DAC is used.

• • \( V_{REF+} \)

\( V_{REF+} \) is the input reference voltage. It is only available as an external pin on a few packages, otherwise it is bonded to \( V_{DDA} \) .

• • \( V_{LCD} = 2.5 \) to 3.6 V

The LCD controller can be powered either externally through \( V_{LCD} \) pin, or internally from an internal voltage generated by the embedded step-up converter.

• • \( V_{DD\_USB} = 3.0 \) to 3.6 V

\( V_{DD\_USB} \) is a dedicated independent USB power supply for full speed transceivers. It is available on PA11 and PA12 pins provided they are configured as USB alternate function.

Note: \( V_{DD\_USB} \) value does not dependent on \( V_{DD} \) and \( V_{DDA} \) . However, \( V_{DD\_USB} \) must be the last supply to be delivered to the device and the first to be switched off. When the three power supplies are shut down, if \( V_{DD\_USB} \) remains active for a short period of time and \( V_{DDA}/V_{DDIO} \) fall below the functional range, the device is not be damaged.

The device is still functional when \( V_{DD\_USB} \) is switched off.

Figure 10. Power supply overview

1. 1. \( V_{DDA} \) and \( V_{SSA} \) must be connected to \( V_{DD} \) and \( V_{SS} \) , respectively.
2. 2. Depending on the operating power supply range used, some peripherals may be used with limited features or performance.
3. 3. \( V_{REF+} \) is only available on TFBGA64 package.

6.1.1 Independent A/D and DAC converter supply and reference voltage

To improve conversion accuracy, the ADC and the DAC have an independent power supply that can be filtered separately, and shielded from noise on the PCB.

• • The ADC voltage supply input is available on a separate \( V_{DDA} \) pin
• • An isolated supply ground connection is provided on the \( V_{SSA} \) pin

On packages with \( V_{REF+} \) pin

To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to \( V_{REF+} \) a separate external reference voltage lower than \( V_{DD} \) . \( V_{REF+} \) is the highest voltage, represented by the full scale value, for an analog input (ADC) or output (DAC) signal.

For DAC:

For ADC:

On packages without \( V_{REF+} \) pin

\( V_{REF+} \) pin is not available. It is internally connected to the ADC voltage supply ( \( V_{DDA} \) ).

6.1.2 Independent LCD supply

The \( V_{LCD} \) pin is provided to control the contrast of the glass LCD. This pin can be used in two ways:

• • It can receive from an external circuitry the desired maximum voltage that is provided on segment and common lines to the glass LCD by the microcontroller.
• • It can also be used to connect an external capacitor that is used by the microcontroller for its voltage step-up converter. This step-up converter is controlled by software to provide the desired voltage to segment and common lines of the glass LCD.

The voltage provided to segment and common lines defines the contrast of the glass LCD pixels. This contrast can be reduced when you configure the dead time between frames.

• • When an external power supply is provided to the \( V_{LCD} \) pin, it should range from 2.5 V to 3.6 V. It does not depend on \( V_{DD} \) .
• • When the LCD is based on the internal step-up converter, the \( V_{LCD} \) pin should be connected to a capacitor (see the product datasheets for further information).

6.1.3 RTC and RTC backup registers

The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability. The RTC contains 5 backup data registers (20 bytes). These backup registers are reset when a tamper detection event occurs. For more details refer to Real-time clock (RTC) section.

RTC registers access

After reset, the RTC Registers (RTC registers and RTC backup registers) are protected against possible stray write accesses. To enable access to the RTC Registers, proceed as follows:

1. 1. Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR register.
2. 2. Set the DBP bit in the PWR_CR register (see Section 6.4.1 ).
3. 3. Select the RTC clock source through RTCSEL[1:0] bits in RCC_CSR register.
4. 4. Enable the RTC clock by programming the RTCEN bit in the RCC_CSR register.

6.1.4 Voltage regulator

An embedded linear voltage regulator supplies all the digital circuitries except for the Standby circuitry. The regulator output voltage ( \( V_{\text{CORE}} \) ) can be programmed by software to three different ranges within 1.2 - 1.8 V (typical) (see Section 6.1.5 ).

The voltage regulator is always enabled after Reset. It works in three different modes: main (MR), low-power (LPR) and power-down, depending on the application modes.

• • In Run mode, the regulator is main (MR) mode and supplies full power to the \( V_{\text{CORE}} \) domain (core, memories and digital peripherals).
• • In Low-power run mode, the regulator is in low-power (LPR) mode and supplies low-power to the \( V_{\text{CORE}} \) domain, preserving the contents of the registers and internal SRAM.
• • In Sleep mode, the regulator is main (MR) mode and supplies full power to the \( V_{\text{CORE}} \) domain, preserving the contents of the registers and internal SRAM.
• • In Low-power sleep mode, the regulator is in low-power (LPR) mode and supplies low-power to the \( V_{\text{CORE}} \) domain, preserving the contents of the registers and internal SRAM.
• • In Stop mode the regulator supplies low power to the \( V_{\text{CORE}} \) domain, preserving the content of registers and internal SRAM.
• • In Standby mode, the regulator is powered off. The content of the registers and SRAM are lost except for the Standby circuitry.

6.1.5 Dynamic voltage scaling management

The dynamic voltage scaling is a power management technique which consists in increasing or decreasing the voltage used for the digital peripherals ( \( V_{\text{CORE}} \) ), according to the circumstances.

Dynamic voltage scaling to increase \( V_{\text{CORE}} \) is known as overvolting. It allows improving the device performance. Refer to Figure 11 for a description of the device operating conditions versus CPU performance and to the datasheet electrical characteristics for ADC clock frequency versus dynamic range.

Dynamic voltage scaling to decrease \( V_{\text{CORE}} \) is known as undervolting. It is performed to save power, particularly in laptops and other mobile devices where the energy comes from a battery and is thus limited.

Range 1

Range 1 is the “high performance” range.

The voltage regulator outputs a 1.8 V voltage (typical) as long as the \( V_{\text{DD}} \) input voltage is above 1.71 V. Flash program and erase operations can be performed in this range.

The clock recovery system (CRS) is available only when the device operates in range 1 (see Section 8: Clock recovery system (CRS) ).

When \( V_{\text{DD}} \) is below 2.0 V, the CPU frequency changes from initial to final state must respect the following conditions:

• • \( f_{\text{CPUfinal}} < 4 \times f_{\text{CPUinitial}} \)
• • In addition, a 5 µs delay must be respected between two changes. For example to switch from 4.2 to 32 MHz, switch from 4.2 to 16 MHz, wait for 5 µs, then switch from 16 to 32 MHz.

Range 2 and 3

The regulator can also be programmed to output a regulated 1.5 V (typical, range 2) or a 1.2 V (typical, range 3) without any limitations on \( V_{DD} \) (1.65 to 3.6 V).

• • At 1.5 V, the Flash memory is still functional but with medium read access time. This is the “medium performance” range. Program and erase operations on the Flash memory are still possible.
• • At 1.2 V, the Flash memory is still functional but with slow read access time. This is the “low performance” range. Program and erase operations on the Flash memory are not possible under these conditions.

Refer to Table 31 for details on the performance for each range.

Table 31. Performance versus \( V_{CORE} \) ranges

Figure 11. Performance versus \( V_{DD} \) and \( V_{CORE} \) range

6.1.6 Dynamic voltage scaling configuration

The following sequence is required to program the voltage regulator ranges:

1. 1. Check \( V_{DD} \) to identify which ranges are allowed (see Figure 11: Performance versus \( V_{DD} \) and \( V_{CORE} \) range ).
2. 2. Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0.
3. 3. Configure the voltage scaling range by setting the VOS[1:0] bits in the PWR_CR register.
4. 4. Poll VOSF bit of in PWR_CSR register. Wait until it is reset to 0.

Note: During voltage scaling configuration, the system clock is stopped until the regulator is stabilized (VOSF=0). This must be taken into account during application development, in case a critical reaction time to interrupt is needed, and depending on peripheral used (timer, communication,...).

6.1.7 Voltage regulator and clock management when \( V_{DD} \) drops below 1.71 V

When \( V_{CORE} \) range 1 is selected and \( V_{DD} \) drops below 1.71 V, the application must reconfigure the system.

A three-step sequence is required to reconfigure the system:

1. 1. Detect that \( V_{DD} \) drops below 1.71 V:
   Use the PVD to monitor the \( V_{DD} \) voltage and to generate an interrupt when the voltage goes under the selected level. To detect the 1.71 V voltage limit, the application can select by software PVD threshold 2 (2.26 V typical). For more details on the PVD, refer to Section 6.2.3 .
2. 2. Adapt the clock frequency to the voltage range that will be selected at next step:
   Below 1.71 V, the system clock frequency is limited to 16 MHz for range 2 and 4.2 MHz for range 3.
3. 3. Select the required voltage range:
   Note that when \( V_{DD} \) is below 1.71 V, only range 2 or range 3 can be selected.

Note: When \( V_{CORE} \) range 2 or range 3 is selected and \( V_{DD} \) drops below 1.71 V, no system reconfiguration is required.

6.1.8 Voltage regulator and clock management when modifying the \( V_{CORE} \) range

When \( V_{DD} \) is above 1.71 V, any of the 3 voltage ranges can be selected:

• • When the voltage range is above the targeted voltage range (e.g. from range 1 to 2):
  1. a) Adapt the clock frequency to the lower voltage range that will be selected at next step.
  2. b) Select the required voltage range.
• • When the voltage range is below the targeted voltage range (e.g. from range 3 to 1):
  1. a) Select the required voltage range.
  2. b) Tune the clock frequency if needed.

When \( V_{DD} \) is below 1.71 V, only range 2 and 3 can be selected:

• • From range 2 to range 3
  • a) Adapt the clock frequency to voltage range 3.
  • b) Select voltage range 3.
• • From range 3 to range 2
  • a) Select the voltage range 2.
  • b) Tune the clock frequency if needed.

6.1.9 Voltage range and limitations when \( V_{DD} \) ranges from 1.71 V to 2.0 V

The STM32L0x3 voltage regulator is based on an architecture designed for Ultra-low-power a. It does not use any external capacitor. Such regulator is sensitive to fast changes of load. In this case, the output voltage is reduced for a short period of time. Considering that the core voltage must be higher than 1.65 V to ensure a 32 MHz operation, this phenomenon is critical for very low \( V_{DD} \) voltages (e.g. 1.71 V \( V_{DD} \) minimum value).

To guarantee 32 MHz operation at \( V_{DD} = 1.8 \text{ V} \pm 5\% \) , with 1 wait state, and \( V_{CORE} \) range 1, the CPU frequency in run mode must be managed to prevent any changes exceeding a ratio of 4 in one shot. A delay of 5 \( \mu\text{s} \) must be respected between 2 changes. There is no limitation when waking up from low-power mode.

6.2 Power supply supervisor

The device has an integrated zeropower power-on reset (POR)/power-down reset (PDR), coupled with a brown out reset (BOR) circuitry. For devices operating between 1.8 and 3.6 V, the BOR is always active at power-on and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently (in which case, the \( V_{DD} \) min value at power-down is 1.65 V). For devices operating between 1.65 V and 3.6 V, the BOR is permanently disabled. Consequently, the start-up time at power-on can be decreased down to 1 ms typically.

Five BOR thresholds can be configured by option bytes, starting from 1.65 to 3 V. To reduce the power consumption in Stop mode, the internal voltage reference, \( V_{REFINT} \) , can be automatically switch off. The device remains in reset mode when \( V_{DD} \) is below a specified threshold, \( V_{POR} \) , \( V_{PDR} \) or \( V_{BOR} \) , without the need for any external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the \( V_{DD}/V_{DDA} \) power supply and compares it to the \( V_{PVD} \) threshold. 7 different PVD levels can be selected by software between 1.85 and 3.05 V, with a 200 mV step. An interrupt can be generated when \( V_{DD}/V_{DDA} \) drops below the \( V_{PVD} \) threshold and/or when \( V_{DD}/V_{DDA} \) is higher than the \( V_{PVD} \) threshold. The interrupt service routine then generates a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

The different power supply supervisor (POR, PDR, BOR, PVD) are illustrated in Figure 12 .

Figure 12. Power supply supervisors

1. 1. The PVD is available on all devices and it is enabled or disabled by software.
2. 2. The BOR is available only on devices operating from 1.8 to 3.6 V, and unless disabled by option byte it will mask the POR/PDR threshold.
3. 3. When the BOR is disabled by option byte, the reset is asserted when \( V_{DD} \) goes below PDR level
4. 4. For devices operating from 1.65 to 3.6 V, there is no BOR and the reset is released when \( V_{DD} \) goes above POR level and asserted when \( V_{DD} \) goes below PDR level

6.2.1 Power-on reset (POR)/power-down reset (PDR)

The device has an integrated POR/PDR circuitry that allows operation down to 1.5 V.

During power-on, the device remains in Reset mode when \( V_{DD}/V_{DDA} \) is below a specified threshold, \( V_{POR} \) , without the need for an external reset circuit. The POR feature is always enabled and the POR threshold is 1.5 V.

During power-down, the PDR keeps the device under reset when the supply voltage ( \( V_{DD} \) ) drops below the \( V_{PDR} \) threshold. The PDR feature is always enabled and the PDR threshold is 1.5 V.

The POR and PDR are used only when the BOR is disabled (see Section 6.2.2: Brown out reset (BOR) ). To insure the minimum operating voltage (1.65 V), the BOR should be configured to BOR Level 1. When the BOR is disabled, a ‘‘gray zone’’ exist between the minimum operating voltage (1.65 V) and the \( V_{POR}/V_{PDR} \) threshold. This means that \( V_{DD} \) can be lower than 1.65 V without device reset until the \( V_{PDR} \) threshold is reached.

For more details concerning the power-on/power-down reset threshold, refer to the electrical characteristics of the datasheet.

Figure 13. Power-on reset/power-down reset waveform

6.2.2 Brown out reset (BOR)

During power-on, the Brown out reset (BOR) keeps the device under reset until the supply voltage reaches the specified \( V_{BOR} \) threshold.

For devices operating from 1.65 to 3.6 V, the BOR option is not available and the power supply is monitored by the POR/PDR. As the POR/PDR thresholds are at 1.5 V, a ‘‘gray zone’’ exists between the \( V_{POR}/V_{PDR} \) thresholds and the minimum product operating voltage 1.65 V.

For devices operating from 1.8 to 3.6 V, the BOR is always active at power-on and it's threshold is 1.8 V.

Then when the system reset is released, the BOR level can be reconfigured or disabled by option byte loading.

If the BOR level is kept at the lowest level, 1.8 V at power-on and 1.65 V at power-down, the system reset is fully managed by the BOR and the product operating voltages are within safe ranges.

And when the BOR option is disabled by option byte, the power-down reset is controlled by the PDR and a “gray zone” exists between the 1.65 V and \( V_{PDR} \) .

\( V_{BOR} \) is configured through device option bytes. By default, the Level 4 threshold is activated. 5 programmable \( V_{BOR} \) thresholds can be selected.

• • BOR Level 1 ( \( V_{BOR0} \) ): reset threshold level for 1.69 to 1.80 V voltage range
• • BOR Level 2 ( \( V_{BOR1} \) ): reset threshold level for 1.94 to 2.1 V voltage range
• • BOR Level 3 ( \( V_{BOR2} \) ): reset threshold level for 2.3 to 2.49 V voltage range
• • BOR Level 4 ( \( V_{BOR3} \) ): reset threshold level for 2.54 to 2.74 V voltage range
• • BOR Level 5 ( \( V_{BOR4} \) ): reset threshold level for 2.77 to 3.0 V voltage range

When the supply voltage ( \( V_{DD} \) ) drops below the selected \( V_{BOR} \) threshold, a device reset is generated. When the \( V_{DD} \) is above the \( V_{BOR} \) upper limit the device reset is released and the system can start.

BOR can be disabled by programming the device option bytes. To disable the BOR function, \( V_{DD} \) must have been higher than \( V_{BOR0} \) to start the device option byte programming sequence. The power-on and power-down is then monitored by the POR and PDR (see Section 6.2.1: Power-on reset (POR)/power-down reset (PDR) )

The BOR threshold hysteresis is \( \sim 100 \) mV (between the rising and the falling edge of the supply voltage).

Figure 14. BOR thresholds

6.2.3 Programmable voltage detector (PVD)

You can use the PVD to monitor the \( V_{DD} \) power supply by comparing it to a threshold selected by the PLS[2:0] bits in the PWR_CR (see Section 6.4.1 ).

The PVD can use an external input analog voltage (PVD_IN) which is compared internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode when PLS[2:0] = 111. The PVD is enabled by setting the PVDE bit.

A PVDO flag is available in the PWR_CSR register (see Section 6.4.2 ). It indicates if \( V_{DD} \) is higher or lower than the PVD threshold. This event is internally connected to EXTI line16 and can generate an interrupt if it has been enabled through the EXTI registers. The rising/falling edge sensitivity of EXTI Line16 should be configured according to the PVD output behavior: if EXTI line 16 is configured to rising edge sensitivity, the interrupt will be

generated when \( V_{DD} \) drops below the PVD threshold. As an example the service routine could perform emergency shutdown tasks.

Figure 15. PVD thresholds

6.2.4 Internal voltage reference ( \( V_{REFINT} \) )

The internal reference ( \( V_{REFINT} \) ) provides stable voltage for analog peripherals. The functions managed through the internal voltage reference ( \( V_{REFINT} \) ) are BOR, PVD, ADC, HSI48, LCD and comparators. The internal voltage reference ( \( V_{REFINT} \) ) is always enabled when one of these features is used.

The internal voltage reference consumption is not negligible, in particular in Stop and Standby mode. To reduce power consumption, the ULP bit (ultra-low-power) in the PWR_CR register can be set to disable the internal voltage reference. However, in this case, when exiting from the Stop/Standby mode, the functions managed through the internal voltage reference are not reliable during the internal voltage reference startup time (up to 3 ms).

To reduce the wakeup time, the device can exit from Stop/Standby mode without waiting for the internal voltage reference startup time. This is performed by setting the FWU bit (Fast wakeup) in the PWR_CR register before entering Stop/Standby mode.

If the ULP bit is set, the functions that were enabled before entering Stop/Standby mode will be disabled during these modes, and enabled again only after the end of the internal voltage reference startup time whatever FWU value. The VREFINTRDYF flag in the PWR_CSR register indicates that the internal voltage reference is ready.

When the device exits from low-power mode on an NRST pulse, it does not wait for internal voltage reference startup (even if ULP=1 and FWU=0). The application should check the VREFINTRDYF flag if necessary.

Note: When the LCD is active (LCDEN bit of LCD_CR set), VREFINT is required. ULP bit must consequently be reset.

6.3 Low-power modes

By default, the microcontroller is in Run mode after a system or a power-on reset. In Run mode the CPU is clocked by HCLK and the program code is executed. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, performance, short startup time and available wakeup sources.

The devices feature five low-power modes:

• • Low-power run mode: regulator in low-power mode, limited clock frequency, limited number of peripherals running (refer to Section 6.3.4 )
• • Sleep mode: Cortex ^® -M0+ core stopped, peripherals kept running (refer to Section 6.3.7 )
• • Low-power sleep mode: Cortex ^® -M0+ core stopped, limited clock frequency, limited number of peripherals running, regulator in low-power mode, Flash stopped ((refer to Section 6.3.8 ))
• • Stop mode (all clocks are stopped, regulator running, regulator in low-power mode (refer to Section 6.3.9 ))
• • Standby mode: V _CORE domain powered off ((refer to Section 6.3.10 ))

In addition, the power consumption in Run mode can be reduced by one of the following means:

• • Slowing down the system clocks
• • Gating the clocks to the APBx and AHBx peripherals when they are unused.

Table 32. Summary of low-power modes

Table 32. Summary of low-power modes (continued)

1. HSI16 can run in Stop mode provided HSI16KERON is set in Clock control register (RCC_CR) .

6.3.1 Behavior of clocks in low-power modes

APB peripheral and DMA clocks can be disabled by software.

Sleep and Low-power sleep modes

The CPU clock is stopped in Sleep and Low-power sleep mode. The memory interface clocks (Flash memory and RAM interfaces) and all peripherals clocks can be stopped by software during Sleep. The memory interface clock is stopped and the RAM is in power-down when in Low-power sleep mode. The AHB to APB bridge clocks are disabled by hardware during Sleep/Low-power sleep mode when all the clocks of the peripherals connected to them are disabled.

Stop and Standby modes

The system clock and all high speed clocks are stopped in Stop and Standby modes:

• • PLL is disabled
• • Internal RC 16 MHz (HSI16) oscillator is disabled
• • External 1-24 MHz (HSE) oscillator is disabled
• • Internal 65 kHz - 4.2 MHz (MSI) oscillator is disabled

When exiting this mode by an interrupt (Stop mode), the internal MSI or HSI16 can be selected as system clock. For both oscillators, their respective configuration (range and trimming) value is kept on Stop mode exit.

When exiting this mode by a reset (Standby mode), the internal MSI oscillator is selected as system clock. The range and the trimming value are reset to the default 2.1 MHz.

If a Flash program operation or an access to APB domain is ongoing, the Stop/Standby mode entry is delayed until the Flash memory or the APB access has completed.

6.3.2 Slowing down system clocks

In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode.

For more details refer to Section 7.3.4: Clock configuration register (RCC_CFGR) .

6.3.3 Peripheral clock gating

In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption.

To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions.

Peripheral clock gating is controlled by the AHB peripheral clock enable register (RCC_AHBENR), APB2 peripheral clock enable register (RCC_APB2ENR), APB1 peripheral clock enable register (RCC_APB1ENR) (see Section 7.3.13: AHB peripheral clock enable register (RCC_AHBENR) , Section 7.3.15: APB1 peripheral clock enable register (RCC_APB1ENR) and Section 7.3.14: APB2 peripheral clock enable register (RCC_APB2ENR) ).

Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in RCC_AHBLPENR and RCC_APBxLPENR registers (x can 1 or 2).

6.3.4 Low-power run mode (LP run)

To further reduce the consumption when the system is in Run mode, the regulator can be configured in low-power mode. In this mode, the system frequency should not exceed f _MSI range1.

Please refer to the product datasheet for more details on voltage regulator and peripherals operating conditions.

Note: To be able to read the RTC calendar register when the APB1 clock frequency is less than seven times the RTC clock frequency (7*RTCLCK), the software must read the calendar time and date registers twice.

If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done.

Low-power run mode can only be entered when V _CORE is in range 2. In addition, the dynamic voltage scaling must not be used when Low-power run mode is selected. Only Stop and Sleep modes with regulator configured in low-power mode is allowed when Low-power run mode is selected.

Note: In Low-power run mode, all I/O pins keep the same state as in Run mode.

Entering Low-power run mode

To enter Low-power run mode proceed as follows:

1. 1. Each digital IP clock must be enabled or disabled by using the RCC_APBxENR and RCC_AHBENR registers.
2. 2. The frequency of the system clock must be decreased to not exceed the frequency of f _MSI range1.
3. 3. The regulator is forced in low-power mode by software (LPRUN and LPDSR bits set)

Exiting Low-power run mode

To exit Low-power run mode proceed as follows:

1. 1. The regulator is forced in Main regulator mode by software.
2. 2. The Flash memory is switched on, if needed.
3. 3. The frequency of the clock system can be increased.

6.3.5 Entering low-power mode

Low-power modes (except for Low-power run mode) are entered by executing the WFI (Wait For Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in Cortex ^® -M0+ System Control register is set on Return from ISR.

Entering low-power mode through WFI or WFE will be executed only is no interrupt and no event is pending.

6.3.6 Exiting low-power mode

The microcontroller exists from Sleep and Stop mode depending on the way the mode was entered:

• • If the WFI instruction or Return from ISR was used to enter the low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device. This includes EXTI lines and any GPIO toggle.
• • If the WFE instruction was used to enter low-power mode, the microcontroller exits the low-power mode as soon as an event occurs. The wakeup event can be generated either by:
  • – An NVIC IRQ interrupt:
    This is done by enabling an interrupt in the peripheral control register but not in the NVIC, and by enabling the SEVONPEND bit in the Cortex ^® -M0+ System Control register. When the microcontroller resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
  • – An event:
    This is done by configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set.

6.3.7 Sleep mode

I/O states in Sleep mode

In Sleep mode, all I/O pins keep the same state as in Run mode.

Entering Sleep mode

The Sleep mode is entered according to Section 6.3.5: Entering low-power mode .

Refer to Table 33: Sleep-now and Table 34: Sleep-on-exit for details on how to enter Sleep mode.

Exiting Sleep mode

The Sleep mode is exited according to Section 6.3.6: Exiting low-power mode .

Refer to Table 33: Sleep-now and Table 34: Sleep-on-exit for more details on how to exit Sleep mode.

Table 33. Sleep-now

Table 34. Sleep-on-exit

6.3.8 Low-power sleep mode (LP sleep)

I/O states in Low-power sleep mode

In Low-power sleep mode, all I/O pins keep the same state as in Run mode.

Entering Low-power sleep mode

To enter Low-power sleep mode, proceed as follows:

1. 1. The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register. This reduces power consumption but increases the wake-up time.
2. 2. Each digital IP clock must be enabled or disabled by using the RCC_APBxENR and RCC_AHBENR registers.
3. 3. The frequency of the system clock must be decreased.
4. 4. The regulator is forced in low-power mode by software (LPDSR bits set).
5. 5. Follow the steps described in Section 6.3.5: Entering low-power mode .

Refer to Table 35: Sleep-now (Low-power sleep) and Table 36: Sleep-on-exit (Low-power sleep) for details on how to enter Low-power sleep mode.

In Low-power sleep mode, the Flash memory can be switched off and the RAM memory remains available.

In this mode, the system frequency should not exceed f_MSI range1.

Please refer to product datasheet for more details on voltage regulator and peripherals operating conditions.

Low-power sleep mode can only be entered when V _CORE is in range 2.

Note: To be able to read the RTC calendar register when the APB1 clock frequency is less than seven times the RTC clock frequency ( \( 7 \times \text{RTCLCK} \) ), the software must read the calendar time and date registers twice.

If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done.

Exiting Low-power sleep mode

The Low-power sleep mode is exited according to Section 6.3.6: Exiting low-power mode .

When exiting Low-power sleep mode by issuing an interrupt or a wakeup event, the regulator is configured in Main regulator mode, the Flash memory is switched on (if necessary), and the system clock can be increased.

When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Low-power sleep mode.

Refer to Table 35: Sleep-now (Low-power sleep) and Table 36: Sleep-on-exit (Low-power sleep) for more details on how to exit Sleep low-power mode.

Table 35. Sleep-now (Low-power sleep)

6.3.9 Stop mode

The Stop mode is based on the Cortex®-M0+ DeepSleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. In Stop mode, all clocks in the V _CORE domain are stopped, the PLL, the MSI, the HSI16 and the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.

To get the lowest consumption in Stop mode, the internal Flash memory also enters low-power mode. When the Flash memory is in power-down mode, an additional startup delay is incurred when waking up from Stop mode.

To minimize the consumption In Stop mode, V _REFINT , the BOR, PVD, and temperature sensor can be switched off before entering Stop mode. This functionality is controlled by the ULP bit in the PWR_CR register. If the ULP bit is set, the reference is switched off on Stop mode entry and enabled again on wakeup. .

I/O states in Low-power sleep mode

In Stop mode, all I/O pins keep the same state as in Run mode.

Entering Stop mode

Refer to Section 6.3.5: Entering low-power mode and to Table 37 for details on how to enter the Stop mode.

If the application needs to disable the external clock before entering Stop mode, the HSEON bit must be first disabled and the system clock switched to HSI16.

Otherwise, if the HSEON bit is kept enabled while external clock (external oscillator) can be removed before entering Stop mode, the clock security system (CSS) feature must be enabled to detect any external oscillator failure and avoid a malfunction behavior when entering Stop mode.

To further reduce power consumption in Stop mode, the internal voltage regulator can be put in low-power mode. This is configured by the LPSDSR bit in the PWR_CR register (see Section 6.4.1 ). The internal voltage regulator can also be kept in Main mode but the consumption will be much higher. As a result, it is always implicitly assumed that the regulator is in low-power mode during Stop mode. The only advantage of keeping the regulator in Main mode is that the wakeup time from Stop mode is shorter.

If Flash memory programming or an access to the APB domain is ongoing, the Stop mode entry is delayed until the memory or APB access has completed.

In Stop mode, the following features can be selected by programming individual control bits:

• • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. Refer to Section 25.3: IWDG functional description in Section 25: Independent watchdog (IWDG) .
• • Real-time clock (RTC): this is configured by the RTCEN bit in the RCC_CSR register (see Section 7.3.21 ).
• • Internal RC oscillator (LSI RC): this is configured by the LSION bit in the RCC_CSR register.
• • External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the RCC_CSR register.

The ADC, DAC and LCD can also consume power in Stop mode, unless they are disabled before entering it. To disable them, the ADDIS bit in the ADC_CR register must be set to 1 and the ENx bit in the DAC_CR register must be written to 0.

Exiting Stop mode

Refer to Section 6.3.6: Exiting low-power mode and to Table 37 for details on how to exit Stop mode.

When exiting Stop mode by issuing an interrupt or a wakeup event, the MSI or HSI16 RC oscillator is selected as system clock depending the bit STOPWUCK in the RCC_CFGR register.

When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced.

Table 37. Stop mode

6.3.10 Standby mode

The Standby mode allows to achieve the lowest power consumption. It is based on the Cortex®-M0+ DeepSleep mode, with the voltage regulator disabled. The V _CORE domain is consequently powered off. The PLL, the MSI, the HSI16 oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for the RTC registers, RTC backup registers and Standby circuitry (see Figure 10 ).

I/O states in Standby mode

In Standby mode, all I/O pins are high impedance except for:

• • Reset pad
• • Wakeup pins (WKUP1, WKUP2, WKUP3)
• • RTC functions (tamper, time-stamp, RTC Alarm out, RTC clock calibration out) on the following I/Os:
  • – Category 3: PC13, PA0
  • – Category 5: PC13, PA0, PE6

Entering Standby mode

Refer to Section 6.3.5: Entering low-power mode and to Table 38 for details on how to enter Standby mode.

In Standby mode, the following features can be selected by programming individual control bits:

• • Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. Refer to Section 25.3: IWDG functional description on page 634 .
• • Real-time clock (RTC): this is configured by the RTCEN bit in the RCC_CSR register (see Section 7.3.21 ).
• • Internal RC oscillator (LSI RC): this is configured by the LSION bit in the RCC_CSR register.
• • External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the RCC_CSR register.

Exiting Standby mode

The microcontroller exits Standby mode when an external Reset (NRST pin), an IWDG Reset, a rising edge on WKUP pins (WKUP1, WKUP2 or WKUP3), an RTC alarm, a tamper event, or a time-stamp event is detected.

After waking up from Standby mode, program execution restarts in the same way as after a Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the PWR_CSR register (see Section 6.4.2 ) indicates that the microcontroller was in Standby mode. All registers are reset to their default value after a system reset except for the register bits in the RTC domain (see Section 27.7: RTC registers , SBF status flag in the PWR power control/status register (PWR_CSR) , Control/status register (RCC_CSR) and Clock control register (RCC_CR) ).

Refer to Section 6.3.6: Exiting low-power mode and to Table 38 for more details on how to exit Standby mode.

Table 38. Standby mode

Debug mode

By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex®-M0+ core is no longer clocked.

However, by setting some configuration bits in the DBG_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to Section 33.9.1: Debug support for low-power modes .

6.3.11 Waking up the device from Stop and Standby modes using the RTC and comparators

The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC Wakeup event, a tamper event, a time-stamp event, or a comparator event, without depending on an external interrupt (Auto-wakeup mode).

These RTC alternate functions can wake up the system from Stop and Standby low-power modes while the comparator events can only wake up the system from Stop mode.

The system can also wake up from low-power modes without depending on an external interrupt (Auto-wakeup mode) by using the RTC alarm or the RTC wakeup events.

The RTC provides a programmable time base for waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the RCC_CSR register (see Section 7.3.21 ):

• • Low-power 32.768 kHz external crystal oscillator (LSE OSC).
  This clock source provides a precise time base with very low-power consumption (less than 1 µA added consumption in typical conditions)
• • Low-power internal RC oscillator (LSI RC)
  This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC Oscillator is designed to use minimum power consumption.

RTC auto-wakeup (AWU) from the Stop mode

• • To wake up from the Stop mode with an RTC alarm event, it is necessary to:
  1. a) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event modes)
  2. b) Enable the RTC Alarm interrupt in the RTC_CR register
  3. c) Configure the RTC to generate the RTC alarm
• • To wake up from the Stop mode with an RTC Tamper or time stamp event, it is necessary to:
  1. a) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt or Event modes)
  2. b) Enable the RTC TimeStamp Interrupt in the RTC_CR register or the RTC Tamper Interrupt in the RTC_TCR register
  3. c) Configure the RTC to detect the tamper or time stamp event
• • To wake up from the Stop mode with an RTC Wakeup event, it is necessary to:
  1. a) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt or Event modes)
  2. b) Enable the RTC Wakeup Interrupt in the RTC_CR register
  3. c) Configure the RTC to generate the RTC Wakeup event

RTC auto-wakeup (AWU) from the Standby mode

• • To wake up from the Standby mode with an RTC alarm event, it is necessary to:
  1. a) Enable the RTC Alarm interrupt in the RTC_CR register
  2. b) Configure the RTC to generate the RTC alarm
• • To wake up from the Stop mode with an RTC Tamper or time stamp event, it is necessary to:
  1. a) Enable the RTC TimeStamp Interrupt in the RTC_CR register or the RTC Tamper Interrupt in the RTC_TCR register
  2. b) Configure the RTC to detect the tamper or time stamp event
• • To wake up from the Stop mode with an RTC Wakeup event, it is necessary to:
  1. a) Enable the RTC Wakeup Interrupt in the RTC_CR register
  2. b) Configure the RTC to generate the RTC Wakeup event

• • To wake up from the Stop mode with a comparator 1 or comparator 2 wakeup event, it is necessary to:
  1. a) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 (Interrupt or Event mode) to be sensitive to the selected edges (falling, rising or falling and rising)
  2. b) Configure the comparator to generate the event.

6.4 Power control registers

The peripheral registers have to be accessed by half-words (16-bit) or words (32-bit).

6.4.1 PWR power control register (PWR_CR)

Address offset: 0x00

Reset value: 0x0000 1000 (reset by wakeup from Standby mode)

Bits 31:15 Reserved, always read as 0.

Bit 14 LPRUN : Low-power run mode

When LPRUN bit is set together with the LPSDSR bit, the regulator is switched from Main mode to low-power mode. Otherwise, it remains in Main mode. The regulator goes back to operate in Main mode when LPRUN is reset.

If this bit is set (with LPSDSR bit set) and the CPU enters sleep or Deep sleep mode (LP sleep or Stop mode), then, when the CPU wakes up from these modes, it enters Run mode but with LPRUN bit set. To enter again Low-power run mode, it is necessary to perform a reset and set LPRUN bit again.

It is forbidden to reset LPSDSR when the MCU is in Low-power run mode. LPSDSR is used as a prepositioning for the entry into low-power mode, indicating to the system which configuration of the regulator will be selected when entering low-power mode. The LPSDSR bit must be set before the LPRUN bit is set. LPSDSR can be reset only when LPRUN bit=0.

0: Voltage regulator in Main mode in Low-power run mode

1: Voltage regulator in low-power mode in Low-power run mode

Bit 13 DS_EE_KOFF : Deep sleep mode with non-volatile memory kept off

When entering low-power mode (Stop or Standby only), if DS_EE_KOFF and RUN_PD bits are both set in FLASH_ACR register (refer to Section 3.7.1: Access control register (FLASH_ACR) ), the non-volatile memory (Flash program memory and data EEPROM) will not be woken up when exiting from Deep sleep mode.

0: NVM woken up when exiting from Deep sleep mode even if the bit RUN_PD is set

1: NVM not woken up when exiting from low-power mode (if the bit RUN_PD is set)

Bits 12:11 VOS[1:0] : Voltage scaling range selection

These bits are used to select the internal regulator voltage range.

Before resetting the power interface by resetting the PWRRST bit in the RCC_APB1RSTR register, these bits have to be set to '10' and the frequency of the system has to be configured accordingly.

00: forbidden (bits are unchanged and keep the previous value, no voltage change occurs)

01: 1.8 V (range 1)

10: 1.5 V (range 2)

11: 1.2 V (range 3)

This bit works in conjunction with ULP bit.

If ULP = 0, FWU is ignored

If ULP = 1 and FWU = 1: \( V_{REFINT} \) startup time is ignored when exiting from low-power mode. The VREFINTRDYF flag in the PWR_CSR register indicates when the \( V_{REFINT} \) is ready again.

If ULP=1 and FWU = 0: Exiting from low-power mode occurs only when the \( V_{REFINT} \) is ready (after its startup time). This bit is not reset by resetting the PWRRST bit in the RCC_APB1RSTR register.

0: Low-power modes exit occurs only when \( V_{REFINT} \) is ready

1: \( V_{REFINT} \) start up time is ignored when exiting low-power modes

When set, the \( V_{REFINT} \) is switched off in low-power mode. The BOR, PVD, and temperature sensor also rely on the voltage reference. This bit is not reset by resetting the PWRRST bit in the RCC_APB1RSTR register. When this bit is set, the LCDEN bit of register LCD_CR must not be set.

0: \( V_{REFINT} \) is on in low-power mode

1: \( V_{REFINT} \) is off in low-power mode

In reset state, the RTC, RTC backup registers and RCC CSR register are protected against parasitic write access. This bit must be set to enable write access to these registers.

0: Access to RTC, RTC Backup and RCC CSR registers disabled

1: Access to RTC, RTC Backup and RCC CSR registers enabled

Note: If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, this bit must remain set to 1.

The DBP bit must remain set while LCD is in use.

These bits are written by software to select the voltage threshold detected by the programmable voltage detector:

000: 1.9 V

001: 2.1 V

010: 2.3 V

011: 2.5 V

100: 2.7 V

101: 2.9 V

110: 3.1 V

111: External input analog voltage (Compare internally to \( V_{REFINT} \) )

PVD_IN input (PB7) has to be configured as analog input when PLS[2:0] = 111.

Note: Refer to the electrical characteristics of the datasheet for more details.

This bit is set and cleared by software.

0: PVD disabled

1: PVD enabled

This bit is always read as 0.

0: No effect

1: Clear the SBF Standby flag (write).

Bit 2 CWUF : Clear wakeup flag

This bit is always read as 0.

0: No effect

1: Clear the WUF Wakeup flag after 2 system clock cycles

Bit 1 PDDS : Power-down deepsleep

This bit is set and cleared by software.

0: Enter Stop mode when the CPU enters Deepsleep.

1: Enter Standby mode when the CPU enters Deepsleep.

Bit 0 LPDSR : Low-power deepsleep/Sleep/Low-power run

– DeepSleep/Sleep modes

When this bit is set, the regulator switches in low-power mode when the CPU enters sleep or Deepsleep mode. The regulator goes back to Main mode when the CPU exits from these modes.

– Low-power run mode

When this bit is set, the regulator switches in low-power mode when the bit LPRUN is set. The regulator goes back to Main mode when the bit LPRUN is reset.

This bit is set and cleared by software.

0: Voltage regulator on during Deepsleep/Sleep/Low-power run mode

1: Voltage regulator in low-power mode during Deepsleep/Sleep/Low-power run mode

6.4.2 PWR power control/status register (PWR_CSR)

Address offset: 0x04

Reset value: 0x0000 0008 (not reset by wakeup from Standby mode)

Additional APB cycles are needed to read this register versus a standard APB read.

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 EWUP3 : Enable WKUP pin 3

This bit is set and cleared by software.

0: WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode.

1: WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3 wakes-up the system from Standby mode).

Note: This bit is reset by a system reset.

Bit 9 EWUP2 : Enable WKUP pin 2

This bit is set and cleared by software.

0: WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not wakeup the device from Standby mode.

1: WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode).

Note: This bit is reset by a system reset.

Bit 8 EWUP1 : Enable WKUP pin 1

This bit is set and cleared by software.

0: WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not wakeup the device from Standby mode.

1: WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode).

Note: This bit is reset by a system reset.

Bits 7:6 Reserved, must be kept at reset value.

Bit 5 REGLPF : Regulator LP flag

This bit is set by hardware when the MCU is in Low-power run mode.

When the MCU exits from Low-power run mode, this bit stays at 1 until the regulator is ready in Main mode. A polling on this bit is recommended to wait for the regulator Main mode. This bit is reset by hardware when the regulator is ready.

0: Regulator is ready in Main mode

1: Regulator voltage is in low-power mode

A delay is required for the internal regulator to be ready after the voltage range is changed. The VOSF bit indicates that the regulator has reached the voltage level defined with bits VOS of PWR_CR register.

This bit is set when VOS[1:0] in PWR_CR register change.

It is reset once the regulator is ready.

• 0: Regulator is ready in the selected voltage range
• 1: Regulator voltage output is changing to the required VOS level.

This bit indicates the state of the internal voltage reference, \( V_{REFINT} \) .

• 0: \( V_{REFINT} \) is OFF
• 1: \( V_{REFINT} \) is ready

This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.

• 0: \( V_{DD} \) is higher than the PVD threshold selected with the PLS[2:0] bits.
• 1: \( V_{DD} \) is lower than the PVD threshold selected with the PLS[2:0] bits.

Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after Standby or reset until the PVDE bit is set.

This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down reset) or by setting the CSBF bit in the PWR power control register (PWR_CR)

• 0: Device has not been in Standby mode
• 1: Device has been in Standby mode

This bit is set by hardware and cleared by a system reset or by setting the CWUF bit in the PWR power control register (PWR_CR)

• 0: No wakeup event occurred
• 1: A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup).

Note: An additional wakeup event is detected if the WKUP pins are enabled (by setting the EWUPx (x=1, 2, 3) bits) when the WKUP pin levels are already high.

6.4.3 PWR register map

The following table summarizes the PWR registers.

Table 39. PWR - register map and reset values

Refer to Section 2.2 on page 58 for the register boundary addresses.