RM0367-STM32L0x3

Introduction

This reference manual targets application developers. It provides complete information on how to use the STM32L0x3 microcontroller memory and peripherals.

The STM32L0x3 is a line of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the corresponding datasheets.

For information on the Arm ^®Cortex ^®-M0+ core, refer to the Cortex ^®-M0+ Technical Reference Manual .

The STM32L0x3 microcontrollers include state-of-the-art patented technology.

• Cortex ^®-M0+ Technical Reference Manual, available from www.arm.com .
• STM32L0 Series Cortex ^®-M0+ programming manual (PM0223).
• STM32L0x3 datasheets.
• STM32L0x3 erratasheet.

1	Documentation conventions . . . . .	52
1.1	General information . . . . .	52
1.2	List of abbreviations for registers . . . . .	52
1.3	Glossary . . . . .	53
1.4	Availability of peripherals . . . . .	53
1.5	Product category definition . . . . .	53
2	System and memory overview . . . . .	56
2.1	System architecture . . . . .	56
2.1.1	S0: Cortex®-bus . . . . .	57
2.1.2	S1: DMA-bus . . . . .	57
2.1.3	BusMatrix . . . . .	57
	AHB/APB bridges . . . . .	57
2.2	Memory organization . . . . .	58
2.2.1	Introduction . . . . .	58
2.2.2	Memory map and register boundary addresses . . . . .	59
2.3	Embedded SRAM . . . . .	64
2.4	Boot configuration . . . . .	64
	Bank swapping (category 5 devices only) . . . . .	65
	Physical remap . . . . .	65
	Embedded bootloader . . . . .	65
3	Flash program memory and data EEPROM (FLASH) . . . . .	66
3.1	Introduction . . . . .	66
3.2	NVM main features . . . . .	66
3.3	NVM functional description . . . . .	67
3.3.1	NVM organization . . . . .	67
3.3.2	Dual-bank boot capability . . . . .	71
3.3.3	Reading the NVM . . . . .	72
	Protocol to read . . . . .	72
	Relation between CPU frequency/Operation mode/NVM read time . . . . .	73
	Data buffering . . . . .	75
3.3.4	Writing/erasing the NVM . . . . .	81
	Write/erase protocol . . . . .	81

Unlocking/locking operations . . . . .	82
Detailed description of NVM write/erase operations. . . . .	85
Parallel write half-page Flash program memory. . . . .	91
Status register . . . . .	95
3.4 Memory protection . . . . .	96
3.4.1 RDP (Read Out Protection) . . . . .	97
3.4.2 PcROP (Proprietary Code Read-Out Protection) . . . . .	98
3.4.3 Protections against unwanted write/erase operations . . . . .	100
3.4.4 Write/erase protection management . . . . .	101
3.4.5 Protection errors . . . . .	102
Write protection error flag (WRPERR) . . . . .	102
Read error (RDERR) . . . . .	102
3.5 NVM interrupts . . . . .	102
3.5.1 Hard fault . . . . .	103
3.6 Memory interface management . . . . .	103
3.6.1 Operation priority and evolution . . . . .	103
Read . . . . .	103
Write/erase . . . . .	103
Option byte loading. . . . .	104
3.6.2 Sequence of operations . . . . .	104
Read as data while write . . . . .	104
Fetch while write. . . . .	104
Write while another write operation is ongoing. . . . .	105
3.6.3 Change the number of wait states while reading . . . . .	105
3.6.4 Power-down . . . . .	105
3.7 Flash register description . . . . .	106
Read registers . . . . .	106
Write to registers . . . . .	106
3.7.1 Access control register (FLASH_ACR) . . . . .	107
3.7.2 Program and erase control register (FLASH_PECR) . . . . .	108
3.7.3 Power-down key register (FLASH_PDKEYR) . . . . .	112
3.7.4 PECR unlock key register (FLASH_PEKEYR) . . . . .	112
3.7.5 Program and erase key register (FLASH_PRGKEYR) . . . . .	112
3.7.6 Option bytes unlock key register (FLASH_OPTKEYR) . . . . .	113
3.7.7 Status register (FLASH_SR) . . . . .	114
3.7.8 Option bytes register (FLASH_OPTR) . . . . .	116
3.7.9 Write protection register 1 (FLASH_WRPROT1) . . . . .	118
3.7.10 Write protection register 2 (FLASH_WRPROT2) . . . . .	119

- - 3.7.11 Flash register map . . . . . 120
- 3.8 Option bytes . . . . . 121
  - 3.8.1 Option bytes description . . . . . 121
  - 3.8.2 Mismatch when loading protection flags . . . . . 122
  - 3.8.3 Reloading Option bytes by software . . . . . 122
4 Cyclic redundancy check calculation unit (CRC) . . . . . 123
- 4.1 Introduction . . . . . 123
- 4.2 CRC main features . . . . . 123
- 4.3 CRC functional description . . . . . 124
  - 4.3.1 CRC block diagram . . . . . 124
  - 4.3.2 CRC internal signals . . . . . 124
  - 4.3.3 CRC operation . . . . . 124
    - Polynomial programmability . . . . . 125
- 4.4 CRC registers . . . . . 126
  - 4.4.1 CRC data register (CRC_DR) . . . . . 126
  - 4.4.2 CRC independent data register (CRC_IDR) . . . . . 126
  - 4.4.3 CRC control register (CRC_CR) . . . . . 127
  - 4.4.4 CRC initial value (CRC_INIT) . . . . . 128
  - 4.4.5 CRC polynomial (CRC_POL) . . . . . 128
  - 4.4.6 CRC register map . . . . . 129
5 Firewall (FW) . . . . . 130
- 5.1 Introduction . . . . . 130
- 5.2 Firewall main features . . . . . 130
- 5.3 Firewall functional description . . . . . 131
  - 5.3.1 Firewall AMBA bus snoop . . . . . 131
  - 5.3.2 Functional requirements . . . . . 131
    - Debug consideration. . . . . 131
    - Write protection . . . . . 132
    - Interrupts management . . . . . 132
  - 5.3.3 Firewall segments . . . . . 132
    - Code segment . . . . . 132
    - Non-volatile data segment . . . . . 132
    - Volatile data segment. . . . . 133
  - 5.3.4 Segment accesses and properties . . . . . 133
    - Segment access depending on the Firewall state . . . . . 133

Segments properties . . . . .	134
5.3.5 Firewall initialization . . . . .	134
5.3.6 Firewall states . . . . .	135
Opening the Firewall . . . . .	136
Closing the Firewall . . . . .	136
5.4 Firewall registers . . . . .	137
5.4.1 Code segment start address (FW_CSSA) . . . . .	137
5.4.2 Code segment length (FW_CSL) . . . . .	137
5.4.3 Non-volatile data segment start address (FW_NVDSSA) . . . . .	138
5.4.4 Non-volatile data segment length (FW_NVDDSL) . . . . .	138
5.4.5 Volatile data segment start address (FW_VDSSA) . . . . .	139
5.4.6 Volatile data segment length (FW_VDSL) . . . . .	139
5.4.7 Configuration register (FW_CR) . . . . .	140
5.4.8 Firewall register map . . . . .	141
6 Power control (PWR) . . . . .	142
6.1 Power supplies . . . . .	142
6.1.1 Independent A/D and DAC converter supply and reference voltage . . . . .	143
On packages with V _REF+pin . . . . .	143
On packages without V _REF+pin . . . . .	143
6.1.2 Independent LCD supply . . . . .	144
6.1.3 RTC and RTC backup registers . . . . .	144
RTC registers access . . . . .	144
6.1.4 Voltage regulator . . . . .	145
6.1.5 Dynamic voltage scaling management . . . . .	145
Range 1 . . . . .	145
Range 2 and 3 . . . . .	146
6.1.6 Dynamic voltage scaling configuration . . . . .	147
6.1.7 Voltage regulator and clock management when VDD drops below 1.71 V . . . . .	147
6.1.8 Voltage regulator and clock management when modifying the VCORE range . . . . .	147
6.1.9 Voltage range and limitations when VDD ranges from 1.71 V to 2.0 V . . . . .	148
6.2 Power supply supervisor . . . . .	148
6.2.1 Power-on reset (POR)/power-down reset (PDR) . . . . .	150
6.2.2 Brown out reset (BOR) . . . . .	150
6.2.3 Programmable voltage detector (PVD) . . . . .	151
6.2.4 Internal voltage reference (VREFINT) . . . . .	152

6.3 Low-power modes . . . . . 153
- 6.3.1 Behavior of clocks in low-power modes . . . . . 154
  - Sleep and Low-power sleep modes . . . . . 154
  - Stop and Standby modes . . . . . 154
- 6.3.2 Slowing down system clocks . . . . . 155
- 6.3.3 Peripheral clock gating . . . . . 155
- 6.3.4 Low-power run mode (LP run) . . . . . 155
  - Entering Low-power run mode . . . . . 155
  - Exiting Low-power run mode . . . . . 156
- 6.3.5 Entering low-power mode . . . . . 156
- 6.3.6 Exiting low-power mode . . . . . 156
- 6.3.7 Sleep mode . . . . . 157
  - I/O states in Sleep mode . . . . . 157
  - Entering Sleep mode . . . . . 157
  - Exiting Sleep mode. . . . . 157
- 6.3.8 Low-power sleep mode (LP sleep) . . . . . 158
  - I/O states in Low-power sleep mode . . . . . 158
  - Entering Low-power sleep mode . . . . . 158
  - Exiting Low-power sleep mode. . . . . 159
- 6.3.9 Stop mode . . . . . 160
  - I/O states in Low-power sleep mode . . . . . 160
  - Entering Stop mode . . . . . 160
  - Exiting Stop mode . . . . . 161
- 6.3.10 Standby mode . . . . . 163
  - I/O states in Standby mode . . . . . 163
  - Entering Standby mode . . . . . 163
  - Exiting Standby mode. . . . . 163
  - Debug mode . . . . . 164
- 6.3.11 Waking up the device from Stop and Standby modes using the RTC and comparators . . . . . 164
  - RTC auto-wakeup (AWU) from the Stop mode . . . . . 165
  - RTC auto-wakeup (AWU) from the Standby mode. . . . . 165
  - Comparator auto-wakeup (AWU) from the Stop mode. . . . . 166
6.4 Power control registers . . . . . 167
- 6.4.1 PWR power control register (PWR_CR) . . . . . 167
- 6.4.2 PWR power control/status register (PWR_CSR) . . . . . 170
- 6.4.3 PWR register map . . . . . 172
7 Reset and clock control (RCC) . . . . . 173

7.1	Reset .....	173
7.1.1	System reset .....	173
	Software reset .....	173
	Low-power management reset .....	173
	Option byte loader reset .....	173
7.1.2	Power reset .....	174
7.1.3	RTC and backup registers reset .....	174
7.2	Clocks .....	175
7.2.1	HSE clock .....	178
	External source (HSE bypass) .....	179
	External crystal/ceramic resonator (HSE crystal) .....	179
7.2.2	HSI16 clock .....	179
	Calibration .....	179
7.2.3	MSI clock .....	180
	Calibration .....	180
7.2.4	HSI48 clock .....	180
7.2.5	PLL .....	181
7.2.6	LSE clock .....	182
	External source (LSE bypass) .....	182
7.2.7	LSI clock .....	182
	LSI measurement .....	182
7.2.8	System clock (SYSCLK) selection .....	183
7.2.9	System clock source frequency versus voltage range .....	183
7.2.10	HSE clock security system (CSS) .....	183
7.2.11	LSE Clock Security System .....	184
7.2.12	RTC and LCD clock .....	184
7.2.13	Watchdog clock .....	185
7.2.14	Clock-out capability .....	185
7.2.15	Internal/external clock measurement using TIM21 .....	185
7.2.16	Clock-independent system clock sources for TIM2/TIM21/TIM22 .....	186
7.3	RCC registers .....	187
7.3.1	Clock control register (RCC_CR) .....	187
7.3.2	Internal clock sources calibration register (RCC_ICSCR) .....	190
7.3.3	Clock recovery RC register (RCC_CRRRCR) .....	191
7.3.4	Clock configuration register (RCC_CFGR) .....	192
7.3.5	Clock interrupt enable register (RCC_CIER) .....	194
7.3.6	Clock interrupt flag register (RCC_CIFR) .....	196
7.3.7	Clock interrupt clear register (RCC_CICR) .....	197

7.3.8	GPIO reset register (RCC_IOPRSTR) . . . . .	198
7.3.9	AHB peripheral reset register (RCC_AHBRSTR) . . . . .	199
7.3.10	APB2 peripheral reset register (RCC_APB2RSTR) . . . . .	200
7.3.11	APB1 peripheral reset register (RCC_APB1RSTR) . . . . .	201
7.3.12	GPIO clock enable register (RCC_IOPENR) . . . . .	204
7.3.13	AHB peripheral clock enable register (RCC_AHBENR) . . . . .	205
7.3.14	APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .	207
7.3.15	APB1 peripheral clock enable register (RCC_APB1ENR) . . . . .	209
7.3.16	GPIO clock enable in Sleep mode register (RCC_IOPSMENR) . . . . .	212
7.3.17	AHB peripheral clock enable in Sleep mode register (RCC_AHBSMENR) . . . . .	213
7.3.18	APB2 peripheral clock enable in Sleep mode register (RCC_APB2SMENR) . . . . .	214
7.3.19	APB1 peripheral clock enable in Sleep mode register (RCC_APB1SMENR) . . . . .	215
7.3.20	Clock configuration register (RCC_CCIPR) . . . . .	217
7.3.21	Control/status register (RCC_CSR) . . . . .	219
7.3.22	RCC register map . . . . .	223
8	Clock recovery system (CRS) . . . . .	226
8.1	Introduction . . . . .	226
8.2	CRS main features . . . . .	226
8.3	CRS implementation . . . . .	226
8.4	CRS functional description . . . . .	227
8.4.1	CRS block diagram . . . . .	227
8.4.2	Synchronization input . . . . .	227
8.4.3	Frequency error measurement . . . . .	228
8.4.4	Frequency error evaluation and automatic trimming . . . . .	228
8.4.5	CRS initialization and configuration . . . . .	229
	RELOAD value . . . . .	229
	FELIM value . . . . .	229
8.5	CRS low-power modes . . . . .	230
8.6	CRS interrupts . . . . .	230
8.7	CRS registers . . . . .	231
8.7.1	CRS control register (CRS_CR) . . . . .	231
8.7.2	CRS configuration register (CRS_CFGR) . . . . .	232
8.7.3	CRS interrupt and status register (CRS_ISR) . . . . .	233

8.7.4	CRS interrupt flag clear register (CRS_ICR) . . . . .	235
8.7.5	CRS register map . . . . .	235
9	General-purpose I/Os (GPIO) . . . . .	237
9.1	Introduction . . . . .	237
9.2	GPIO main features . . . . .	237
9.3	GPIO functional description . . . . .	237
9.3.1	General-purpose I/O (GPIO) . . . . .	239
9.3.2	I/O pin alternate function multiplexer and mapping . . . . .	240
9.3.3	I/O port control registers . . . . .	241
9.3.4	I/O port data registers . . . . .	241
9.3.5	I/O data bitwise handling . . . . .	241
9.3.6	GPIO locking mechanism . . . . .	241
9.3.7	I/O alternate function input/output . . . . .	242
9.3.8	External interrupt/wakeup lines . . . . .	242
9.3.9	Input configuration . . . . .	242
9.3.10	Output configuration . . . . .	243
9.3.11	Alternate function configuration . . . . .	244
9.3.12	Analog configuration . . . . .	245
9.3.13	Using the HSE or LSE oscillator pins as GPIOs . . . . .	246
9.3.14	Using the GPIO pins in the RTC supply domain . . . . .	246
9.4	GPIO registers . . . . .	246
9.4.1	GPIO port mode register (GPIOx_MODER) (x = A to E and H) . . . . .	246
9.4.2	GPIO port output type register (GPIOx_OTYPER) (x = A to E and H) . . . . .	247
9.4.3	GPIO port output speed register (GPIOx_OSPEEDR) (x = A to E and H) . . . . .	247
9.4.4	GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to E and H) . . . . .	248
9.4.5	GPIO port input data register (GPIOx_IDR) (x = A to E and H) . . . . .	248
9.4.6	GPIO port output data register (GPIOx_ODR) (x = A to E and H) . . . . .	249
9.4.7	GPIO port bit set/reset register (GPIOx_BSRR) (x = A to E and H) . . . . .	249
9.4.8	GPIO port configuration lock register (GPIOx_LCKR) (x = A to E and H) . . . . .	249

- 9.4.9 GPIO alternate function low register (GPIOx_AFRRL)
  (x = A to E and H) . . . . . 251
- 9.4.10 GPIO alternate function high register (GPIOx_AFRH)
  (x = A to E and H) . . . . . 251
- 9.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to E and H) . . . . . 252
- 9.4.12 GPIO register map . . . . . 252
10 System configuration controller (SYSCFG) . . . . . 254
- 10.1 Introduction . . . . . 254
- 10.2 SYSCFG registers . . . . . 255
  - 10.2.1 SYSCFG memory remap register (SYSCFG_CFGR1) . . . . . 255
  - 10.2.2 SYSCFG peripheral mode configuration register (SYSCFG_CFGR2) 257
  - 10.2.3 Reference control and status register (SYSCFG_CFGR3) . . . . . 258
  - 10.2.4 SYSCFG external interrupt configuration register 1
    (SYSCFG_EXTICR1) . . . . . 260
  - 10.2.5 SYSCFG external interrupt configuration register 2
    (SYSCFG_EXTICR2) . . . . . 261
  - 10.2.6 SYSCFG external interrupt configuration register 3
    (SYSCFG_EXTICR3) . . . . . 261
  - 10.2.7 SYSCFG external interrupt configuration register 4
    (SYSCFG_EXTICR4) . . . . . 262
  - 10.2.8 SYSCFG register map . . . . . 262
11 Direct memory access controller (DMA) . . . . . 264
- 11.1 Introduction . . . . . 264
- 11.2 DMA main features . . . . . 264
- 11.3 DMA implementation . . . . . 265
  - 11.3.1 DMA . . . . . 265
  - 11.3.2 DMA request mapping . . . . . 265
  - DMA controller . . . . . 265
- 11.4 DMA functional description . . . . . 267
  - 11.4.1 DMA block diagram . . . . . 267
  - 11.4.2 DMA transfers . . . . . 268
  - 11.4.3 DMA arbitration . . . . . 269
  - 11.4.4 DMA channels . . . . . 270
    - Programmable data sizes . . . . . 270
    - Pointer incrementation . . . . . 270
    - Channel configuration procedure . . . . . 271
    - Channel state and disabling a channel. . . . . 271

Circular mode (in memory-to-peripheral/peripheral-to-memory transfers) . . . . .	272
Memory-to-memory mode . . . . .	272
Peripheral-to-peripheral mode . . . . .	273
Programming transfer direction, assigning source/destination . . . . .	273
11.4.5 DMA data width, alignment and endianness . . . . .	273
Addressing AHB peripherals not supporting byte/half-word write transfers . . . . .	274
11.4.6 DMA error management . . . . .	275
11.5 DMA interrupts . . . . .	275
11.6 DMA registers . . . . .	275
11.6.1 DMA interrupt status register (DMA_ISR) . . . . .	276
11.6.2 DMA interrupt flag clear register (DMA_IFCR) . . . . .	278
11.6.3 DMA channel x configuration register (DMA_CCRx) . . . . .	279
11.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx) . . . . .	282
11.6.5 DMA channel x peripheral address register (DMA_CPARx) . . . . .	283
11.6.6 DMA channel x memory address register (DMA_CMARx) . . . . .	283
11.6.7 DMA channel selection register (DMA_CSELR) . . . . .	285
11.6.8 DMA register map . . . . .	285
12 Nested vectored interrupt controller (NVIC) . . . . .	288
12.1 Main features . . . . .	288
12.2 SysTick calibration value register . . . . .	288
12.3 Interrupt and exception vectors . . . . .	288
13 Extended interrupt and event controller (EXTI) . . . . .	291
13.1 Introduction . . . . .	291
13.2 EXTI main features . . . . .	291
13.3 EXTI functional description . . . . .	291
13.3.1 EXTI block diagram . . . . .	292
13.3.2 Wakeup event management . . . . .	292
13.3.3 Peripherals asynchronous interrupts . . . . .	293
13.3.4 Hardware interrupt selection . . . . .	293
13.3.5 Hardware event selection . . . . .	293
13.3.6 Software interrupt/event selection . . . . .	293
13.4 EXTI interrupt/event line mapping . . . . .	294
13.5 EXTI registers . . . . .	296
13.5.1 EXTI interrupt mask register (EXTI_IMR) . . . . .	296
13.5.2 EXTI event mask register (EXTI_EMR) . . . . .	296

13.5.3	EXTI rising edge trigger selection register (EXTI_RTSR) . . . . .	297
13.5.4	Falling edge trigger selection register (EXTI_FTSR) . . . . .	298
13.5.5	EXTI software interrupt event register (EXTI_SWIER) . . . . .	298
13.5.6	EXTI pending register (EXTI_PR) . . . . .	299
13.5.7	EXTI register map . . . . .	300
14	Analog-to-digital converter (ADC) . . . . .	301
14.1	Introduction . . . . .	301
14.2	ADC main features . . . . .	302
14.3	ADC functional description . . . . .	303
14.3.1	ADC pins and internal signals . . . . .	303
14.3.2	ADC voltage regulator (ADVREGEN) . . . . .	304
	Analog reference for the ADC internal voltage regulator . . . . .	304
	ADVREG enable sequence . . . . .	305
	ADVREG disable sequence . . . . .	305
14.3.3	Calibration (ADCAL) . . . . .	305
	Calibration factor forcing software procedure . . . . .	307
14.3.4	ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .	307
14.3.5	ADC clock (CKMODE, PRESC[3:0], LFMEN) . . . . .	308
	Low frequency . . . . .	309
14.3.6	ADC connectivity . . . . .	310
14.3.7	Configuring the ADC . . . . .	311
14.3.8	Channel selection (CHSEL, SCANDIR) . . . . .	311
	Temperature sensor, V _REFINTand LCD_VLCD1 internal channels . . . . .	311
14.3.9	Programmable sampling time (SMP) . . . . .	312
14.3.10	Single conversion mode (CONT = 0) . . . . .	312
14.3.11	Continuous conversion mode (CONT = 1) . . . . .	313
14.3.12	Starting conversions (ADSTART) . . . . .	313
14.3.13	Timings . . . . .	314
14.3.14	Stopping an ongoing conversion (ADSTP) . . . . .	315
14.4	Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . . . . .	315
14.4.1	Discontinuous mode (DISCEN) . . . . .	316
14.4.2	Programmable resolution (RES) - Fast conversion mode . . . . .	316
14.4.3	End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . .	317
14.4.4	End of conversion sequence (EOS flag) . . . . .	317
14.4.5	Example timing diagrams (single/continuous modes hardware/software triggers) . . . . .	318
14.5	Data management . . . . .	320

14.5.1	Data register and data alignment (ADC_DR, ALIGN) . . . . .	320
14.5.2	ADC overrun (OVR, OVRMOD) . . . . .	320
14.5.3	Managing a sequence of data converted without using the DMA . . . . .	321
14.5.4	Managing converted data without using the DMA without overrun . . . . .	321
14.5.5	Managing converted data using the DMA . . . . .	321
	DMA one shot mode (DMACFG = 0) . . . . .	322
	DMA circular mode (DMACFG = 1) . . . . .	322
14.6	Low-power features . . . . .	323
14.6.1	Wait mode conversion . . . . .	323
14.6.2	Auto-off mode (AUTOFF) . . . . .	324
14.7	Analog window watchdog (AWDEN, AWDSGL, AWDCH, ADC_TR) . . . . .	325
14.7.1	Description of the analog watchdog . . . . .	325
14.7.2	ADC_AWD1_OUT output signal generation . . . . .	326
14.7.3	Analog watchdog threshold control . . . . .	328
14.8	Oversampler . . . . .	329
14.8.1	ADC operating modes supported when oversampling . . . . .	331
14.8.2	Analog watchdog . . . . .	331
14.8.3	Triggered mode . . . . .	331
14.9	Temperature sensor and internal reference voltage . . . . .	332
	Main features . . . . .	333
	Reading the temperature . . . . .	333
	Calculating the actual V _DDAvoltage using the internal reference voltage . . . . .	334
	Converting a supply-relative ADC measurement to an absolute voltage value . . . . .	334
14.10	VLCD voltage monitoring . . . . .	334
14.11	ADC interrupts . . . . .	335
14.12	ADC registers . . . . .	336
14.12.1	ADC interrupt and status register (ADC_ISR) . . . . .	336
14.12.2	ADC interrupt enable register (ADC_IER) . . . . .	337
14.12.3	ADC control register (ADC_CR) . . . . .	339
14.12.4	ADC configuration register 1 (ADC_CFGR1) . . . . .	341
14.12.5	ADC configuration register 2 (ADC_CFGR2) . . . . .	345
14.12.6	ADC sampling time register (ADC_SMPR) . . . . .	346
14.12.7	ADC watchdog threshold register (ADC_TR) . . . . .	347
14.12.8	ADC channel selection register (ADC_CHSELR) . . . . .	347
14.12.9	ADC data register (ADC_DR) . . . . .	348
14.12.10	ADC Calibration factor (ADC_CALFACT) . . . . .	348

- - 14.12.11 ADC common configuration register (ADC_CCR) . . . . . 349
- 14.13 ADC register map . . . . . 350
15 Digital-to-analog converter (DAC) . . . . . 352
- 15.1 Introduction . . . . . 352
- 15.2 DAC1 main features . . . . . 352
- 15.3 DAC output buffer enable . . . . . 354
- 15.4 DAC channel enable . . . . . 354
- 15.5 Single mode functional description . . . . . 354
  - 15.5.1 DAC data format . . . . . 354
  - 15.5.2 DAC channel conversion . . . . . 354
    - Independent trigger with single LFSR generation . . . . . 355
    - Independent trigger with single triangle generation . . . . . 355
  - 15.5.3 DAC output voltage . . . . . 356
  - 15.5.4 DAC trigger selection . . . . . 356
- 15.6 Dual-mode functional description . . . . . 357
  - 15.6.1 DAC data format . . . . . 357
  - 15.6.2 DAC channel conversion in dual mode . . . . . 357
  - 15.6.3 Description of dual conversion modes . . . . . 357
    - Independent trigger without wave generation. . . . . 358
    - Independent trigger with single LFSR generation . . . . . 358
    - Independent trigger with different LFSR generation. . . . . 358
    - Independent trigger with single triangle generation . . . . . 359
    - Independent trigger with different triangle generation . . . . . 359
    - Simultaneous software start . . . . . 359
    - Simultaneous trigger without wave generation. . . . . 359
    - Simultaneous trigger with single LFSR generation. . . . . 360
    - Simultaneous trigger with different LFSR generation . . . . . 360
    - Simultaneous trigger with single triangle generation . . . . . 360
    - Simultaneous trigger with different triangle generation . . . . . 361
  - 15.6.4 DAC output voltage . . . . . 361
  - 15.6.5 DAC trigger selection . . . . . 361
- 15.7 Noise generation . . . . . 361
- 15.8 Triangle-wave generation . . . . . 362
- 15.9 DMA request . . . . . 363
  - DMA underrun . . . . . 363
- 15.10 DAC registers . . . . . 364

15.10.1	DAC control register (DAC_CR) . . . . .	364
15.10.2	DAC software trigger register (DAC_SWTRIGR) . . . . .	368
15.10.3	DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . .	368
15.10.4	DAC channel1 12-bit left-aligned data holding register (DAC_DHR12L1) . . . . .	369
15.10.5	DAC channel1 8-bit right-aligned data holding register (DAC_DHR8R1) . . . . .	369
15.10.6	DAC channel2 12-bit right-aligned data holding register (DAC_DHR12R2) . . . . .	369
15.10.7	DAC channel2 12-bit left-aligned data holding register (DAC_DHR12L2) . . . . .	370
15.10.8	DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . .	370
15.10.9	Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . .	371
15.10.10	Dual DAC 12-bit left-aligned data holding register (DAC_DHR12LD) . . . . .	371
15.10.11	Dual DAC 8-bit right-aligned data holding register (DAC_DHR8RD) . . . . .	371
15.10.12	DAC channel1 data output register (DAC_DOR1) . . . . .	372
15.10.13	DAC channel2 data output register (DAC_DOR2) . . . . .	372
15.10.14	DAC status register (DAC_SR) . . . . .	372
15.10.15	DAC register map . . . . .	374
16	Comparator (COMP) . . . . .	376
16.1	Introduction . . . . .	376
16.2	COMP main features . . . . .	376
16.3	COMP functional description . . . . .	377
16.3.1	COMP block diagram . . . . .	377
16.3.2	COMP pins and internal signals . . . . .	377
16.3.3	COMP reset and clocks . . . . .	378
16.3.4	Comparator LOCK mechanism . . . . .	378
16.3.5	Power mode . . . . .	378
16.4	COMP interrupts . . . . .	378
16.5	COMP registers . . . . .	378
16.5.1	Comparator 1 control and status register (COMP1_CSR) . . . . .	378
16.5.2	Comparator 2 control and status register (COMP2_CSR) . . . . .	380
16.5.3	COMP register map . . . . .	382

17	Liquid crystal display controller (LCD) . . . . .	383
17.1	Introduction . . . . .	383
	Glossary . . . . .	383
17.2	LCD main features . . . . .	384
17.3	LCD implementation . . . . .	385
17.4	LCD functional description . . . . .	385
17.4.1	General description . . . . .	385
17.4.2	Frequency generator . . . . .	386
17.4.3	Common driver . . . . .	387
	COM signal bias . . . . .	387
	COM signal duty . . . . .	388
	8 to 1 Mux. . . . .	390
17.4.4	Segment driver . . . . .	390
	In the case of 1/4 or 1/8 duty . . . . .	390
	Blink . . . . .	394
17.4.5	Voltage generator and contrast control . . . . .	394
	LCD supply source . . . . .	394
	LCD intermediate voltages . . . . .	395
	LCD drive selection . . . . .	395
	External decoupling . . . . .	397
	Deadtime . . . . .	397
17.4.6	Double buffer memory . . . . .	398
17.4.7	COM and SEG multiplexing . . . . .	398
	Output pins versus duty modes . . . . .	398
	Remapping capability for small packages . . . . .	398
	Summary of COM and SEG functions versus duty and remap . . . . .	399
17.4.8	Flowchart . . . . .	403
17.5	LCD low-power modes . . . . .	404
17.6	LCD interrupts . . . . .	404
	Start of frame (SOF) . . . . .	404
	Update display done (UDD) . . . . .	404
17.7	LCD registers . . . . .	405
17.7.1	LCD control register (LCD_CR) . . . . .	405
17.7.2	LCD frame control register (LCD_FCR) . . . . .	406
17.7.3	LCD status register (LCD_SR) . . . . .	408
17.7.4	LCD clear register (LCD_CLR) . . . . .	409
17.7.5	LCD display memory (LCD_RAM) . . . . .	410
17.7.6	LCD register map . . . . .	411

18	Touch sensing controller (TSC) . . . . .	413
18.1	Introduction . . . . .	413
18.2	TSC main features . . . . .	413
18.3	TSC functional description . . . . .	414
18.3.1	TSC block diagram . . . . .	414
18.3.2	Surface charge transfer acquisition overview . . . . .	414
18.3.3	Reset and clocks . . . . .	416
18.3.4	Charge transfer acquisition sequence . . . . .	417
18.3.5	Spread spectrum feature . . . . .	418
18.3.6	Max count error . . . . .	418
18.3.7	Sampling capacitor I/O and channel I/O mode selection . . . . .	419
18.3.8	Acquisition mode . . . . .	420
18.3.9	I/O hysteresis and analog switch control . . . . .	420
18.4	TSC low-power modes . . . . .	421
18.5	TSC interrupts . . . . .	421
18.6	TSC registers . . . . .	422
18.6.1	TSC control register (TSC_CR) . . . . .	422
18.6.2	TSC interrupt enable register (TSC_IER) . . . . .	424
18.6.3	TSC interrupt clear register (TSC_ICR) . . . . .	425
18.6.4	TSC interrupt status register (TSC_ISR) . . . . .	426
18.6.5	TSC I/O hysteresis control register (TSC_IOHCR) . . . . .	426
18.6.6	TSC I/O analog switch control register (TSC_IOASCR) . . . . .	427
18.6.7	TSC I/O sampling control register (TSC_IOSCR) . . . . .	427
18.6.8	TSC I/O channel control register (TSC_IOCCR) . . . . .	428
18.6.9	TSC I/O group control status register (TSC_IOGCSR) . . . . .	428
18.6.10	TSC I/O group x counter register (TSC_IOGxCR) . . . . .	429
18.6.11	TSC register map . . . . .	430
19	AES hardware accelerator (AES) . . . . .	432
19.1	Introduction . . . . .	432
19.2	AES main features . . . . .	432
19.3	AES implementation . . . . .	433
19.4	AES functional description . . . . .	433
19.4.1	AES block diagram . . . . .	433
19.4.2	AES internal signals . . . . .	433

19.4.3 AES cryptographic core . . . . . 434
- Overview. . . . . 434
- Typical data processing . . . . . 434
- Chaining modes . . . . . 434
- Electronic codebook (ECB) mode . . . . . 435
- Cipher block chaining (CBC) mode . . . . . 436
- Counter (CTR) mode . . . . . 437
19.4.4 AES procedure to perform a cipher operation . . . . . 437
- Introduction. . . . . 437
- Initialization of AES. . . . . 438
- Data append . . . . . 438
19.4.5 AES decryption key preparation . . . . . 440
19.4.6 AES ciphertext stealing and data padding . . . . . 441
19.4.7 AES task suspend and resume . . . . . 441
19.4.8 AES basic chaining modes (ECB, CBC) . . . . . 442
- Overview. . . . . 442
- ECB/CBC encryption sequence . . . . . 445
- ECB/CBC decryption sequence . . . . . 445
- Suspend/resume operations in ECB/CBC modes . . . . . 446
- Alternative single ECB/CBC decryption using Mode 4 . . . . . 447
19.4.9 AES counter (CTR) mode . . . . . 447
- Overview. . . . . 447
- CTR encryption and decryption . . . . . 448
- Suspend/resume operations in CTR mode . . . . . 450
19.4.10 AES data registers and data swapping . . . . . 450
- Data input and output . . . . . 450
- Data swapping . . . . . 450
- Data padding . . . . . 452
19.4.11 AES key registers . . . . . 452
19.4.12 AES initialization vector registers . . . . . 452
19.4.13 AES DMA interface . . . . . 452
- Data input using DMA. . . . . 453
- Data output using DMA . . . . . 453
- DMA operation in different operating modes . . . . . 454
19.4.14 AES error management . . . . . 455
- Read error flag (RDERR) . . . . . 455
- Write error flag (WDERR). . . . . 455
19.5 AES interrupts . . . . . 455
19.6 AES processing latency . . . . . 456
19.7 AES registers . . . . . 457

19.7.1	AES control register (AES_CR) . . . . .	457
19.7.2	AES status register (AES_SR) . . . . .	459
19.7.3	AES data input register (AES_DINR) . . . . .	460
19.7.4	AES data output register (AES_DOUTR) . . . . .	460
19.7.5	AES key register 0 (AES_KEYR0) . . . . .	461
19.7.6	AES key register 1 (AES_KEYR1) . . . . .	462
19.7.7	AES key register 2 (AES_KEYR2) . . . . .	462
19.7.8	AES key register 3 (AES_KEYR3) . . . . .	462
19.7.9	AES initialization vector register 0 (AES_IVR0) . . . . .	463
19.7.10	AES initialization vector register 1 (AES_IVR1) . . . . .	463
19.7.11	AES initialization vector register 2 (AES_IVR2) . . . . .	464
19.7.12	AES initialization vector register 3 (AES_IVR3) . . . . .	464
19.7.13	AES register map . . . . .	464
20	True random number generator (RNG) . . . . .	466
20.1	Introduction . . . . .	466
20.2	RNG main features . . . . .	466
20.3	RNG functional description . . . . .	467
20.3.1	RNG block diagram . . . . .	467
20.3.2	RNG internal signals . . . . .	467
20.3.3	Random number generation . . . . .	468
	Noise source . . . . .	469
	Post processing . . . . .	469
	Output buffer . . . . .	469
	Health checks . . . . .	470
20.3.4	RNG initialization . . . . .	470
20.3.5	RNG operation . . . . .	470
	Normal operations . . . . .	470
	Low-power operations . . . . .	471
	Software post-processing . . . . .	471
20.3.6	RNG clocking . . . . .	471
20.3.7	Error management . . . . .	471
	Clock error detection . . . . .	471
	Noise source error detection . . . . .	472
20.3.8	RNG low-power usage . . . . .	472
20.4	RNG interrupts . . . . .	472
20.5	RNG processing time . . . . .	472

20.6	RNG entropy source validation . . . . .	473
20.6.1	Introduction . . . . .	473
20.6.2	Validation conditions . . . . .	473
20.6.3	Data collection . . . . .	473
20.7	RNG registers . . . . .	473
20.7.1	RNG control register (RNG_CR) . . . . .	473
20.7.2	RNG status register (RNG_SR) . . . . .	475
20.7.3	RNG data register (RNG_DR) . . . . .	476
20.7.4	RNG register map . . . . .	476
21	General-purpose timers (TIM2/TIM3) . . . . .	477
21.1	TIM2/TIM3 introduction . . . . .	477
21.2	TIM2/TIM3 main features . . . . .	477
21.3	TIM2/TIM3 functional description . . . . .	479
21.3.1	Time-base unit . . . . .	479
	Prescaler description . . . . .	479
21.3.2	Counter modes . . . . .	481
	Upcounting mode . . . . .	481
	Downcounting mode . . . . .	484
	Center-aligned mode (up/down counting) . . . . .	487
21.3.3	Clock selection . . . . .	491
	Internal clock source (CK_INT) . . . . .	491
	External clock source mode 1 . . . . .	492
	External clock source mode 2 . . . . .	494
21.3.4	Capture/compare channels . . . . .	495
21.3.5	Input capture mode . . . . .	497
21.3.6	PWM input mode . . . . .	499
21.3.7	Forced output mode . . . . .	500
21.3.8	Output compare mode . . . . .	500
21.3.9	PWM mode . . . . .	501
	PWM edge-aligned mode . . . . .	502
	Downcounting configuration . . . . .	503
	PWM center-aligned mode . . . . .	503
21.3.10	One-pulse mode . . . . .	505
	Particular case: OCx fast enable: . . . . .	506
21.3.11	Clearing the OCxREF signal on an external event . . . . .	506
21.3.12	Encoder interface mode . . . . .	507
21.3.13	Timer input XOR function . . . . .	509

21.3.14	Timers and external trigger synchronization . . . . .	510
	Slave mode: Reset mode . . . . .	510
	Slave mode: Gated mode . . . . .	511
	Slave mode: Trigger mode . . . . .	512
	Slave mode: External Clock mode 2 + trigger mode . . . . .	513
21.3.15	Timer synchronization . . . . .	514
	Using one timer as prescaler for another timer . . . . .	514
	Using one timer to enable another timer . . . . .	515
	Using one timer to start another timer . . . . .	517
	Starting 2 timers synchronously in response to an external trigger . . . . .	519
21.3.16	Debug mode . . . . .	520
21.4	TIM2/TIM3 registers . . . . .	521
21.4.1	TIMx control register 1 (TIMx_CR1) . . . . .	521
21.4.2	TIMx control register 2 (TIMx_CR2) . . . . .	523
21.4.3	TIMx slave mode control register (TIMx_SMCR) . . . . .	524
21.4.4	TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . .	526
21.4.5	TIMx status register (TIMx_SR) . . . . .	527
21.4.6	TIMx event generation register (TIMx_EGR) . . . . .	529
21.4.7	TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . .	530
	Output compare mode . . . . .	530
	Input capture mode. . . . .	531
21.4.8	TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . .	533
	Output compare mode . . . . .	533
	Input capture mode. . . . .	534
21.4.9	TIMx capture/compare enable register (TIMx_CCER) . . . . .	534
21.4.10	TIMx counter (TIMx_CNT) . . . . .	536
21.4.11	TIMx prescaler (TIMx_PSC) . . . . .	536
21.4.12	TIMx auto-reload register (TIMx_ARR) . . . . .	536
21.4.13	TIMx capture/compare register 1 (TIMx_CCR1) . . . . .	537
21.4.14	TIMx capture/compare register 2 (TIMx_CCR2) . . . . .	537
21.4.15	TIMx capture/compare register 3 (TIMx_CCR3) . . . . .	538
21.4.16	TIMx capture/compare register 4 (TIMx_CCR4) . . . . .	538
21.4.17	TIMx DMA control register (TIMx_DCR) . . . . .	539
21.4.18	TIMx DMA address for full transfer (TIMx_DMAR) . . . . .	539
	Example of how to use the DMA burst feature . . . . .	540
21.4.19	TIM2 option register (TIM2_OR) . . . . .	541
21.4.20	TIM3 option register (TIM3_OR) . . . . .	542
21.5	TIMx register map . . . . .	543

22	General-purpose timers (TIM21/22) . . . . .	545
22.1	Introduction . . . . .	545
22.2	TIM21/22 main features . . . . .	545
22.2.1	TIM21/22 main features . . . . .	545
22.3	TIM21/22 functional description . . . . .	547
22.3.1	Timebase unit . . . . .	547
	Prescaler description . . . . .	547
22.3.2	Counter modes . . . . .	549
	Upcounting mode . . . . .	549
	Downcounting mode . . . . .	553
	Center-aligned mode (up/down counting) . . . . .	556
22.3.3	Clock selection . . . . .	560
	Internal clock source (CK_INT) . . . . .	560
	External clock source mode 2 . . . . .	562
22.3.4	Capture/compare channels . . . . .	563
22.3.5	Input capture mode . . . . .	565
22.3.6	PWM input mode . . . . .	567
22.3.7	Forced output mode . . . . .	568
22.3.8	Output compare mode . . . . .	568
22.3.9	PWM mode . . . . .	569
	PWM center-aligned mode . . . . .	571
	Hints on using center-aligned mode . . . . .	572
22.3.10	Clearing the OCxREF signal on an external event . . . . .	572
22.3.11	One-pulse mode . . . . .	573
	Particular case: OCx fast enable . . . . .	575
22.3.12	Encoder interface mode . . . . .	575
22.3.13	TIM21/22 external trigger synchronization . . . . .	577
	Slave mode: Reset mode . . . . .	577
	Slave mode: Gated mode . . . . .	578
	Slave mode: Trigger mode . . . . .	579
22.3.14	Timer synchronization (TIM21/22) . . . . .	580
22.3.15	Debug mode . . . . .	580
22.4	TIM21/22 registers . . . . .	581
22.4.1	TIM21/22 control register 1 (TIMx_CR1) . . . . .	581
22.4.2	TIM21/22 control register 2 (TIMx_CR2) . . . . .	583
22.4.3	TIM21/22 slave mode control register (TIMx_SMCR) . . . . .	584
22.4.4	TIM21/22 Interrupt enable register (TIMx_DIER) . . . . .	587
22.4.5	TIM21/22 status register (TIMx_SR) . . . . .	587

22.4.6	TIM21/22 event generation register (TIMx_EGR) . . . . .	589
22.4.7	TIM21/22 capture/compare mode register 1 (TIMx_CCMR1) . . . . .	590
	Output compare mode . . . . .	590
	Input capture mode. . . . .	592
22.4.8	TIM21/22 capture/compare enable register (TIMx_CCER) . . . . .	593
22.4.9	TIM21/22 counter (TIMx_CNT) . . . . .	594
22.4.10	TIM21/22 prescaler (TIMx_PSC) . . . . .	594
22.4.11	TIM21/22 auto-reload register (TIMx_ARR) . . . . .	594
22.4.12	TIM21/22 capture/compare register 1 (TIMx_CCR1) . . . . .	595
22.4.13	TIM21/22 capture/compare register 2 (TIMx_CCR2) . . . . .	595
22.4.14	TIM21 option register (TIM21_OR) . . . . .	596
22.4.15	TIM22 option register (TIM22_OR) . . . . .	597
22.4.16	TIM21/22 register map . . . . .	598
23	Basic timers (TIM6/7) . . . . .	600
23.1	Introduction . . . . .	600
23.2	TIM6/7 main features . . . . .	600
23.3	TIM6/7 functional description . . . . .	601
23.3.1	Time-base unit . . . . .	601
	Prescaler description . . . . .	601
23.3.2	Counting mode . . . . .	603
23.3.3	Clock source . . . . .	606
23.3.4	Debug mode . . . . .	607
23.4	TIM6/7 registers . . . . .	608
23.4.1	TIM6/7 control register 1 (TIMx_CR1) . . . . .	608
23.4.2	TIM6/7 control register 2 (TIMx_CR2) . . . . .	609
23.4.3	TIM6/7 DMA/Interrupt enable register (TIMx_DIER) . . . . .	609
23.4.4	TIM6/7 status register (TIMx_SR) . . . . .	610
23.4.5	TIM6/7 event generation register (TIMx_EGR) . . . . .	610
23.4.6	TIM6/7 counter (TIMx_CNT) . . . . .	610
23.4.7	TIM6/7 prescaler (TIMx_PSC) . . . . .	611
23.4.8	TIM6/7 auto-reload register (TIMx_ARR) . . . . .	611
23.4.9	TIM6/7 register map . . . . .	612
24	Low-power timer (LPTIM) . . . . .	613
24.1	Introduction . . . . .	613
24.2	LPTIM main features . . . . .	613

24.3 LPTIM implementation . . . . . 614
24.4 LPTIM functional description . . . . . 614
- 24.4.1 LPTIM block diagram . . . . . 614
- 24.4.2 LPTIM trigger mapping . . . . . 615
- 24.4.3 LPTIM reset and clocks . . . . . 615
- 24.4.4 Glitch filter . . . . . 615
- 24.4.5 Prescaler . . . . . 616
- 24.4.6 Trigger multiplexer . . . . . 617
- 24.4.7 Operating mode . . . . . 617
  - One-shot mode . . . . . 617
  - Continous mode . . . . . 618
- 24.4.8 Timeout function . . . . . 619
- 24.4.9 Waveform generation . . . . . 619
- 24.4.10 Register update . . . . . 620
- 24.4.11 Counter mode . . . . . 621
- 24.4.12 Timer enable . . . . . 622
- 24.4.13 Encoder mode . . . . . 622
- 24.4.14 Debug mode . . . . . 623
24.5 LPTIM low-power modes . . . . . 623
24.6 LPTIM interrupts . . . . . 624
24.7 LPTIM registers . . . . . 624
- 24.7.1 LPTIM interrupt and status register (LPTIM_ISR) . . . . . 625
- 24.7.2 LPTIM interrupt clear register (LPTIM_ICR) . . . . . 626
- 24.7.3 LPTIM interrupt enable register (LPTIM_IER) . . . . . 626
- 24.7.4 LPTIM configuration register (LPTIM_CFGR) . . . . . 627
- 24.7.5 LPTIM control register (LPTIM_CR) . . . . . 630
- 24.7.6 LPTIM compare register (LPTIM_CMP) . . . . . 631
- 24.7.7 LPTIM autoreload register (LPTIM_ARR) . . . . . 632
- 24.7.8 LPTIM counter register (LPTIM_CNT) . . . . . 632
- 24.7.9 LPTIM register map . . . . . 633

25 Independent watchdog (IWDG) . . . . . 634
- 25.1 Introduction . . . . . 634
- 25.2 IWDG main features . . . . . 634
- 25.3 IWDG functional description . . . . . 634
  - 25.3.1 IWDG block diagram . . . . . 634

25.3.2	Window option . . . . .	635
	Configuring the IWDG when the window option is enabled . . . . .	635
	Configuring the IWDG when the window option is disabled . . . . .	635
25.3.3	Hardware watchdog . . . . .	636
25.3.4	Register access protection . . . . .	636
25.3.5	Debug mode . . . . .	636
25.4	IWDG registers . . . . .	637
25.4.1	IWDG key register (IWDG_KR) . . . . .	637
25.4.2	IWDG prescaler register (IWDG_PR) . . . . .	638
25.4.3	IWDG reload register (IWDG_RLR) . . . . .	639
25.4.4	IWDG status register (IWDG_SR) . . . . .	640
25.4.5	IWDG window register (IWDG_WINR) . . . . .	641
25.4.6	IWDG register map . . . . .	642
26	System window watchdog (WWDG) . . . . .	643
26.1	Introduction . . . . .	643
26.2	WWDG main features . . . . .	643
26.3	WWDG functional description . . . . .	643
26.3.1	WWDG block diagram . . . . .	644
26.3.2	Enabling the watchdog . . . . .	644
26.3.3	Controlling the down-counter . . . . .	644
26.3.4	How to program the watchdog timeout . . . . .	644
26.3.5	Debug mode . . . . .	646
26.4	WWDG interrupts . . . . .	646
26.5	WWDG registers . . . . .	646
26.5.1	WWDG control register (WWDG_CR) . . . . .	646
26.5.2	WWDG configuration register (WWDG_CFR) . . . . .	647
26.5.3	WWDG status register (WWDG_SR) . . . . .	647
26.5.4	WWDG register map . . . . .	648
27	Real-time clock (RTC) . . . . .	649
27.1	Introduction . . . . .	649
27.2	RTC main features . . . . .	650
27.3	RTC implementation . . . . .	650
27.4	RTC functional description . . . . .	651
27.4.1	RTC block diagram . . . . .	651

27.4.2	GPIOs controlled by the RTC . . . . .	652
27.4.3	Clock and prescalers . . . . .	653
27.4.4	Real-time clock and calendar . . . . .	654
27.4.5	Programmable alarms . . . . .	655
27.4.6	Periodic auto-wakeup . . . . .	655
27.4.7	RTC initialization and configuration . . . . .	656
	RTC register access . . . . .	656
	RTC register write protection . . . . .	656
	Calendar initialization and configuration . . . . .	656
	Daylight saving time . . . . .	657
	Programming the alarm . . . . .	657
	Programming the wakeup timer . . . . .	657
27.4.8	Reading the calendar . . . . .	657
	When BYPSHAD control bit is cleared in the RTC_CR register. . . . .	657
	When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow registers) . . . . .	658
27.4.9	Resetting the RTC . . . . .	658
27.4.10	RTC synchronization . . . . .	659
27.4.11	RTC reference clock detection . . . . .	659
27.4.12	RTC smooth digital calibration . . . . .	660
	Calibration when PREDIV_A<3 . . . . .	661
	Verifying the RTC calibration . . . . .	661
	Re-calibration on-the-fly . . . . .	662
27.4.13	Time-stamp function . . . . .	662
27.4.14	Tamper detection . . . . .	663
	RTC backup registers . . . . .	663
	Tamper detection initialization . . . . .	663
	Trigger output generation on tamper event . . . . .	664
	Timestamp on tamper event . . . . .	664
	Edge detection on tamper inputs . . . . .	664
	Level detection with filtering on RTC_TAMPx inputs . . . . .	664
27.4.15	Calibration clock output . . . . .	665
27.4.16	Alarm output . . . . .	665
	Alarm output . . . . .	665
27.5	RTC low-power modes . . . . .	666
27.6	RTC interrupts . . . . .	666
27.7	RTC registers . . . . .	667
27.7.1	RTC time register (RTC_TR) . . . . .	667
27.7.2	RTC date register (RTC_DR) . . . . .	668

27.7.3	RTC control register (RTC_CR) . . . . .	669
27.7.4	RTC initialization and status register (RTC_ISR) . . . . .	672
27.7.5	RTC prescaler register (RTC_PRER) . . . . .	675
27.7.6	RTC wakeup timer register (RTC_WUTR) . . . . .	676
27.7.7	RTC alarm A register (RTC_ALRMAR) . . . . .	677
27.7.8	RTC alarm B register (RTC_ALRMBR) . . . . .	678
27.7.9	RTC write protection register (RTC_WPR) . . . . .	679
27.7.10	RTC sub second register (RTC_SSR) . . . . .	679
27.7.11	RTC shift control register (RTC_SHIFTR) . . . . .	680
27.7.12	RTC timestamp time register (RTC_TSTR) . . . . .	681
27.7.13	RTC timestamp date register (RTC_TSDR) . . . . .	682
27.7.14	RTC time-stamp sub second register (RTC_TSSSR) . . . . .	683
27.7.15	RTC calibration register (RTC_CALR) . . . . .	684
27.7.16	RTC tamper configuration register (RTC_TAMPCR) . . . . .	685
27.7.17	RTC alarm A sub second register (RTC_ALRMASSR) . . . . .	688
27.7.18	RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .	689
27.7.19	RTC option register (RTC_OR) . . . . .	690
27.7.20	RTC backup registers (RTC_BKPxR) . . . . .	690
27.7.21	RTC register map . . . . .	691
28	Inter-integrated circuit (I2C) interface . . . . .	693
28.1	Introduction . . . . .	693
28.2	I2C main features . . . . .	693
28.3	I2C implementation . . . . .	694
28.4	I2C functional description . . . . .	694
28.4.1	I2C1/3 block diagram . . . . .	695
28.4.2	I2C2 block diagram . . . . .	696
28.4.3	I2C pins and internal signals . . . . .	697
28.4.4	I2C clock requirements . . . . .	697
28.4.5	Mode selection . . . . .	697
	Communication flow . . . . .	698
28.4.6	I2C initialization . . . . .	698
	Enabling and disabling the peripheral . . . . .	698
	Noise filters . . . . .	698
	I2C timings . . . . .	700
28.4.7	Software reset . . . . .	703
28.4.8	Data transfer . . . . .	704

Reception . . . . . 704
Transmission . . . . . 705
Hardware transfer management. . . . . 705
28.4.9 I2C slave mode . . . . . 706
- I2C slave initialization . . . . . 706
- Slave clock stretching (NOSTRETCH = 0). . . . . 707
- Slave without clock stretching (NOSTRETCH = 1). . . . . 707
- Slave byte control mode. . . . . 708
- Slave transmitter. . . . . 709
- Slave receiver. . . . . 713
28.4.10 I2C master mode . . . . . 715
- I2C master initialization . . . . . 715
- Master communication initialization (address phase). . . . . 717
- Initialization of a master receiver addressing a 10-bit address slave . . . . . 718
- Master transmitter. . . . . 719
- Master receiver. . . . . 723
28.4.11 I2C_TIMINGR register configuration examples . . . . . 727
28.4.12 SMBus specific features . . . . . 728
- Introduction. . . . . 728
- Bus protocols . . . . . 728
- Address resolution protocol (ARP). . . . . 728
- Received command and data acknowledge control. . . . . 729
- Host notify protocol. . . . . 729
- SMBus alert . . . . . 729
- Packet error checking. . . . . 729
- Timeouts. . . . . 729
- Bus idle detection. . . . . 731
28.4.13 SMBus initialization . . . . . 731
- Received command and data acknowledge control (Slave mode). . . . . 731
- Specific address (Slave mode). . . . . 731
- Packet error checking. . . . . 731
- Timeout detection. . . . . 732
- Bus idle detection. . . . . 732
28.4.14 SMBus: I2C_TIMEOUTR register configuration examples . . . . . 733
28.4.15 SMBus slave mode . . . . . 733
- SMBus slave transmitter. . . . . 733
- SMBus Slave receiver . . . . . 735
- SMBus master transmitter . . . . . 737
- SMBus master receiver . . . . . 739
28.4.16 Wakeup from Stop mode on address match . . . . . 741
28.4.17 Error conditions . . . . . 741

Bus error (BERR) . . . . .	741
Arbitration lost (ARLO) . . . . .	742
Overrun/underrun error (OVR) . . . . .	742
Packet error checking error (PECERR) . . . . .	742
Timeout Error (TIMEOUT) . . . . .	742
Alert (ALERT) . . . . .	743
28.4.18 DMA requests . . . . .	743
Transmission using DMA . . . . .	743
Reception using DMA . . . . .	744
28.4.19 Debug mode . . . . .	744
28.5 I2C low-power modes . . . . .	744
28.6 I2C interrupts . . . . .	745
28.7 I2C registers . . . . .	746
28.7.1 I2C control register 1 (I2C_CR1) . . . . .	746
28.7.2 I2C control register 2 (I2C_CR2) . . . . .	749
28.7.3 I2C own address 1 register (I2C_OAR1) . . . . .	751
28.7.4 I2C own address 2 register (I2C_OAR2) . . . . .	752
28.7.5 I2C timing register (I2C_TIMINGR) . . . . .	753
28.7.6 I2C timeout register (I2C_TIMEOUTR) . . . . .	754
28.7.7 I2C interrupt and status register (I2C_ISR) . . . . .	755
28.7.8 I2C interrupt clear register (I2C_ICR) . . . . .	757
28.7.9 I2C PEC register (I2C_PECR) . . . . .	758
28.7.10 I2C receive data register (I2C_RXDR) . . . . .	759
28.7.11 I2C transmit data register (I2C_TXDR) . . . . .	759
28.7.12 I2C register map . . . . .	760
29 Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .	762
29.1 Introduction . . . . .	762
29.2 USART main features . . . . .	762
29.3 USART extended features . . . . .	763
29.4 USART implementation . . . . .	764
29.5 USART functional description . . . . .	764
29.5.1 USART character description . . . . .	767
29.5.2 USART transmitter . . . . .	769
Character transmission . . . . .	769
Single byte communication . . . . .	770
Break characters . . . . .	771

Idle characters . . . . .	771
29.5.3 USART receiver . . . . .	772
Start bit detection . . . . .	772
Character reception . . . . .	773
Break character . . . . .	773
Idle character . . . . .	773
Overrun error . . . . .	774
Selecting the proper oversampling method . . . . .	774
Framing error . . . . .	776
Configurable stop bits during reception . . . . .	777
29.5.4 USART baud rate generation . . . . .	777
How to derive USARTDIV from USART_BRR register values . . . . .	778
29.5.5 Tolerance of the USART receiver to clock deviation . . . . .	779
29.5.6 USART auto baud rate detection . . . . .	781
29.5.7 Multiprocessor communication using USART . . . . .	782
Idle line detection (WAKE=0) . . . . .	783
4-bit/7-bit address mark detection (WAKE=1) . . . . .	783
29.5.8 Modbus communication using USART . . . . .	784
Modbus/RTU . . . . .	784
Modbus/ASCII . . . . .	784
29.5.9 USART parity control . . . . .	785
Even parity . . . . .	785
Odd parity . . . . .	785
Parity checking in reception . . . . .	785
Parity generation in transmission . . . . .	785
29.5.10 USART LIN (local interconnection network) mode . . . . .	786
LIN transmission . . . . .	786
LIN reception . . . . .	786
29.5.11 USART synchronous mode . . . . .	788
29.5.12 USART Single-wire Half-duplex communication . . . . .	791
29.5.13 USART Smartcard mode . . . . .	791
Block mode (T=1) . . . . .	794
Direct and inverse convention . . . . .	795
29.5.14 USART IrDA SIR ENDEC block . . . . .	796
IrDA low-power mode . . . . .	797
29.5.15 USART continuous communication in DMA mode . . . . .	798
Transmission using DMA . . . . .	798
Reception using DMA . . . . .	799
Error flagging and interrupt generation in multibuffer communication . . . . .	800

29.5.16	RS232 hardware flow control and RS485 driver enable using USART . . . . .	800
	RS232 RTS flow control . . . . .	801
	RS232 CTS flow control . . . . .	801
	RS485 Driver Enable . . . . .	802
29.5.17	Wakeup from Stop mode using USART . . . . .	802
	Using Mute mode with Stop mode . . . . .	803
	Determining the maximum USART baud rate allowing to wakeup correctly from Stop mode when the USART clock source is the HSI clock. . . . .	803
29.6	USART in low-power modes . . . . .	804
29.7	USART interrupts . . . . .	804
29.8	USART registers . . . . .	806
29.8.1	USART control register 1 (USART_CR1) . . . . .	806
29.8.2	USART control register 2 (USART_CR2) . . . . .	809
29.8.3	USART control register 3 (USART_CR3) . . . . .	813
29.8.4	USART baud rate register (USART_BRR) . . . . .	817
29.8.5	USART guard time and prescaler register (USART_GTPR) . . . . .	817
29.8.6	USART receiver timeout register (USART_RTOR) . . . . .	818
29.8.7	USART request register (USART_RQR) . . . . .	819
29.8.8	USART interrupt and status register (USART_ISR) . . . . .	820
29.8.9	USART interrupt flag clear register (USART_ICR) . . . . .	825
29.8.10	USART receive data register (USART_RDR) . . . . .	826
29.8.11	USART transmit data register (USART_TDR) . . . . .	826
29.8.12	USART register map . . . . .	827
30	Low-power universal asynchronous receiver transmitter (LPUART) . . . . .	829
30.1	Introduction . . . . .	829
30.2	LPUART main features . . . . .	830
30.3	LPUART implementation . . . . .	830
30.4	LPUART functional description . . . . .	831
30.4.1	LPUART character description . . . . .	833
30.4.2	LPUART transmitter . . . . .	835
	Character transmission. . . . .	835
	Single byte communication. . . . .	836
	Break characters . . . . .	837
	Idle characters . . . . .	837
30.4.3	LPUART receiver . . . . .	837

Start bit detection . . . . .	837
Character reception . . . . .	838
Break character . . . . .	838
Idle character . . . . .	838
Overrun error . . . . .	839
Selecting the clock source . . . . .	839
Framing error . . . . .	840
Configurable stop bits during reception . . . . .	840
30.4.4 LPUART baud rate generation . . . . .	840
30.4.5 Tolerance of the LPUART receiver to clock deviation . . . . .	842
30.4.6 Multiprocessor communication using LPUART . . . . .	843
Idle line detection (WAKE=0) . . . . .	843
4-bit/7-bit address mark detection (WAKE=1) . . . . .	844
30.4.7 LPUART parity control . . . . .	845
Even parity . . . . .	845
Odd parity . . . . .	845
Parity checking in reception . . . . .	846
Parity generation in transmission . . . . .	846
30.4.8 Single-wire Half-duplex communication using LPUART . . . . .	846
30.4.9 Continuous communication in DMA mode using LPUART . . . . .	846
Transmission using DMA . . . . .	847
Reception using DMA . . . . .	848
Error flagging and interrupt generation in multibuffer communication . . . . .	849
30.4.10 RS232 Hardware flow control and RS485 Driver Enable using LPUART . . . . .	849
RS232 RTS flow control . . . . .	850
RS232 CTS flow control . . . . .	850
RS485 Driver Enable . . . . .	851
30.4.11 Wakeup from Stop mode using LPUART . . . . .	852
Using Mute mode with Stop mode . . . . .	853
Determining the maximum LPUART baud rate allowing to wakeup correctly from Stop mode when the LPUART clock source is the HSI clock . . . . .	853
30.5 LPUART in low-power mode . . . . .	854
30.6 LPUART interrupts . . . . .	854
30.7 LPUART registers . . . . .	856
30.7.1 Control register 1 (LPUART_CR1) . . . . .	856
30.7.2 Control register 2 (LPUART_CR2) . . . . .	859
30.7.3 Control register 3 (LPUART_CR3) . . . . .	861
30.7.4 Baud rate register (LPUART_BRR) . . . . .	863
30.7.5 Request register (LPUART_RQR) . . . . .	863

30.7.6	Interrupt & status register (LPUART_ISR) . . . . .	864
30.7.7	Interrupt flag clear register (LPUART_ICR) . . . . .	867
30.7.8	Receive data register (LPUART_RDR) . . . . .	868
30.7.9	Transmit data register (LPUART_TDR) . . . . .	868
30.7.10	LPUART register map . . . . .	870
31	Serial peripheral interface/ inter-IC sound (SPI/I2S) . . . . .	871
31.1	Introduction . . . . .	871
31.1.1	SPI main features . . . . .	871
31.1.2	SPI extended features . . . . .	872
31.1.3	I2S features . . . . .	872
31.2	SPI/I2S implementation . . . . .	872
31.3	SPI functional description . . . . .	873
31.3.1	General description . . . . .	873
31.3.2	Communications between one master and one slave . . . . .	874
	Full-duplex communication . . . . .	874
	Half-duplex communication . . . . .	874
	Simplex communications . . . . .	875
31.3.3	Standard multi-slave communication . . . . .	877
31.3.4	Multi-master communication . . . . .	878
31.3.5	Slave select (NSS) pin management . . . . .	878
31.3.6	Communication formats . . . . .	880
	Clock phase and polarity controls . . . . .	880
	Data frame format . . . . .	881
31.3.7	SPI configuration . . . . .	882
31.3.8	Procedure for enabling SPI . . . . .	882
31.3.9	Data transmission and reception procedures . . . . .	883
	Rx and Tx buffers . . . . .	883
	Tx buffer handling . . . . .	883
	Rx buffer handling . . . . .	883
	Sequence handling . . . . .	883
31.3.10	Procedure for disabling the SPI . . . . .	885
31.3.11	Communication using DMA (direct memory addressing) . . . . .	886
31.3.12	SPI status flags . . . . .	888
	Tx buffer empty flag (TXE) . . . . .	888
	Rx buffer not empty (RXNE) . . . . .	888
	Busy flag (BSY) . . . . .	888
31.3.13	SPI error flags . . . . .	889

Overrun flag (OVR) . . . . .	889
Mode fault (MODF) . . . . .	889
CRC error (CRCERR) . . . . .	890
TI mode frame format error (FRE) . . . . .	890
31.4 SPI special features . . . . .	890
31.4.1 TI mode . . . . .	890
TI protocol in master mode . . . . .	890
31.4.2 CRC calculation . . . . .	891
CRC principle . . . . .	891
CRC transfer managed by CPU . . . . .	891
CRC transfer managed by DMA . . . . .	892
Resetting the SPIx_TXCRC and SPIx_RXCRC values . . . . .	892
31.5 SPI interrupts . . . . .	893
31.6 I ²S functional description . . . . .	894
31.6.1 I ²S general description . . . . .	894
31.6.2 I ²S full-duplex . . . . .	895
31.6.3 Supported audio protocols . . . . .	896
I ²S Philips standard . . . . .	897
MSB justified standard . . . . .	899
LSB justified standard . . . . .	900
PCM standard . . . . .	902
31.6.4 Clock generator . . . . .	903
31.6.5 I ²S master mode . . . . .	905
Procedure . . . . .	905
Transmission sequence . . . . .	905
Reception sequence . . . . .	906
31.6.6 I ²S slave mode . . . . .	907
Transmission sequence . . . . .	907
Reception sequence . . . . .	908
31.6.7 I ²S status flags . . . . .	908
Busy flag (BSY) . . . . .	908
Tx buffer empty flag (TXE) . . . . .	909
RX buffer not empty (RXNE) . . . . .	909
Channel Side flag (CHSIDE) . . . . .	909
31.6.8 I ²S error flags . . . . .	909
Underrun flag (UDR) . . . . .	909
Overrun flag (OVR) . . . . .	910
Frame error flag (FRE) . . . . .	910
31.6.9 I ²S interrupts . . . . .	910
31.6.10 DMA features . . . . .	910

31.7	SPI and I ²S registers . . . . .	911
31.7.1	SPI control register 1 (SPI_CR1) (not used in I ²S mode) . . . . .	911
31.7.2	SPI control register 2 (SPI_CR2) . . . . .	913
31.7.3	SPI status register (SPI_SR) . . . . .	914
31.7.4	SPI data register (SPI_DR) . . . . .	916
31.7.5	SPI CRC polynomial register (SPI_CRCPR) (not used in I ²S mode) . . . . .	916
31.7.6	SPI RX CRC register (SPI_RXCRCR) (not used in I ²S mode) . . . . .	917
31.7.7	SPI TX CRC register (SPI_TXCRCR) (not used in I ²S mode) . . . . .	917
31.7.8	SPI_I ²S configuration register (SPI_I2SCFGR) . . . . .	918
31.7.9	SPI_I ²S prescaler register (SPI_I2SPR) . . . . .	919
31.7.10	SPI register map . . . . .	920
32	Universal serial bus full-speed device interface (USB) . . . . .	921
32.1	Introduction . . . . .	921
32.2	USB main features . . . . .	921
32.3	USB implementation . . . . .	921
32.4	USB functional description . . . . .	922
32.4.1	Description of USB blocks . . . . .	923
32.5	Programming considerations . . . . .	924
32.5.1	Generic USB device programming . . . . .	924
32.5.2	System and power-on reset . . . . .	925
	USB reset (RESET interrupt) . . . . .	925
	Structure and usage of packet buffers . . . . .	925
	Endpoint initialization . . . . .	927
	IN packets (data transmission) . . . . .	927
	OUT and SETUP packets (data reception) . . . . .	928
	Control transfers . . . . .	929
32.5.3	Double-buffered endpoints . . . . .	930
32.5.4	Isochronous transfers . . . . .	932
32.5.5	Suspend/Resume events . . . . .	933
32.6	USB and USB SRAM registers . . . . .	936
32.6.1	Common registers . . . . .	936
	USB control register (USB_CNTR) . . . . .	936
	USB interrupt status register (USB_ISTR) . . . . .	938
	USB frame number register (USB_FNR) . . . . .	941
	USB device address (USB_DADDR) . . . . .	941
	Buffer table address (USB_BTABLE) . . . . .	942

LPM control and status register (USB_LPMCSR) . . . . .	942
Battery charging detector (USB_BCDR) . . . . .	943
Endpoint-specific registers . . . . .	944
USB endpoint n register (USB_EPNR), n=[0..7] . . . . .	944
32.6.2 Buffer descriptor table . . . . .	949
Transmission buffer address n (USB_ADDRn_TX) . . . . .	949
Transmission byte count n (USB_COUNTn_TX) . . . . .	949
Reception buffer address n (USB_ADDRn_RX) . . . . .	950
Reception byte count n (USB_COUNTn_RX) . . . . .	950
32.6.3 USB register map . . . . .	952
33 Debug support (DBG) . . . . .	954
33.1 Overview . . . . .	954
33.2 Reference Arm® documentation . . . . .	955
33.3 Pinout and debug port pins . . . . .	955
33.3.1 SWD port pins . . . . .	955
33.3.2 SW-DP pin assignment . . . . .	955
33.3.3 Internal pull-up & pull-down on SWD pins . . . . .	956
33.4 ID codes and locking mechanism . . . . .	956
33.4.1 MCU device ID code . . . . .	956
DBG_IDCODE . . . . .	956
33.5 SWD port . . . . .	957
33.5.1 SWD protocol introduction . . . . .	957
33.5.2 SWD protocol sequence . . . . .	957
33.5.3 SW-DP state machine (reset, idle states, ID code) . . . . .	958
33.5.4 DP and AP read/write accesses . . . . .	959
33.5.5 SW-DP registers . . . . .	959
33.5.6 SW-AP registers . . . . .	960
33.6 Core debug . . . . .	961
33.7 BPU (Break Point Unit) . . . . .	961
33.7.1 BPU functionality . . . . .	961
33.8 DWT (Data Watchpoint) . . . . .	962
33.8.1 DWT functionality . . . . .	962
33.8.2 DWT Program Counter Sample Register . . . . .	962
33.9 MCU debug component (DBG) . . . . .	962
33.9.1 Debug support for low-power modes . . . . .	962
33.9.2 Debug support for timers, watchdog and I ²C . . . . .	963

33.9.3	Debug MCU configuration register (DBG_CR) . . . . .	963
33.9.4	Debug MCU APB1 freeze register (DBG_APB1_FZ) . . . . .	965
33.9.5	Debug MCU APB2 freeze register (DBG_APB2_FZ) . . . . .	967
33.10	DBG register map . . . . .	968
34	Device electronic signature . . . . .	969
34.1	Memory size register . . . . .	969
34.1.1	Flash size register . . . . .	969
34.2	Unique device ID registers (96 bits) . . . . .	969
Appendix A	Code examples. . . . .	971
A.1	Introduction . . . . .	971
A.2	NVM/RCC Operation code example . . . . .	971
A.2.1	Increasing the CPU frequency preparation sequence code . . . . .	971
A.2.2	Decreasing the CPU frequency preparation sequence code . . . . .	971
A.2.3	Switch from PLL to HSI16 sequence code . . . . .	972
A.2.4	Switch to PLL sequence code. . . . .	972
A.3	NVM Operation code example . . . . .	973
A.3.1	Unlocking the data EEPROM and FLASH_PECR register code example . . . . .	973
A.3.2	Locking data EEPROM and FLASH_PECR register code example . . . . .	973
A.3.3	Unlocking the NVM program memory code example . . . . .	973
A.3.4	Unlocking the option bytes area code example . . . . .	974
A.3.5	Write to data EEPROM code example . . . . .	974
A.3.6	Erase to data EEPROM code example . . . . .	974
A.3.7	Program Option byte code example . . . . .	975
A.3.8	Erase Option byte code example . . . . .	975
A.3.9	Program a single word to Flash program memory code example . . . . .	976
A.3.10	Program half-page to Flash program memory code example . . . . .	977
A.3.11	Erase a page in Flash program memory code example . . . . .	978
A.3.12	Mass erase code example . . . . .	979
A.4	Clock Controller. . . . .	980
A.4.1	HSE start sequence code example . . . . .	980
A.4.2	PLL configuration modification code example . . . . .	981
A.4.3	MCO selection code example. . . . .	982
A.5	GPIOs . . . . .	982
A.5.1	Locking mechanism code example. . . . .	982

A.5.2	Alternate function selection sequence code example . . . . .	982
A.5.3	Analog GPIO configuration code example . . . . .	982
A.6	DMA . . . . .	983
A.6.1	DMA Channel Configuration sequence code example . . . . .	983
A.7	Interrupts and event . . . . .	983
A.7.1	NVIC initialization example . . . . .	983
A.7.2	Extended interrupt selection code example . . . . .	983
A.8	ADC . . . . .	984
A.8.1	Calibration code example . . . . .	984
A.8.2	ADC enable sequence code example . . . . .	984
A.8.3	ADC disable sequence code example . . . . .	985
A.8.4	ADC clock selection code example . . . . .	985
A.8.5	Single conversion sequence code example - Software trigger . . . . .	985
A.8.6	Continuous conversion sequence code example - Software trigger . . . . .	986
A.8.7	Single conversion sequence code example - Hardware trigger . . . . .	986
A.8.8	Continuous conversion sequence code example - Hardware trigger . . . . .	987
A.8.9	DMA one shot mode sequence code example . . . . .	987
A.8.10	DMA circular mode sequence code example . . . . .	988
A.8.11	Wait mode sequence code example . . . . .	988
A.8.12	Auto off and no wait mode sequence code example . . . . .	988
A.8.13	Auto off and wait mode sequence code example . . . . .	989
A.8.14	Analog watchdog code example . . . . .	989
A.8.15	Oversampling code example . . . . .	990
A.8.16	Temperature configuration code example . . . . .	990
A.8.17	Temperature computation code example . . . . .	990
A.9	DAC . . . . .	991
A.9.1	Independent trigger without wave generation code example . . . . .	991
A.9.2	Independent trigger with single triangle generation code example . . . . .	991
A.9.3	DMA initialization code example . . . . .	991
A.10	TSC code example . . . . .	992
A.10.1	TSC configuration code example . . . . .	992
A.10.2	TSC interrupt code example . . . . .	993
A.11	Timers . . . . .	993
A.11.1	Upcounter on TI2 rising edge code example . . . . .	993
A.11.2	Up counter on each 2 ETR rising edges code example . . . . .	993
A.11.3	Input capture configuration code example . . . . .	994

A.11.4	Input capture data management code example . . . . .	994
A.11.5	PWM input configuration code example . . . . .	995
A.11.6	PWM input with DMA configuration code example . . . . .	995
A.11.7	Output compare configuration code example . . . . .	996
A.11.8	Edge-aligned PWM configuration example. . . . .	996
A.11.9	Center-aligned PWM configuration example . . . . .	997
A.11.10	ETR configuration to clear OCxREF code example . . . . .	997
A.11.11	Encoder interface code example . . . . .	998
A.11.12	Reset mode code example . . . . .	998
A.11.13	Gated mode code example. . . . .	999
A.11.14	Trigger mode code example . . . . .	999
A.11.15	External clock mode 2 + trigger mode code example. . . . .	1000
A.11.16	One-Pulse mode code example . . . . .	1000
A.11.17	Timer prescaling another timer code example . . . . .	1001
A.11.18	Timer enabling another timer code example. . . . .	1001
A.11.19	Master and slave synchronization code example . . . . .	1002
A.11.20	Two timers synchronized by an external trigger code example . . . . .	1004
A.11.21	DMA burst feature code example . . . . .	1005
A.12	Low-power timer (LPTIM) . . . . .	1006
A.12.1	Pulse counter configuration code example. . . . .	1006
A.13	IWDG code example . . . . .	1006
A.13.1	IWDG configuration code example . . . . .	1006
A.13.2	IWDG configuration with window code example. . . . .	1006
A.14	WWDG code example. . . . .	1007
A.14.1	WWDG configuration code example. . . . .	1007
A.15	RTC code example . . . . .	1007
A.15.1	RTC calendar configuration code example. . . . .	1007
A.15.2	RTC alarm configuration code example . . . . .	1008
A.15.3	RTC WUT configuration code example . . . . .	1008
A.15.4	RTC read calendar code example . . . . .	1009
A.15.5	RTC calibration code example . . . . .	1009
A.15.6	RTC tamper and time stamp configuration code example . . . . .	1009
A.15.7	RTC tamper and time stamp code example . . . . .	1010
A.15.8	RTC clock output code example . . . . .	1010
A.16	I2C code example . . . . .	1010
A.16.1	I2C configured in slave mode code example . . . . .	1010

A.16.2 I2C slave transmitter code example . . . . . 1011
A.16.3 I2C slave receiver code example . . . . . 1011
A.16.4 I2C configured in master mode to receive code example. . . . . 1011
A.16.5 I2C configured in master mode to transmit code example . . . . . 1012
A.16.6 I2C master transmitter code example. . . . . 1012
A.16.7 I2C master receiver code example . . . . . 1012
A.16.8 I2C configured in master mode to transmit with DMA code example . 1012
A.16.9 I2C configured in slave mode to receive with DMA code example . . 1013
A.17 USART code example. . . . . 1013
- A.17.1 USART transmitter configuration code example. . . . . 1013
- A.17.2 USART transmit byte code example. . . . . 1013
- A.17.3 USART transfer complete code example . . . . . 1013
- A.17.4 USART receiver configuration code example. . . . . 1013
- A.17.5 USART receive byte code example . . . . . 1014
- A.17.6 USART LIN mode code example . . . . . 1014
- A.17.7 USART synchronous mode code example. . . . . 1014
- A.17.8 USART single-wire half-duplex code example . . . . . 1015
- A.17.9 USART smartcard mode code example . . . . . 1015
- A.17.10 USART IrDA mode code example . . . . . 1015
- A.17.11 USART DMA code example . . . . . 1016
- A.17.12 USART hardware flow control code example . . . . . 1016
A.18 LPUART code example. . . . . 1017
- A.18.1 LPUART receiver configuration code example. . . . . 1017
- A.18.2 LPUART receive byte code example . . . . . 1017
A.19 SPI code example . . . . . 1017
- A.19.1 SPI master configuration code example. . . . . 1017
- A.19.2 SPI slave configuration code example . . . . . 1017
- A.19.3 SPI full duplex communication code example . . . . . 1017
- A.19.4 SPI master configuration with DMA code example. . . . . 1018
- A.19.5 SPI slave configuration with DMA code example . . . . . 1018
- A.19.6 SPI interrupt code example . . . . . 1018
A.20 DBG code example . . . . . 1018
- A.20.1 DBG read device Id code example. . . . . 1018
- A.20.2 DBG debug in LPM code example . . . . . 1018

Revision history . . . . . 1019

List of tables

Table 1.	STM32L0x3 memory density . . . . .	54
Table 2.	Overview of features per category . . . . .	54
Table 3.	STM32L0x3 peripheral register boundary addresses . . . . .	60
Table 4.	Boot modes . . . . .	64
Table 5.	NVM organization (category 3 devices) . . . . .	67
Table 6.	NVM organization for UFB = 0 (192 Kbyte category 5 devices) . . . . .	68
Table 7.	Flash memory and data EEPROM remapping (192 Kbyte category 5 devices) . . . . .	69
Table 8.	NVM organization for UFB = 0 (128 Kbyte category 5 devices) . . . . .	69
Table 9.	Flash memory and data EEPROM remapping (128 Kbyte category 5 devices) . . . . .	70
Table 10.	NVM organization for UFB = 0 (64 Kbyte category 5 devices) . . . . .	70
Table 11.	Boot pin and BFB2 bit configuration . . . . .	71
Table 12.	Link between master clock power range and frequencies . . . . .	73
Table 13.	Delays to memory access and number of wait states . . . . .	73
Table 14.	Internal buffer management . . . . .	76
Table 15.	Configurations for buffers and speculative reading . . . . .	79
Table 16.	Dhrystone performances in all memory interface configurations . . . . .	80
Table 17.	NVM write/erase timings . . . . .	94
Table 18.	NVM write/erase duration . . . . .	94
Table 19.	Protection level and content of RDP Option bytes . . . . .	98
Table 20.	Link between protection bits of FLASH_WRPROTx register and protected address in Flash program memory . . . . .	99
Table 21.	Memory access vs mode, protection and Flash program memory sectors . . . . .	100
Table 22.	Flash interrupt request . . . . .	103
Table 23.	Flash interface - register map and reset values . . . . .	120
Table 24.	Option byte format . . . . .	121
Table 25.	Option byte organization . . . . .	121
Table 26.	CRC internal input/output signals . . . . .	124
Table 27.	CRC register map and reset values . . . . .	129
Table 28.	Segment accesses according to the Firewall state . . . . .	133
Table 29.	Segment granularity and area ranges . . . . .	134
Table 30.	Firewall register map and reset values . . . . .	141
Table 31.	Performance versus VCORE ranges . . . . .	146
Table 32.	Summary of low-power modes . . . . .	153
Table 33.	Sleep-now . . . . .	157
Table 34.	Sleep-on-exit . . . . .	158
Table 35.	Sleep-now (Low-power sleep) . . . . .	159
Table 36.	Sleep-on-exit (Low-power sleep) . . . . .	160
Table 37.	Stop mode . . . . .	162
Table 38.	Standby mode . . . . .	164
Table 39.	PWR - register map and reset values . . . . .	172
Table 40.	HSE/LSE clock sources . . . . .	178
Table 41.	System clock source frequency . . . . .	183
Table 42.	RCC register map and reset values . . . . .	223
Table 43.	CRS features . . . . .	226
Table 44.	Effect of low-power modes on CRS . . . . .	230
Table 45.	Interrupt control bits . . . . .	230
Table 46.	CRS register map and reset values . . . . .	235

Table 47.	Port bit configuration table . . . . .	239
Table 48.	GPIO register map and reset values . . . . .	252
Table 49.	SYSCFG register map and reset values . . . . .	262
Table 50.	DMA implementation . . . . .	265
Table 51.	DMA requests for each channel . . . . .	266
Table 52.	Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .	274
Table 53.	DMA interrupt requests . . . . .	275
Table 54.	DMA register map and reset values . . . . .	285
Table 55.	List of vectors . . . . .	288
Table 56.	EXTI lines connections . . . . .	295
Table 57.	Extended interrupt/event controller register map and reset values . . . . .	300
Table 58.	ADC input/output pins . . . . .	303
Table 59.	ADC internal input/output signals . . . . .	304
Table 60.	External triggers . . . . .	304
Table 61.	Latency between trigger and start of conversion . . . . .	309
Table 62.	Configuring the trigger polarity . . . . .	315
Table 63.	tSAR timings depending on resolution . . . . .	317
Table 64.	Analog watchdog comparison . . . . .	326
Table 65.	Analog watchdog channel selection . . . . .	326
Table 66.	Maximum output results vs N and M. Grayed values indicates truncation . . . . .	330
Table 67.	ADC interrupts . . . . .	335
Table 68.	ADC register map and reset values . . . . .	350
Table 69.	DAC pins . . . . .	353
Table 70.	External triggers . . . . .	356
Table 71.	DAC register map and reset values . . . . .	374
Table 72.	COMP register map and reset values . . . . .	382
Table 73.	Implementation . . . . .	385
Table 74.	Example of frame rate calculation . . . . .	386
Table 75.	Blink frequency . . . . .	394
Table 76.	VLCD rail connections to GPIO pins . . . . .	397
Table 77.	Remapping capability . . . . .	399
Table 78.	LCD behavior in low-power modes . . . . .	404
Table 79.	LCD interrupt requests . . . . .	404
Table 80.	LCD register map and reset values . . . . .	411
Table 81.	Acquisition sequence summary . . . . .	416
Table 82.	Spread spectrum deviation versus AHB clock frequency . . . . .	418
Table 83.	I/O state depending on its mode and IODEF bit value . . . . .	419
Table 84.	Effect of low-power modes on TSC . . . . .	421
Table 85.	Interrupt control bits . . . . .	421
Table 86.	TSC register map and reset values . . . . .	430
Table 87.	AES internal input/output signals . . . . .	433
Table 88.	CTR mode initialization vector definition . . . . .	449
Table 89.	Key endianness in AES_KEYRx registers . . . . .	452
Table 90.	DMA channel configuration for memory-to-AES data transfer . . . . .	453
Table 91.	DMA channel configuration for AES-to-memory data transfer . . . . .	454
Table 92.	AES interrupt requests . . . . .	456
Table 93.	Processing latency (in clock cycle) . . . . .	456
Table 94.	AES register map and reset values . . . . .	464
Table 95.	RNG internal input/output signals . . . . .	467
Table 96.	RNG interrupt requests . . . . .	472
Table 97.	RNG register map and reset map . . . . .	476
Table 98.	Counting direction versus encoder signals . . . . .	508

Table 99.	TIM2/TIM3 internal trigger connection . . . . .	525
Table 100.	Output control bit for standard OCx channels. . . . .	535
Table 101.	TIM2/3 register map and reset values . . . . .	543
Table 102.	Counting direction versus encoder signals. . . . .	576
Table 103.	TIMx Internal trigger connection . . . . .	586
Table 104.	Output control bit for standard OCx channels. . . . .	594
Table 105.	TIM21/22 register map and reset values . . . . .	598
Table 106.	TIM6/7 register map and reset values . . . . .	612
Table 107.	STM32L0x3 LPTIM features. . . . .	614
Table 108.	LPTIM1 external trigger connection . . . . .	615
Table 109.	Prescaler division ratios . . . . .	616
Table 110.	Encoder counting scenarios . . . . .	622
Table 111.	Effect of low-power modes on the LPTIM. . . . .	623
Table 112.	Interrupt events. . . . .	624
Table 113.	LPTIM register map and reset values. . . . .	633
Table 114.	IWDG register map and reset values . . . . .	642
Table 115.	WWDG register map and reset values . . . . .	648
Table 116.	RTC implementation. . . . .	650
Table 117.	RTC pin PC13 configuration. . . . .	652
Table 118.	RTC_OUT mapping . . . . .	653
Table 119.	Effect of low-power modes on RTC . . . . .	666
Table 120.	Interrupt control bits . . . . .	666
Table 121.	RTC register map and reset values . . . . .	691
Table 122.	STM32L0x3 I2C features . . . . .	694
Table 123.	I2C input/output pins. . . . .	697
Table 124.	I2C internal input/output signals . . . . .	697
Table 125.	Comparison of analog vs. digital filters. . . . .	699
Table 126.	I2C-SMBus specification data setup and hold times . . . . .	702
Table 127.	I2C configuration. . . . .	706
Table 128.	I2C-SMBus specification clock timings. . . . .	717
Table 129.	Examples of timing settings for f _I2CCLK= 8 MHz . . . . .	727
Table 130.	Examples of timings settings for f _I2CCLK= 16 MHz . . . . .	727
Table 131.	SMBus timeout specifications. . . . .	729
Table 132.	SMBus with PEC configuration. . . . .	732
Table 133.	Examples of TIMEOUTA settings for various I2CCLK frequencies (max t _TIMEOUT= 25 ms) . . . . .	733
Table 134.	Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . .	733
Table 135.	Examples of TIMEOUTA settings for various I2CCLK frequencies (max t _IDLE= 50 µs) . . . . .	733
Table 136.	Effect of low-power modes on the I2C . . . . .	744
Table 137.	I2C Interrupt requests. . . . .	745
Table 138.	I2C register map and reset values . . . . .	760
Table 139.	STM32L0x3 USART/LPUART features . . . . .	764
Table 140.	Noise detection from sampled data . . . . .	776
Table 141.	Error calculation for programmed baud rates at f _CK= 32 MHz in both cases of oversampling by 16 or by 8. . . . .	779
Table 142.	Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .	780
Table 143.	Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . .	780
Table 144.	Frame formats . . . . .	785
Table 145.	Effect of low-power modes on the USART. . . . .	804
Table 146.	USART interrupt requests. . . . .	804
Table 147.	USART register map and reset values . . . . .	827

Table 148.	STM32L0x3 USART/LPUART features . . . . .	831
Table 149.	Error calculation for programmed baud rates at fck = 32.768 kHz . . . . .	841
Table 150.	Error calculation for programmed baud rates at fck = 32 MHz . . . . .	841
Table 151.	Tolerance of the LPUART receiver . . . . .	842
Table 152.	Frame formats . . . . .	845
Table 153.	Effect of low-power modes on the LPUART . . . . .	854
Table 154.	LPUART interrupt requests . . . . .	854
Table 155.	LPUART register map and reset values . . . . .	870
Table 156.	STM32L0x3 SPI implementation . . . . .	872
Table 157.	SPI interrupt requests . . . . .	893
Table 158.	Audio-frequency precision using standard 8 MHz HSE . . . . .	904
Table 159.	I ²S interrupt requests . . . . .	910
Table 160.	SPI register map and reset values . . . . .	920
Table 161.	STM32L0x3 USB implementation . . . . .	921
Table 162.	Double-buffering buffer flag definition . . . . .	931
Table 163.	Bulk double-buffering memory buffers usage . . . . .	931
Table 164.	Isochronous memory buffers usage . . . . .	933
Table 165.	Resume event detection . . . . .	934
Table 166.	Reception status encoding . . . . .	947
Table 167.	Endpoint type encoding . . . . .	947
Table 168.	Endpoint kind meaning . . . . .	947
Table 169.	Transmission status encoding . . . . .	948
Table 170.	Definition of allocated buffer memory . . . . .	951
Table 171.	USB register map and reset values . . . . .	952
Table 172.	SW debug port pins . . . . .	955
Table 173.	REV_ID values . . . . .	957
Table 174.	Packet request (8-bits) . . . . .	957
Table 175.	ACK response (3 bits) . . . . .	958
Table 176.	DATA transfer (33 bits) . . . . .	958
Table 177.	SW-DP registers . . . . .	959
Table 178.	32-bit debug port registers addressed through the shifted value A[3:2] . . . . .	960
Table 179.	Core debug registers . . . . .	961
Table 180.	DBG register map and reset values . . . . .	968
Table 181.	Document revision history . . . . .	1019

List of figures

Figure 1.	System architecture . . . . .	56
Figure 2.	Memory map . . . . .	59
Figure 3.	Structure of one internal buffer . . . . .	75
Figure 4.	Timing to fetch and execute instructions with prefetch disabled . . . . .	77
Figure 5.	Timing to fetch and execute instructions with prefetch enabled . . . . .	79
Figure 6.	RDP levels . . . . .	98
Figure 7.	CRC calculation unit block diagram . . . . .	124
Figure 8.	STM32L0x3 firewall connection schematics . . . . .	131
Figure 9.	Firewall functional states . . . . .	135
Figure 10.	Power supply overview . . . . .	143
Figure 11.	Performance versus VDD and VCORE range . . . . .	146
Figure 12.	Power supply supervisors . . . . .	149
Figure 13.	Power-on reset/power-down reset waveform . . . . .	150
Figure 14.	BOR thresholds . . . . .	151
Figure 15.	PVD thresholds . . . . .	152
Figure 16.	Simplified diagram of the reset circuit . . . . .	174
Figure 17.	Clock tree . . . . .	177
Figure 18.	Using TIM21 channel 1 input capture to measure frequencies . . . . .	185
Figure 19.	CRS block diagram . . . . .	227
Figure 20.	CRS counter behavior . . . . .	228
Figure 21.	Basic structure of an I/O port bit . . . . .	238
Figure 22.	Basic structure of a 5-Volt tolerant I/O port bit . . . . .	238
Figure 23.	Input floating / pull up / pull down configurations . . . . .	243
Figure 24.	Output configuration . . . . .	244
Figure 25.	Alternate function configuration . . . . .	245
Figure 26.	High impedance-analog configuration . . . . .	245
Figure 27.	DMA request mapping . . . . .	266
Figure 28.	DMA block diagram . . . . .	268
Figure 29.	Extended interrupts and events controller (EXTI) block diagram . . . . .	292
Figure 30.	Extended interrupt/event GPIO mapping . . . . .	294
Figure 31.	ADC block diagram . . . . .	303
Figure 32.	ADC calibration . . . . .	306
Figure 33.	Calibration factor forcing . . . . .	307
Figure 34.	Enabling/disabling the ADC . . . . .	308
Figure 35.	ADC clock scheme . . . . .	308
Figure 36.	ADC connectivity . . . . .	310
Figure 37.	Analog to digital conversion time . . . . .	314
Figure 38.	ADC conversion timings . . . . .	314
Figure 39.	Stopping an ongoing conversion . . . . .	315
Figure 40.	Single conversions of a sequence, software trigger . . . . .	318
Figure 41.	Continuous conversion of a sequence, software trigger . . . . .	318
Figure 42.	Single conversions of a sequence, hardware trigger . . . . .	319
Figure 43.	Continuous conversions of a sequence, hardware trigger . . . . .	319
Figure 44.	Data alignment and resolution (oversampling disabled: OVSE = 0) . . . . .	320
Figure 45.	Example of overrun (OVR) . . . . .	321
Figure 46.	Wait mode conversion (continuous mode, software trigger) . . . . .	323
Figure 47.	Behavior with WAIT = 0, AUTOFF = 1 . . . . .	324

Figure 48.	Behavior with WAIT = 1, AUTOFF = 1 . . . . .	325
Figure 49.	Analog watchdog guarded area . . . . .	326
Figure 50.	ADC_AWD1_OUT signal generation . . . . .	327
Figure 51.	ADC_AWD1_OUT signal generation (AWD flag not cleared by software) . . . . .	328
Figure 52.	ADC1_AWD_OUT signal generation (on a single channel) . . . . .	328
Figure 53.	Analog watchdog threshold update . . . . .	329
Figure 54.	20-bit to 16-bit result truncation . . . . .	330
Figure 55.	Numerical example with 5-bits shift and rounding . . . . .	330
Figure 56.	Triggered oversampling mode (TOVS bit = 1) . . . . .	332
Figure 57.	Temperature sensor and VREFINT channel block diagram . . . . .	333
Figure 58.	DAC block diagram . . . . .	353
Figure 59.	Data registers in single DAC channel mode . . . . .	354
Figure 60.	Timing diagram for conversion with trigger disabled TEN = 0 . . . . .	355
Figure 61.	Data registers in dual DAC channel mode . . . . .	357
Figure 62.	DAC LFSR register calculation algorithm . . . . .	361
Figure 63.	DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .	362
Figure 64.	DAC triangle wave generation . . . . .	362
Figure 65.	DAC conversion (SW trigger enabled) with triangle wave generation . . . . .	363
Figure 66.	Comparator 1 and 2 block diagrams . . . . .	377
Figure 67.	LCD controller block diagram . . . . .	385
Figure 68.	1/3 bias, 1/4 duty . . . . .	388
Figure 69.	Static duty case 1 . . . . .	389
Figure 70.	Static duty case 2 . . . . .	389
Figure 71.	1/2 duty, 1/2 bias . . . . .	390
Figure 72.	1/3 duty, 1/3 bias . . . . .	391
Figure 73.	1/4 duty, 1/3 bias . . . . .	392
Figure 74.	1/8 duty, 1/4 bias . . . . .	393
Figure 75.	LCD voltage control . . . . .	396
Figure 76.	Deadtime . . . . .	397
Figure 77.	SEG/COM mux feature example . . . . .	402
Figure 78.	Flowchart example . . . . .	403
Figure 79.	TSC block diagram . . . . .	414
Figure 80.	Surface charge transfer analog I/O group structure . . . . .	415
Figure 81.	Sampling capacitor voltage variation . . . . .	416
Figure 82.	Charge transfer acquisition sequence . . . . .	417
Figure 83.	Spread spectrum variation principle . . . . .	418
Figure 84.	AES block diagram . . . . .	433
Figure 85.	ECB encryption and decryption principle . . . . .	435
Figure 86.	CBC encryption and decryption principle . . . . .	436
Figure 87.	CTR encryption and decryption principle . . . . .	437
Figure 88.	STM32 cryptolib AES flowchart example . . . . .	438
Figure 89.	Encryption key derivation for ECB/CBC decryption (Mode 2). . . . .	441
Figure 90.	Example of suspend mode management . . . . .	442
Figure 91.	ECB encryption . . . . .	442
Figure 92.	ECB decryption . . . . .	443
Figure 93.	CBC encryption . . . . .	443
Figure 94.	CBC decryption . . . . .	444
Figure 95.	ECB/CBC encryption (Mode 1) . . . . .	445
Figure 96.	ECB/CBC decryption (Mode 3) . . . . .	446
Figure 97.	Message construction in CTR mode . . . . .	448
Figure 98.	CTR encryption . . . . .	448
Figure 99.	CTR decryption . . . . .	449

Figure 100. 128-bit block construction with respect to data swap . . . . .	451
Figure 101. DMA transfer of a 128-bit data block during input phase . . . . .	453
Figure 102. DMA transfer of a 128-bit data block during output phase . . . . .	454
Figure 103. AES interrupt signal generation . . . . .	456
Figure 104. RNG block diagram . . . . .	467
Figure 105. Entropy source model . . . . .	468
Figure 106. General-purpose timer block diagram . . . . .	478
Figure 107. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	480
Figure 108. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	480
Figure 109. Counter timing diagram, internal clock divided by 1 . . . . .	481
Figure 110. Counter timing diagram, internal clock divided by 2 . . . . .	482
Figure 111. Counter timing diagram, internal clock divided by 4 . . . . .	482
Figure 112. Counter timing diagram, internal clock divided by N . . . . .	483
Figure 113. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .	483
Figure 114. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .	484
Figure 115. Counter timing diagram, internal clock divided by 1 . . . . .	485
Figure 116. Counter timing diagram, internal clock divided by 2 . . . . .	485
Figure 117. Counter timing diagram, internal clock divided by 4 . . . . .	486
Figure 118. Counter timing diagram, internal clock divided by N . . . . .	486
Figure 119. Counter timing diagram, Update event when repetition counter is not used . . . . .	487
Figure 120. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .	488
Figure 121. Counter timing diagram, internal clock divided by 2 . . . . .	489
Figure 122. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	489
Figure 123. Counter timing diagram, internal clock divided by N . . . . .	490
Figure 124. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .	490
Figure 125. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .	491
Figure 126. Control circuit in normal mode, internal clock divided by 1 . . . . .	492
Figure 127. TI2 external clock connection example. . . . .	492
Figure 128. Control circuit in external clock mode 1 . . . . .	493
Figure 129. External trigger input block . . . . .	494
Figure 130. Control circuit in external clock mode 2 . . . . .	495
Figure 131. Capture/compare channel (example: channel 1 input stage). . . . .	496
Figure 132. Capture/compare channel 1 main circuit . . . . .	496
Figure 133. Output stage of capture/compare channel (channel 1). . . . .	497
Figure 134. PWM input mode timing . . . . .	499
Figure 135. Output compare mode, toggle on OC1. . . . .	501
Figure 136. Edge-aligned PWM waveforms (ARR=8). . . . .	502
Figure 137. Center-aligned PWM waveforms (ARR=8). . . . .	504
Figure 138. Example of one-pulse mode. . . . .	505
Figure 139. Clearing TIMx_OCxREF . . . . .	507
Figure 140. Example of counter operation in encoder interface mode . . . . .	509
Figure 141. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .	509
Figure 142. Control circuit in reset mode . . . . .	510
Figure 143. Control circuit in gated mode . . . . .	511
Figure 144. Control circuit in trigger mode . . . . .	512
Figure 145. Control circuit in external clock mode 2 + trigger mode . . . . .	514
Figure 146. Master/Slave timer example . . . . .	514
Figure 147. Gating timer y with OC1REF of timer x. . . . .	516
Figure 148. Gating timer y with Enable of timer x . . . . .	517
Figure 149. Triggering timer y with update of timer x. . . . .	518
Figure 150. Triggering timer y with Enable of timer x . . . . .	518

Figure 151. Triggering timer x and y with timer x TI1 input . . . . .	519
Figure 152. General-purpose timer block diagram (TIM21/22) . . . . .	546
Figure 153. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	548
Figure 154. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	549
Figure 155. Counter timing diagram, internal clock divided by 1 . . . . .	550
Figure 156. Counter timing diagram, internal clock divided by 2 . . . . .	551
Figure 157. Counter timing diagram, internal clock divided by 4 . . . . .	551
Figure 158. Counter timing diagram, internal clock divided by N . . . . .	552
Figure 159. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .	552
Figure 160. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .	553
Figure 161. Counter timing diagram, internal clock divided by 1 . . . . .	554
Figure 162. Counter timing diagram, internal clock divided by 2 . . . . .	554
Figure 163. Counter timing diagram, internal clock divided by 4 . . . . .	555
Figure 164. Counter timing diagram, internal clock divided by N . . . . .	555
Figure 165. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .	557
Figure 166. Counter timing diagram, internal clock divided by 2 . . . . .	557
Figure 167. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	558
Figure 168. Counter timing diagram, internal clock divided by N . . . . .	558
Figure 169. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .	559
Figure 170. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .	559
Figure 171. Control circuit in normal mode, internal clock divided by 1 . . . . .	560
Figure 172. TI2 external clock connection example. . . . .	561
Figure 173. Control circuit in external clock mode 1 . . . . .	562
Figure 174. External trigger input block . . . . .	562
Figure 175. Control circuit in external clock mode 2 . . . . .	563
Figure 176. Capture/compare channel (example: channel 1 input stage). . . . .	564
Figure 177. Capture/compare channel 1 main circuit . . . . .	564
Figure 178. Output stage of capture/compare channel (channel 1 and 2). . . . .	565
Figure 179. PWM input mode timing . . . . .	567
Figure 180. Output compare mode, toggle on OC1 . . . . .	569
Figure 181. Edge-aligned PWM waveforms (ARR=8). . . . .	570
Figure 182. Center-aligned PWM waveforms (ARR=8). . . . .	571
Figure 183. Clearing TIMx_OCxREF . . . . .	573
Figure 184. Example of one pulse mode . . . . .	574
Figure 185. Example of counter operation in encoder interface mode . . . . .	576
Figure 186. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .	577
Figure 187. Control circuit in reset mode . . . . .	578
Figure 188. Control circuit in gated mode . . . . .	579
Figure 189. Control circuit in trigger mode . . . . .	580
Figure 190. Basic timer block diagram . . . . .	600
Figure 191. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	602
Figure 192. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	602
Figure 193. Counter timing diagram, internal clock divided by 1 . . . . .	603
Figure 194. Counter timing diagram, internal clock divided by 2 . . . . .	604
Figure 195. Counter timing diagram, internal clock divided by 4 . . . . .	604
Figure 196. Counter timing diagram, internal clock divided by N . . . . .	605
Figure 197. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .	605
Figure 198. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .	606

Figure 199. Control circuit in normal mode, internal clock divided by 1 . . . . .	607
Figure 200. Low-power timer block diagram . . . . .	614
Figure 201. Glitch filter timing diagram . . . . .	616
Figure 202. LPTIM output waveform, single counting mode configuration . . . . .	618
Figure 203. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set). . . . .	618
Figure 204. LPTIM output waveform, Continuous counting mode configuration . . . . .	619
Figure 205. Waveform generation . . . . .	620
Figure 206. Encoder mode counting sequence . . . . .	623
Figure 207. Independent watchdog block diagram . . . . .	634
Figure 208. Watchdog block diagram . . . . .	644
Figure 209. Window watchdog timing diagram . . . . .	645
Figure 210. RTC block diagram . . . . .	651
Figure 211. I2C1/3 block diagram . . . . .	695
Figure 212. I2C2 block diagram . . . . .	696
Figure 213. I2C bus protocol . . . . .	698
Figure 214. Setup and hold timings . . . . .	700
Figure 215. I2C initialization flow . . . . .	703
Figure 216. Data reception . . . . .	704
Figure 217. Data transmission . . . . .	705
Figure 218. Slave initialization flow . . . . .	708
Figure 219. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0 . . . . .	710
Figure 220. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1 . . . . .	711
Figure 221. Transfer bus diagrams for I2C slave transmitter . . . . .	712
Figure 222. Transfer sequence flow for slave receiver with NOSTRETCH = 0 . . . . .	713
Figure 223. Transfer sequence flow for slave receiver with NOSTRETCH = 1 . . . . .	714
Figure 224. Transfer bus diagrams for I2C slave receiver . . . . .	714
Figure 225. Master clock generation . . . . .	716
Figure 226. Master initialization flow . . . . .	718
Figure 227. 10-bit address read access with HEAD10R = 0 . . . . .	718
Figure 228. 10-bit address read access with HEAD10R = 1 . . . . .	719
Figure 229. Transfer sequence flow for I2C master transmitter for N≤255 bytes . . . . .	720
Figure 230. Transfer sequence flow for I2C master transmitter for N>255 bytes . . . . .	721
Figure 231. Transfer bus diagrams for I2C master transmitter . . . . .	722
Figure 232. Transfer sequence flow for I2C master receiver for N≤255 bytes . . . . .	724
Figure 233. Transfer sequence flow for I2C master receiver for N >255 bytes . . . . .	725
Figure 234. Transfer bus diagrams for I2C master receiver . . . . .	726
Figure 235. Timeout intervals for $t_{LOW:SEXT}$ , $t_{LOW:MEXT}$ . . . . .	730
Figure 236. Transfer sequence flow for SMBus slave transmitter N bytes + PEC . . . . .	734
Figure 237. Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . .	735
Figure 238. Transfer sequence flow for SMBus slave receiver N Bytes + PEC . . . . .	736
Figure 239. Bus transfer diagrams for SMBus slave receiver (SBC=1). . . . .	737
Figure 240. Bus transfer diagrams for SMBus master transmitter . . . . .	738
Figure 241. Bus transfer diagrams for SMBus master receiver . . . . .	740
Figure 242. USART block diagram . . . . .	766
Figure 243. Word length programming . . . . .	768
Figure 244. Configurable stop bits . . . . .	770
Figure 245. TC/TXE behavior when transmitting . . . . .	771
Figure 246. Start bit detection when oversampling by 16 or 8 . . . . .	772
Figure 247. Data sampling when oversampling by 16 . . . . .	775
Figure 248. Data sampling when oversampling by 8 . . . . .	776
Figure 249. Mute mode using Idle line detection . . . . .	783

Figure 250. Mute mode using address mark detection . . . . .	784
Figure 251. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . .	787
Figure 252. Break detection in LIN mode vs. Framing error detection. . . . .	788
Figure 253. USART example of synchronous transmission. . . . .	789
Figure 254. USART data clock timing diagram (M bits = 00) . . . . .	789
Figure 255. USART data clock timing diagram (M bits = 01) . . . . .	790
Figure 256. RX data setup/hold time . . . . .	790
Figure 257. ISO 7816-3 asynchronous protocol . . . . .	792
Figure 258. Parity error detection using the 1.5 stop bits . . . . .	793
Figure 259. IrDA SIR ENDEC- block diagram . . . . .	797
Figure 260. IrDA data modulation (3/16) -Normal Mode . . . . .	798
Figure 261. Transmission using DMA . . . . .	799
Figure 262. Reception using DMA . . . . .	800
Figure 263. Hardware flow control between 2 USARTs . . . . .	800
Figure 264. RS232 RTS flow control . . . . .	801
Figure 265. RS232 CTS flow control . . . . .	802
Figure 266. USART interrupt mapping diagram . . . . .	805
Figure 267. LPUART block diagram . . . . .	832
Figure 268. Word length programming . . . . .	834
Figure 269. Configurable stop bits . . . . .	835
Figure 270. TC/TXE behavior when transmitting . . . . .	837
Figure 271. Mute mode using Idle line detection . . . . .	844
Figure 272. Mute mode using address mark detection . . . . .	845
Figure 273. Transmission using DMA . . . . .	848
Figure 274. Reception using DMA . . . . .	849
Figure 275. Hardware flow control between 2 LPUARTs . . . . .	849
Figure 276. RS232 RTS flow control . . . . .	850
Figure 277. RS232 CTS flow control . . . . .	851
Figure 278. LPUART interrupt mapping diagram . . . . .	855
Figure 279. SPI block diagram. . . . .	873
Figure 280. Full-duplex single master/ single slave application. . . . .	874
Figure 281. Half-duplex single master/ single slave application . . . . .	875
Figure 282. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . .	876
Figure 283. Master and three independent slaves. . . . .	877
Figure 284. Multi-master application . . . . .	878
Figure 285. Hardware/software slave select management . . . . .	879
Figure 286. Data clock timing diagram . . . . .	881
Figure 287. TXE/RXNE/BSY behavior in master / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers . . . . .	884
Figure 288. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers . . . . .	885
Figure 289. Transmission using DMA . . . . .	887
Figure 290. Reception using DMA . . . . .	888
Figure 291. TI mode transfer . . . . .	891
Figure 292. I ²S block diagram . . . . .	894
Figure 293. Full-duplex communication . . . . .	896
Figure 294. I ²S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . .	897
Figure 295. I ²S Philips standard waveforms (24-bit frame with CPOL = 0). . . . .	897
Figure 296. Transmitting 0x8EAA33 . . . . .	898
Figure 297. Receiving 0x8EAA33 . . . . .	898
Figure 298. I ²S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . .	898

Figure 299. Example of 16-bit data frame extended to 32-bit channel frame . . . . .	899
Figure 300. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . .	899
Figure 301. MSB justified 24-bit frame length with CPOL = 0 . . . . .	899
Figure 302. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .	900
Figure 303. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . .	900
Figure 304. LSB justified 24-bit frame length with CPOL = 0 . . . . .	900
Figure 305. Operations required to transmit 0x3478AE. . . . .	901
Figure 306. Operations required to receive 0x3478AE . . . . .	901
Figure 307. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . .	901
Figure 308. Example of 16-bit data frame extended to 32-bit channel frame . . . . .	902
Figure 309. PCM standard waveforms (16-bit) . . . . .	902
Figure 310. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .	902
Figure 311. Audio sampling frequency definition . . . . .	903
Figure 312. I ²S clock generator architecture . . . . .	903
Figure 313. USB peripheral block diagram . . . . .	922
Figure 314. Packet buffer areas with examples of buffer description table locations . . . . .	926
Figure 315. Block diagram of STM32L0x3 MCU and Cortex ^®-M0+-level debug support . . . . .	954

RM0367-STM32L0x3

Introduction

Contents

List of tables

List of figures

Chapters

RM0367-STM32L0x3

Introduction

Related documents

Contents

List of tables

List of figures

Chapters