31. Revision history

Reset and clock control (RCC) section

• – Updated Section 7.4.8: APB1 peripheral clock enable register (RCC_APB1ENR), Section 7.4.5: APB1 peripheral reset register (RCC_APB1RSTR), Section 7.4.13: Clock configuration register 3 (RCC_CFGR3) and Section 7.4.14: RCC register map.

System configuration controller (SYSCFG) section

• – Updated Section 9.1.7: SYSCFG configuration register 2 (SYSCFG_CFGR2) and Section 9.1.10: SYSCFG register map

Analog-digital converters (ADC) section

• – Table 42: ADC1 (master) & 2 (slave) - External triggers for regular channels,
• – Table 43: ADC1 & ADC2 - External trigger for injected channels,
• – Figure 85: VBAT channel block diagram

Updated the following sections:

Advanced-control timers (TIM1), General-purpose timers (TIM2/TIM3/TIM4/TIM15/16/17)

• – Section 19.6.16: TIM15 break and dead-time register (TIM15_BDTR),
• – Section 19.6.13: TIM16&TIM17 break and dead-time register (TIMx_BDTR),
• – Section 19.6.17: TIM16&TIM17 register map,
• – ETF[3:0] description in Section 17.4.3: TIM1 slave mode control register (TIMx_SMCR), Section 18.4.3: TIM2 slave mode control register (TIM2_SMCR)(TIM3_SMCR)(TIMx_SMCR)N/A
• – C1F[3:0] description in Section 17.4.7: TIM1 capture/compare mode register 1 (TIMx_CCMR1), Section 18.4.7: TIM2 capture/compare mode register 1 (TIM2_CCMR1)(TIM3_CCMR1)(TIMx_CCMR1)N/A, Section 19.6.8: TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1)
• – BK2F3:0] and BKF[3:0] description in Section 17.4.18: TIM1 break and dead-time register (TIMx_BDTR).

Reset and Clock (RCC)

• – the bit field for MCOPRE in Section 7.4.2: Clock configuration register (RCC_CFGR),
• – Bits [32:16] description in Section 7.4.13: Clock configuration register 3 (RCC_CFGR3),

Universal synchronous asynchronous receiver transmitter (USART)

• – Section 26: Universal synchronous/asynchronous receiver transmitter (USART/UART): addition of 0.5 stop bit in smartcard mode, addition of TCBGT bit in USARTx_CR3 and USARTx_ISR registers, addition of TCGBTFCF bit in USARTx_ICR register.

Updated I2C2 section:

• – Updated Figure 248: Setup and hold timings.
• – Updated Section 48.4.5: I2C initialization updating and adding notes in Section : I2C timings.
• – Updated Section 33.7.5: Timing register (I2C_TIMINGRFMP/I2C_TIMINGR) SCLDEL[3:0] and SDADEL[3:0] bits description.
• – Updated Section 48.4.5: I2C initialization, Section 25.4.9: I2C controller mode and Section 33.7.5: Timing register (I2C_TIMINGRFMP/I2C_TIMINGR) adding the sentence “The STM32CubeMX tool calculates and provides the I2C_TIMIGR content in the I2C configuration window”.

Updated Touch sensing controller section:

• – Updated Section 16.4.4: Charge transfer acquisition sequence adding note about the TSC control register configuration forbidden.
• – Updated Section 16.7.1: TSC control register (TSC_CR) adding note for CTPL[3:0] bits and PGPSC[2:0] bits.

Updated USART section:

• – Updated Section 26.5.17: Wake-up from Stop mode using USART adding paragraph “how to determine the maximum USART baudrate”.
• – Updated whole USART document replacing any occurrence of: nCTS by CTS, nRTS by RTS, SCLK by CK.
• – Updated Section 26.8.9: USART interrupt flag clear register (USART_ICR) replacing “w” by “rc_wl”.
• – Updated Section 26.8.8: USART interrupt and status register (USART_ISR) RTOF field replacing USARTx_CR2 by USARTx_CR1.
• – Updated Section 26.8.3: USART control register 3 (USART_CR3) ‘ONEBIT’ bit 11 description adding a note.
• – Updated Section 26: Universal synchronous/asynchronous receiver transmitter (USART/UART) changing register name USARTx_regname in USART_regname.
• – Changed tWUSTOP to tWUUSART and updated Section 26.5.5: Tolerance of the USART receiver to clock deviation.
• – Added Section : Determining the maximum USART baud rate allowing to wake up correctly from Stop mode when the USART clock source is the HSI clock.
• – Updated Section 26.5.17: Wake-up from Stop mode using USART adding paragraph about USART/LPUART HSI or LSE source clocks.

Updated RTC section:

• – Updated Section 24.3.7: RTC initialization and configuration step 3 in Section : Programming the wakeup timer .
• – Updated Section 24.6.4: RTC initialization and status register (RTC_ISR) bit 2 WUTWF: wakeup timer write flag.
• – Updated WUCKSEL bits in Figure 241: RTC block diagram .
• – Added case of RTC clocked by LSE in Section 24.3.9: Resetting the RTC .
• – Updated Figure 241: RTC block diagram adding note.
• – Updated section with only 2 RTC Tamper.
• – Updated Section 24.3.15: Calibration clock output .
• – Added caution at the end of Section 24.6.3: RTC control register (RTC_CR) .
• – Updated caution at the end of Section 24.6.16: RTC tamper and alternate function configuration register (RTC_TAFCR) .

Updated RCC section:

• – Updated Section 7.4.9: RTC domain control register (RCC_BDCR) LSEDRV[1:0] bits: '01' and '10' combinations swapped.
• – Updated Section 7.2.9: RTC clock adding “the RTC remains clocked and functional under system reset” when the RTC clock is LSE.
• – Updated Figure 14: STM32F318x8STM32F3xx clock tree replacing ‘USARTx (x=1,2,3)’ by ‘USART1’
• – Updated Section 7.4.10: Control/status register (RCC_CSR) and Updated Section 7.4.14: RCC register map adding V18PWRIRSTF bit 23.

Updated TIMERS section:

• – Updated Section 18.3.13: One-pulse mode modifying “IC2S=01” by “CC2S=01”.
• – Updated Section 19.5.21: Slave mode – combined reset + trigger mode (TIM15 only) adding (TIM15 only) on the title.
• – Updated Section 19.6.8: TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) and Section 19.6.27: TIM15 register map replacing bit 7 ‘reserved’ by OC1CE.
• – Updated Section 19.7.6: TIMx capture/compare mode register 1 (TIM16_CCMR1) (TIMx_CCMR1)(x = 16 to 17) and Section 19.7.41: TIM16/TIM17 register map replacing bit 7 ‘reserved’ by OC1CE.
• – Added Section 17.3.4: External trigger input .
• – Updated Section 18.4.14: TIM2 prescaler (TIM2_PSC)(TIM3_PSC)(TIMx_PSC)N/A and Section 20.4.7: TIM6TIMx prescaler (TIM6_PSC)(TIMx_PSC)(x = 6 to 7)(x = 3 to 7) PSC[15:0] bits description .
• – Updated Section 17.4.5: TIM1 status register (TIM1_SRTIMx_SR)N/A and Section 17.4.68: TIM1 register map CC5IF and CC6IF bit names.

Updated Embedded Flash memory section:

• – Updated Section 3.5.1: Flash access control register (FLASH_ACR) bits LATENCY[2:0] replacing SYSCLK by HCLK.

Updated ADC section:

• – Updated Section 12.3.3: Clocks note, replacing option a) by option b) and removing 'or 10'.

Updated Operational amplifier section (OPAMP) section:

• – Updated Section Table 55.: Connections with dedicated I/O on STM32F318x8 PD14 instead of PB14 on VP1.

Updated interrupts and events section:

• – Updated Table 32: STM32F318x8STM32F3xx vector table :
  • - Replacing 'USART2 global interrupt & EXTI Line 26' by 'USART2 global interrupt' and 'USART3 global interrupt & EXTI Line 28' by 'USART3 global interrupt'.
  • - Adding I2C2 event interrupt and I2C2 error interrupt.
• – Updated Section 11.2.6: External and internal interrupt/event line mapping putting EXTI Line 26 & 28 reserved and updating the note.
• – Updated Interrupt mask register (EXTI_IMR1) and Event mask register (EXTI_EMR1) bits 18, 21, 26, 28, 29, 31 reserved.
• – Updated Rising trigger selection register (EXTI_RTSR1) , Falling trigger selection register (EXTI_FTSR1) , Software interrupt event register (EXTI_SWIER1) and Pending register (EXTI_PR1) bits 18, 21, 23 to 29, 31 reserved.
• – Updated Section 11.3.7: Interrupt mask register (EXTI_IMR2) and Section 11.3.8: Event mask register (EXTI_EMR2) bits 3,2,1 reserved.
• – Updated Section 11.3.9: Rising trigger selection register (EXTI_RTSR2) , Section 11.3.10: Falling trigger selection register (EXTI_FTSR2) , Section 11.3.11: Software interrupt event register (EXTI_SWIER2) and Section 11.3.12: Pending register (EXTI_PR2) bit 1 reserved.

Updated:

• – Figure 1: System architecture
• – Note removed from Section 3.3.1: Read protection (RDP)
• – Typo in FLASH_SR bits
• – Section 6.2.2: Programmable voltage detector (PVD)
• – Section 7.1.2: System reset
• – SYSCFGEN bit description in Section 7.4.7: APB2 peripheral clock enable register (RCC_APB2ENR)
• – Section 24: Real-time clock (RTC)
• – Section 28.4.2: Flexible SWJ-DP pin assignment

Added:

• – Section 30: Important security notice

Master and slave terms in Section 25: Inter-integrated circuit interface (I2C) replaced with controller and target, respectively.