11. Interrupts and events

11.1 Nested vectored interrupt controller (NVIC)

11.1.1 NVIC main features

• • 66 maskable interrupt channels (not including the sixteen Cortex-M4 with FPU interrupt lines)
• • 16 programmable priority levels (4 bits of interrupt priority are used)
• • Low-latency exception and interrupt handling
• • Power management control
• • Implementation of System Control Registers

The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts.

All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to the PM0214 programming manual for Cortex-M4 products.

11.1.2 SysTick calibration value register

The SysTick calibration value is set to 9000, which gives a reference time base of 1 ms with the SysTick clock set to 9 MHz (max \( f_{HCLK}/8 \) ).

11.1.3 Interrupt and exception vectors

Table 28. STM32F3xx vector table

Table 28. STM32F3xx vector table (continued)

Table 28. STM32F3xx vector table (continued)

Table 28. STM32F3xx vector table (continued)

11.2 Extended interrupts and events controller (EXTI)

The extended interrupts and events controller (EXTI) manages the external and internal asynchronous events/interrupts and generates the event request to the CPU/Interrupt Controller and a wake-up request to the Power Manager.

The EXTI allows the management of up to 36 external/internal event line (28 external event lines and 8 internal event lines).

The active edge of each external interrupt line can be chosen independently, whilst for internal interrupt the active edge is always the rising one. An interrupt could be left pending: in case of an external one, a status register is instantiated and indicates the source of the interrupt; an event is always a simple pulse and it is used for triggering the core wake-up. For internal interrupts, the pending status is assured by the generating peripheral, so no need for a specific flag. Each input line can be masked independently for interrupt or event

generation, in addition, the internal lines are sampled only in STOP mode. This controller allows also to emulate the (only) external events by software, multiplexed with the corresponding hardware event line, by writing to a dedicated register.

11.2.1 Main features

The EXTI main features are the following:

• • support generation of up to 36 event/interrupt requests
• • Independent configuration of each line as an external or an internal event requests
• • Independent mask on each event/interrupt line
• • Automatic disable of internal lines when system is not in STOP mode
• • Independent trigger for external event/interrupt line
• • Dedicated status bit for external interrupt line
• • Emulation for all the external event requests.

11.2.2 Block diagram

The extended interrupt/event block diagram is shown in the following figure.

Figure 22. External interrupt/event block diagram

11.2.3 Wake-up event management

STM32F3xx devices are able to handle external or internal events to wake up the core (WFE). The wake-up event can be generated either by:

• • enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex-M4 System Control register. When the MCU resumes from WFE, the EXTI peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
• • or by configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set.

11.2.4 Asynchronous Internal Interrupts

Some communication peripherals (UART, I2C) are able to generate events when the system is in run mode and also when the system is in stop mode allowing to wake up the system from stop mode.

To accomplish this, the peripheral is asked to generate both a synchronized (to the system clock, for example, APB clock) and an asynchronous version of the event.

11.2.5 Functional description

For the external interrupt lines, to generate the interrupt, the interrupt line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a '1' to the corresponding bit in the interrupt mask register. When the selected edge occurs on the external interrupt line, an interrupt request is generated. The pending bit corresponding to the interrupt line is also set. This request is reset by writing a 1 in the pending register.

For the internal interrupt lines, the active edge is always the rising edge. The interrupt is enabled by default in the interrupt mask register and there is no corresponding pending bit in the pending register.

To generate the event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a '1' to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set.

For the external lines, an interrupt/event request can also be generated by software by writing a 1 in the software interrupt/event register.

Note: The interrupts or events associated to the internal lines can be triggered only when the system is in STOP mode. If the system is still running, no interrupt/event is generated.

Hardware interrupt selection

To configure a line as interrupt source, use the following procedure:

• • Configure the corresponding mask bit in the EXTI_IMR register.
• • Configure the Trigger Selection bits of the Interrupt line (EXTI_RTSR and EXTI_FTSR)
• • Configure the enable and mask bits that control the NVIC IRQ channel mapped to the EXTI so that an interrupt coming from one of the EXTI lines can be correctly acknowledged.

Hardware event selection

To configure a line as event source, use the following procedure:

• • Configure the corresponding mask bit in the EXTI_EMR register.
• • Configure the Trigger Selection bits of the Event line (EXTI_RTSR and EXTI_FTSR)

Software interrupt/event selection

Any of the external lines can be configured as software interrupt/event lines. The following is the procedure to generate a software interrupt.

• • Configure the corresponding mask bit (EXTI_IMR, EXTI_EMR)
• • Set the required bit of the software interrupt register (EXTI_SWIER)

11.2.6 External and internal interrupt/event line mapping

36 interrupt/event lines are available: 8 lines are internal (including the reserved ones); the remaining 28 lines are external.

The GPIOs are connected to the 16 external interrupt/event lines in the following manner:

Figure 23. External interrupt/event GPIO mapping

MS34225V1

The remaining lines are connected as follows:

• • EXTI line 16 is connected to the PVD output
• • EXTI line 17 is connected to the RTC Alarm event
• • EXTI line 18 is reserved
• • EXTI line 19 is connected to RTC tamper and timestamps
• • EXTI line 20 is connected to RTC wake-up timer
• • EXTI line 21 is reserved
• • EXTI line 22 is connected to Comparator 2 output
• • EXTI line 23 is connected to I2C1 wake-up
• • EXTI line 24 is connected to I2C2 wake-up
• • EXTI line 25 is connected to USART1 wake-up
• • EXTI line 26 is reserved
• • EXTI line 27 is connected to I2C3 wake-up
• • EXTI line 28 is reserved
• • EXTI line 29 is reserved
• • EXTI line 30 is connected to Comparator 4 output
• • EXTI line 31 is reserved
• • EXTI line 32 is connected to Comparator 6 output
• • EXTI line 33 is reserved
• • EXTI line 34 is reserved
• • EXTI line 35 is reserved

Note: EXTI lines 23, 24, 25 and 27 are internal.

11.3 EXTI registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.

The peripheral registers have to be accessed by words (32-bit).

11.3.1 Interrupt mask register (EXTI_IMR1)

Address offset: 0x00

Reset value: 0x1F80 0000 (Refer to the note below)

Bit 31 Reserved, must be kept at reset value.

Bit 30 MRx : Interrupt Mask on external/internal line x (x = 30)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is not masked

Bit 29 Reserved, must be kept at reset value.

Bits 29:28 Reserved, must be kept at reset value.

Bit 27 MRx : Interrupt Mask on external/internal line x (x = 27)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is not masked

Bit 26 Reserved, must be kept at reset value.

Bits 25:22 MRx : Interrupt Mask on external/internal line x (x = 25 to 22)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is not masked

Bit 21 Reserved, must be kept at reset value.

Bits 20:19 MRx : Interrupt Mask on external/internal line x (x = 20 to 19)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is not masked

Bit 18 Reserved, must be kept at reset value.

Bits 17:0 MRx : Interrupt Mask on external/internal line x (x = 17 to 0)

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is not masked

Note: The reset value for the internal lines (23, 24, 25, 26, 27 and 28) is set to '1' to enable the interrupt by default.

11.3.2 Event mask register (EXTI_EMR1)

Address offset: 0x04

Reset value: 0x0000 0000

Bit 31 Reserved, must be kept at reset value.

Bit 30 MRx : Event mask on external/internal line x (x = 30)

0: Event request from Line x is masked

1: Event request from Line x is not masked

Bits 29:28 Reserved, must be kept at reset value.

1. Bit 27 MRx : Event Mask on external/internal line x (x = 27)
   0: Event request from Line x is masked
   1: Event request from Line x is not masked
2. Bit 27 Reserved, must be kept at reset value.
3. Bit 26 Reserved, must be kept at reset value.
4. Bits 25:22 MRx : Event Mask on external/internal line x (x = 25 to 22)
   0: Event request from Line x is masked
   1: Event request from Line x is not masked
5. Bit 24 Reserved, must be kept at reset value.
6. Bit 21 Reserved, must be kept at reset value.
7. Bits 20:19 MRx : Event Mask on external/internal line x (x = 20 to 19)
   0: Event request from Line x is masked
   1: Event request from Line x is not masked
8. Bit 18 Reserved, must be kept at reset value.
9. Bits 17:0 MRx : Event Mask on external/internal line x (x = 17 to 0)
   0: Event request from Line x is masked
   1: Event request from Line x is not masked

11.3.3 Rising trigger selection register (EXTI_RTSR1)

Address offset: 0x08

Reset value: 0x0000 0000

1. Bit 31 Reserved, must be kept at reset value.
2. Bit 30 TRx : Rising trigger event configuration bit of line x (x = 30)
   0: Rising trigger disabled (for Event and Interrupt) for input line
   1: Rising trigger enabled (for Event and Interrupt) for input line.
3. Bits 29:23 Reserved, must be kept at reset value.
4. Bit 22 TRx : Rising trigger event configuration bit of line x (x = 22)
   0: Rising trigger disabled (for Event and Interrupt) for input line
   1: Rising trigger enabled (for Event and Interrupt) for input line.
5. Bit 21 Reserved, must be kept at reset value.

Bits 20:19 TRx : Rising trigger event configuration bit of line x (x = 20 to 19)

0: Rising trigger disabled (for Event and Interrupt) for input line

1: Rising trigger enabled (for Event and Interrupt) for input line.

Bit 18 Reserved, must be kept at reset value.

Bits 17:0 TRx : Rising trigger event configuration bit of line x (x = 17 to 0)

0: Rising trigger disabled (for Event and Interrupt) for input line

1: Rising trigger enabled (for Event and Interrupt) for input line.

Note: The external wake-up lines are edge-triggered. No glitches must be generated on these lines. If a rising edge on an external interrupt line occurs during a write operation in the EXTI_RTSR register, the pending bit is not set.

Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.

11.3.4 Falling trigger selection register (EXTI_FTSR1)

Address offset: 0x0C

Reset value: 0x0000 0000

Bit 31 Reserved, must be kept at reset value.

Bit 30 TRx : Falling trigger event configuration bit of line x (x = 30)

0: Falling trigger disabled (for Event and Interrupt) for input line

1: Falling trigger enabled (for Event and Interrupt) for input line.

Bits 29:23 Reserved, must be kept at reset value.

Bit 22 TRx : Falling trigger event configuration bit of line x (x = 22)

0: Falling trigger disabled (for Event and Interrupt) for input line

1: Falling trigger enabled (for Event and Interrupt) for input line.

Bit 21 Reserved, must be kept at reset value.

Bits 20:19 TRx : Falling trigger event configuration bit of line x (x = 20 to 19)

0: Falling trigger disabled (for Event and Interrupt) for input line

1: Falling trigger enabled (for Event and Interrupt) for input line.

Bit 18 Reserved, must be kept at reset value.

Bits 17:0 TRx : Falling trigger event configuration bit of line x (x = 17 to 0)

0: Falling trigger disabled (for Event and Interrupt) for input line

1: Falling trigger enabled (for Event and Interrupt) for input line.

Note: The external wake-up lines are edge-triggered. No glitches must be generated on these lines. If a falling edge on an external interrupt line occurs during a write operation to the EXTI_FTSR register, the pending bit is not set.

Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.

11.3.5 Software interrupt event register (EXTI_SWIER1)

Address offset: 0x10

Reset value: 0x0000 0000

Bit 31 Reserved, must be kept at reset value.

Bit 30 SWIERx : Software interrupt on line x (x = 30)

If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation.

This bit is cleared by clearing the corresponding bit in the EXTI_PR register (by writing a '1' into the bit).

Bits 29:23 Reserved, must be kept at reset value.

Bit 22 SWIERx : Software interrupt on line x (x = 22)

If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation.

This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a '1' into the bit).

Bit 21 Reserved, must be kept at reset value.

Bits 20:19 SWIERx : Software interrupt on line x (x = 22 to 19)

If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation.

This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a '1' into the bit).

Bit 18 Reserved, must be kept at reset value.

Bits 17:0 SWIERx : Software interrupt on line x (x = 17 to 0)

If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation.

This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a '1' into the bit).

11.3.6 Pending register (EXTI_PR1)

Address offset: 0x14

Reset value: 0x0000 0000

Bit 31 Reserved, must be kept at reset value.

Bit 30 PRx : Pending bit on line x (x = 30)

0: No trigger request occurred

1: Selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line.

This bit is cleared by writing a '1' to the bit.

Bits 29:23 Reserved, must be kept at reset value.

Bit 22 PRx : Pending bit on line x (x = 22)

0: No trigger request occurred

1: Selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line.

This bit is cleared by writing a '1' to the bit.

Bit 21 Reserved, must be kept at reset value.

Bits 20:19 PRx : Pending bit on line x (x = 20 to 19)

0: No trigger request occurred

1: Selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line.

This bit is cleared by writing a '1' to the bit.

Bit 18 Reserved, must be kept at reset value.

Bits 17:0 PRx : Pending bit on line x (x = 17 to 0)

0: No trigger request occurred

1: Selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line.

This bit is cleared by writing a '1' to the bit.

11.3.7 Interrupt mask register (EXTI_IMR2)

Address offset: 0x20

Reset value: 0xFFFF FFFE (See note below)

Bits 31:1 Reserved, must be kept at reset value

Bit 0 MRx : Interrupt mask on external/internal line x, x = 32

0: Interrupt request from Line x is masked

1: Interrupt request from Line x is not masked

Note: The reset value for the reserved lines is set to '1'.

11.3.8 Event mask register (EXTI_EMR2)

Address offset: 0x24

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value

Bit 0 MR32 : Event mask on external/internal line x, x = 32

0: Event request from Line x is masked

1: Event request from Line x is not masked

11.3.9 Rising trigger selection register (EXTI_RTSR2)

Address offset: 0x28

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 TRx : Rising trigger event configuration bit of line x (x = 32)

0: Rising trigger disabled (for Event and Interrupt) for input line

1: Rising trigger enabled (for Event and Interrupt) for input line.

Note: The external wake-up lines are edge-triggered. No glitches must be generated on these lines. If a rising edge on an external interrupt line occurs during a write operation to the EXTI_RTSR register, the pending bit is not set.

Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.

11.3.10 Falling trigger selection register (EXTI_FTSR2)

Address offset: 0x2C

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 TRx : Falling trigger event configuration bit of line x (x = 32)

0: Falling trigger disabled (for Event and Interrupt) for input line

1: Falling trigger enabled (for Event and Interrupt) for input line.

Note: The external wake-up lines are edge-triggered. No glitches must be generated on these lines. If a falling edge on an external interrupt line occurs during a write operation to the EXTI_FTSR register, the pending bit is not set.

Rising and falling edge triggers can be set for the same interrupt line. In this case, both generate a trigger condition.r

11.3.11 Software interrupt event register (EXTI_SWIER2)

Address offset: 0x30

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 SWIERx : Software interrupt on line x (x = 32)

If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an interrupt request generation.

This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a '1' to the bit).

11.3.12 Pending register (EXTI_PR2)

Address offset: 0x34

Reset value: 0x0000 0000

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 PRx : Pending bit on line x (x = 32)

• 0: No trigger request occurred
• 1: Selected trigger request occurred

This bit is set when the selected edge event arrives on the external interrupt line.

This bit is cleared by writing a '1' into the bit.

11.3.13 EXTI register map

Table 29. External interrupt/event controller register map and reset values

Table 29. External interrupt/event controller register map and reset values (continued)

Refer to Section 2.2 on page 40 for the register boundary addresses.