9. System configuration controller (SYSCFG)

The STM32F3xx devices feature a set of configuration registers. The main purposes of the system configuration controller are the following:

• Enabling/disabling I ²C Fm+ on some I/O ports
• Remapping some DMA trigger sources from TIM16, TIM17, TIM6, DAC1_CH1 to different DMA channels
• Remapping the memory located at the beginning of the code area
• Managing the external interrupt line connection to the GPIOs
• Remapping TIM1 ITR3 source
• Remapping DAC1 triggers
• Managing robustness feature
• Configuring encoder mode

9.1 SYSCFG registers

9.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1)

This register is used for specific configurations on memory remap.

Two bits are used to configure the type of memory accessible at address 0x0000 0000. These bits are used to select the physical remap by software and so, bypass the BOOT pin and the option bit setting.

After reset these bits take the value selected by the BOOT pin (BOOT0) and by the option bit (BOOT1).

Address offset: 0x00

Reset value: 0x7C00 000X (X is the memory mode selected by the BOOT0 pin and BOOT1 option bit)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FPU_IE[5:0]						Res	I2C3_FMP	ENCODER_MODE	I2C2_FMP	I2C1_FMP	I2C_PB9_FMP	I2C_PB8_FMP	I2C_PB7_FMP	I2C_PB6_FMP
rw	rw	rw	rw	rw	rw		rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res	Res	TIM6_DAC1_DMA_RMP	TIM17_DMA_RMP	TIM16_DMA_RMP	Res	Res	Res	Res	TIM1_ITR3_RMP	Res	Res	Res	Res	MEM_MODE
		rw	rw	rw					rw					rw	rw

Bits 31:26 FPU_IE[5..0] : Floating Point Unit interrupts enable bits

FPU_IE[5]: Inexact interrupt enable

FPU_IE[4]: Input normal interrupt enable

FPU_IE[3]: Overflow interrupt enable

FPU_IE[2]: underflow interrupt enable

FPU_IE[1]: Divide-by-zero interrupt enable

FPU_IE[0]: Invalid operation interrupt enable

Bit 25 Reserved, must be kept at reset value.

Bit 24 I2C3_FMP : I2C3 fast mode Plus driving capability activation

This bit is set and cleared by software. It enables the Fm+ on I2C3 pins selected through AF selection bits.

0: Fm+ mode is not enabled on I2C3 pins selected through AF selection bits

1: Fm+ mode is enabled on I2C3 pins selected through AF selection bits.

Bits 23:22 ENCODER_MODE : Encoder mode

This bit is set and cleared by software.

00: No redirection.

01: TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively.

10: Reserved

11: Reserved.

Bit 21 I2C2_FMP : I2C2 fast mode Plus driving capability activation

This bit is set and cleared by software. It enables the Fm+ on I2C2 pins selected through AF selection bits.

0: Fm+ mode is not enabled on I2C2 pins selected through AF selection bits

1: Fm+ mode is enabled on I2C2 pins selected through AF selection bits.

Bit 20 I2C1_FMP : I2C1 Fm+ driving capability activation

This bit is set and cleared by software. It enables the Fm+ on I2C1 pins selected through AF selection bits.

0: Fm+ mode is not enabled on I2C1 pins selected through AF selection bits

1: Fm+ mode is enabled on I2C1 pins selected through AF selection bits.

Bits 19:16 I2C_PBx_FMP : Fm+ driving capability activation on the pad

These bits are set and cleared by software. Each bit enables I ²C Fm+ mode for PB6, PB7, PB8, and PB9 I/Os.

0: PBx pin operates in standard mode (Sm), x = 6..9

1: I ²C Fm+ mode enabled on PBx pin, and the Speed control is bypassed.

Bits 15:14 Reserved, must be kept at reset value.

Bit 13 TIM6_DAC1_CH1_DMA_RMP : TIM6 and DAC channel1 DMA remap

This bit must to be set by software in order to remap TIM6_UP and DAC_CH1 DMA requests on DMA1 channel 3. This bit is set and cleared by software. It controls the remapping of TIM6 (UP) and DAC channel1 DMA request.

0: No remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA2 channel 3)

1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3)

Bit 12 TIM17_DMA_RMP : TIM17 DMA request remapping bit

This bit is set and cleared by software. It controls the remapping of TIM17 DMA request.

0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 1)

1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7)

Bit 11 TIM16_DMA_RMP : TIM16 DMA request remapping bit

This bit is set and cleared by software. It controls the remapping of TIM16 DMA request.

0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 3)

1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6)

Bits 10:7 Reserved, must be kept at reset value.

Bit 6 TIM1_ITR3_RMP : Timer 1 ITR3 selection

This bit is set and cleared by software. It controls the mapping of TIM1 ITR3.

0: No remap

1: Remap (TIM1_ITR3 = TIM17_OC)

Bits 5:2 Reserved, must be kept at reset value.

Bits 1:0 MEM_MODE : Memory mapping selection bits

This bit is set and cleared by software. It controls the memory internal mapping at address 0x0000 0000. After reset these bits take on the memory mapping selected by BOOT0 pin and BOOT1 option bit.

x0: Main Flash memory mapped at 0x0000 0000

01: System Flash memory mapped at 0x0000 0000

11: Embedded SRAM (on the D-Code bus) mapped at 0x0000 0000

9.1.2 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)

Address offset: 0x08

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTI3[3:0]				EXTI2[3:0]				EXTI1[3:0]				EXTI0[3:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 EXTI3[3:0] : EXTI 3 configuration bits

These bits are written by software to select the source input for the EXTI3 external interrupt.

x000: PA[3] pin
x001: PB[3] pin
x010: PC[3] pin
other configurations: reserved

Bits 11:8 EXTI2[3:0] : EXTI 2 configuration bits

These bits are written by software to select the source input for the EXTI2 external interrupt.

x000: PA[2] pin
x001: PB[2] pin
x010: PC[2] pin
x011: PD[2] pin
other configurations: reserved

Bits 7:4 EXTI1[3:0] : EXTI 1 configuration bits

These bits are written by software to select the source input for the EXTI1 external interrupt.

x000: PA[1] pin
x001: PB[1] pin
x010: PC[1] pin
x101: PF[1] pin
other configurations: reserved

Bits 3:0 EXTI0[3:0] : EXTI 0 configuration bits

These bits are written by software to select the source input for the EXTI0 external interrupt.

Note: x000: PA[0] pin
x001: PB[0] pin
x010: PC[0] pin
x101: PF[0] pin
other configurations: reserved

9.1.3 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2)

Address offset: 0x0C

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTI7[3:0]				EXTI6[3:0]				EXTI5[3:0]				EXTI4[3:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 EXTI7[3:0] : EXTI 7 configuration bits

These bits are written by software to select the source input for the EXTI7 external interrupt.

x000: PA[7] pin

x001: PB[7] pin

x010: PC[7] pin

Other configurations: reserved

Bits 11:8 EXTI6[3:0] : EXTI 6 configuration bits

These bits are written by software to select the source input for the EXTI6 external interrupt.

x000: PA[6] pin

x001: PB[6] pin

x010: PC[6] pin

Other configurations: reserved

Bits 7:4 EXTI5[3:0] : EXTI 5 configuration bits

These bits are written by software to select the source input for the EXTI5 external interrupt.

x000: PA[5] pin

x001: PB[5] pin

x010: PC[5] pin

Other configurations: reserved

Bits 3:0 EXTI4[3:0] : EXTI 4 configuration bits

These bits are written by software to select the source input for the EXTI4 external interrupt.

x000: PA[4] pin

x001: PB[4] pin

x010: PC[4] pin

Other configurations: reserved

Note: Some of the I/O pins mentioned in the above register may not be available on small packages.

9.1.4 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3)

Address offset: 0x10

Reset value: 0x0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTI11[3:0]				EXTI10[3:0]				EXTI9[3:0]				EXTI8[3:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 EXTI11[3:0] : EXTI 11 configuration bits

These bits are written by software to select the source input for the EXTI11 external interrupt.

x000: PA[11] pin
x001: PB[11] pin
x010: PC[11] pin
other configurations: reserved

Bits 11:8 EXTI10[3:0] : EXTI 10 configuration bits

These bits are written by software to select the source input for the EXTI10 external interrupt.

x000: PA[10] pin
x001: PB[10] pin
x010: PC[10] pin
other configurations: reserved

Bits 7:4 EXTI9[3:0] : EXTI 9 configuration bits

These bits are written by software to select the source input for the EXTI9 external interrupt.

x000: PA[9] pin
x001: PB[9] pin
x010: PC[9] pin
other configurations: reserved

Bits 3:0 EXTI8[3:0] : EXTI 8 configuration bits

These bits are written by software to select the source input for the EXTI8 external interrupt.

x000: PA[8] pin
x001: PB[8] pin
x010: PC[8] pin
other configurations: reserved

Note: Some of the I/O pins mentioned in the above register may not be available on small packages.

9.1.5 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)

Address offset: 0x14

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EXTI15[3:0]				EXTI14[3:0]				EXTI13[3:0]				EXTI12[3:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:12 EXTI15[3:0] : EXTI15 configuration bits

These bits are written by software to select the source input for the EXTI15 external interrupt.

x000: PA[15] pin

x001: PB[15] pin

x010: PC[15] pin

Other configurations: reserved

Bits 11:8 EXTI14[3:0] : EXTI14 configuration bits

These bits are written by software to select the source input for the EXTI14 external interrupt.

x000: PA[14] pin

x001: PB[14] pin

x010: PC[14] pin

Other configurations: reserved

Bits 7:4 EXTI13[3:0] : EXTI13 configuration bits

These bits are written by software to select the source input for the EXTI13 external interrupt.

x000: PA[13] pin

x001: PB[13] pin

x010: PC[13] pin

Other configurations: reserved

Bits 3:0 EXTI12[3:0] : EXTI12 configuration bits

These bits are written by software to select the source input for the EXTI12 external interrupt.

x000: PA[12] pin

x001: PB[12] pin

x010: PC[12] pin

Other configurations: reserved

Note: Some of the I/O pins mentioned in the above register may not be available on small packages.

9.1.6 SYSCFG configuration register 2 (SYSCFG_CFGR2)

Address offset: 0x18

System reset value: 0x0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	PVD_LOCK ⁽¹⁾	Res	Res
													rw

1. This bit is not available on the STM32F318xx

Bits 31:3 Reserved, must be kept at reset value

Bit 3 Reserved, must be kept at reset value

Bit 2 PVD_LOCK : PVD lock enable bit

This bit is set by software and cleared by a system reset. It can be used to enable and lock the PVD connection to TIM1/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register.

0: PVD interrupt disconnected from TIM1/15/16/17 Break input. PVDE and PLS[2:0] bits can be programmed by the application.

1: PVD interrupt connected to TIM1/15/16/17 Break input, PVDE and PLS[2:0] bits are read only (This bit is not available on the STM32F318xx).

Bits 1: 0 Reserved, must be kept at reset value

9.1.7 SYSCFG register map

Table 22. SYSCFG register map and reset values

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	SYSCFG_CFGR1	FPU_IE[5:0]						Res	I2C3_FMP	ENCODER_MODE [1:0]	Res	I2C2_FMP	I2C1_FMP	I2C_PB9_FMP	I2C_PB8_FMP	I2C_PB7_FMP	I2C_PB6_FMP	Res	Res	TIM6_DAC1_DMA_RMP	TIM17_DMA_RMP	TIM16_DMA_RMP	Res	Res	Res	DAC_TRIG_RMP	TIM1_ITH3_RMP	Res	Res	Res	Res	MEM_MODE
0x00	Reset value	1	1	1	1	1	0			0	0	0	0	0	0	0	0			0	0	0				0	0					X	X
0x08	SYSCFG_EXTICR1	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	EXTI3[3:0]				EXTI2[3:0]				EXTI1[3:0]				EXTI0[3:0]
0x08	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x0C	SYSCFG_EXTICR2	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	EXTI7[3:0]				EXTI6[3:0]				EXTI5[3:0]				EXTI4[3:0]
0x0C	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x10	SYSCFG_EXTICR3	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	EXTI11[3:0]				EXTI10[3:0]				EXTI9[3:0]				EXTI8[3:0]
0x10	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x14	SYSCFG_EXTICR4	Res.	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	EXTI15[3:0]				EXTI14[3:0]				EXTI13[3:0]				EXTI12[3:0]
0x14	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x18	SYSCFG_CFGR2	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res.	Res	Res	Res	Res.	Res	Res	PVD_LOCK ⁽¹⁾	Res.
0x18	Reset value																														0

1. This bit is not available on the STM32F318xx

Refer to Section 2.2 on page 40 for the register boundary addresses.