RM0366-STM32F301x6-8-318x8

This reference manual targets application developers. It provides complete information on how to use the STM32F301x6/8 and STM32F318x8 microcontroller memory and peripherals. The STM32F301x6/8 and STM32F318x8 devices will be referred to as “STM32F3xx” throughout the document, unless otherwise specified.

The STM32F3xx is a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the applicable datasheets.

For information on the Arm ^®Cortex ^®-M4 core with FPU, refer to the Cortex ^®-M4F technical reference manual.

STM32F3xx microcontrollers include ST state-of-the-art patented technology.

Available from STMicroelectronics web site www.st.com :

• STM32F301x6/8 and STM32F318x8 datasheets
• STM32F301x6/8 device errata sheet (ES0237)
• STM32F318 device errata sheet (ES0257)
• STM32F3xx/STM32F4xx Cortex ^®-M4 programming manual (PM0214)

1	Documentation conventions . . . . .	36
1.1	General information . . . . .	36
1.2	List of abbreviations for registers . . . . .	36
1.3	Register reset value . . . . .	36
1.4	Glossary . . . . .	37
1.5	Availability of peripherals . . . . .	37
2	System and memory overview . . . . .	38
2.1	System architecture . . . . .	38
2.1.1	S0: I-bus . . . . .	39
2.1.2	S1: D-bus . . . . .	39
2.1.3	S2: S-bus . . . . .	39
2.1.4	S3: DMA-bus . . . . .	39
2.1.5	BusMatrix . . . . .	39
2.2	Memory organization . . . . .	40
2.2.1	Introduction . . . . .	40
2.2.2	Memory map and register boundary addresses . . . . .	41
2.3	Embedded SRAM . . . . .	44
2.4	Flash memory overview . . . . .	44
2.5	Boot configuration . . . . .	44
2.5.1	Embedded boot loader . . . . .	45
3	Embedded flash memory . . . . .	46
3.1	Flash main features . . . . .	46
3.2	Flash memory functional description . . . . .	46
3.2.1	Flash memory organization . . . . .	46
3.2.2	Read operations . . . . .	47
3.2.3	Flash program and erase operations . . . . .	49
3.3	Memory protection . . . . .	55
3.3.1	Read protection (RDP) . . . . .	55
3.3.2	Write protection . . . . .	57
3.3.3	Option byte block write protection . . . . .	57
3.4	Flash interrupts . . . . .	57

3.5	Flash register description . . . . .	58
3.5.1	Flash access control register (FLASH_ACR) . . . . .	58
3.5.2	Flash key register (FLASH_KEYR) . . . . .	58
3.5.3	Flash option key register (FLASH_OPTKEYR) . . . . .	59
3.5.4	Flash status register (FLASH_SR) . . . . .	59
3.5.5	Flash control register (FLASH_CR) . . . . .	60
3.5.6	Flash address register (FLASH_AR) . . . . .	61
3.5.7	Option byte register (FLASH_OBR) . . . . .	62
3.5.8	Write protection register (FLASH_WRPR) . . . . .	63
3.6	Flash register map . . . . .	63
4	Option byte description . . . . .	65
5	Cyclic redundancy check calculation unit (CRC) . . . . .	68
5.1	Introduction . . . . .	68
5.2	CRC main features . . . . .	68
5.3	CRC functional description . . . . .	69
5.3.1	CRC block diagram . . . . .	69
5.3.2	CRC internal signals . . . . .	69
5.3.3	CRC operation . . . . .	69
5.4	CRC registers . . . . .	71
5.4.1	CRC data register (CRC_DR) . . . . .	71
5.4.2	CRC independent data register (CRC_IDR) . . . . .	71
5.4.3	CRC control register (CRC_CR) . . . . .	72
5.4.4	CRC initial value (CRC_INIT) . . . . .	73
5.4.5	CRC polynomial (CRC_POL) . . . . .	73
5.4.6	CRC register map . . . . .	74
6	Power control (PWR) . . . . .	75
6.1	Power supplies . . . . .	75
6.1.1	Independent A/D and D/A converter supply and reference voltage . . . . .	77
6.1.2	Battery backup domain . . . . .	77
6.1.3	Voltage regulator . . . . .	78
6.2	Power supply supervisor . . . . .	78
6.2.1	Power on reset (POR)/power down reset (PDR) . . . . .	78
6.2.2	Programmable voltage detector (PVD) . . . . .	79

6.2.3 External NPOR signal ..... 80
6.3 Low-power modes ..... 80
- 6.3.1 Slowing down system clocks ..... 81
- 6.3.2 Peripheral clock gating ..... 81
- 6.3.3 Sleep mode ..... 82
- 6.3.4 Stop mode ..... 83
- 6.3.5 Standby mode ..... 84
- 6.3.6 Auto-wakeup from low-power mode ..... 86
6.4 Power control registers ..... 87
- 6.4.1 Power control register (PWR_CR) ..... 87
- 6.4.2 Power control/status register (PWR_CSR) ..... 88
- 6.4.3 PWR register map ..... 89
7 Reset and clock control (RCC) ..... 90
- 7.1 Reset ..... 90
  - 7.1.1 Power reset ..... 90
  - 7.1.2 System reset ..... 90
  - 7.1.3 RTC domain reset ..... 91
- 7.2 Clocks ..... 92
  - 7.2.1 HSE clock ..... 94
  - 7.2.2 HSI clock ..... 95
  - 7.2.3 PLL ..... 96
  - 7.2.4 LSE clock ..... 96
  - 7.2.5 LSI clock ..... 97
  - 7.2.6 System clock (SYSCLK) selection ..... 97
  - 7.2.7 Clock security system (CSS) ..... 97
  - 7.2.8 ADC clock ..... 98
  - 7.2.9 RTC clock ..... 98
  - 7.2.10 Timers (TIMx) clock ..... 98
  - 7.2.11 Watchdog clock ..... 99
  - 7.2.12 I2S clock ..... 99
  - 7.2.13 Clock-out capability ..... 99
  - 7.2.14 Internal/external clock measurement with TIM16 ..... 99
- 7.3 Low-power modes ..... 100
- 7.4 RCC registers ..... 102
  - 7.4.1 Clock control register (RCC_CR) ..... 102

7.4.2	Clock configuration register (RCC_CFGR)	104
7.4.3	Clock interrupt register (RCC_CIR)	106
7.4.4	APB2 peripheral reset register (RCC_APB2RSTR)	109
7.4.5	APB1 peripheral reset register (RCC_APB1RSTR)	110
7.4.6	AHB peripheral clock enable register (RCC_AHBENR)	111
7.4.7	APB2 peripheral clock enable register (RCC_APB2ENR)	113
7.4.8	APB1 peripheral clock enable register (RCC_APB1ENR)	114
7.4.9	RTC domain control register (RCC_BDCR)	117
7.4.10	Control/status register (RCC_CSR)	118
7.4.11	AHB peripheral reset register (RCC_AHBRSTR)	120
7.4.12	Clock configuration register 2 (RCC_CFGR2)	121
7.4.13	Clock configuration register 3 (RCC_CFGR3)	122
7.4.14	RCC register map	124
8	General-purpose I/Os (GPIO)	126
8.1	Introduction	126
8.2	GPIO main features	126
8.3	GPIO functional description	126
8.3.1	General-purpose I/O (GPIO)	128
8.3.2	I/O pin alternate function multiplexer and mapping	129
8.3.3	I/O port control registers	130
8.3.4	I/O port data registers	130
8.3.5	I/O data bitwise handling	130
8.3.6	GPIO locking mechanism	130
8.3.7	I/O alternate function input/output	131
8.3.8	External interrupt/wake-up lines	131
8.3.9	Input configuration	131
8.3.10	Output configuration	132
8.3.11	Alternate function configuration	133
8.3.12	Analog configuration	134
8.3.13	Using the HSE or LSE oscillator pins as GPIOs	135
8.3.14	Using the GPIO pins in the RTC supply domain	135
8.4	GPIO registers	136
8.4.1	GPIO port mode register (GPIOx_MODER) (x = A to D and F)	136
8.4.2	GPIO port output type register (GPIOx_OTYPER) (x = A to D and F)	136

- 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR)
  (x = A to D and F) . . . . . 137
- 8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)
  (x = A to D and F) . . . . . 137
- 8.4.5 GPIO port input data register (GPIOx_IDR)
  (x = A to D and F) . . . . . 138
- 8.4.6 GPIO port output data register (GPIOx_ODR)
  (x = A to D and F) . . . . . 138
- 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR)
  (x = A to D and F) . . . . . 139
- 8.4.8 GPIO port configuration lock register (GPIOx_LCKR)
  (x = A to E and F) . . . . . 139
- 8.4.9 GPIO alternate function low register (GPIOx_AFRL)
  (x = A to D and F) . . . . . 140
- 8.4.10 GPIO alternate function high register (GPIOx_AFRH)
  (x = A to D and F) . . . . . 140
- 8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to D and F) . . . . . 141
- 8.4.12 GPIO register map . . . . . 142
9 System configuration controller (SYSCFG) . . . . . 144
- 9.1 SYSCFG registers . . . . . 144
  - 9.1.1 SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . 144
  - 9.1.2 SYSCFG external interrupt configuration register 1
    (SYSCFG_EXTICR1) . . . . . 146
  - 9.1.3 SYSCFG external interrupt configuration register 2
    (SYSCFG_EXTICR2) . . . . . 147
  - 9.1.4 SYSCFG external interrupt configuration register 3
    (SYSCFG_EXTICR3) . . . . . 148
  - 9.1.5 SYSCFG external interrupt configuration register 4
    (SYSCFG_EXTICR4) . . . . . 149
  - 9.1.6 SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . 150
  - 9.1.7 SYSCFG register map . . . . . 151
10 Direct memory access controller (DMA) . . . . . 152
- 10.1 Introduction . . . . . 152
- 10.2 DMA main features . . . . . 152
- 10.3 DMA implementation . . . . . 153
  - 10.3.1 DMA1 . . . . . 153
  - 10.3.2 DMA request mapping . . . . . 153
- 10.4 DMA functional description . . . . . 156

10.4.1	DMA block diagram . . . . .	156
10.4.2	DMA transfers . . . . .	157
10.4.3	DMA arbitration . . . . .	158
10.4.4	DMA channels . . . . .	158
10.4.5	DMA data width, alignment, and endianness . . . . .	162
10.4.6	DMA error management . . . . .	163
10.5	DMA interrupts . . . . .	164
10.6	DMA registers . . . . .	164
10.6.1	DMA interrupt status register (DMA_ISR) . . . . .	164
10.6.2	DMA interrupt flag clear register (DMA_IFCR) . . . . .	166
10.6.3	DMA channel x configuration register (DMA_CCRx) . . . . .	168
10.6.4	DMA channel x number of data to transfer register (DMA_CNDTRx) . . . . .	170
10.6.5	DMA channel x peripheral address register (DMA_CPARx) . . . . .	171
10.6.6	DMA channel x memory address register (DMA_CMARx) . . . . .	172
10.6.7	DMA register map . . . . .	172
11	Interrupts and events . . . . .	175
11.1	Nested vectored interrupt controller (NVIC) . . . . .	175
11.1.1	NVIC main features . . . . .	175
11.1.2	SysTick calibration value register . . . . .	175
11.1.3	Interrupt and exception vectors . . . . .	175
11.2	Extended interrupts and events controller (EXTI) . . . . .	178
11.2.1	Main features . . . . .	179
11.2.2	Block diagram . . . . .	179
11.2.3	Wake-up event management . . . . .	180
11.2.4	Asynchronous Internal Interrupts . . . . .	180
11.2.5	Functional description . . . . .	180
11.2.6	External and internal interrupt/event line mapping . . . . .	182
11.3	EXTI registers . . . . .	183
11.3.1	Interrupt mask register (EXTI_IMR1) . . . . .	183
11.3.2	Event mask register (EXTI_EMR1) . . . . .	184
11.3.3	Rising trigger selection register (EXTI_RTSR1) . . . . .	185
11.3.4	Falling trigger selection register (EXTI_FTSR1) . . . . .	186
11.3.5	Software interrupt event register (EXTI_SWIER1) . . . . .	187
11.3.6	Pending register (EXTI_PR1) . . . . .	188
11.3.7	Interrupt mask register (EXTI_IMR2) . . . . .	189
11.3.8	Event mask register (EXTI_EMR2) . . . . .	189

11.3.9	Rising trigger selection register (EXTI_RTSR2) .....	189
11.3.10	Falling trigger selection register (EXTI_FTSR2) .....	190
11.3.11	Software interrupt event register (EXTI_SWIER2) .....	190
11.3.12	Pending register (EXTI_PR2) .....	191
11.3.13	EXTI register map .....	191
12	Analog-to-digital converters (ADC) .....	193
12.1	Introduction .....	193
12.2	ADC main features .....	193
12.3	ADC functional description .....	195
12.3.1	ADC block diagram .....	195
12.3.2	Pins and internal signals .....	196
12.3.3	Clocks .....	196
12.3.4	ADC1 connectivity .....	198
12.3.5	Slave AHB interface .....	198
12.3.6	ADC voltage regulator (ADVREGEN) .....	199
12.3.7	Single-ended and differential input channels .....	199
12.3.8	Calibration (ADCAL, ADCALDIF, ADCx_CALFACT) .....	200
12.3.9	ADC on-off control (ADEN, ADDIS, ADRDY) .....	202
12.3.10	Constraints when writing the ADC control bits .....	203
12.3.11	Channel selection (SQRx, JSQRx) .....	204
12.3.12	Channel-wise programmable sampling time (SMPR1, SMPR2) .....	205
12.3.13	Single conversion mode (CONT=0) .....	205
12.3.14	Continuous conversion mode (CONT=1) .....	206
12.3.15	Starting conversions (ADSTART, JADSTART) .....	207
12.3.16	Timing .....	207
12.3.17	Stopping an ongoing conversion (ADSTP, JADSTP) .....	208
12.3.18	Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) .....	210
12.3.19	Injected channel management .....	212
12.3.20	Discontinuous mode (DISCEN, DISCNUM, JDISCEN) .....	214
12.3.21	Queue of context for injected conversions .....	215
12.3.22	Programmable resolution (RES) - fast conversion mode .....	223
12.3.23	End of conversion, end of sampling phase (EOC, JEOC, EOSMP) ..	223
12.3.24	End of conversion sequence (EOS, JEOS) .....	224
12.3.25	Timing diagrams example (single/continuous modes, hardware/software triggers) .....	224

12.3.26	Data management . . . . .	226
12.3.27	Dynamic low-power features . . . . .	231
12.3.28	Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . .	236
12.3.29	Temperature sensor . . . . .	240
12.3.30	VBAT supply monitoring . . . . .	241
12.3.31	Monitoring the internal voltage reference . . . . .	242
12.4	ADC interrupts . . . . .	243
12.5	ADC registers (for each ADC) . . . . .	244
12.5.1	ADC interrupt and status register (ADCx_ISR, x=1) . . . . .	244
12.5.2	ADC interrupt enable register (ADCx_IER, x=1) . . . . .	246
12.5.3	ADC control register (ADCx_CR, x=1) . . . . .	248
12.5.4	ADC configuration register (ADCx_CFGR, x=1) . . . . .	251
12.5.5	ADC sample time register 1 (ADCx_SMPR1, x=1) . . . . .	254
12.5.6	ADC sample time register 2 (ADCx_SMPR2, x=1) . . . . .	256
12.5.7	ADC watchdog threshold register 1 (ADCx_TR1, x=1) . . . . .	256
12.5.8	ADC watchdog threshold register 2 (ADCx_TR2, x = 1) . . . . .	257
12.5.9	ADC watchdog threshold register 3 (ADCx_TR3, x=1) . . . . .	258
12.5.10	ADC regular sequence register 1 (ADCx_SQR1, x=1) . . . . .	259
12.5.11	ADC regular sequence register 2 (ADCx_SQR2, x=1) . . . . .	260
12.5.12	ADC regular sequence register 3 (ADCx_SQR3, x=1) . . . . .	262
12.5.13	ADC regular sequence register 4 (ADCx_SQR4, x=1) . . . . .	263
12.5.14	ADC regular Data Register (ADCx_DR, x=1) . . . . .	264
12.5.15	ADC injected sequence register (ADCx_JSQR, x=1) . . . . .	265
12.5.16	ADC offset register (ADCx_OFRy, x=1) (y=1..4) . . . . .	267
12.5.17	ADC injected data register (ADCx_JDRy, x=1, y= 1..4) . . . . .	268
12.5.18	ADC Analog Watchdog 2 Configuration Register (ADCx_AWD2CR, x=1) . . . . .	268
12.5.19	ADC Analog Watchdog 3 Configuration Register (ADCx_AWD3CR, x=1) . . . . .	269
12.5.20	ADC Differential Mode Selection Register (ADCx_DIFSEL, x=1) . . . . .	269
12.5.21	ADC Calibration Factors (ADCx_CALFACT, x=1) . . . . .	270
12.6	ADC common registers . . . . .	271
12.6.1	ADC Common status register (ADCx_CSR, x=1) . . . . .	271
12.6.2	ADC common control register (ADCx_CCR, x=1) . . . . .	273
12.7	ADC register map . . . . .	274
13	Digital-to-analog converter (DAC1) . . . . .	278

13.1	Introduction . . . . .	278
13.2	DAC1 main features . . . . .	278
13.3	DAC output buffer enable . . . . .	279
13.4	DAC channel enable . . . . .	280
13.5	Single mode functional description . . . . .	280
13.5.1	DAC data format . . . . .	280
13.5.2	DAC channel conversion . . . . .	280
13.5.3	DAC output voltage . . . . .	281
13.5.4	DAC trigger selection . . . . .	282
13.6	Noise generation . . . . .	283
13.7	Triangle-wave generation . . . . .	284
13.8	DMA request . . . . .	285
13.9	DAC registers . . . . .	286
13.9.1	DAC control register (DAC_CR) . . . . .	286
13.9.2	DAC software trigger register (DAC_SWTRIGR) . . . . .	288
13.9.3	DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . .	288
13.9.4	DAC channel1 12-bit left-aligned data holding register (DAC_DHR12L1) . . . . .	289
13.9.5	DAC channel1 8-bit right-aligned data holding register (DAC_DHR8R1) . . . . .	289
13.9.6	DAC channel1 data output register (DAC_DOR1) . . . . .	289
13.9.7	DAC status register (DAC_SR) . . . . .	290
13.9.8	DAC register map . . . . .	291
14	Comparator (COMP) . . . . .	292
14.1	Introduction . . . . .	292
14.2	COMP main features . . . . .	292
14.3	COMP functional description . . . . .	293
14.3.1	COMP block diagram . . . . .	293
14.3.2	COMP pins and internal signals . . . . .	294
14.3.3	COMP reset and clocks . . . . .	294
14.3.4	Comparator LOCK mechanism . . . . .	295
14.3.5	Comparator output blanking function . . . . .	295
14.4	COMP interrupts . . . . .	296
14.5	COMP registers . . . . .	296

14.5.1	COMP2 control and status register (COMP2_CSR) . . . . .	296
14.5.2	COMP4 control and status register (COMP4_CSR) . . . . .	298
14.5.3	COMP6 control and status register (COMP6_CSR) . . . . .	299
14.5.4	COMP register map . . . . .	302
15	Operational amplifier (OPAMP) . . . . .	303
15.1	OPAMP introduction . . . . .	303
15.2	OPAMP main features . . . . .	303
15.3	OPAMP functional description . . . . .	303
15.3.1	General description . . . . .	303
15.3.2	Clock . . . . .	303
15.3.3	Operational amplifiers and comparators interconnections . . . . .	304
15.3.4	Using the OPAMP output as an ADC input . . . . .	304
15.3.5	Calibration . . . . .	304
15.3.6	Timer controlled Multiplexer mode . . . . .	305
15.3.7	OPAMP modes . . . . .	306
15.4	OPAMP registers . . . . .	309
15.4.1	OPAMP2 control register (OPAMP2_CSR) . . . . .	309
15.4.2	OPAMP register map . . . . .	312
16	Touch sensing controller (TSC) . . . . .	313
16.1	Introduction . . . . .	313
16.2	TSC main features . . . . .	313
16.3	TSC functional description . . . . .	314
16.3.1	TSC block diagram . . . . .	314
16.3.2	Surface charge transfer acquisition overview . . . . .	314
16.3.3	Reset and clocks . . . . .	317
16.3.4	Charge transfer acquisition sequence . . . . .	317
16.3.5	Spread spectrum feature . . . . .	318
16.3.6	Max count error . . . . .	319
16.3.7	Sampling capacitor I/O and channel I/O mode selection . . . . .	319
16.3.8	Acquisition mode . . . . .	320
16.3.9	I/O hysteresis and analog switch control . . . . .	320
16.4	TSC low-power modes . . . . .	321
16.5	TSC interrupts . . . . .	321
16.6	TSC registers . . . . .	321

16.6.1	TSC control register (TSC_CR) . . . . .	321
16.6.2	TSC interrupt enable register (TSC_IER) . . . . .	324
16.6.3	TSC interrupt clear register (TSC_ICR) . . . . .	325
16.6.4	TSC interrupt status register (TSC_ISR) . . . . .	325
16.6.5	TSC I/O hysteresis control register (TSC_IOHCR) . . . . .	326
16.6.6	TSC I/O analog switch control register (TSC_IOASCR) . . . . .	326
16.6.7	TSC I/O sampling control register (TSC_IOSCR) . . . . .	327
16.6.8	TSC I/O channel control register (TSC_IOCCR) . . . . .	327
16.6.9	TSC I/O group control status register (TSC_IOGCSR) . . . . .	328
16.6.10	TSC I/O group x counter register (TSC_IOGxCR) . . . . .	328
16.6.11	TSC register map . . . . .	329
17	Advanced-control timer (TIM1) . . . . .	331
17.1	TIM1 introduction . . . . .	331
17.2	TIM1 main features . . . . .	332
17.3	TIM1 functional description . . . . .	335
17.3.1	Time-base unit . . . . .	335
17.3.2	Counter modes . . . . .	337
17.3.3	Repetition counter . . . . .	348
17.3.4	External trigger input . . . . .	350
17.3.5	Clock selection . . . . .	351
17.3.6	Capture/compare channels . . . . .	355
17.3.7	Input capture mode . . . . .	358
17.3.8	PWM input mode . . . . .	359
17.3.9	Forced output mode . . . . .	359
17.3.10	Output compare mode . . . . .	360
17.3.11	PWM mode . . . . .	361
17.3.12	Asymmetric PWM mode . . . . .	364
17.3.13	Combined PWM mode . . . . .	365
17.3.14	Combined 3-phase PWM mode . . . . .	366
17.3.15	Complementary outputs and dead-time insertion . . . . .	367
17.3.16	Using the break function . . . . .	369
17.3.17	Clearing the OCxREF signal on an external event . . . . .	374
17.3.18	6-step PWM generation . . . . .	376
17.3.19	One-pulse mode . . . . .	377
17.3.20	Retriggerable one pulse mode . . . . .	378

17.3.21	Encoder interface mode . . . . .	379
17.3.22	UIF bit remapping . . . . .	381
17.3.23	Timer input XOR function . . . . .	382
17.3.24	Interfacing with Hall sensors . . . . .	382
17.3.25	Timer synchronization . . . . .	385
17.3.26	ADC synchronization . . . . .	389
17.3.27	DMA burst mode . . . . .	389
17.3.28	Debug mode . . . . .	390
17.4	TIM1 registers . . . . .	391
17.4.1	TIM1 control register 1 (TIM1_CR1) . . . . .	391
17.4.2	TIM1 control register 2 (TIM1_CR2) . . . . .	392
17.4.3	TIM1 slave mode control register (TIM1_SMCR) . . . . .	395
17.4.4	TIM1 DMA/interrupt enable register (TIM1_DIER) . . . . .	397
17.4.5	TIM1 status register (TIM1_SR) . . . . .	399
17.4.6	TIM1 event generation register (TIM1_EGR) . . . . .	401
17.4.7	TIM1 capture/compare mode register 1 (TIM1_CCMR1) . . . . .	402
17.4.8	TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) . . . . .	403
17.4.9	TIM1 capture/compare mode register 2 (TIM1_CCMR2) . . . . .	406
17.4.10	TIM1 capture/compare mode register 2 [alternate] (TIM1_CCMR2) . . . . .	407
17.4.11	TIM1 capture/compare enable register (TIM1_CCER) . . . . .	408
17.4.12	TIM1 counter (TIM1_CNT) . . . . .	412
17.4.13	TIM1 prescaler (TIM1_PSC) . . . . .	412
17.4.14	TIM1 auto-reload register (TIM1_ARR) . . . . .	412
17.4.15	TIM1 repetition counter register (TIM1_RCR) . . . . .	413
17.4.16	TIM1 capture/compare register 1 (TIM1_CCR1) . . . . .	413
17.4.17	TIM1 capture/compare register 2 (TIM1_CCR2) . . . . .	414
17.4.18	TIM1 capture/compare register 3 (TIM1_CCR3) . . . . .	414
17.4.19	TIM1 capture/compare register 4 (TIM1_CCR4) . . . . .	415
17.4.20	TIM1 break and dead-time register (TIM1_BDTR) . . . . .	415

- 17.4.21 TIM1 DMA control register (TIM1_DCR) . . . . . 418
- 17.4.22 TIM1 DMA address for full transfer (TIM1_DMAR) . . . . . 419
- 17.4.23 TIM1 option registers (TIM1_OR) . . . . . 420
- 17.4.24 TIM1 capture/compare mode register 3 (TIM1_CCMR3) . . . . . 420
- 17.4.25 TIM1 capture/compare register 5 (TIM1_CCR5) . . . . . 421
- 17.4.26 TIM1 capture/compare register 6 (TIM1_CCR6) . . . . . 422
- 17.4.27 TIM1 register map . . . . . 423
18 General-purpose timer (TIM2) . . . . . 426
- 18.1 TIM2 introduction . . . . . 426
- 18.2 TIM2 main features . . . . . 426
- 18.3 TIM2 functional description . . . . . 428
  - 18.3.1 Time-base unit . . . . . 428
  - 18.3.2 Counter modes . . . . . 430
  - 18.3.3 Clock selection . . . . . 440
  - 18.3.4 Capture/Compare channels . . . . . 444
  - 18.3.5 Input capture mode . . . . . 446
  - 18.3.6 PWM input mode . . . . . 447
  - 18.3.7 Forced output mode . . . . . 448
  - 18.3.8 Output compare mode . . . . . 449
  - 18.3.9 PWM mode . . . . . 450
  - 18.3.10 Asymmetric PWM mode . . . . . 453
  - 18.3.11 Combined PWM mode . . . . . 454
  - 18.3.12 Clearing the OCxREF signal on an external event . . . . . 455
  - 18.3.13 One-pulse mode . . . . . 457
  - 18.3.14 Retriggerable one pulse mode . . . . . 458
  - 18.3.15 Encoder interface mode . . . . . 459
  - 18.3.16 UIF bit remapping . . . . . 461
  - 18.3.17 Timer input XOR function . . . . . 461
  - 18.3.18 Timers and external trigger synchronization . . . . . 462
  - 18.3.19 Timer synchronization . . . . . 465
  - 18.3.20 DMA burst mode . . . . . 470
  - 18.3.21 Debug mode . . . . . 471

18.4	TIM2 registers .....	472
18.4.1	TIM2 control register 1 (TIM2_CR1) .....	472
18.4.2	TIM2 control register 2 (TIM2_CR2) .....	473
18.4.3	TIM2 slave mode control register (TIM2_SMCR) .....	475
18.4.4	TIM2 DMA/Interrupt enable register (TIM2_DIER) .....	478
18.4.5	TIM2 status register (TIM2_SR) .....	479
18.4.6	TIM2 event generation register (TIM2_EGR) .....	480
18.4.7	TIM2 capture/compare mode register 1 (TIM2_CCMR1) .....	481
18.4.8	TIM2 capture/compare mode register 1 [alternate] (TIM2_CCMR1) ..	483
18.4.9	TIM2 capture/compare mode register 2 (TIM2_CCMR2) .....	485
18.4.10	TIM2 capture/compare mode register 2 [alternate] (TIM2_CCMR2) ..	486
18.4.11	TIM2 capture/compare enable register (TIM2_CCER) .....	487
18.4.12	TIM2 counter (TIM2_CNT) .....	488
18.4.13	TIM2 counter [alternate] (TIM2_CNT) .....	489
18.4.14	TIM2 prescaler (TIM2_PSC) .....	489
18.4.15	TIM2 auto-reload register (TIM2_ARR) .....	489
18.4.16	TIM2 capture/compare register 1 (TIM2_CCR1) .....	490
18.4.17	TIM2 capture/compare register 2 (TIM2_CCR2) .....	490
18.4.18	TIM2 capture/compare register 3 (TIM2_CCR3) .....	491
18.4.19	TIM2 capture/compare register 4 (TIM2_CCR4) .....	491
18.4.20	TIM2 DMA control register (TIM2_DCR) .....	492
18.4.21	TIM2 DMA address for full transfer (TIM2_DMAR) .....	492
18.4.22	TIMx register map .....	494
19	General-purpose timers (TIM15/TIM16/TIM17) .....	496
19.1	TIM15/TIM16/TIM17 introduction .....	496
19.2	TIM15 main features .....	496
19.3	TIM16/TIM17 main features .....	497
19.4	TIM15/TIM16/TIM17 functional description .....	500
19.4.1	Time-base unit .....	500
19.4.2	Counter modes .....	502
19.4.3	Repetition counter .....	506
19.4.4	Clock selection .....	507
19.4.5	Capture/compare channels .....	509
19.4.6	Input capture mode .....	511
19.4.7	PWM input mode (only for TIM15) .....	512

19.4.8	Forced output mode . . . . .	513
19.4.9	Output compare mode . . . . .	514
19.4.10	PWM mode . . . . .	515
19.4.11	Combined PWM mode (TIM15 only) . . . . .	516
19.4.12	Complementary outputs and dead-time insertion . . . . .	517
19.4.13	Using the break function . . . . .	519
19.4.14	6-step PWM generation . . . . .	523
19.4.15	One-pulse mode . . . . .	524
19.4.16	Retriggerable one pulse mode (TIM15 only) . . . . .	525
19.4.17	UIF bit remapping . . . . .	526
19.4.18	Timer input XOR function (TIM15 only) . . . . .	527
19.4.19	External trigger synchronization (TIM15 only) . . . . .	528
19.4.20	Slave mode – combined reset + trigger mode (TIM15 only) . . . . .	530
19.4.21	DMA burst mode . . . . .	530
19.4.22	Timer synchronization (TIM15) . . . . .	532
19.4.23	Using timer output as trigger for other timers (TIM16/TIM17) . . . . .	532
19.4.24	Debug mode . . . . .	532
19.5	TIM15 registers . . . . .	533
19.5.1	TIM15 control register 1 (TIM15_CR1) . . . . .	533
19.5.2	TIM15 control register 2 (TIM15_CR2) . . . . .	534
19.5.3	TIM15 slave mode control register (TIM15_SMCR) . . . . .	536
19.5.4	TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .	537
19.5.5	TIM15 status register (TIM15_SR) . . . . .	538
19.5.6	TIM15 event generation register (TIM15_EGR) . . . . .	540
19.5.7	TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . .	541
19.5.8	TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) . . . . .	542
19.5.9	TIM15 capture/compare enable register (TIM15_CCER) . . . . .	545
19.5.10	TIM15 counter (TIM15_CNT) . . . . .	548
19.5.11	TIM15 prescaler (TIM15_PSC) . . . . .	548
19.5.12	TIM15 auto-reload register (TIM15_ARR) . . . . .	548
19.5.13	TIM15 repetition counter register (TIM15_RCR) . . . . .	549
19.5.14	TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .	549
19.5.15	TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .	550
19.5.16	TIM15 break and dead-time register (TIM15_BDTR) . . . . .	550
19.5.17	TIM15 DMA control register (TIM15_DCR) . . . . .	552
19.5.18	TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .	553

19.5.19	TIM15 register map	553
19.6	TIM16/TIM17 registers	556
19.6.1	TIMx control register 1 (TIMx_CR1)(x = 16 to 17)	556
19.6.2	TIMx control register 2 (TIMx_CR2)(x = 16 to 17)	557
19.6.3	TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17)	558
19.6.4	TIMx status register (TIMx_SR)(x = 16 to 17)	559
19.6.5	TIMx event generation register (TIMx_EGR)(x = 16 to 17)	560
19.6.6	TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 16 to 17)	561
19.6.7	TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 16 to 17)	562
19.6.8	TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17)	564
19.6.9	TIMx counter (TIMx_CNT)(x = 16 to 17)	566
19.6.10	TIMx prescaler (TIMx_PSC)(x = 16 to 17)	567
19.6.11	TIMx auto-reload register (TIMx_ARR)(x = 16 to 17)	567
19.6.12	TIMx repetition counter register (TIMx_RCR)(x = 16 to 17)	568
19.6.13	TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17)	568
19.6.14	TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17)	569
19.6.15	TIMx DMA control register (TIMx_DCR)(x = 16 to 17)	571
19.6.16	TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17)	571
19.6.17	TIM16 option register (TIM16_OR)	572
19.6.18	TIM16/TIM17 register map	573
20	Basic timers (TIM6)	575
20.1	TIM6 introduction	575
20.2	TIM6 main features	575
20.3	TIM6 functional description	576
20.3.1	Time-base unit	576
20.3.2	Counting mode	578
20.3.3	UIF bit remapping	581
20.3.4	Clock source	581
20.3.5	Debug mode	582
20.4	TIM6 registers	582
20.4.1	TIM6 control register 1 (TIM6_CR1)	582
20.4.2	TIM6 control register 2 (TIM6_CR2)	584
20.4.3	TIM6 DMA/Interrupt enable register (TIM6_DIER)	584
20.4.4	TIM6 status register (TIM6_SR)	585

- 20.4.5 TIM6 event generation register (TIM6_EGR) . . . . . 585
- 20.4.6 TIM6 counter (TIM6_CNT) . . . . . 585
- 20.4.7 TIM6 prescaler (TIM6_PSC) . . . . . 586
- 20.4.8 TIM6 auto-reload register (TIM6_ARR) . . . . . 586
- 20.4.9 TIM6 register map . . . . . 587
21 Infrared interface (IRTIM) . . . . . 588
22 System window watchdog (WWDG) . . . . . 589
- 22.1 Introduction . . . . . 589
- 22.2 WWDG main features . . . . . 589
- 22.3 WWDG functional description . . . . . 589
  - 22.3.1 WWDG block diagram . . . . . 590
  - 22.3.2 Enabling the watchdog . . . . . 590
  - 22.3.3 Controlling the down-counter . . . . . 590
  - 22.3.4 How to program the watchdog timeout . . . . . 590
  - 22.3.5 Debug mode . . . . . 592
- 22.4 WWDG interrupts . . . . . 592
- 22.5 WWDG registers . . . . . 592
  - 22.5.1 WWDG control register (WWDG_CR) . . . . . 592
  - 22.5.2 WWDG configuration register (WWDG_CFR) . . . . . 593
  - 22.5.3 WWDG status register (WWDG_SR) . . . . . 593
  - 22.5.4 WWDG register map . . . . . 594
23 Independent watchdog (IWDG) . . . . . 595
- 23.1 Introduction . . . . . 595
- 23.2 IWDG main features . . . . . 595
- 23.3 IWDG functional description . . . . . 595
  - 23.3.1 IWDG block diagram . . . . . 595
  - 23.3.2 Window option . . . . . 596
  - 23.3.3 Hardware watchdog . . . . . 597
  - 23.3.4 Register access protection . . . . . 597
  - 23.3.5 Debug mode . . . . . 597
- 23.4 IWDG registers . . . . . 598
  - 23.4.1 IWDG key register (IWDG_KR) . . . . . 598
  - 23.4.2 IWDG prescaler register (IWDG_PR) . . . . . 599

23.4.3	IWDG reload register (IWDG_RLR) . . . . .	600
23.4.4	IWDG status register (IWDG_SR) . . . . .	601
23.4.5	IWDG window register (IWDG_WINR) . . . . .	602
23.4.6	IWDG register map . . . . .	603
24	Real-time clock (RTC) . . . . .	604
24.1	Introduction . . . . .	604
24.2	RTC main features . . . . .	605
24.3	RTC functional description . . . . .	606
24.3.1	RTC block diagram . . . . .	606
24.3.2	GPIOs controlled by the RTC . . . . .	607
24.3.3	Clock and prescalers . . . . .	609
24.3.4	Real-time clock and calendar . . . . .	609
24.3.5	Programmable alarms . . . . .	610
24.3.6	Periodic auto-wake-up . . . . .	610
24.3.7	RTC initialization and configuration . . . . .	611
24.3.8	Reading the calendar . . . . .	612
24.3.9	Resetting the RTC . . . . .	613
24.3.10	RTC synchronization . . . . .	614
24.3.11	RTC reference clock detection . . . . .	614
24.3.12	RTC smooth digital calibration . . . . .	615
24.3.13	Time-stamp function . . . . .	617
24.3.14	Tamper detection . . . . .	618
24.3.15	Calibration clock output . . . . .	619
24.3.16	Alarm output . . . . .	620
24.4	RTC low-power modes . . . . .	620
24.5	RTC interrupts . . . . .	620
24.6	RTC registers . . . . .	621
24.6.1	RTC time register (RTC_TR) . . . . .	621
24.6.2	RTC date register (RTC_DR) . . . . .	622
24.6.3	RTC control register (RTC_CR) . . . . .	624
24.6.4	RTC initialization and status register (RTC_ISR) . . . . .	627
24.6.5	RTC prescaler register (RTC_PRER) . . . . .	630
24.6.6	RTC wake-up timer register (RTC_WUTR) . . . . .	631
24.6.7	RTC alarm A register (RTC_ALRMAR) . . . . .	632
24.6.8	RTC alarm B register (RTC_ALRMBR) . . . . .	633

24.6.9	RTC write protection register (RTC_WPR) . . . . .	634
24.6.10	RTC sub second register (RTC_SSR) . . . . .	634
24.6.11	RTC shift control register (RTC_SHIFTR) . . . . .	635
24.6.12	RTC timestamp time register (RTC_TSTR) . . . . .	636
24.6.13	RTC timestamp date register (RTC_TSDR) . . . . .	637
24.6.14	RTC time-stamp sub second register (RTC_TSSSR) . . . . .	638
24.6.15	RTC calibration register (RTC_CALR) . . . . .	639
24.6.16	RTC tamper and alternate function configuration register (RTC_TAFCR) . . . . .	640
24.6.17	RTC alarm A sub second register (RTC_ALRMASSR) . . . . .	643
24.6.18	RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .	644
24.6.19	RTC backup registers (RTC_BKPxR) . . . . .	645
24.6.20	RTC register map . . . . .	645
25	Inter-integrated circuit interface (I2C) . . . . .	648
25.1	Introduction . . . . .	648
25.2	I2C main features . . . . .	648
25.3	I2C implementation . . . . .	649
25.4	I2C functional description . . . . .	649
25.4.1	I2C block diagram . . . . .	650
25.4.2	I2C pins and internal signals . . . . .	650
25.4.3	I2C clock requirements . . . . .	651
25.4.4	I2C mode selection . . . . .	651
25.4.5	I2C initialization . . . . .	652
25.4.6	I2C reset . . . . .	656
25.4.7	I2C data transfer . . . . .	657
25.4.8	I2C target mode . . . . .	659
25.4.9	I2C controller mode . . . . .	668
25.4.10	I2C_TIMINGR register configuration examples . . . . .	679
25.4.11	SMBus specific features . . . . .	681
25.4.12	SMBus initialization . . . . .	684
25.4.13	SMBus I2C_TIMEOUTR register configuration examples . . . . .	686
25.4.14	SMBus target mode . . . . .	686
25.4.15	SMBus controller mode . . . . .	690
25.4.16	Wake-up from Stop mode on address match . . . . .	693
25.4.17	Error conditions . . . . .	694
25.5	I2C in low-power modes . . . . .	696

25.6	I2C interrupts . . . . .	696
25.7	I2C DMA requests . . . . .	697
25.7.1	Transmission using DMA . . . . .	697
25.7.2	Reception using DMA . . . . .	697
25.8	I2C debug modes . . . . .	697
25.9	I2C registers . . . . .	698
25.9.1	I2C control register 1 (I2C_CR1) . . . . .	698
25.9.2	I2C control register 2 (I2C_CR2) . . . . .	700
25.9.3	I2C own address 1 register (I2C_OAR1) . . . . .	702
25.9.4	I2C own address 2 register (I2C_OAR2) . . . . .	703
25.9.5	I2C timing register (I2C_TIMINGR) . . . . .	704
25.9.6	I2C timeout register (I2C_TIMEOUTR) . . . . .	705
25.9.7	I2C interrupt and status register (I2C_ISR) . . . . .	706
25.9.8	I2C interrupt clear register (I2C_ICR) . . . . .	708
25.9.9	I2C PEC register (I2C_PECR) . . . . .	709
25.9.10	I2C receive data register (I2C_RXDR) . . . . .	709
25.9.11	I2C transmit data register (I2C_TXDR) . . . . .	710
25.9.12	I2C register map . . . . .	711
26	Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .	712
26.1	Introduction . . . . .	712
26.2	USART main features . . . . .	712
26.3	USART extended features . . . . .	713
26.4	USART implementation . . . . .	714
26.5	USART functional description . . . . .	714
26.5.1	USART character description . . . . .	717
26.5.2	USART transmitter . . . . .	719
26.5.3	USART receiver . . . . .	721
26.5.4	USART baud rate generation . . . . .	728
26.5.5	Tolerance of the USART receiver to clock deviation . . . . .	730
26.5.6	USART auto baud rate detection . . . . .	731
26.5.7	Multiprocessor communication using USART . . . . .	732
26.5.8	Modbus communication using USART . . . . .	734
26.5.9	USART parity control . . . . .	735
26.5.10	USART LIN (local interconnection network) mode . . . . .	736

26.5.11	USART synchronous mode . . . . .	738
26.5.12	USART single-wire half-duplex communication . . . . .	741
26.5.13	USART smartcard mode . . . . .	741
26.5.14	USART IrDA SIR ENDEC block . . . . .	746
26.5.15	USART continuous communication in DMA mode . . . . .	748
26.5.16	RS232 hardware flow control and RS485 driver enable using USART . . . . .	750
26.5.17	Wake-up from Stop mode using USART . . . . .	752
26.6	USART in low-power modes . . . . .	754
26.7	USART interrupts . . . . .	754
26.8	USART registers . . . . .	756
26.8.1	USART control register 1 (USART_CR1) . . . . .	756
26.8.2	USART control register 2 (USART_CR2) . . . . .	759
26.8.3	USART control register 3 (USART_CR3) . . . . .	763
26.8.4	USART baud rate register (USART_BRR) . . . . .	767
26.8.5	USART guard time and prescaler register (USART_GTPR) . . . . .	767
26.8.6	USART receiver timeout register (USART_RTOR) . . . . .	768
26.8.7	USART request register (USART_RQR) . . . . .	769
26.8.8	USART interrupt and status register (USART_ISR) . . . . .	770
26.8.9	USART interrupt flag clear register (USART_ICR) . . . . .	775
26.8.10	USART receive data register (USART_RDR) . . . . .	777
26.8.11	USART transmit data register (USART_TDR) . . . . .	777
26.8.12	USART register map . . . . .	778
27	Serial peripheral interface / integrated interchip sound (SPI/I2S) . . .	780
27.1	Introduction . . . . .	780
27.2	SPI main features . . . . .	780
27.3	I2S main features . . . . .	781
27.4	SPI/I2S implementation . . . . .	781
27.5	SPI functional description . . . . .	782
27.5.1	General description . . . . .	782
27.5.2	Communications between one master and one slave . . . . .	783
27.5.3	Standard multislave communication . . . . .	785
27.5.4	Multimaster communication . . . . .	786
27.5.5	Slave select (NSS) pin management . . . . .	787
27.5.6	Communication formats . . . . .	788

27.5.7	Configuration of SPI . . . . .	790
27.5.8	Procedure for enabling SPI . . . . .	791
27.5.9	Data transmission and reception procedures . . . . .	791
27.5.10	SPI status flags . . . . .	801
27.5.11	SPI error flags . . . . .	802
27.5.12	NSS pulse mode . . . . .	803
27.5.13	TI mode . . . . .	803
27.5.14	CRC calculation . . . . .	804
27.6	SPI interrupts . . . . .	806
27.7	I2S functional description . . . . .	807
27.7.1	I2S general description . . . . .	807
27.7.2	I2S full duplex . . . . .	808
27.7.3	Supported audio protocols . . . . .	809
27.7.4	Start-up description . . . . .	815
27.7.5	Clock generator . . . . .	817
27.7.6	I ²S master mode . . . . .	819
27.7.7	I ²S slave mode . . . . .	821
27.7.8	I2S status flags . . . . .	823
27.7.9	I2S error flags . . . . .	824
27.7.10	DMA features . . . . .	825
27.8	I2S interrupts . . . . .	825
27.9	SPI and I2S registers . . . . .	826
27.9.1	SPI control register 1 (SPIx_CR1) . . . . .	826
27.9.2	SPI control register 2 (SPIx_CR2) . . . . .	828
27.9.3	SPI status register (SPIx_SR) . . . . .	830
27.9.4	SPI data register (SPIx_DR) . . . . .	832
27.9.5	SPI CRC polynomial register (SPIx_CRCPR) . . . . .	832
27.9.6	SPI Rx CRC register (SPIx_RXCRCR) . . . . .	832
27.9.7	SPI Tx CRC register (SPIx_TXCRCR) . . . . .	833
27.9.8	SPIx_I2S configuration register (SPIx_I2SCFGR) . . . . .	833
27.9.9	SPIx_I2S prescaler register (SPIx_I2SPR) . . . . .	835
27.9.10	SPI/I2S register map . . . . .	836
28	Debug support (DBG) . . . . .	837
28.1	Overview . . . . .	837
28.2	Reference Arm documentation . . . . .	838

28.3	SWJ debug port (serial wire and JTAG) . . . . .	838
28.3.1	Mechanism to select the JTAG-DP or the SW-DP . . . . .	839
28.4	Pinout and debug port pins . . . . .	839
28.4.1	SWJ debug port pins . . . . .	840
28.4.2	Flexible SWJ-DP pin assignment . . . . .	840
28.4.3	Internal pull-up and pull-down on JTAG pins . . . . .	840
28.4.4	Using serial wire and releasing the unused debug pins as GPIOs . . . . .	842
28.5	STM32F3xx JTAG TAP connection . . . . .	842
28.6	ID codes and locking mechanism . . . . .	843
28.6.1	MCU device ID code . . . . .	843
28.6.2	Boundary scan TAP . . . . .	844
28.6.3	Cortex ^®-M4F TAP . . . . .	844
28.6.4	Cortex ^®-M4F JEDEC-106 ID code . . . . .	844
28.7	JTAG debug port . . . . .	844
28.8	SW debug port . . . . .	846
28.8.1	SW protocol introduction . . . . .	846
28.8.2	SW protocol sequence . . . . .	846
28.8.3	SW-DP state machine (reset, idle states, ID code) . . . . .	847
28.8.4	DP and AP read/write accesses . . . . .	848
28.8.5	SW-DP registers . . . . .	848
28.8.6	SW-AP registers . . . . .	849
28.9	AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP . . . . .	849
28.10	Core debug . . . . .	850
28.11	Capability of the debugger host to connect under system reset . . . . .	851
28.12	FPB (Flash patch breakpoint) . . . . .	851
28.13	DWT (data watchpoint trigger) . . . . .	851
28.14	ITM (instrumentation trace macrocell) . . . . .	852
28.14.1	General description . . . . .	852
28.14.2	Time stamp packets, synchronization, and overflow packets . . . . .	852
28.15	Arm ^®Arm ^®MCU debug component (DBGMCU) . . . . .	854
28.15.1	Debug support for low-power modes . . . . .	854
28.15.2	Debug support for timers, watchdog I ²C . . . . .	854
28.15.3	Debug MCU configuration register . . . . .	854
28.15.4	Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . .	856
28.15.5	Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) . . . . .	857

- 28.15.6 TRACE pin assignment . . . . . 858
- 28.15.7 TPU formatter . . . . . 859
- 28.15.8 TPU frame synchronization packets . . . . . 860
- 28.15.9 Transmission of the synchronization frame packet . . . . . 860
- 28.15.10 Synchronous mode . . . . . 860
- 28.15.11 Asynchronous mode . . . . . 860
- 28.15.12 TRACECLKIN connection inside the STM32F3xx . . . . . 861
- 28.15.13 TPIU registers . . . . . 862
- 28.15.14 Example of configuration . . . . . 863
28.16 DBG register map . . . . . 863
29 Device electronic signature . . . . . 864
- 29.1 Unique device ID register (96 bits) . . . . . 864
- 29.2 Flash memory size data register . . . . . 865
30 Important security notice . . . . . 866
31 Revision history . . . . . 867

List of tables

Table 1.	STM32F3xx peripheral register boundary addresses . . . . .	42
Table 2.	Boot modes . . . . .	44
Table 3.	Flash module organization . . . . .	46
Table 4.	Flash memory read protection status . . . . .	55
Table 5.	Access status versus protection level and execution modes . . . . .	56
Table 6.	Flash interrupt request . . . . .	57
Table 7.	Flash interface - register map and reset values . . . . .	63
Table 8.	Option byte format . . . . .	65
Table 9.	Option byte organization . . . . .	65
Table 10.	Description of the option bytes . . . . .	66
Table 11.	CRC internal input/output signals . . . . .	69
Table 12.	CRC register map and reset values . . . . .	74
Table 13.	Low-power mode summary . . . . .	81
Table 14.	Sleep-now . . . . .	82
Table 15.	Sleep-on-exit . . . . .	83
Table 16.	Stop mode . . . . .	84
Table 17.	Standby mode . . . . .	85
Table 18.	PWR register map and reset values . . . . .	89
Table 19.	RCC register map and reset values . . . . .	124
Table 20.	Port bit configuration table . . . . .	128
Table 21.	GPIO register map and reset values . . . . .	142
Table 22.	SYSCFG register map and reset values . . . . .	151
Table 23.	DMA implementation . . . . .	153
Table 24.	DMA requests for each channel . . . . .	155
Table 25.	Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .	162
Table 26.	DMA interrupt requests . . . . .	164
Table 27.	DMA register map and reset values . . . . .	172
Table 28.	STM32F3xx vector table . . . . .	175
Table 29.	External interrupt/event controller register map and reset values . . . . .	191
Table 30.	ADC internal signals . . . . .	196
Table 31.	ADC pins . . . . .	196
Table 32.	Configuring the trigger polarity for regular external triggers . . . . .	210
Table 33.	Configuring the trigger polarity for injected external triggers . . . . .	210
Table 34.	ADC1 (master) - External triggers for regular channels . . . . .	211
Table 35.	ADC1 - External trigger for injected channels . . . . .	212
Table 36.	TSAR timings depending on resolution . . . . .	223
Table 37.	Offset computation versus data resolution . . . . .	226
Table 38.	Analog watchdog channel selection . . . . .	236
Table 39.	Analog watchdog 1 comparison . . . . .	237
Table 40.	Analog watchdog 2 and 3 comparison . . . . .	237
Table 41.	ADC interrupts per each ADC . . . . .	243
Table 42.	ADC global register map . . . . .	274
Table 43.	ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC, x=1) . . . . .	274
Table 44.	ADC register map and reset values (master and slave ADC common registers) offset =0x300, x=1) . . . . .	276
Table 45.	DACx pins . . . . .	279
Table 46.	External triggers (DAC1) . . . . .	282

Table 47.	DAC register map and reset values . . . . .	291
Table 48.	STM32F3xx comparator input/outputs summary . . . . .	294
Table 49.	COMP register map and reset values. . . . .	302
Table 50.	Connections with dedicated I/O . . . . .	303
Table 51.	OPAMP register map and reset values . . . . .	312
Table 52.	Acquisition sequence summary . . . . .	316
Table 53.	Spread spectrum deviation versus AHB clock frequency . . . . .	318
Table 54.	I/O state depending on its mode and IODEF bit value . . . . .	319
Table 55.	Effect of low-power modes on TSC . . . . .	321
Table 56.	Interrupt control bits . . . . .	321
Table 57.	TSC register map and reset values . . . . .	329
Table 58.	Behavior of timer outputs versus BRK/BRK2 inputs . . . . .	373
Table 59.	Counting direction versus encoder signals . . . . .	380
Table 60.	TIM1 internal trigger connection . . . . .	397
Table 61.	Output control bits for complementary OCx and OCxN channels with break feature . . . . .	411
Table 62.	TIM1 register map and reset values . . . . .	423
Table 63.	Counting direction versus encoder signals . . . . .	460
Table 64.	TIMx internal trigger connection . . . . .	477
Table 65.	Output control bit for standard OCx channels . . . . .	488
Table 66.	TIM2 register map and reset values . . . . .	494
Table 67.	TIMx Internal trigger connection . . . . .	537
Table 68.	Output control bits for complementary OCx and OCxN channels with break feature (TIM15) . . . . .	547
Table 69.	TIM15 register map and reset values . . . . .	553
Table 70.	Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) . . . . .	566
Table 71.	TIM16/TIM17 register map and reset values . . . . .	573
Table 72.	TIM6 register map and reset values . . . . .	587
Table 73.	WWDG register map and reset values . . . . .	594
Table 74.	IWDG register map and reset values . . . . .	603
Table 75.	RTC pin PC13 configuration . . . . .	608
Table 76.	LSE pin PC14 configuration . . . . .	608
Table 77.	LSE pin PC15 configuration . . . . .	608
Table 78.	Effect of low-power modes on RTC . . . . .	620
Table 79.	Interrupt control bits . . . . .	621
Table 80.	RTC register map and reset values . . . . .	645
Table 81.	I2C implementation . . . . .	649
Table 82.	I2C input/output pins . . . . .	650
Table 83.	I2C internal input/output signals . . . . .	651
Table 84.	Comparison of analog and digital filters . . . . .	653
Table 85.	I ²C-bus and SMBus specification data setup and hold times . . . . .	655
Table 86.	I2C configuration . . . . .	659
Table 87.	I ²C-bus and SMBus specification clock timings . . . . .	670
Table 88.	Timing settings for f _I2CCLKof 8 MHz . . . . .	680
Table 89.	Timing settings for f _I2CCLKof 16 MHz . . . . .	680
Table 90.	Timing settings for f _I2CCLKof 48 MHz . . . . .	681
Table 91.	SMBus timeout specifications . . . . .	683
Table 92.	SMBus with PEC configuration . . . . .	685
Table 93.	TIMEOUTA[11:0] for maximum t _TIMEOUTof 25 ms . . . . .	686
Table 94.	TIMEOUTB[11:0] for maximum t _LOW:SEXTand t _LOW:MEXTof 8 ms . . . . .	686
Table 95.	TIMEOUTA[11:0] for maximum t _IDLEof 50 µs . . . . .	686
Table 96.	Effect of low-power modes to I2C . . . . .	696

Table 97.	I2C interrupt requests . . . . .	696
Table 98.	I2C register map and reset values . . . . .	711
Table 99.	STM32F3xx USART features . . . . .	714
Table 100.	Noise detection from sampled data . . . . .	726
Table 101.	Error calculation for programmed baud rates at $f_{CK} = 72\text{MHz}$ in both cases of oversampling by 16 or by 8. . . . .	729
Table 102.	Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .	731
Table 103.	Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . .	731
Table 104.	Frame formats . . . . .	735
Table 105.	Effect of low-power modes on the USART . . . . .	754
Table 106.	USART interrupt requests. . . . .	754
Table 107.	USART register map and reset values . . . . .	778
Table 108.	STM32F301x6/8 and STM32F318x8 SPI/I2S implementation . . . . .	781
Table 109.	SPI interrupt requests . . . . .	806
Table 110.	Audio-frequency precision using standard 8 MHz HSE . . . . .	819
Table 111.	I2S interrupt requests . . . . .	825
Table 112.	SPI/I2S register map and reset values . . . . .	836
Table 113.	SWJ debug port pins . . . . .	840
Table 114.	Flexible SWJ-DP pin assignment . . . . .	840
Table 115.	JTAG debug port data registers . . . . .	844
Table 116.	32-bit debug port registers addressed through the shifted value A[3:2] . . . . .	845
Table 117.	Packet request (8-bits) . . . . .	846
Table 118.	ACK response (3 bits). . . . .	847
Table 119.	DATA transfer (33 bits). . . . .	847
Table 120.	SW-DP registers . . . . .	848
Table 121.	Cortex ^®-M4F AHB-AP registers . . . . .	850
Table 122.	Core debug registers . . . . .	850
Table 123.	Main ITM registers . . . . .	853
Table 124.	Asynchronous TRACE pin assignment. . . . .	858
Table 125.	Flexible TRACE pin assignment. . . . .	859
Table 126.	Important TPIU registers. . . . .	862
Table 127.	DBG register map and reset values . . . . .	863
Table 128.	Document revision history . . . . .	867

List of figures

Figure 1.	System architecture . . . . .	38
Figure 2.	Programming procedure . . . . .	50
Figure 3.	Flash memory Page Erase procedure . . . . .	52
Figure 4.	Flash memory Mass Erase procedure . . . . .	53
Figure 5.	CRC calculation unit block diagram . . . . .	69
Figure 6.	Power supply overview (STM32F301xx devices) . . . . .	75
Figure 7.	Power supply overview (STM32F318xx devices) . . . . .	76
Figure 8.	Power on reset/power down reset waveform . . . . .	79
Figure 9.	PVD thresholds . . . . .	80
Figure 10.	Simplified diagram of the reset circuit . . . . .	91
Figure 11.	STM32F3xx clock tree . . . . .	93
Figure 12.	HSE/ LSE clock sources . . . . .	94
Figure 13.	Frequency measurement with TIM16 in capture mode . . . . .	99
Figure 14.	Basic structure of an I/O port bit . . . . .	127
Figure 15.	Basic structure of a 5-Volt tolerant I/O port bit . . . . .	127
Figure 16.	Input floating / pull up / pull down configurations . . . . .	132
Figure 17.	Output configuration . . . . .	133
Figure 18.	Alternate function configuration . . . . .	134
Figure 19.	High impedance-analog configuration . . . . .	134
Figure 20.	DMA request mapping . . . . .	154
Figure 21.	DMA block diagram . . . . .	156
Figure 22.	External interrupt/event block diagram . . . . .	179
Figure 23.	External interrupt/event GPIO mapping . . . . .	182
Figure 24.	ADC block diagram . . . . .	195
Figure 25.	ADC clock scheme . . . . .	197
Figure 26.	ADC1 connectivity . . . . .	198
Figure 27.	ADC calibration . . . . .	201
Figure 28.	Updating the ADC calibration factor . . . . .	201
Figure 29.	Mixing single-ended and differential channels . . . . .	202
Figure 30.	Enabling / Disabling the ADC . . . . .	203
Figure 31.	Analog-to-digital conversion time . . . . .	208
Figure 32.	Stopping ongoing regular conversions . . . . .	209
Figure 33.	Stopping ongoing regular and injected conversions . . . . .	209
Figure 34.	Triggers are shared between ADC master & ADC slave . . . . .	211
Figure 35.	Injected conversion latency . . . . .	213
Figure 36.	Example of JSQR queue of context (sequence change) . . . . .	216
Figure 37.	Example of JSQR queue of context (trigger change) . . . . .	217
Figure 38.	Example of JSQR queue of context with overflow before conversion . . . . .	217
Figure 39.	Example of JSQR queue of context with overflow during conversion . . . . .	218
Figure 40.	Example of JSQR queue of context with empty queue (case JQM=0) . . . . .	218
Figure 41.	Example of JSQR queue of context with empty queue (case JQM=1) . . . . .	219
Figure 42.	Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion. . . . .	219
Figure 43.	Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion and a new trigger occurs. . . . .	220
Figure 44.	Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs outside an ongoing conversion . . . . .	220

Figure 45.	Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . .	221
Figure 46.	Flushing JSQR queue of context by setting ADDIS=1 (JQM=0). . . . .	221
Figure 47.	Flushing JSQR queue of context by setting ADDIS=1 (JQM=1). . . . .	222
Figure 48.	Example of JSQR queue of context when changing SW and HW triggers. . . . .	222
Figure 49.	Single conversions of a sequence, software trigger . . . . .	224
Figure 50.	Continuous conversion of a sequence, software trigger. . . . .	225
Figure 51.	Single conversions of a sequence, hardware trigger . . . . .	225
Figure 52.	Continuous conversions of a sequence, hardware trigger . . . . .	225
Figure 53.	Right alignment (offset disabled, unsigned value) . . . . .	227
Figure 54.	Right alignment (offset enabled, signed value). . . . .	228
Figure 55.	Left alignment (offset disabled, unsigned value) . . . . .	228
Figure 56.	Left alignment (offset enabled, signed value). . . . .	229
Figure 57.	Example of overrun (OVR) . . . . .	230
Figure 58.	AUTODLY=1, regular conversion in continuous mode, software trigger . . . . .	233
Figure 59.	AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=0; JDISCEN=0) . . . . .	233
Figure 60.	AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=1, JDISCEN=1) . . . . .	234
Figure 61.	AUTODLY=1, regular continuous conversions interrupted by injected conversions . . . . .	235
Figure 62.	AUTODLY=1 in auto- injected mode (JAUTO=1). . . . .	235
Figure 63.	Analog watchdog's guarded area . . . . .	236
Figure 64.	ADC _y_AWD _x_OUT signal generation (on all regular channels). . . . .	238
Figure 65.	ADC _y_AWD _x_OUT signal generation (AWD _xflag not cleared by SW) . . . . .	239
Figure 66.	ADC _y_AWD _x_OUT signal generation (on a single regular channel) . . . . .	239
Figure 67.	ADC _y_AWD _x_OUT signal generation (on all injected channels) . . . . .	239
Figure 68.	Temperature sensor channel block diagram . . . . .	240
Figure 69.	VBAT channel block diagram . . . . .	241
Figure 70.	DAC1 block diagram. . . . .	279
Figure 71.	Data registers in single DAC channel mode . . . . .	280
Figure 72.	Timing diagram for conversion with trigger disabled TEN = 0 . . . . .	281
Figure 73.	DAC LFSR register calculation algorithm . . . . .	283
Figure 74.	DAC conversion (SW trigger enabled) with LFSR wave generation. . . . .	283
Figure 75.	DAC triangle wave generation . . . . .	284
Figure 76.	DAC conversion (SW trigger enabled) with triangle wave generation . . . . .	284
Figure 77.	Comparator 2 block diagram . . . . .	293
Figure 78.	Comparator 4 block diagram . . . . .	293
Figure 79.	Comparator 6 block diagram . . . . .	293
Figure 80.	Comparator output blanking . . . . .	296
Figure 81.	Comparator and operational amplifier connections . . . . .	304
Figure 82.	Timer controlled Multiplexer mode . . . . .	305
Figure 83.	Standalone mode: external gain setting mode . . . . .	306
Figure 84.	Follower configuration. . . . .	307
Figure 85.	PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . .	308
Figure 86.	PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for filtering . . . . .	308
Figure 87.	TSC block diagram . . . . .	314
Figure 88.	Surface charge transfer analog I/O group structure . . . . .	315
Figure 89.	Sampling capacitor voltage variation . . . . .	316
Figure 90.	Charge transfer acquisition sequence . . . . .	317
Figure 91.	Spread spectrum variation principle . . . . .	318
Figure 92.	Advanced-control timer block diagram . . . . .	333

Figure 93.	Counter timing diagram with prescaler division change from 1 to 2 . . . . .	336
Figure 94.	Counter timing diagram with prescaler division change from 1 to 4 . . . . .	336
Figure 95.	Counter timing diagram, internal clock divided by 1 . . . . .	338
Figure 96.	Counter timing diagram, internal clock divided by 2 . . . . .	338
Figure 97.	Counter timing diagram, internal clock divided by 4 . . . . .	339
Figure 98.	Counter timing diagram, internal clock divided by N . . . . .	339
Figure 99.	Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	340
Figure 100.	Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	340
Figure 101.	Counter timing diagram, internal clock divided by 1 . . . . .	342
Figure 102.	Counter timing diagram, internal clock divided by 2 . . . . .	342
Figure 103.	Counter timing diagram, internal clock divided by 4 . . . . .	343
Figure 104.	Counter timing diagram, internal clock divided by N . . . . .	343
Figure 105.	Counter timing diagram, update event when repetition counter is not used . . . . .	344
Figure 106.	Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .	345
Figure 107.	Counter timing diagram, internal clock divided by 2 . . . . .	346
Figure 108.	Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	346
Figure 109.	Counter timing diagram, internal clock divided by N . . . . .	347
Figure 110.	Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .	347
Figure 111.	Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .	348
Figure 112.	Update rate examples depending on mode and TIMx_RCR register settings . . . . .	349
Figure 113.	External trigger input block . . . . .	350
Figure 114.	Control circuit in normal mode, internal clock divided by 1 . . . . .	351
Figure 115.	TI2 external clock connection example . . . . .	352
Figure 116.	Control circuit in external clock mode 1 . . . . .	353
Figure 117.	External trigger input block . . . . .	353
Figure 118.	Control circuit in external clock mode 2 . . . . .	354
Figure 119.	Capture/compare channel (example: channel 1 input stage) . . . . .	355
Figure 120.	Capture/compare channel 1 main circuit . . . . .	356
Figure 121.	Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .	356
Figure 122.	Output stage of capture/compare channel (channel 4) . . . . .	357
Figure 123.	Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .	357
Figure 124.	PWM input mode timing . . . . .	359
Figure 125.	Output compare mode, toggle on OC1 . . . . .	361
Figure 126.	Edge-aligned PWM waveforms (ARR=8) . . . . .	362
Figure 127.	Center-aligned PWM waveforms (ARR=8) . . . . .	363
Figure 128.	Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .	365
Figure 129.	Combined PWM mode on channel 1 and 3 . . . . .	366
Figure 130.	3-phase combined PWM signals with multiple trigger pulses per period . . . . .	367
Figure 131.	Complementary output with dead-time insertion . . . . .	368
Figure 132.	Dead-time waveforms with delay greater than the negative pulse . . . . .	368
Figure 133.	Dead-time waveforms with delay greater than the positive pulse . . . . .	369
Figure 134.	Various output behavior in response to a break event on BKIN (OSSI = 1) . . . . .	372
Figure 135.	PWM output state following BKIN and BKIN2 pins assertion (OSSI=1) . . . . .	373
Figure 136.	PWM output state following BKIN assertion (OSSI=0) . . . . .	374
Figure 137.	Clearing TIMx_OCxREF . . . . .	375
Figure 138.	6-step generation, COM example (OSSR=1) . . . . .	376
Figure 139.	Example of one pulse mode . . . . .	377
Figure 140.	Retriggerable one pulse mode . . . . .	379
Figure 141.	Example of counter operation in encoder interface mode . . . . .	380
Figure 142.	Example of encoder interface mode with TI1FP1 polarity inverted . . . . .	381
Figure 143.	Measuring time interval between edges on 3 signals . . . . .	382
Figure 144.	Example of Hall sensor interface . . . . .	384

Figure 145. Control circuit in reset mode . . . . .	385
Figure 146. Control circuit in Gated mode . . . . .	386
Figure 147. Control circuit in trigger mode . . . . .	387
Figure 148. Control circuit in external clock mode 2 + trigger mode . . . . .	388
Figure 149. General-purpose timer block diagram . . . . .	427
Figure 150. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	429
Figure 151. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	429
Figure 152. Counter timing diagram, internal clock divided by 1 . . . . .	430
Figure 153. Counter timing diagram, internal clock divided by 2 . . . . .	431
Figure 154. Counter timing diagram, internal clock divided by 4 . . . . .	431
Figure 155. Counter timing diagram, internal clock divided by N . . . . .	432
Figure 156. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .	432
Figure 157. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .	433
Figure 158. Counter timing diagram, internal clock divided by 1 . . . . .	434
Figure 159. Counter timing diagram, internal clock divided by 2 . . . . .	434
Figure 160. Counter timing diagram, internal clock divided by 4 . . . . .	435
Figure 161. Counter timing diagram, internal clock divided by N . . . . .	435
Figure 162. Counter timing diagram, Update event . . . . .	436
Figure 163. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .	437
Figure 164. Counter timing diagram, internal clock divided by 2 . . . . .	438
Figure 165. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	438
Figure 166. Counter timing diagram, internal clock divided by N . . . . .	439
Figure 167. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .	439
Figure 168. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .	440
Figure 169. Control circuit in normal mode, internal clock divided by 1 . . . . .	441
Figure 170. TI2 external clock connection example. . . . .	441
Figure 171. Control circuit in external clock mode 1 . . . . .	442
Figure 172. External trigger input block . . . . .	443
Figure 173. Control circuit in external clock mode 2 . . . . .	444
Figure 174. Capture/Compare channel (example: channel 1 input stage) . . . . .	445
Figure 175. Capture/Compare channel 1 main circuit . . . . .	445
Figure 176. Output stage of Capture/Compare channel (channel 1). . . . .	446
Figure 177. PWM input mode timing . . . . .	448
Figure 178. Output compare mode, toggle on OC1 . . . . .	450
Figure 179. Edge-aligned PWM waveforms (ARR=8). . . . .	451
Figure 180. Center-aligned PWM waveforms (ARR=8). . . . .	452
Figure 181. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .	453
Figure 182. Combined PWM mode on channels 1 and 3 . . . . .	455
Figure 183. Clearing TIMx_OCxREF . . . . .	456
Figure 184. Example of one-pulse mode. . . . .	457
Figure 185. Retriggerable one-pulse mode . . . . .	459
Figure 186. Example of counter operation in encoder interface mode . . . . .	460
Figure 187. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .	461
Figure 188. Control circuit in reset mode . . . . .	462
Figure 189. Control circuit in gated mode . . . . .	463
Figure 190. Control circuit in trigger mode . . . . .	464
Figure 191. Control circuit in external clock mode 2 + trigger mode . . . . .	465
Figure 192. Master/Slave timer example . . . . .	466
Figure 193. Master/slave connection example with 1 channel only timers . . . . .	466
Figure 194. Gating TIM2 with OC1REF of TIM1 . . . . .	467
Figure 195. Gating TIM2 with Enable of TIM1 . . . . .	468
Figure 196. Triggering TIM2 with update of TIM1 . . . . .	469

Figure 197. Triggering TIM2 with Enable of TIM1 . . . . .	469
Figure 198. TIM15 block diagram . . . . .	498
Figure 199. TIM16/TIM17 block diagram . . . . .	499
Figure 200. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	501
Figure 201. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	501
Figure 202. Counter timing diagram, internal clock divided by 1 . . . . .	503
Figure 203. Counter timing diagram, internal clock divided by 2 . . . . .	503
Figure 204. Counter timing diagram, internal clock divided by 4 . . . . .	504
Figure 205. Counter timing diagram, internal clock divided by N . . . . .	504
Figure 206. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .	505
Figure 207. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .	505
Figure 208. Update rate examples depending on mode and TIMx_RCR register settings . . . . .	507
Figure 209. Control circuit in normal mode, internal clock divided by 1 . . . . .	508
Figure 210. TI2 external clock connection example. . . . .	508
Figure 211. Control circuit in external clock mode 1 . . . . .	509
Figure 212. Capture/compare channel (example: channel 1 input stage). . . . .	510
Figure 213. Capture/compare channel 1 main circuit . . . . .	510
Figure 214. Output stage of capture/compare channel (channel 1). . . . .	511
Figure 215. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .	511
Figure 216. PWM input mode timing . . . . .	513
Figure 217. Output compare mode, toggle on OC1 . . . . .	515
Figure 218. Edge-aligned PWM waveforms (ARR=8) . . . . .	516
Figure 219. Combined PWM mode on channel 1 and 2 . . . . .	517
Figure 220. Complementary output with dead-time insertion. . . . .	518
Figure 221. Dead-time waveforms with delay greater than the negative pulse. . . . .	518
Figure 222. Dead-time waveforms with delay greater than the positive pulse. . . . .	519
Figure 223. Output behavior in response to a break . . . . .	522
Figure 224. 6-step generation, COM example (OSSR=1) . . . . .	523
Figure 225. Example of one pulse mode . . . . .	524
Figure 226. Retriggerable one pulse mode . . . . .	526
Figure 227. Measuring time interval between edges on 2 signals . . . . .	527
Figure 228. Control circuit in reset mode . . . . .	528
Figure 229. Control circuit in gated mode . . . . .	529
Figure 230. Control circuit in trigger mode . . . . .	530
Figure 231. Basic timer block diagram. . . . .	575
Figure 232. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	577
Figure 233. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	577
Figure 234. Counter timing diagram, internal clock divided by 1 . . . . .	578
Figure 235. Counter timing diagram, internal clock divided by 2 . . . . .	579
Figure 236. Counter timing diagram, internal clock divided by 4 . . . . .	579
Figure 237. Counter timing diagram, internal clock divided by N . . . . .	580
Figure 238. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .	580
Figure 239. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .	581
Figure 240. Control circuit in normal mode, internal clock divided by 1 . . . . .	582
Figure 241. IRTIM internal hardware connections with TIM16 and TIM17 . . . . .	588
Figure 242. Watchdog block diagram . . . . .	590
Figure 243. Window watchdog timing diagram . . . . .	591
Figure 244. Independent watchdog block diagram . . . . .	595

Figure 245.	RTC block diagram . . . . .	606
Figure 246.	Block diagram . . . . .	650
Figure 247.	I ²C-bus protocol . . . . .	652
Figure 248.	Setup and hold timings . . . . .	654
Figure 249.	I2C initialization flow . . . . .	656
Figure 250.	Data reception . . . . .	657
Figure 251.	Data transmission . . . . .	658
Figure 252.	Target initialization flow . . . . .	661
Figure 253.	Transfer sequence flow for I2C target transmitter, NOSTRETCH = 0 . . . . .	663
Figure 254.	Transfer sequence flow for I2C target transmitter, NOSTRETCH = 1 . . . . .	664
Figure 255.	Transfer bus diagrams for I2C target transmitter (mandatory events only) . . . . .	665
Figure 256.	Transfer sequence flow for I2C target receiver, NOSTRETCH = 0 . . . . .	666
Figure 257.	Transfer sequence flow for I2C target receiver, NOSTRETCH = 1 . . . . .	667
Figure 258.	Transfer bus diagrams for I2C target receiver (mandatory events only) . . . . .	667
Figure 259.	Controller clock generation . . . . .	669
Figure 260.	Controller initialization flow . . . . .	671
Figure 261.	10-bit address read access with HEAD10R = 0 . . . . .	671
Figure 262.	10-bit address read access with HEAD10R = 1 . . . . .	672
Figure 263.	Transfer sequence flow for I2C controller transmitter, N ≤ 255 bytes. . . . .	673
Figure 264.	Transfer sequence flow for I2C controller transmitter, N > 255 bytes. . . . .	674
Figure 265.	Transfer bus diagrams for I2C controller transmitter (mandatory events only) . . . . .	675
Figure 266.	Transfer sequence flow for I2C controller receiver, N ≤ 255 bytes . . . . .	677
Figure 267.	Transfer sequence flow for I2C controller receiver, N > 255 bytes. . . . .	678
Figure 268.	Transfer bus diagrams for I2C controller receiver (mandatory events only) . . . . .	679
Figure 269.	Timeout intervals for t _LOW:SEXT, t _LOW:MEXT. . . . .	683
Figure 270.	Transfer sequence flow for SMBus target transmitter N bytes + PEC . . . . .	687
Figure 271.	Transfer bus diagram for SMBus target transmitter (SBC = 1). . . . .	687
Figure 272.	Transfer sequence flow for SMBus target receiver N bytes + PEC . . . . .	689
Figure 273.	Bus transfer diagrams for SMBus target receiver (SBC = 1) . . . . .	690
Figure 274.	Bus transfer diagrams for SMBus controller transmitter . . . . .	691
Figure 275.	Bus transfer diagrams for SMBus controller receiver . . . . .	693
Figure 276.	USART block diagram . . . . .	716
Figure 277.	Word length programming . . . . .	718
Figure 278.	Configurable stop bits . . . . .	720
Figure 279.	TC/TXE behavior when transmitting . . . . .	721
Figure 280.	Start bit detection when oversampling by 16 or 8. . . . .	722
Figure 281.	Data sampling when oversampling by 16 . . . . .	726
Figure 282.	Data sampling when oversampling by 8 . . . . .	726
Figure 283.	Mute mode using Idle line detection . . . . .	733
Figure 284.	Mute mode using address mark detection . . . . .	734
Figure 285.	Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .	737
Figure 286.	Break detection in LIN mode vs. Framing error detection. . . . .	738
Figure 287.	USART example of synchronous transmission. . . . .	739
Figure 288.	USART data clock timing diagram (M bits = 00). . . . .	739
Figure 289.	USART data clock timing diagram (M bits = 01) . . . . .	740
Figure 290.	RX data setup/hold time . . . . .	740
Figure 291.	ISO 7816-3 asynchronous protocol . . . . .	742
Figure 292.	Parity error detection using the 1.5 stop bits . . . . .	743
Figure 293.	IrDA SIR ENDEC- block diagram . . . . .	747

Figure 294. IrDA data modulation (3/16) - normal mode . . . . .	747
Figure 295. Transmission using DMA . . . . .	749
Figure 296. Reception using DMA . . . . .	750
Figure 297. Hardware flow control between 2 USARTs . . . . .	750
Figure 298. RS232 RTS flow control . . . . .	751
Figure 299. RS232 CTS flow control . . . . .	752
Figure 300. USART interrupt mapping diagram . . . . .	755
Figure 301. SPI block diagram. . . . .	782
Figure 302. Full-duplex single master/ single slave application. . . . .	783
Figure 303. Half-duplex single master/ single slave application . . . . .	784
Figure 304. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . .	785
Figure 305. Master and three independent slaves. . . . .	786
Figure 306. Multimaster application . . . . .	787
Figure 307. Hardware/software slave select management . . . . .	788
Figure 308. Data clock timing diagram . . . . .	789
Figure 309. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .	790
Figure 310. Packing data in FIFO for transmission and reception . . . . .	794
Figure 311. Master full-duplex communication . . . . .	797
Figure 312. Slave full-duplex communication . . . . .	798
Figure 313. Master full-duplex communication with CRC . . . . .	799
Figure 314. Master full-duplex communication in packed mode . . . . .	800
Figure 315. NSSP pulse generation in Motorola SPI master mode. . . . .	803
Figure 316. TI mode transfer . . . . .	804
Figure 317. I2S block diagram . . . . .	807
Figure 318. I2S full-duplex block diagram . . . . .	808
Figure 319. I ²S Philips protocol waveforms (16/32-bit full accuracy). . . . .	810
Figure 320. I ²S Philips standard waveforms (24-bit frame) . . . . .	810
Figure 321. Transmitting 0x8EAA33 . . . . .	810
Figure 322. Receiving 0x8EAA33 . . . . .	811
Figure 323. I ²S Philips standard (16-bit extended to 32-bit packet frame) . . . . .	811
Figure 324. Example of 16-bit data frame extended to 32-bit channel frame . . . . .	811
Figure 325. MSB Justified 16-bit or 32-bit full-accuracy length . . . . .	812
Figure 326. MSB justified 24-bit frame length . . . . .	812
Figure 327. MSB justified 16-bit extended to 32-bit packet frame . . . . .	812
Figure 328. LSB justified 16-bit or 32-bit full-accuracy . . . . .	813
Figure 329. LSB justified 24-bit frame length . . . . .	813
Figure 330. Operations required to transmit 0x3478AE. . . . .	813
Figure 331. Operations required to receive 0x3478AE . . . . .	814
Figure 332. LSB justified 16-bit extended to 32-bit packet frame . . . . .	814
Figure 333. Example of 16-bit data frame extended to 32-bit channel frame . . . . .	814
Figure 334. PCM standard waveforms (16-bit) . . . . .	815
Figure 335. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .	815
Figure 336. Start sequence in master mode . . . . .	816
Figure 337. Audio sampling frequency definition . . . . .	817
Figure 338. I ²S clock generator architecture . . . . .	817
Figure 339. Block diagram of STM32 MCU and Cortex ^®-M4F-level debug support . . . . .	837
Figure 340. SWJ debug port . . . . .	839
Figure 341. JTAG TAP connections . . . . .	843
Figure 342. TPIU block diagram . . . . .	858

RM0366-STM32F301x6-8-318x8

Contents

List of tables

List of figures

Chapters

RM0366-STM32F301x6-8-318x8

Related documents

Contents

List of tables

List of figures

Chapters