35. Revision history

• – Section 9: System configuration controller (SYSCFG).
• – Section 25: Inter-integrated circuit (I2C) interface.

• – Transfer bus diagrams for I2C slave transmitter,
• – Transfer bus diagrams for I2C slave receiver,
• – Transfer bus diagrams for I2C master transmitter,
• – Transfer bus diagrams for SMBus slave transmitter (SBC=1),
• – Transfer bus diagrams for SMBus slave transmitter (SBC=1).

• – Updated Table: Available features related to each product

• – Figure: ADC block diagram,
• – Figure: ADC block diagram,
• – Figure: VBAT channel block diagram,
• – Section: ADC configuration register (ADCx_CFGR, x=1..2),
• – Section: ADC Analog Watchdog 2 Configuration Register (ADCx_AWD2CR, x=1..2),
• – Section: ADC Analog Watchdog 3 Configuration Register (ADCx_AWD3CR, x=1..2),
• – Section: ADC Differential Mode Selection Register (ADCx_DIFSEL, x=1..2)

• – Figure: STM32F318x8STM32F3xx clock tree,
• – Section: Clock configuration register 3 (RCC_CFGR3),
• – Section: Control/status register (RCC_CSR),
• – Section: RCC register map.

• – Section: SYSCFG configuration register 2 (SYSCFG_CFGR2)
• – Section: SYSCFG register map.

• – Table: STM32F302xB/C/D/E vector table.

• – Figure: STM32F302xB/C/D/E comparator and operational amplifier connections.

Added Section: Peripheral interconnect matrix .
Extended the applicability to STM32F302xD/E devices.
Updated the following chapters:
Overview of the manual
– Table: Available features related to each product
System and memory overview
– Section: System architecture
– Table: STM32F302xD/E peripheral register boundary addresses (new table)
– Section: Embedded SRAM
Embedded Flash memory
– Section: Flash main features
– Section: Flash memory functional description
– Table: Flash module organization
Option byte description
– Table: Option byte organization
– Table: Description of the option bytes
Flexible memory controller (FMC)
– New chapter.
Power control (PWR)
– Section: Independent A/D and D/A converter supply and reference voltage
Reset and clock control (RCC)
– Section: Clocks
– Section: RCC registers
General purpose I/Os (GPIO)
– Section : GPIO main features
– Section: GPIO registers
System configuration controller
– Section: SYSCFG registers
Direct memory access controller (DMA)
– Table: STM32F302xB/C/D/E summary of DMA1 requests for each channel
– Table: STM32F302xB/C/D/E summary of DMA2 requests for each channel

Updated TIMER section:

• – Updated Table 115: TIM1 internal trigger connection removing the line where the “Slave TIM” is mentioned as reserved.
• – Updated Section 22.4.19: Slave mode – combined reset + trigger mode (TIM15 only) adding (TIM15 only) on the title.
• – Updated Section 22.5.8: TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) and Section 22.5.19: TIM15 register map replacing bit 7 ‘reserved’ by OC1CE.
• – Updated Section 21.4.14: TIMx prescaler (TIMx_PSC)(x = 2 to 4) , Section 23.4.7: TIM6 prescaler (TIM6_PSC) PSC[15:0] bits description
• – Updated Section 20.4.5: TIM1 status register (TIM1_SR) and Section 20.4.27: TIM1 register map CC5IF and CC6IF bit names.
• – Added Section 20.3.4: External trigger input .
• – Updated Section 20.3.27: DMA burst mode adding note ‘reserved registers can be written with a null value’.
• – Updated Section 20.3.28: Debug mode adding ‘for safety purposes’ paragraph.
• – Updated Table 116: Output control bits for complementary OCx and OCxN channels with break feature in Section 20: Advanced-control timer (TIM1) .

Updated RCC section:

• – Updated Figure 14: STM32F302x6/8 clock tree replacing ‘USARTx(x=1,2,3)’ by ‘USART1’.
• – Updated Figure 13: STM32F302xD/E clock tree adding x2 factor going to TIM2/3/4 when PLLCLK is timer clock source.
• – Updated Section 9.4.2: Clock configuration register (RCC_CFGR) renaming USBPRES by USBPRE and adding bit22 USBPRE description.
• – Updated Section 9.4.9: RTC domain control register (RCC_BDCR) LSEDRV[1:0] bits: ‘01’ and ‘10’ combinations swapped.
• – Updated Section 9.2.9: RTC clock adding “the RTC remains clocked and functional under system reset” when the RTC clock is LSE.

Updated Embedded Flash memory section:

• – Updated Section 4.5.1: Flash access control register (FLASH_ACR) bits LATENCY[2:0] replacing SYSCLK by HCLK.

Updated operational amplifier section (OPAMP) section:

• – Updated Table 105: Connections with dedicated I/O .

Updated DEBUG section:

• – Updated Section 33.14.2: Debug support for timers, watchdog, bxCAN and I ² C adding paragraphs for timers having complementary outputs.
• – Updated Section 33.14.4: Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) and Section 33.14.5: Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) DBG_TIMx_STOP bit description.

Updated RTC section:

• – Updated Figure 283: RTC block diagram adding note on RTC_TAMP3 and replacing RTC_WUTR 'ck_apre' input by 'ck_spre' input.
• – Updated Section 27.6.16: RTC tamper and alternate function configuration register (RTC_TAFCR) adding Tamper 2, Tamper 3 bits and adding note on the Tamper 3 bits.
• – Updated WUCKSEL bits in Figure 283: RTC block diagram .
• – Added case of RTC clocked by LSE in Section 27.3.9: Resetting the RTC .
• – Added caution at the end of Section 27.6.3: RTC control register (RTC_CR) .
• – Updated caution at the end of Section 27.6.16: RTC tamper and alternate function configuration register (RTC_TAFCR) .
• – Updated ADD1H and SUB1H bit descriptions in Section 27.6.3: RTC control register (RTC_CR) .
• – Updated Section : RTC backup registers and Section 27.6.19: RTC backup registers (RTC_BKPxR) : RTC_BKPxR registers cannot be reset when the Flash readout protection is disabled.

Updated Touch sensing controller section:

• – Updated Section 19.3.4: Charge transfer acquisition sequence adding note about the TSC control register configuration forbidden.
• – Updated Section 19.6.1: TSC control register (TSC_CR) adding note for CTPL[3:0] bits and PGPPSC[2:0] bits.

Updated USART section:

• – Updated Section Table 154.: STM32F302xx USART features replacing 'USART4, 5' by 'UART4, 5'.
• – Updated Section 29.5.17: Wakeup from Stop mode using USART adding paragraph "determining the maximum USART baudrate".
• – Updated whole USART document replacing any occurrence of: nCTS by CTS, nRTS by RTS, SCLK by CK.
• – Updated Section 29.8.9: USART interrupt flag clear register (USART_ICR) replacing "w" by "rc_wl".
• – Updated Section 29.8.8: USART interrupt and status register (USART_ISR) RTOF field replacing USART_CR2 by USART_CR1.
• – Updated Section 29.8.3: USART control register 3 (USART_CR3) 'ONEBIT' bit 11 description adding a note.
• – Updated Section 29: Universal synchronous/asynchronous receiver transmitter (USART/UART) changing register name USARTx_regnname in USART_regnname.
• – Changed tWUSTOP to tWUUSART and updated Section 29.5.5: Tolerance of the USART receiver to clock deviation .
• – Updated Section 29.8.8: USART interrupt and status register (USART_ISR) RWU bit available independently of the wakeup from stop feature availability.
• – Updated Section 29.8.12: USART register map RWU bit.

Updated COMP section:

• – Updated Section 17.2: COMP main features COMP1 and COMP2 combined in a window comparator for STM32F302xB/C only.
• – Updated Figure 118: Comparator 1 and 2 block diagrams .
• – Updated Section 17.5.2: COMP2 control and status register (COMP2_CSR) replacing note 2 on bit 9 by ‘not available in STM32F302x6/8/D/E devices’ and updating bit 9 description.

Updated FMC section:

• – Updated Section 14.5.4: NOR Flash/PSRAM controller asynchronous transactions putting ‘de-asserting the NOE signal’.
• – Updated Section : FIFO status and interrupt register x (FMC_SRx) bit0 (IRS) and Bit2 (IFS) adding a note.
• – Updated Section : SRAM/NOR-Flash chip-select timing registers x (FMC_BTRx) adding new paragraph.
• – Updated Section : SRAM/NOR-Flash write timing registers x (FMC_BWTRx) adding new paragraph.
• – Updated Figure 49: NAND Flash/PC Card controller waveforms for common memory access replacing ‘MEMxHIZ’ by ‘MEMxHIZ+1’ and adding note 2.
• – Updated Section 14.6.5: NAND Flash prewait functionality .
• – Updated Common memory space timing register x (FMC_PMEMx) MEMHOLD[7:0] description.
• – Updated Attribute memory space timing registers x (FMC_PATTx) ATTHOLD[7:0] description.
• – Updated Section 14.3: AHB interface .

Updated ADC section:

• – Updated Section 15.2: ADC main features and Section 15.3.29: Dual ADC modes (STM32F302xB/C/D/E only) replacing ‘STM32F302xB/xC only’ by ‘STM32F302xB/C/D/E only’.
• – Updated Section 15.3.3: Clocks note, replacing option a) by option b) and removing ‘or 10’.

Updated SPI2S section:

Updated Figure 358: I2S full-duplex block diagram in Section 30.7.2: I2S full duplex .

Updated interrupts and events section:

• – Updated Section 13.2.6: External and internal interrupt/event line mapping removing STM32F302x6/8 in EXTI lines 21, 34 and 35, updating the note and adding STM32F302xB/C/D/E only in EXTI lines 26, 28.
• – Updated Interrupt mask register (EXTI_IMR1) and Event mask register (EXTI_EMR1) bits 29, 31 reserved.
• – Updated Rising trigger selection register (EXTI_RTSR1) , Falling trigger selection register (EXTI_FTSR1) , Software interrupt event register (EXTI_SWIER1) and Pending register (EXTI_PR1) bits 23 up to 29, 31 reserved.
• – Updated Section 13.3.7: Interrupt mask register (EXTI_IMR2) and Section 13.3.8: Event mask register (EXTI_EMR2) bit 1 reserved.
• – Updated Section 13.3.9: Rising trigger selection register (EXTI_RTSR2) , Section 13.3.10: Falling trigger selection register (EXTI_FTSR2) , Section 13.3.11: Software interrupt event register (EXTI_SWIER2) and Section 13.3.12: Pending register (EXTI_PR2) bit 0 reserved.

Updated DMA section:

• – updated Table 49: Programmable data width & endianness (when bits PINC = MINC = 1) .

Updated I2C2 section:

• – Updated Figure 288: Setup and hold timings .
• – Updated Section 28.4.5: I2C initialization updating and adding notes in Section : I2C timings .
• – Updated Section 33.7.5: Timing register (I2C_TIMINGRFMP12C_TIMINGR) SCLDEL[3:0] and SDADEL[3:0] bits description.
• – Updated Section 28.4.5: I2C initialization , Section 28.4.9: I2C master mode and Section 33.7.5: Timing register (I2C_TIMINGRFMP12C_TIMINGR) adding the sentence “The STM32CubeMX tool calculates and provides the I2C_TIMIGR content in the I2C configuration window”.
• – Updated Section 28.4.9: I2C master mode note in Master communication initialization (address phase) paragraph.
• – Updated Section 33.7.2: Control register 2 (I2C_CR2FMP12C_CR2) completing the note of bit 13 ‘START’ description.

Updated comparator section:

• – Updated root part numbers in Section 17.1: Introduction..
• – Updated Figure 118: Comparator 1 and 2 block diagrams adding PA5 input in the 2 MUX with note 4, replacing note 1 by note 4 for TIM3_OC1 and TIM3_OCREP_CLR outputs.
• – Updated Table 102: STM32F302xB/C/D/E comparator input/outputs summary adding PA4 and PA5 comparator inputs connected to I/Os.
• – Updated Table 103: STM32F302xB/C/D/E comparator input/outputs summary adding PA4 comparator input connected to I/Os.
• – Updated Section 17.5.2: COMP2 control and status register (COMP2_CSR) COMP2OUTSEL[3:0] and COMP2INMSEL[2:0] bit description.
• – Updated Section 17.5.3: COMP4 control and status register (COMP4_CSR) COMP4OUTSEL[3:0] and COMP4INMSEL[2:0] bit description.
• – Updated Section 17.5.4: COMP6 control and status register (COMP6_CSR) COMP6OUTSEL[3:0], COMP6INMSEL[2:0] and COMP6MODE[3:2] bit description.
• – Added note 'depending on the product, when a timer is not available, the corresponding combination is reserved' in all the COMPxOUTSEL[3:0] bit description for x = 1...7

Updated opamp section:

• – Updated Figure 121: STM32F302xB/C/D/E comparator and operational amplifier connections.

Updated RTC section:

• – Updated Figure 285: RTC block diagram removing 1 Hz and 512 Hz text and changing mux connection (RTC_SSR output instead of ck_spre).
• – Updated note in Section 27.3.15: Calibration clock output.

Updated Section 2.2: List of abbreviations for registers , Section 3.1: System architecture , Section 6.2: CRC main features , sections 12.1 to 12.4 and their subsections, Section 12.6.1: DMA interrupt status register (DMA_ISR) , Section 12.6.2: DMA interrupt flag clear register (DMA_IFCR) , External clock source mode 2 , Section 20.3.16: Using the break function , Section 20.3.28: Debug mode , Section 20.4.3: TIM1 slave mode control register (TIM1_SMCR) , Section 20.4.5: TIM1 status register (TIM1_SR) , Section 33.4.24: TIM8 option register 1 (TIM8_OR1) , External clock source mode 2 , Timer synchronization , Section 22.4.13: Using the break function , Section 22.5.5: TIM15 status register (TIM15_SR) , Section 27.3.4: Real-time clock and calendar , Section 27.3.6: Periodic auto-wakeup , Section 27.3.11: RTC reference clock detection , Section 27.6.3: RTC control register (RTC_CR) , Section 27.6.13: RTC timestamp date register (RTC_TSDR) , Section 28.6: I2C interrupts , Section 28.7.1: I2C control register 1 (I2C_CR1) , Section 28.7.3: I2C own address 1 register (I2C_OAR1) , Section 29.5.1: USART character description , Section 29.8.10: USART receive data register (USART_RDR) , Section 29.8.11: USART transmit data register (USART_TDR) , Simplex communications , Clock generator , Section 32.6: USB and USB SRAM registers and Section 32.6.2: Buffer descriptor table .

Split CCMR1 and CCMR2 in Section 20.4: TIM1 registers , Section 21.4: TIM2/TIM3/TIM4 registers , Section 22.5: TIM15 registers and Section 22.6: TIM16/TIM17 registers .

Added Section 2.1: General information , Section 12.5: DMA interrupts , Section 22.4.15: Retriggerable one pulse mode (TIM15 only) , Section 22.4.22: Using timer output as trigger for other timers (TIM16/TIM17) and Section 25.4: WWDG interrupts .

Updated Table 117: TIM1 register map and reset values , Table 121: TIM2/TIM3/TIM4 register map and reset values , Table 123: Output control bits for complementary OCx and OCxN channels with break feature (TIM15) , Table 124: TIM15 register map and reset values , Table 125: Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) , Table 126: TIM16/TIM17 register map and reset values , Table 126: TIM16/TIM17 register map and reset values , Table 151: Effect of low-power modes on the I2C , Table 152: I2C Interrupt requests , Table 163: STM32F302x6/8 SPI/I2S implementation and Table 164: STM32F302xB/C/D/E SPI and SPI/I2S implementation .

Added footnote 5 to Table 154: STM32F302xx USART features and footnote to Figure 350: Packing data in FIFO for transmission and reception .

Updated Figure 63: Example of JSQR queue of context (sequence change) , Figure 64: Example of JSQR queue of context (trigger change) , Figure 67: Example of JSQR queue of context with empty queue (case JQM=0) , Figure 130: Charge transfer acquisition sequence , Figure 189: General-purpose timer block diagram , Figure 239: TIM15 block diagram , Figure 282: Watchdog block diagram and Figure 286: I2C block diagram .

Added Figure 233: Master/slave connection example with 1 channel only timers and Figure 380: Single-CAN block diagram .

Minor text edits across the whole document.