17. Comparator (COMP)

17.1 Introduction

STM32F302xB/C/D/E embed four general purpose comparators that can be used either as standalone devices (all terminal are available on I/Os) or combined with the timers. STM32F302x6/8 embed three comparators, COMP2, COMP4 and COMP6.

STM32F302xx embed four general purpose comparators COMP1, COMP2, COMP4 and COMP6 that can be used either as standalone devices (all terminal are available on I/Os) or combined with the timers.

The comparators can be used for a variety of functions including:

• Wakeup from low-power mode triggered by an analog signal,
• Analog signal conditioning,
• Cycle-by-cycle current control loop when combined with the DAC and a PWM output from a timer.

17.2 COMP main features

• Rail-to-rail comparators
• Each comparator has positive and configurable negative inputs used for flexible voltage selection:
- – Multiplexed I/O pins
- – DAC1 channel 1
- – Internal reference voltage and three submultiple values (1/4, 1/2, 3/4) provided by scaler (buffered voltage divider)
• Programmable speed / consumption (only on STM32F302xBxC)
• Programmable hysteresis (only on STM32F302xBxC)
• The outputs can be redirected to an I/O or to timer inputs for triggering:
- – Capture events
- – OCREF_CLR events (for cycle-by-cycle current control)
- – Break events for fast PWM shutdowns
• COMP1 and COMP2 comparators can be combined in a window comparator. This applies to STM32F302xB/C devices only.
• Comparator outputs with blanking source
• Each comparator has interrupt generation capability with wakeup from Sleep and Stop modes (through the EXTI controller)

17.3 COMP functional description

17.3.1 COMP block diagram

The block diagram of the comparators is shown in Figure 118: Comparator 1 and 2 block diagrams .

Figure 118. Comparator 1 and 2 block diagrams

Block diagram of Comparator 1 and 2. The diagram shows two comparators, COMP1 and COMP2. COMP1 has inputs COMP1_INP (+) and COMP1_INM (-). COMP1_INP is connected to PA1 and a multiplexer for window mode. COMP1_INM is connected to a multiplexer with inputs PA0, PA4 (DAC1_CH1), PA5 (DAC1_CH2), VREFINT, 3/4 VREFINT, 1/2 VREFINT, and 1/4 VREFINT. The output COMP1_OUT is connected to PA0/PF4/PA6/PA11/PB8 and to a list of interrupt and timer signals. COMP2 has inputs COMP2_INP (+) and COMP2_INM (-). COMP2_INP is connected to PA3 and a multiplexer for window mode. COMP2_INM is connected to a multiplexer with inputs PA2, PA4 (DAC1_CH1), PA5 (DAC1_CH2), VREFINT, 3/4 VREFINT, 1/2 VREFINT, and 1/4 VREFINT. The output COMP2_OUT is connected to PA2/PA7/PA12/PB9 and to a list of interrupt and timer signals. Both comparators have a 'Polarity selection' block. The diagram is labeled MS34232V4.

1. Available only on STM32F302xB/C.
2. Window mode is not supported on STM32F302x6/8/D/E.
3. COMP1 is not available on STM32F302x6/8.
4. Available only on STM32F302xB/C/D/E.

17.3.2 COMP pins and internal signals

The I/Os used as comparators inputs must be configured in analog mode in the GPIOs registers.

The comparator output can be connected to the I/Os using the alternate function channel given in “Alternate function mapping” table in the datasheet.

The table below summarizes the I/Os that can be used as comparators inputs and outputs.

The output can also be internally redirected to a variety of timer input for the following purposes:

• Emergency shut-down of PWM signals, using BKIN and BKIN2 inputs
• Cycle-by-cycle current control, using OCREF_CLR inputs
• Input capture for timing measures

It is possible to have the comparator output simultaneously redirected internally and externally.

Table 102. STM32F302xB/C/D/E comparator input/outputs summary

-	Comparator input/outputs
-	COMP1	COMP2	COMP4	COMP6
Comparator inverting input: connection to internal signals	DAC1_CH1 Vrefint $\frac{3}{4}$ Vrefint $\frac{1}{2}$ Vrefint $\frac{1}{4}$ Vrefint
Comparator inputs connected to I/Os (+: non inverting input; -: inverting input)	+: PA1 -: PA0 -: PA4 -: PA5	+: PA3 ⁽¹⁾ +: PA7 -: PA2 -: PA4 -: PA5	+: PB0 +: PE7 ⁽¹⁾ -: PB2 -: PE8 -: PA4 -: PA5	+: PB11 +: PD11 ⁽¹⁾ -: PB15 -: PD10 -: PA4 -: PA5
Comparator outputs (motor control protection)	T1BKIN T1BKIN2 T1BKIN2
Outputs on I/Os	PA0 PF4 PA6 PA11 PB8	PA2 PA7 ⁽¹⁾ PA12 PB9	PB1	PA10 PC6
Outputs to internal signals	TIM1_OCrefClear TIM1_IC1 TIM2_IC4 TIM2_OCrefClear TIM3_IC1 TIM3_OCrefClear		TIM3_IC3 TIM3_OCrefClear TIM4_IC2 TIM15_OCrefClear TIM15_IC2	TIM2_IC2 TIM2_OCrefClear TIM16_OCrefClear TIM16_IC1 TIM4_IC4

1. Only on STM32F302xB/C devices.

Table 103. STM32F302x6/8 comparator input/outputs summary

-	Comparator input/outputs
-	COMP2	COMP4	COMP6
Comparator inverting Input: connection to internal signals	DAC1_CH1 Vrefint $\frac{3}{4}$ Vrefint $\frac{1}{2}$ Vrefint $\frac{1}{4}$ Vrefint
Comparator Inputs connected to I/Os (+: non inverting input; -: inverting input)	+: PA7 -: PA2 -: PA4	+: PB0 -: PB2 -: PA4	+: PB11 -: PB15 -: PA4
Comparator outputs (motor control protection)	T1BKIN T1BKIN2
Outputs on I/Os	PA2 PA12 PB12	PB1	PA10 PC6
Outputs to internal signals	TIM1_OCREF_CLR TIM1_IC1 TIM2_IC4 TIM2_OCREF_CLR	TIM15_OCREF_CLR TIM15_IC2	TIM2_IC2 TIM2_OCREF_CLR TIM16_OCREF_CLR TIM16_IC1

17.3.3 COMP reset and clocks

The COMP clock provided by the clock controller is synchronous with the PCLK2 (APB2 clock).

There is no clock enable control bit provided in the RCC controller. To use a clock source for the comparator, the SYSCFG clock enable control bit must be set in the RCC controller.

Important: The polarity selection logic and the output redirection to the port works independently from the PCLK2 clock. This allows the comparator to work even in Stop mode.

17.3.4 Comparator LOCK mechanism

The comparators can be used for safety purposes, such as over-current or thermal protection. For applications having specific functional safety requirements, it is necessary to insure that the comparator programming cannot be altered in case of spurious register access or program counter corruption.

For this purpose, the comparator control and status registers can be write-protected (read-only).

Once the programming is completed, using bits 30:0 of COMPx_CSR, the COMPx LOCK bit can be set to 1. This causes the whole COMPx_CSR register to become read-only, including the COMPx LOCK bit.

The write protection can only be reset by a MCU reset.

17.3.5 Hysteresis (STM32F302xBxC only)

The comparator includes a programmable hysteresis to avoid spurious output transitions in case of noisy signals. The hysteresis can be disabled if it is not needed (for instance when exiting from low-power mode) to be able to force the hysteresis value using external components.

17.3.6 Comparator output blanking function

The purpose of the blanking function is to prevent the current regulation to trip upon short current spikes at the beginning of the PWM period (typically the recovery current in power switches anti parallel diodes). It consists of a selection of a blanking window which is a timer output compare signal. The selection is done by software (refer to the comparator register description for possible blanking signals). Then, the complementary of the blanking signal is ANDed with the comparator output to provide the wanted comparator output. See the example provided in the figure below.

Figure 119. Comparator output blanking

The figure illustrates the timing and logic for the comparator output blanking function. It is divided into two main parts: a timing diagram at the top and a logic schematic at the bottom.

Timing Diagram:

PWM: Shows a periodic square wave signal.
Current limit: A dashed horizontal line representing a threshold.
Current: A sawtooth-like signal that rises linearly and then drops sharply. It spikes above the current limit at the start of each PWM period. Arrows indicate the rising and falling edges of the current signal.
Raw comp output: A signal that pulses high whenever the current exceeds the current limit. It has narrow pulses at the start of each PWM period and wider pulses when the current remains above the limit.
Blanking window: A signal that is high during a short duration at the beginning of each PWM period, coinciding with the current spikes.
Final comp output: The output signal after blanking. It is high only when the raw comp output is high AND the blanking window is low. This effectively suppresses the short spikes at the start of the PWM periods.

Logic Schematic:

Inputs: Comp out (from the raw comparator output) and Blank (the complement of the blanking window signal).
Logic: An AND gate with an inverter on the blank input.
Output: Comp out (to TIM_BK ...) .

MS30964V1

Timing diagram and logic schematic for comparator output blanking.

17.3.7 Power mode (STM32F302xB/C only)

The comparator power consumption versus propagation delay can be adjusted to have the optimum trade-off for a given application. The bits COMPxMODE[1:0] in COMPx_CSR registers can be programmed as follows:

• 00: High speed / full power
• 01: Medium speed / medium power
• 10: Low speed / low-power
• 11: Very-low speed / ultra-low-power

17.4 COMP interrupts

The comparator outputs are internally connected to the Extended interrupts and events controller. Each comparator has its own EXTI line and can generate either interrupts or events. The same mechanism is used to exit from low-power modes.

Refer to Interrupt and events section for more details.

17.5 COMP registers

17.5.1 COMP1 control and status register (COMP1_CSR)

Note: This register is available in STM32F302xB/C/D/E only

Address offset: 0x1C

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
COMP1 LOCK	COMP1 OUT	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	COMP1 BLANKING			COMP1HYST [1:0] ⁽¹⁾
rwo	r										rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP1 POL	Res.	COMP1OUTSEL				Res.	Res.	Res.	COMP1INMSEL[2:0]			COMP1MODE [1:0] ⁽¹⁾		COMP1 _INP_ DAC	COMP 1EN
rw		rw	rw	rw	rw				rw	rw	rw	rw	rw	rw	rw

1. Only in STM32F302xB/C.

Bit 31 COMP1LOCK : Comparator 1 lock

This bit is write-once. It is set by software. It can only be cleared by a system reset.

It allows to have COMP1_CSR register as read-only.

0: COMP1_CSR is read-write.

1: COMP1_CSR is read-only.

Bit 30 COMP1OUT : Comparator 1 output

This read-only bit is a copy of comparator 1 output state.

0: Output is low (non-inverting input below inverting input).

1: Output is high (non-inverting input above inverting input).

Bits 29:21 Reserved, must be kept at reset value.

Bits 20:18 COMP1_BLANKING : Comparator 1 blanking source

These bits select which Timer output controls the comparator 1 output blanking.

000: No blanking
001: TIM1 OC5 selected as blanking source
010: TIM2 OC3 selected as blanking source
011: TIM3 OC3 selected as blanking source
Other configurations: reserved

Bits 17:16 COMP1HYST[1:0] Comparator 1 hysteresis

These bits control the hysteresis level.

00: No hysteresis
01: Low hysteresis
10: Medium hysteresis
11: High hysteresis

Please refer to the electrical characteristics for the hysteresis values.

Bit 15 COMP1POL : Comparator 1 output polarity

This bit is used to invert the comparator 1 output.

0: Output is not inverted
1: Output is inverted

Bit 14 Reserved, must be kept at reset value.

Bits 13:10 COMP1OUTSEL[3:0] : Comparator 1 output selection

These bits select which Timer input must be connected with the comparator1 output.

0000: No selection
0001: (BRK_ACTH) Timer 1 break input
0010: (BRK2) Timer 1 break input 2
0101: Timer 1 break input 2
0110: Timer 1 OCrefclear input
0111: Timer 1 input capture 1
1000: Timer 2 input capture 4
1001: Timer 2 OCrefclear input
1010: Timer 3 input capture 1
1011: Timer 3 OCrefclear input
Remaining combinations: reserved.

Note: Depending on the product, when a timer is not available, the corresponding combination is reserved.

Bits 9:7 Reserved, must be kept at reset value.

Bits 6:4 COMP1INMSEL[2:0] : Comparator 1 inverting input selection

These bits allows to select the source connected to the inverting input of the comparator 1.

000: 1/4 of Vrefint
001: 1/2 of Vrefint
010: 3/4 of Vrefint
011: Vrefint
100: PA4 or DAC1 output if enabled
101: PA5
110: PA0
111: Reserved

Bits 3:2 COMP1MODE[1:0] : Comparator 1 mode

These bits control the operating mode of the comparator1 and allows to adjust the speed/consumption.

00: High speed
01: Medium speed
10: Low-power
11: Ultra-low-power

Bit 1 COMP1_INP_DAC : Comparator 1 non inverting input connection to DAC output.

This bit closes a switch between comparator 1 non-inverting input (PA0) and DAC out I/O (PA4).

0: Switch open
1: Switch closed

Note: This switch is solely intended to redirect signals onto high impedance input, such as COMP1 non-inverting input (highly resistive switch).

Bit 0 COMP1EN : Comparator 1 enable

This bit switches COMP1 ON/OFF.

0: Comparator 1 disabled
1: Comparator 1 enabled

17.5.2 COMP2 control and status register (COMP2_CSR)

Address offset: 0x20

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
COMP2 LOCK	COMP2 OUT	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	COMP2_BLANKING[2:0]			COMP2HYST [1:0] ⁽¹⁾
rwo	r										rw	rw	rw	rw	rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP 2POL	Res.	COMP2OUTSEL[3:0]				COMP2 WIN MODE (2)	Res.	COMP2 INPSEL (1)	COMP2INMSEL[2:0]			COMP2MODE [1:0] ⁽¹⁾		COMP2 _INP_D AC ⁽³⁾	COMP2 EN
rw		rw	rw	rw	rw	rw		rw	rw	rw	rw	rw	rw	rw	rw

1. Only in STM32F302xB/C devices.

2. Not available in STM32F302x6/8/D/E devices.

3. Only in STM32F302x6/8 devices.

Bit 31 COMP2LOCK : Comparator 2 lock

This bit is write-once. It is set by software. It can only be cleared by a system reset.
It allows to have COMP2_CSR register as read-only.
0: COMP2_CSR is read-write.
1: COMP2_CSR is read-only.

Bit 30 COMP2OUT : Comparator 2 output

This read-only bit is a copy of comparator 1output state.
0: Output is low (non-inverting input below inverting input).
1: Output is high (non-inverting input above inverting input).

Bits 29:21 Reserved, must be kept at reset value.

Bits 20:18 COMP2_BLANKING[2:0] : Comparator 2 output blanking source

These bits select which Timer output controls the comparator 1 output blanking.

000: No blanking

001: TIM1 OC5 selected as blanking source

010: TIM2 OC3 selected as blanking source

011: TIM3 OC3 selected as blanking source

Other configurations: reserved

Bits 17:16 COMP2HYST[1:0] : Comparator 2 Hysteresis

On the STM32F302xB/C, these bits control the hysteresis level.

00: No hysteresis

01: Low hysteresis

10: Medium hysteresis

11: High hysteresis

Please refer to the electrical characteristics for the hysteresis values.

On the STM32F302x6/8, these bits are reserved and must be kept at reset value.

Bit 15 COMP2POL : Comparator 2 output polarity

This bit is used to invert the comparator 2 output.

0: Output is not inverted

1: Output is inverted

Bit 14 Reserved, must be kept at reset value.

Bits 13:10 COMP2OUTSEL[3:0] : Comparator 2 output selection

These bits select which Timer input must be connected with the comparator2 output.

0000: No selection

0001: (BRK_ACTH) Timer 1 break input

0010: (BRK2) Timer 1 break input 2

0011: Reserved

0100: Reserved

0101: Timer 1 break input2

0110: Timer 1 OCREF_CLR input

0111: Timer 1 input capture 1

1000: Timer 2 input capture 4

1001: Timer 2 OCREF_CLR input

1010: Timer 3 input capture 1

1011: Timer 3 OCrefclear input

Remaining combinations: reserved.

Note: Depending on the product, when a timer is not available, the corresponding combination is reserved.

Bit 9 COMP2WINMODE : Comparator 2 window mode (only in STM32F302xB/C devices)

This bit selects the window mode: Both non inverting inputs of comparators share the non inverting input of Comparator 1 (PA1).

0: Comparators 1 and 2 can not be used in window mode.

1: Comparators 1 and 2 can be used in window mode.

Bit 8 Reserved, must be kept at reset value.

Bit 7 COMP2INPSEL : Comparator 2 non inverting input selection (Only in STM32F302xB/C devices)

0: PA7 is selected.

1: PA3 is selected.

Note: On STM32F302x6/x8 and STM32F302xD/E, this bit is reserved. COMP2_VINP is available on PA3 whatever value is written in bit 7.

Bits 6:4 COMP2INMSEL[2:0] : Comparator 2 inverting input selection

These bits allows to select the source connected to the inverting input of the comparator 2.
0000: 1/4 of Vrefint
0001: 1/2 of Vrefint
0010: 3/4 of Vrefint
0011: Vrefint
0100: PA4 or DAC1_CH1 output if enabled
0101: PA5 (only on STM32F302xB/C/D/E)
0110: PA2
Remaining combinations: reserved.

Bits 3:2 COMP2MODE[1:0] : Comparator 2 mode (only in STM32F302xB/C devices)

These bits control the operating mode of the comparator2 and allows to adjust the speed/consumption.
00: High speed
01: Medium speed
10: Low-power
11: Ultra-low-power

Bit 1 COMP2_INP_DAC : Comparator 2 non inverting input connection to DAC output. (STM32F302x6/8 devices only)

This bit closes a switch between comparator 2 non-inverting input and DAC out I/O.
0: Switch open
1: Switch closed

This switch is solely intended to redirect signals onto high impedance input, such as COMP2 non-inverting input (highly resistive switch)

Bit 0 COMP2EN : Comparator 2 enable

This bit switches COMP2 ON/OFF.
0: Comparator 2 disabled
1: Comparator 2 enabled

17.5.3 COMP4 control and status register (COMP4_CSR)

Address offset: 0x28

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
COMP4LOCK	COMP4OUT	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res	Res.	COMP4_BLANKING[2:0]			COMP4HYST [1:0] ⁽¹⁾
rwo	r										rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP4POL	Res.	COMP4OUTSEL[3:0]				Res.	Res.	COMP4INPSEL ⁽¹⁾	COMP4INMSEL[2:0]			COMP4MODE [1:0] ⁽¹⁾		Res.	COMP4EN
rw		rw	rw	rw	rw			rw	rw	rw	rw	rw	rw		rw

1. Only in STM32F302xB/C.

Bit 31 COMP4LOCK : Comparator 4 lock

This bit is write-once. It is set by software. It can only be cleared by a system reset.

It allows to have COMP4_CSR register as read-only.

0: COMP4_CSR is read-write.

1: COMP4_CSR is read-only.

Bit 30 COMP4OUT : Comparator 4 output

This read-only bit is a copy of comparator 4 output state.

0: Output is low (non-inverting input below inverting input).

1: Output is high (non-inverting input above inverting input).

Bits 29: Reserved, must be kept at reset value.

Bits 20:18 COMP4_BLANKING : Comparator 4 blanking source

These bits select which Timer output controls the comparator 4 output blanking.

000: No blanking

001: TIM3 OC4 selected as blanking source

010: Reserved

011: TIM15 OC1 selected as blanking source

Other configurations: reserved, must be kept at reset value

Note: Depending on the product, when a timer is not available, the corresponding combination is reserved.

Bits 17:16 COMP4HYST[1:0] : Comparator 4 Hysteresis

On the STM32F302xBC, these bits control the hysteresis level.

00: No hysteresis

01: Low hysteresis

10: Medium hysteresis

11: High hysteresis

Please refer to the electrical characteristics for the hysteresis values.

On the STM32F302x6/8 and STM32F302xD/E, , these bits are reserved and must be kept at reset value.

Bit 15 COMP4POL : Comparator 4 output polarity

This bit is used to invert the comparator 4 output.

0: Output is not inverted

1: Output is inverted

Bit 14 Reserved, must be kept at reset value.

Bits 13:10 COMP4OUTSEL[3:0] : Comparator 4 output selection

These bits select which Timer input must be connected with the comparator4 output.

0000: No timer input selected
0001: (BRK) Timer 1 break input
0010: (BRK2) Timer 1 break input 2
0011: Reserved
0100: Reserved
0101: Timer 1 break input 2
0110: Timer 3 input capture 3
0111: Reserved
1000: Timer 15 input capture 2
1001: Timer 4 input capture 2
1010: Timer 15 OCREF_CLR input
1011: Timer 3 OCrefclear input

Remaining combinations: reserved.

Note: Depending on the product, when a timer is not available, the corresponding combination is reserved.

Bits 9:8 Reserved, must be kept at reset value.

Bit 7 COMP4INPSEL : Comparator 4 non inverting input selection

0: PB0
1: PE7

Note: On STM32F302x6/8 and STM32F302xD/E, this bit is reserved. COMP4_VINP is available on PB0 whatever value is written in bit 7.

Bits 6:4 COMP4INMSEL[2:0] : Comparator 4 inverting input selection

These bits allows to select the source connected to the inverting input of the comparator 4.

0000: 1/4 of Vrefint
0001: 1/2 of Vrefint
0010: 3/4 of Vrefint
0011: Vrefint
0100: PA4 or DAC1_CH1 output if enabled
0101: PA5 (only on STM32F302xB/C/D/E)
0110: PE8
0111: PB2

Remaining combinations: reserved.

Bits 3:2 COMP4MODE[1:0] : Comparator 1 mode (only in STM32F302xB/C devices)

These bits control the operating mode of the comparator 4 and allows to adjust the speed/consumption.

00: Ultra-low-power
01: Low-power
10: Medium speed
11: High speed

Bit 1 Reserved, must be kept at reset value.

Bit 0 COMP4EN : Comparator 4 enable

This bit switches COMP4 ON/OFF.

0: Comparator 4 disabled
1: Comparator 4 enabled

17.5.4 COMP6 control and status register (COMP6_CSR)

Address offset: 0x30

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
COMP6LOCK	COMP6OUT	Res.			Res.			Res.			COMP6_BLANKING[2:0]			COMP6HYST[1:0] ⁽¹⁾
rw	r										rw	rw	rw	rw	rw

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP6POL	Res.	COMP6OUTSEL[3:0]				Res.	Res.	COMP6INPSEL ⁽¹⁾	COMP6INMSEL[2:0]				COMP6MODE[1:0] ⁽¹⁾	Res.	COMP6EN
rw		rw	rw	rw	rw			rw	rw	rw	rw	rw	rw		rw

1. Only in STM32F302xB/C devices.

Bit 31 COMP6LOCK : Comparator 6 lock

This bit is write-once. It is set by software. It can only be cleared by a system reset.

It allows to have COMP6_CSR register as read-only.

0: COMP6_CSR is read-write.

1: COMP6_CSR is read-only.

Bit 30 COMP6OUT : Comparator 6 output

This read-only bit is a copy of comparator 6 output state.

0: Output is low (non-inverting input below inverting input).

1: Output is high (non-inverting input above inverting input).

Bits 29: Reserved, must be kept at reset value.

Bits 20:18 COMP6_BLANKING : Comparator 6 blanking source

These bits select which Timer output controls the comparator 6 output blanking.

000: No blanking

001: Reserved

010: Reserved

011: TIM2 OC4 selected as blanking source

100: TIM15 OC2 selected as blanking source

Other configurations: reserved

The blanking signal is active high (masking comparator output signal). It is up to the user to program the comparator and blanking signal polarity correctly.

Bits 17:16 COMP6HYST[1:0] : Comparator 6 Hysteresis

On the STM32F302xBC, these bits control the hysteresis level.

00: No hysteresis

01: Low hysteresis

10: Medium hysteresis

11: High hysteresis

Please refer to the electrical characteristics for the hysteresis values.

On the STM32F302x6/8, these bits are reserved and must be kept at reset value.

Bit 15 COMP6POL : Comparator 6 output polarity

This bit is used to invert the comparator 6 output.

0: Output is not inverted

1: Output is inverted

Bit 14 Reserved, must be kept at reset value.

Bits 13:10 COMP6OUTSEL[3:0] : Comparator 6 output selection

These bits select which Timer input must be connected with the comparator 6 output.

0000: No timer input
0001: (BRK_ACTH) Timer 1 break input
0010: (BRK2) Timer 1 break input 2
0101: Timer 1 break input 2
0110: Timer 2 input capture 2
1000: Timer 2 OCREF_CLR input
1001: Timer 16 OCREF_CLR input
1010: Timer 16 input capture 1
1011: Timer 4 input capture 4

Remaining combinations: reserved.

Note: Depending on the product, when a timer is not available, the corresponding combination is reserved.

Bits 9:8 Reserved, must be kept at reset value.

Bit 7 COMP6INPSEL : Comparator 6 non inverting input selection

0: PD11
1: PB11

Note: On STM32F302x6/8 and STM32F302xD/E, this bit is reserved. COMP6_VINP is available on PB11 whatever value is written on bit 7.

Bits 6:4 COMP6INMSEL[2:0] : Comparator 6 inverting input selection

These bits allows to select the source connected to the inverting input of the comparator 6.

0000: 1/4 of Vrefint
0001: 1/2 of Vrefint
0010: 3/4 of Vrefint
0011: Vrefint
0100: PA4 or DAC1_CH1 output if enabled
0101: PA5 (only on STM32F302xB/C/D/E)
0110: PD10
0111: PB15

Remaining combinations: reserved.

Bits 3:2 COMP6MODE[1:0] : Comparator 6 mode (only in STM32F302xB/C devices)

These bits control the operating mode of the comparator 6 and allows to adjust the speed/consumption.

00: Ultra-low-power
01: Low-power
10: Medium speed
11: High speed

Bit 1 Reserved, must be kept at reset value.

Bit 0 COMP6EN : Comparator 6 enable

This bit switches COMP6 ON/OFF.

0: Comparator 6 disabled
1: Comparator 6 enabled

17.5.5 COMP register map

The following table summarizes the comparator registers.

Table 104. COMP register map and reset values

Offset	Register	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1
0x1C	COMP1_CSR	COMP1LOCK	COMP1OUT	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	COMPx_BLANKING[2:0]		COMP1HYST[1:0]		COMP1POL	Res.	COMP1OUTSEL[3:0]				Res.	Res.	Res.	COMP1INSEL[2:0]		COMP1MODE[1:0]		COMP1_INP_DAC	COMP1EN
0x1C	Reset value	0	0										0	0	0	0	0	0		0	0	0	0				0	0	0	0	0	0
0x20	COMP2_CSR	COMP2LOCK	COMP2OUT	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	COMP2_BLANKING		Res.		COMP2POL	Res.	COMP2OUTSEL[3:0]				COMP2WINMODE	Res.	COMP2INSEL	COMP2INMSEL[2:0]		COMP2MODE[1:0]		COMP2_INP_DAC	COMP2EN
0x20	Reset value	0	0										0	0	0		0	0		0	0	0	0	0		0	0	0	0	0	0
0x28	COMP4_CSR	COMP4LOCK	COMP4OUT	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	COMP4_BLANKING		Res.		COMP4POL	Res.	COMP4OUTSEL[3:0]				Res.	Res.	COMP4INSEL	COMP4INMSEL[2:0]		COMP4MODE[1:0]		Res.	COMP4EN
0x28	Reset value	0	0										0	0	0		0	0		0	0	0	0		0	0	0	0	0	0
0x30	COMP6_CSR	COMP6LOCK	COMP6OUT	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	COMP6_BLANKING		Res.		COMP6POL	Res.	COMP6OUTSEL[3:0]				Res.	Res.	COMP6INSEL	COMP6INMSEL[2:0]		COMP6MODE[1:0]		Res.	COMP6EN
0x30	Reset value	0	0										0	0	0		0	0		0	0	0	0		0	0	0	0	0	0

Refer to Section 3.2 on page 51 for the register boundary addresses.