16. Digital-to-analog converter (DAC1)

16.1 Introduction

The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In 12-bit mode, the data could be left- or right-aligned. An input reference voltage, $V_{REF+}$ (shared with ADC), is available. The output can optionally be buffered for higher current drive.

16.2 DAC1 main features

• DAC1 integrates one 12-bit DAC channel DAC1_OUT1

The DAC main features are the following:

• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave generation
• Triangular-wave generation
• DMA capability for each channel
• DMA underrun error detection
• External triggers for conversion
• Programmable internal buffer
• Input voltage reference, $V_{DDA}$

Figure 111 shows the block diagram of the DAC1 channel and Table 99 gives the pin description.

Figure 111. DAC1 block diagram

Figure 111. DAC1 block diagram. The diagram shows the internal architecture of the DAC1. On the left, a 'Trigger selector' block receives inputs from SWTRIGx, TIM6_TRGO, TIM3_TRGO (1), TIM2_TRGO, TIM4_TRGO (1), and TIM15_TRGO. It also has a TSELx[2:0] bits input. The output of the trigger selector goes to a 'Control logic' block. The 'Control logic' block also receives inputs from a 'DAC control register' (via DMAENx), a 'DHRx' register (via a 12-bit bus), and 'DMA requestx', 'TENx', 'MAMP x[3:0] bits', and 'WAVEx [1:0] bits'. The 'Control logic' block contains 'LFSRx' and 'trianglex' sub-blocks. Its output goes to a 'DORx' register (via a 12-bit bus). The 'DORx' register output goes to a 'Digital-to-analog converterx' block (via a 12-bit bus). The 'Digital-to-analog converterx' block also receives inputs from V_DDA, V_SSA, and V_REF+. Its output goes to a buffer, which then connects to the 'DACx_OUTy' pin. The 'BOFF' bit from the 'DAC control register' is also connected to the buffer. The diagram is labeled MS32667V1.

1. TIM3_TRGO and TIM4_TRGO are only available on STM32F302xB/C/D/E devices.

Table 99. DACx pins

Name	Signal type	Remarks
V _DDA	Input, analog supply	Analog power supply
V _SSA	Input, analog supply ground	Ground for analog power supply
DAC1_OUT1	Analog output signal	DAC1 channel 1 analog output

Note: Once the DAC1 channel 1 is enabled, the corresponding GPIO pin (PA4) is automatically connected to the analog converter output (DACx_OUTy). In order to avoid parasitic consumption, the PA4, pin should first be configured to analog (AIN).

16.3 DAC output buffer enable

The DAC integrates one output buffer that can be used to reduce the output impedance on DAC1_OUT1 output, and to drive external loads directly without having to add an external operational amplifier.

The DAC channel output buffer can be enabled and disabled through the BOFF1 bit in the DAC_CR register.

16.4 DAC channel enable

The DAC channel can be powered on by setting the EN1 bit in the DAC_CR register. The DAC channel is then enabled after a startup time $t_{\text{WAKEUP}}$ .

Note: The EN1 bit enables the analog DAC Channel macrocell only. The DAC Channel digital interface is enabled even if the EN1 bit is reset.

16.5 Single mode functional description

16.5.1 DAC data format

There are three possibilities:

• 8-bit right alignment: the software has to load data into the DAC_DHR8Rx [7:0] bits (stored into the DHRx[11:4] bits)
• 12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4] bits (stored into the DHRx[11:0] bits)
• 12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0] bits (stored into the DHRx[11:0] bits)

Depending on the loaded DAC_DHRyyxx register, the data written by the user is shifted and stored into the corresponding DHRx (data holding registerx, which are internal non-memory-mapped registers). The DHRx register is then loaded into the DORx register either automatically, by software trigger or by an external event trigger.

Figure 112. Data registers in single DAC channel mode

Diagram showing the data registers in single DAC channel mode. It displays three rows of a 32-bit register (bits 31 to 0) with different alignment options. The first row shows 8-bit right alignment, where data is stored in bits 7-0. The second row shows 12-bit left alignment, where data is stored in bits 15-4. The third row shows 12-bit right alignment, where data is stored in bits 11-0. The diagram is labeled ai14710b.

15	7	0
		■	8-bit right aligned
■			12-bit left aligned
	■	■	12-bit right aligned

ai14710b

Diagram showing the data registers in single DAC channel mode. It displays three rows of a 32-bit register (bits 31 to 0) with different alignment options. The first row shows 8-bit right alignment, where data is stored in bits 7-0. The second row shows 12-bit left alignment, where data is stored in bits 15-4. The third row shows 12-bit right alignment, where data is stored in bits 11-0. The diagram is labeled ai14710b.

16.5.2 DAC channel conversion

The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must be performed by loading the DAC_DHRx register (write to DAC_DHR8Rx, DAC_DHR12Lx, DAC_DHR12Rx).

Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR register is set) and a trigger occurs, the transfer is performed three PCLK1 clock cycles later.

When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage becomes available after a time $t_{\text{SETTLING}}$ that depends on the power supply voltage and the analog output load.

Figure 113. Timing diagram for conversion with trigger disabled TEN = 0

Timing diagram for conversion with trigger disabled TEN = 0. The diagram shows three signals: APB1_CLK (a periodic square wave), DHR (Digital-to-Analog Register), and DOR (Data Output Register). The DHR signal is shown with a value of 0x1AC. The DOR signal is shown with a value of 0x1AC, and an arrow points from it to the text 'Output voltage available on DAC_OUT pin'. A horizontal double-headed arrow labeled 't Settling' indicates the time interval between the DHR value change and the DOR value change. The diagram is labeled 'ai14711b' in the bottom right corner.

Independent trigger with single LFSR generation

To configure the DAC in this conversion mode (see Section 16.6: Noise generation ), the following sequence is required:

1. Set the DAC channel trigger enable bit TENx.
2. Configure the trigger source by setting TSELx[2:0] bits.
3. Configure the DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask value in the MAMPx[3:0] bits
4. Load the DAC channel data into the desired DAC_DHRx register (DHR12RD, DHR12LD or DHR8RD).

When a DAC channelx trigger arrives, the LFSRx counter, with the same mask, is added to the DHRx register and the sum is transferred into DAC_DORx (three APB clock cycles later). Then the LFSRx counter is updated.

Independent trigger with single triangle generation

To configure the DAC in this conversion mode (see Section 16.7: Triangle-wave generation ), the following sequence is required:

1. Set the DAC channelx trigger enable TENx bits.
2. Configure the trigger source by setting TSELx[2:0] bits.
3. Configure the DAC channelx WAVEx[1:0] bits as “1x” and the same maximum amplitude value in the MAMPx[3:0] bits
4. Load the DAC channelx data into the desired DAC_DHRx register. (DHR12RD, DHR12LD or DHR8RD).

When a DAC channelx trigger arrives, the DAC channelx triangle counter, with the same triangle amplitude, is added to the DHRx register and the sum is transferred into DAC_DORx (three APB clock cycles later). The DAC channelx triangle counter is then updated.

16.5.3 DAC output voltage

Digital inputs are converted to output voltages on a linear conversion between 0 and $V_{REF+}$ (or $V_{DDA}$ depending on the package).

The analog output voltages on each DAC channel pin are determined by the following equation:

DAC_{output} = V_{REF+} \times \frac{DOR}{4096}

Note: ( $V_{REF+}$ is replaced by $V_{DDA}$ on the 64-, 49-, 48- and 32-pin packages)

16.5.4 DAC trigger selection

If the TENx control bit is set, conversion can then be triggered by an external event (timer counter, external interrupt line). The TSELx[2:0] control bits determine which possible events will trigger conversion as shown in Table 100 .

Table 100. External triggers (DAC1)

Source	Type	TSEL[2:0]
TIM6_TRGO event	Internal signal from on-chip timers	000
TIM3_TRGO event ⁽¹⁾		001
Reserved		010
TIM15_TRGO event		011
TIM2_TRGO event		100
TIM4_TRGO event		101
EXTI line9	External pin	110
SWTRIG	Software control bit	111

1. To select TIM3_TRGO event as DAC1 trigger source, the DAC_TRIG_RMP bit must be set in SYSCFG_CFGR1 register.

Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on the selected external interrupt line 9, the last data stored into the DAC_DHRx register are transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1 cycles after the trigger occurs.

If the software trigger is selected, the conversion starts once the SWTRIG bit is set. SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the DAC_DHRx register contents.

Note: TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only one APB1 clock cycle.

16.6 Noise generation

In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift register) is available. DAC noise generation is selected by setting WAVEx[1:0] to “01”. The preloaded value in LFSR is 0xAA. This register is updated three APB clock cycles after each trigger event, following a specific calculation algorithm.

Figure 114. DAC LFSR register calculation algorithm

Diagram of the DAC LFSR register calculation algorithm. It shows a 12-bit shift register with cells numbered 11 down to 0. The output of cell 0 is fed back through an XOR gate and also through a 12-bit NOR gate. The output of the XOR gate is fed back to cell 11. The output of the NOR gate is also fed back to cell 11. The feedback signals are labeled X^12, X^6, X^4, X, and X^0. The diagram is labeled ai14713c.

The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this value is then stored into the DAC_DORx register.

If LFSR is 0x0000, a ‘1’ is injected into it (antilock-up mechanism).

It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.

Figure 115. DAC conversion (SW trigger enabled) with LFSR wave generation

Timing diagram showing the relationship between APB1_CLK, DHR, DOR, and SWTRIG signals. APB1_CLK is a periodic square wave. DHR is a signal that is initially 0x00 and then changes to 0xAA. DOR is a signal that is initially 0xAA and then changes to 0xD55. SWTRIG is a signal that is initially low and then goes high. Vertical dashed lines indicate the timing of the signals relative to the clock. The diagram is labeled ai14714b.

Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the DAC_CR register.

16.7 Triangle-wave generation

It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal. DAC triangle-wave generation is selected by setting WAVE[1:0]to “10”. The amplitude is configured through the MAMP[3:0]bits in the DAC_CRregister. An internal triangle counter is incremented three APB clock cycles after each trigger event. The value of this counter is then added to the DAC_DHRxregister without overflow and the sum is stored into the DAC_DORxregister. The triangle counter is incremented as long as it is less than the maximum amplitude defined by the MAMP[3:0]bits. Once the configured amplitude is reached, the counter is decremented down to 0, then incremented again and so on.

It is possible to reset triangle wave generation by resetting the WAVE[1:0]bits.

Figure 116. DAC triangle wave generation

A graph showing the output of a DAC over time. The y-axis represents the DAC output value, with labels for '0', 'DAC_DHRx base value', and 'MAMP[3:0] max amplitude + DAC_DHRx base value'. The x-axis represents time. The waveform is a triangle wave that starts at the base value, rises linearly (labeled 'Incrementation'), reaches the maximum amplitude, and then falls linearly (labeled 'Decrementation') back towards the base value. The pattern repeats. A dashed line indicates the continuation of the waveform. The identifier 'ai14715c' is in the bottom right corner.

Figure 116: DAC triangle wave generation graph

Figure 117. DAC conversion (SW trigger enabled) with triangle wave generation

A timing diagram showing four signals over time: APB1_CLK(a periodic square wave), DHR(Digital-to-Analog Register, holding the value 0xABE), DOR(Data Output Register, showing values 0xABE, 0xABF, and 0xAC0), and SWTRIG(Software Trigger, a pulse signal). The DORsignal changes its value in response to the SWTRIGpulses, incrementing by 1 (0xABE to 0xABF) and then by 2 (0xABF to 0xAC0), illustrating the triangle wave generation. Vertical dashed lines align the signals. The identifier 'ai14716b' is in the bottom right corner.

Figure 117: Timing diagram for DAC conversion with triangle wave generation

Note: The DAC trigger must be enabled for triangle generation by setting the TENxbit in the DAC_CRregister.

The MAMP[3:0]bits must be configured before enabling the DAC, otherwise they cannot be changed.

16.8 DMA request

The DAC channel has a DMA capability. One DMA channel is used to service DAC channel DMA requests.

A DAC DMA request is generated when an external trigger (but not a software trigger) occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred to the DAC_DORx register.

DMA underrun

The DAC DMA request is not queued so that if a second external trigger arrives before the acknowledgment for the first external trigger is received (first request), then no new request is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set, reporting the error condition. DMA data transfers are then disabled and no further DMA request is treated. The DAC channelx continues to convert old data.

The software should clear the DMAUDRx flag by writing “1”, clear the DMAEN bit of the used DMA stream and re-initialize both DMA and DAC channelx to restart the transfer correctly. The software should modify the DAC trigger conversion frequency or lighten the DMA workload to avoid a new DMA. Finally, the DAC conversion can be resumed by enabling both DMA data transfer and conversion trigger.

An interrupt is also generated if the corresponding DMAUDRIE1 bit in the DAC_CR register is enabled.

16.9 DAC registers

Refer to Section 2.2 on page 45 for a list of abbreviations used in register descriptions.

The peripheral registers have to be accessed by words (32-bit).

16.9.1 DAC control register (DAC_CR)

Address offset: 0x00

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.			Res.			Res.			Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	DMAUDRIE1	DMAEN1	MAMP1[3:0]			WAVE1[1:0]			TSEL1[2:0]			TEN1	BOFF1	EN1
		rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 DMAUDRIE1 : DAC channel1 DMA Underrun Interrupt enable

This bit is set and cleared by software.

0: DAC channel1 DMA Underrun Interrupt disabled

1: DAC channel1 DMA Underrun Interrupt enabled

Bit 12 DMAEN1 : DAC channel1 DMA enable

This bit is set and cleared by software.

0: DAC channel1 DMA mode disabled

1: DAC channel1 DMA mode enabled

Bits 11:8 MAMP1[3:0] : DAC channel1 mask/amplitude selector

These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode.

0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1

0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3

0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7

0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15

0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31

0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63

0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127

0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255

1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511

1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023

1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047

≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095

Bits 7:6 WAVE1[1:0] : DAC channel1 noise/triangle wave generation enable

These bits are set and cleared by software.

00: Wave generation disabled

01: Noise wave generation enabled

1x: Triangle wave generation enabled

Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).

Bits 5:3 TSEL1[2:0] : DAC channel1 trigger selection

These bits select the external event used to trigger DAC channel1.

000: Timer 6 TRGO event
001: Timer 3 TRGO event depending on the value of DAC_TRIG_RMP bit in SYSCFG_CFGR1 register (STM32F302x6/8 only)
010: Reserved
011: Timer 15 TRGO event
100: Timer 2 TRGO event
101: Timer 4 TRGO event (STM32F302x6/8 only)
110: EXTI line9
111: Software trigger

Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).

Bit 2 TEN1 : DAC channel1 trigger enable

This bit is set and cleared by software to enable/disable DAC channel1 trigger.

0: DAC channel1 trigger disabled and data written into the DAC_DHRx register are transferred one APB1 clock cycle later to the DAC_DOR1 register
1: DAC channel1 trigger enabled and data from the DAC_DHRx register are transferred three APB1 clock cycles later to the DAC_DOR1 register

Note: When software trigger is selected, the transfer from the DAC_DHRx register to the DAC_DOR1 register takes only one APB1 clock cycle.

Bit 1 BOFF1 : DAC channel1 output buffer disable

This bit is set and cleared by software to enable/disable DAC channel1 output buffer.

0: DAC channel1 output buffer enabled
1: DAC channel1 output buffer disabled

Bit 0 EN1 : DAC channel1 enable

This bit is set and cleared by software to enable/disable DAC channel1.

0: DAC channel1 disabled
1: DAC channel1 enabled

16.9.2 DAC software trigger register (DAC_SWTRIGR)

Address offset: 0x04

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SWTRIG1
															w

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 SWTRIG1 : DAC channel1 software trigger

This bit is set and cleared by software to enable/disable the software trigger.

0: Software trigger disabled

1: Software trigger enabled

Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register.

16.9.3 DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1)

Address offset: 0x08

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	DACC1DHR[11:0]
				rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 DACC1DHR[11:0] : DAC channel1 12-bit right-aligned data

These bits are written by software which specifies 12-bit data for DAC channel1.

16.9.4 DAC channel1 12-bit left-aligned data holding register (DAC_DHR12L1)

Address offset: 0x0C

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACC1DHR[11:0]												v	Res.	Res.	Res.
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:4 DACC1DHR[11:0] : DAC channel1 12-bit left-aligned data

These bits are written by software which specifies 12-bit data for DAC channel1.

Bits 3:0 Reserved, must be kept at reset value.

16.9.5 DAC channel1 8-bit right-aligned data holding register (DAC_DHR8R1)

Address offset: 0x10

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DACC1DHR[7:0]
								rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 DACC1DHR[7:0] : DAC channel1 8-bit right-aligned data

These bits are written by software which specifies 8-bit data for DAC channel1.

16.9.6 DAC channel1 data output register (DAC_DOR1)

Address offset: 0x2C

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	DACC1DOR[11:0]
				r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 DACC1DOR[11:0] : DAC channel1 data output

These bits are read-only, they contain data output for DAC channel1.

16.9.7 DAC status register (DAC_SR)

Address offset: 0x34

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	DMAUDR1 rc_w1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 DMAUDR1 : DAC channel1 DMA underrun flag

This bit is set by hardware and cleared by software (by writing it to 1).

0: No DMA underrun error condition occurred for DAC channel1

1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)

Bits 12:0 Reserved, must be kept at reset value.

16.9.8 DAC register map

Table 101 summarizes the DAC registers.

Table 101. DAC register map and reset values

Offset	Register name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	DAC_CR	Res.	Res.	Res.	Res.	Res.														DMAUDRIE1	DMAEN1	MAMP1[3:0]										TEN1	BOFF1	EN1
0x00	Reset value																			0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x04	DAC_SWTRIGR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SWTRIG1
0x04	Reset value																															0
0x08	DAC_DHR12R1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DACC1DHR[11:0]
0x08	Reset value																					0	0	0	0	0	0	0	0	0	0	0
0x0C	DAC_DHR12L1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DACC1DHR[11:0]
0x0C	Reset value																			0	0	0	0	0	0	0	0	0	0	0	0	0
0x10	DAC_DHR8R1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DACC1DHR[7:0]
0x10	Reset value																					0	0	0	0	0	0	0	0	0	0	0
0x2C	DAC_DOR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DACC1DOR[11:0]
0x2C	Reset value																					0	0	0	0	0	0	0	0	0	0	0
0x34	DAC_SR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	DMAUDR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
0x34	Reset value																			0

Refer to Section 3.2 on page 51 for the register boundary addresses.