RM0365-STM32F302xB-C-D-E-302x6-8

Introduction

This document is addressed to application developers. It provides complete information on how to use the STM32F302xB/C/D/E and STM32F302x6/8 microcontroller memory and peripherals. These devices are referred to as STM32F302xx throughout the document, unless otherwise specified.

The STM32F302xx is a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics refer to the STM32F302xB/C, STM32F302xD/E and STM32F302x6/8 datasheets.

For information on the Arm ^®Cortex ^®-M4 core with FPU, refer to the programming manual PM0214.

• STM32F302xB/C, STM32F302xD/E and STM32F302x6/8 datasheets available from www.st.com
• STM32 Cortex ^®-M4 MCUs and MPUs programming manual (PM0214) available from www.st.com .

1 Overview of the manual . . . . . 43
2 Documentation conventions . . . . . 45
- 2.1 General information . . . . . 45
- 2.2 List of abbreviations for registers . . . . . 45
- 2.3 Glossary . . . . . 46
- 2.4 Availability of peripherals . . . . . 46
3 System and memory overview . . . . . 47
- 3.1 System architecture . . . . . 47
  - 3.1.1 S0: I-bus . . . . . 49
  - 3.1.2 S1: D-bus . . . . . 49
  - 3.1.3 S2: S-bus . . . . . 49
  - 3.1.4 S3, S4: DMA-bus . . . . . 49
  - 3.1.5 BusMatrix . . . . . 50
- 3.2 Memory organization . . . . . 51
  - 3.2.1 Introduction . . . . . 51
  - 3.2.2 Memory map and register boundary addresses . . . . . 52
- 3.3 Embedded SRAM . . . . . 60
  - 3.3.1 Parity check . . . . . 60
- 3.4 Flash memory overview . . . . . 60
- 3.5 Boot configuration . . . . . 61
  - 3.5.1 Embedded boot loader . . . . . 61
4 Embedded Flash memory . . . . . 62
- 4.1 Flash main features . . . . . 62
- 4.2 Flash memory functional description . . . . . 62
  - 4.2.1 Flash memory organization . . . . . 62
  - 4.2.2 Read operations . . . . . 63
  - 4.2.3 Flash program and erase operations . . . . . 65
- 4.3 Memory protection . . . . . 72
  - 4.3.1 Read protection . . . . . 72
  - 4.3.2 Write protection . . . . . 74

4.3.3	Option byte block write protection . . . . .	74
4.4	Flash interrupts . . . . .	74
4.5	Flash register description . . . . .	75
4.5.1	Flash access control register (FLASH_ACR) . . . . .	75
4.5.2	Flash key register (FLASH_KEYR) . . . . .	75
4.5.3	Flash option key register (FLASH_OPTKEYR) . . . . .	76
4.5.4	Flash status register (FLASH_SR) . . . . .	76
4.5.5	Flash control register (FLASH_CR) . . . . .	77
4.5.6	Flash address register (FLASH_AR) . . . . .	78
4.5.7	Option byte register (FLASH_OBR) . . . . .	79
4.5.8	Write protection register (FLASH_WRP) . . . . .	80
4.6	Flash register map . . . . .	80
5	Option byte description . . . . .	82
6	Cyclic redundancy check calculation unit (CRC) . . . . .	85
6.1	Introduction . . . . .	85
6.2	CRC main features . . . . .	85
6.3	CRC functional description . . . . .	86
6.3.1	CRC block diagram . . . . .	86
6.3.2	CRC internal signals . . . . .	86
6.3.3	CRC operation . . . . .	86
6.4	CRC registers . . . . .	88
6.4.1	CRC data register (CRC_DR) . . . . .	88
6.4.2	CRC independent data register (CRC_IDR) . . . . .	88
6.4.3	CRC control register (CRC_CR) . . . . .	89
6.4.4	CRC initial value (CRC_INIT) . . . . .	90
6.4.5	CRC polynomial (CRC_POL) . . . . .	90
6.4.6	CRC register map . . . . .	91
7	Peripheral interconnect matrix . . . . .	92
7.1	Introduction . . . . .	92
7.2	Connection summary . . . . .	92
7.3	Interconnection details . . . . .	95
7.3.1	DMA interconnections . . . . .	95
7.3.2	From ADC to ADC . . . . .	95

7.3.3	From ADC to TIM . . . . .	95
7.3.4	From TIM and EXTI to ADC . . . . .	96
7.3.5	From OPAMP to ADC . . . . .	96
7.3.6	From TS to ADC . . . . .	96
7.3.7	From VBAT to ADC . . . . .	96
7.3.8	From VREFINT to ADC . . . . .	97
7.3.9	From COMP to TIM . . . . .	97
7.3.10	From TIM to COMP . . . . .	98
7.3.11	From DAC to COMP . . . . .	98
7.3.12	From VREFINT to COMP . . . . .	99
7.3.13	From DAC to OPAMP . . . . .	99
7.3.14	From TIM to OPAMP . . . . .	99
7.3.15	From TIM to TIM . . . . .	99
7.3.16	From break input sources to TIM . . . . .	100
7.3.17	From HSE, HSI, LSE, LSI, MCO, RTC to TIM . . . . .	100
7.3.18	From TIM and EXTI to DAC . . . . .	101
7.3.19	From TIM to IRTIM . . . . .	101
8	Power control (PWR) . . . . .	102
8.1	Power supplies . . . . .	102
8.1.1	Independent A/D and D/A converter supply and reference voltage . . . . .	103
8.1.2	Battery Backup domain . . . . .	103
8.1.3	Voltage regulator . . . . .	104
8.2	Power supply supervisor . . . . .	105
8.2.1	Power on reset (POR)/power down reset (PDR) . . . . .	105
8.2.2	Programmable voltage detector (PVD) . . . . .	105
8.3	Low-power modes . . . . .	106
8.3.1	Slowing down system clocks . . . . .	107
8.3.2	Peripheral clock gating . . . . .	107
8.3.3	Sleep mode . . . . .	107
8.3.4	Stop mode . . . . .	108
8.3.5	Standby mode . . . . .	110
8.3.6	Auto-wakeup from low-power mode . . . . .	112
8.4	Power control registers . . . . .	113
8.4.1	Power control register (PWR_CR) . . . . .	113
8.4.2	Power control/status register (PWR_CSR) . . . . .	114
8.4.3	PWR register map . . . . .	115

9	Reset and clock control (RCC) . . . . .	116
9.1	Reset . . . . .	116
9.1.1	Power reset . . . . .	116
9.1.2	System reset . . . . .	116
9.1.3	RTC domain reset . . . . .	117
9.2	Clocks . . . . .	118
9.2.1	HSE clock . . . . .	122
9.2.2	HSI clock . . . . .	123
9.2.3	PLL . . . . .	124
9.2.4	LSE clock . . . . .	124
9.2.5	LSI clock . . . . .	125
9.2.6	System clock (SYSCLK) selection . . . . .	125
9.2.7	Clock security system (CSS) . . . . .	125
9.2.8	ADC clock . . . . .	126
9.2.9	RTC clock . . . . .	126
9.2.10	Timers (TIMx) clock . . . . .	126
9.2.11	Watchdog clock . . . . .	127
9.2.12	I2S clock . . . . .	127
9.2.13	Clock-out capability . . . . .	127
9.2.14	Internal/external clock measurement with TIM16 . . . . .	128
9.3	Low-power modes . . . . .	129
9.4	RCC registers . . . . .	130
9.4.1	Clock control register (RCC_CR) . . . . .	130
9.4.2	Clock configuration register (RCC_CFGR) . . . . .	132
9.4.3	Clock interrupt register (RCC_CIR) . . . . .	135
9.4.4	APB2 peripheral reset register (RCC_APB2RSTR) . . . . .	138
9.4.5	APB1 peripheral reset register (RCC_APB1RSTR) . . . . .	139
9.4.6	AHB peripheral clock enable register (RCC_AHBENR) . . . . .	141
9.4.7	APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .	143
9.4.8	APB1 peripheral clock enable register (RCC_APB1ENR) . . . . .	144
9.4.9	RTC domain control register (RCC_BDCR) . . . . .	147
9.4.10	Control/status register (RCC_CSR) . . . . .	148
9.4.11	AHB peripheral reset register (RCC_AHBRSTR) . . . . .	150
9.4.12	Clock configuration register 2 (RCC_CFGR2) . . . . .	151
9.4.13	Clock configuration register 3 (RCC_CFGR3) . . . . .	153
9.4.14	RCC register map . . . . .	155

10	General-purpose I/Os (GPIO) . . . . .	158
10.1	Introduction . . . . .	158
10.2	GPIO main features . . . . .	158
10.3	GPIO functional description . . . . .	158
10.3.1	General-purpose I/O (GPIO) . . . . .	160
10.3.2	I/O pin alternate function multiplexer and mapping . . . . .	161
10.3.3	I/O port control registers . . . . .	162
10.3.4	I/O port data registers . . . . .	162
10.3.5	I/O data bitwise handling . . . . .	162
10.3.6	GPIO locking mechanism . . . . .	162
10.3.7	I/O alternate function input/output . . . . .	163
10.3.8	External interrupt/wakeup lines . . . . .	163
10.3.9	Input configuration . . . . .	163
10.3.10	Output configuration . . . . .	164
10.3.11	Alternate function configuration . . . . .	165
10.3.12	Analog configuration . . . . .	166
10.3.13	Using the HSE or LSE oscillator pins as GPIOs . . . . .	167
10.3.14	Using the GPIO pins in the RTC supply domain . . . . .	167
10.4	GPIO registers . . . . .	167
10.4.1	GPIO port mode register (GPIOx_MODER) (x = A to H) . . . . .	167
10.4.2	GPIO port output type register (GPIOx_OTYPER) (x = A to H) . . . . .	168
10.4.3	GPIO port output speed register (GPIOx_OSPEEDR) (x = A to H) . . . . .	168
10.4.4	GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to H) . . . . .	169
10.4.5	GPIO port input data register (GPIOx_IDR) (x = A to H) . . . . .	169
10.4.6	GPIO port output data register (GPIOx_ODR) (x = A to H) . . . . .	170
10.4.7	GPIO port bit set/reset register (GPIOx_BSRR) (x = A to H) . . . . .	170
10.4.8	GPIO port configuration lock register (GPIOx_LCKR) (x = A to H) . . . . .	170
10.4.9	GPIO alternate function low register (GPIOx_AFRL) (x = A to H) . . . . .	172
10.4.10	GPIO alternate function high register (GPIOx_AFRH) (x = A to H) . . . . .	172

10.4.11	GPIO port bit reset register (GPIOx_BRR) (x = A to H) . . . . .	172
10.4.12	GPIO register map . . . . .	173
11	System configuration controller (SYSCFG) . . . . .	175
11.1	SYSCFG registers . . . . .	175
11.1.1	SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .	175
11.1.2	SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . .	177
11.1.3	SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) . . . . .	178
11.1.4	SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) . . . . .	180
11.1.5	SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) . . . . .	181
11.1.6	SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .	182
11.1.7	SYSCFG register map . . . . .	184
12	Direct memory access controller (DMA) . . . . .	185
12.1	Introduction . . . . .	185
12.2	DMA main features . . . . .	185
12.3	DMA implementation . . . . .	186
12.3.1	DMA1 and DMA2 . . . . .	186
12.3.2	DMA request mapping . . . . .	186
12.4	DMA functional description . . . . .	191
12.4.1	DMA block diagram . . . . .	191
12.4.2	DMA transfers . . . . .	192
12.4.3	DMA arbitration . . . . .	193
12.4.4	DMA channels . . . . .	194
12.4.5	DMA data width, alignment and endianness . . . . .	197
12.4.6	DMA error management . . . . .	199
12.5	DMA interrupts . . . . .	199
12.6	DMA registers . . . . .	199
12.6.1	DMA interrupt status register (DMA_ISR) . . . . .	200
12.6.2	DMA interrupt flag clear register (DMA_IFCR) . . . . .	202
12.6.3	DMA channel x configuration register (DMA_CCRx) . . . . .	203
12.6.4	DMA channel x number of data to transfer register (DMA_CNDTRx) . . . . .	206
12.6.5	DMA channel x peripheral address register (DMA_CPARx) . . . . .	207
12.6.6	DMA channel x memory address register (DMA_CMARx) . . . . .	207

12.6.7	DMA register map .....	208
13	Interrupts and events .....	211
13.1	Nested vectored interrupt controller (NVIC) .....	211
13.1.1	NVIC main features .....	211
13.1.2	SysTick calibration value register .....	211
13.1.3	Interrupt and exception vectors .....	211
13.2	Extended interrupts and events controller (EXTI) .....	218
13.2.1	Main features .....	218
13.2.2	Block diagram .....	219
13.2.3	Wakeup event management .....	219
13.2.4	Asynchronous Internal Interrupts .....	219
13.2.5	Functional description .....	220
13.2.6	External and internal interrupt/event line mapping .....	221
13.3	EXTI registers .....	222
13.3.1	Interrupt mask register (EXTI_IMR1) .....	222
13.3.2	Event mask register (EXTI_EMR1) .....	223
13.3.3	Rising trigger selection register (EXTI_RTSR1) .....	223
13.3.4	Falling trigger selection register (EXTI_FTSR1) .....	224
13.3.5	Software interrupt event register (EXTI_SWIER1) .....	225
13.3.6	Pending register (EXTI_PR1) .....	225
13.3.7	Interrupt mask register (EXTI_IMR2) .....	226
13.3.8	Event mask register (EXTI_EMR2) .....	226
13.3.9	Rising trigger selection register (EXTI_RTSR2) .....	227
13.3.10	Falling trigger selection register (EXTI_FTSR2) .....	227
13.3.11	Software interrupt event register (EXTI_SWIER2) .....	228
13.3.12	Pending register (EXTI_PR2) .....	228
13.3.13	EXTI register map .....	229
14	Flexible static memory controller (FSMC) .....	231
14.1	FMC main features .....	231
14.2	Block diagram .....	232
14.3	AHB interface .....	233
14.3.1	Supported memories and transactions .....	233
14.4	External device address mapping .....	234
14.4.1	NOR/PSRAM address mapping .....	235

14.4.2	NAND Flash memory/PC Card address mapping . . . . .	236
14.5	NOR Flash/PSRAM controller . . . . .	237
14.5.1	External memory interface signals . . . . .	238
14.5.2	Supported memories and transactions . . . . .	240
14.5.3	General timing rules . . . . .	241
14.5.4	NOR Flash/PSRAM controller asynchronous transactions . . . . .	242
14.5.5	Synchronous transactions . . . . .	259
14.5.6	NOR/PSRAM controller registers . . . . .	266
14.6	NAND Flash/PC Card controller . . . . .	273
14.6.1	External memory interface signals . . . . .	274
14.6.2	NAND Flash / PC Card supported memories and transactions . . . . .	276
14.6.3	Timing diagrams for NAND Flash memory and PC Card . . . . .	276
14.6.4	NAND Flash operations . . . . .	277
14.6.5	NAND Flash prewait functionality . . . . .	278
14.6.6	Computation of the error correction code (ECC) in NAND Flash memory . . . . .	279
14.6.7	PC Card/CompactFlash operations . . . . .	280
14.6.8	NAND Flash/PC Card controller registers . . . . .	282
14.6.9	FMC register map . . . . .	289
15	Analog-to-digital converters (ADC) . . . . .	291
15.1	Introduction . . . . .	291
15.2	ADC main features . . . . .	292
15.3	ADC functional description . . . . .	294
15.3.1	ADC block diagram . . . . .	294
15.3.2	Pins and internal signals . . . . .	295
15.3.3	Clocks . . . . .	296
15.3.4	ADC1/2 connectivity . . . . .	298
15.3.5	Slave AHB interface . . . . .	299
15.3.6	ADC voltage regulator (ADVREGEN) . . . . .	299
15.3.7	Single-ended and differential input channels . . . . .	299
15.3.8	Calibration (ADCAL, ADCALDIF, ADCx_CALFACT) . . . . .	300
15.3.9	ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .	303
15.3.10	Constraints when writing the ADC control bits . . . . .	304
15.3.11	Channel selection (SQRx, JSQRx) . . . . .	304
15.3.12	Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . .	305
15.3.13	Single conversion mode (CONT=0) . . . . .	306

15.3.14	Continuous conversion mode (CONT=1) . . . . .	306
15.3.15	Starting conversions (ADSTART, JADSTART) . . . . .	307
15.3.16	Timing . . . . .	308
15.3.17	Stopping an ongoing conversion (ADSTP, JADSTP) . . . . .	308
15.3.18	Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . .	310
15.3.19	Injected channel management . . . . .	313
15.3.20	Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . .	314
15.3.21	Queue of context for injected conversions . . . . .	315
15.3.22	Programmable resolution (RES) - fast conversion mode . . . . .	324
15.3.23	End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . . . .	324
15.3.24	End of conversion sequence (EOS, JEOS) . . . . .	325
15.3.25	Timing diagrams example (single/continuous modes, hardware/software triggers) . . . . .	325
15.3.26	Data management . . . . .	326
15.3.27	Dynamic low-power features . . . . .	332
15.3.28	Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . .	337
15.3.29	Dual ADC modes (STM32F302xB/C/D/E only) . . . . .	341
15.3.30	Temperature sensor . . . . .	354
15.3.31	VBAT supply monitoring . . . . .	356
15.3.32	Monitoring the internal voltage reference . . . . .	357
15.4	ADC interrupts . . . . .	359
15.5	ADC registers (for each ADC) . . . . .	360
15.5.1	ADC interrupt and status register (ADCx_ISR, x=1..2) . . . . .	360
15.5.2	ADC interrupt enable register (ADCx_IER, x=1..2) . . . . .	362
15.5.3	ADC control register (ADCx_CR, x=1..2) . . . . .	364
15.5.4	ADC configuration register (ADCx_CFGR, x=1..2) . . . . .	367
15.5.5	ADC sample time register 1 (ADCx_SMPR1, x=1..2) . . . . .	371
15.5.6	ADC sample time register 2 (ADCx_SMPR2, x=1..2) . . . . .	373
15.5.7	ADC watchdog threshold register 1 (ADCx_TR1, x=1..2) . . . . .	373
15.5.8	ADC watchdog threshold register 2 (ADCx_TR2, x = 1..2) . . . . .	374
15.5.9	ADC watchdog threshold register 3 (ADCx_TR3, x=1..2) . . . . .	375
15.5.10	ADC regular sequence register 1 (ADCx_SQR1, x=1..2) . . . . .	376
15.5.11	ADC regular sequence register 2 (ADCx_SQR2, x=1..2) . . . . .	377
15.5.12	ADC regular sequence register 3 (ADCx_SQR3, x=1..2) . . . . .	379
15.5.13	ADC regular sequence register 4 (ADCx_SQR4, x=1..2) . . . . .	380
15.5.14	ADC regular Data Register (ADCx_DR, x=1..2) . . . . .	381

15.5.15	ADC injected sequence register (ADCx_JSQR, x=1..2) . . . . .	382
15.5.16	ADC offset register (ADCx_OF Ry, x=1..2) (y=1..4) . . . . .	384
15.5.17	ADC injected data register (ADCx_JDRy, x=1..2, y= 1..4) . . . . .	385
15.5.18	ADC Analog Watchdog 2 Configuration Register (ADCx_AWD2CR, x=1..2) . . . . .	385
15.5.19	ADC Analog Watchdog 3 Configuration Register (ADCx_AWD3CR, x=1..2) . . . . .	386
15.5.20	ADC Differential Mode Selection Register (ADCx_DIFSEL, x=1..2) . . . . .	386
15.5.21	ADC Calibration Factors (ADCx_CALFACT, x=1..2) . . . . .	387
15.6	ADC common registers . . . . .	388
15.6.1	ADC Common status register (ADCx_CSR, x=12) . . . . .	388
15.6.2	ADC common control register (ADCx_CCR, x=12) . . . . .	390
15.6.3	ADC common regular data register for dual mode (ADCx_CDR, x=12) . . . . .	393
15.7	ADC register map . . . . .	393
16	Digital-to-analog converter (DAC1) . . . . .	397
16.1	Introduction . . . . .	397
16.2	DAC1 main features . . . . .	397
16.3	DAC output buffer enable . . . . .	398
16.4	DAC channel enable . . . . .	399
16.5	Single mode functional description . . . . .	399
16.5.1	DAC data format . . . . .	399
16.5.2	DAC channel conversion . . . . .	399
16.5.3	DAC output voltage . . . . .	400
16.5.4	DAC trigger selection . . . . .	401
16.6	Noise generation . . . . .	402
16.7	Triangle-wave generation . . . . .	403
16.8	DMA request . . . . .	404
16.9	DAC registers . . . . .	405
16.9.1	DAC control register (DAC_CR) . . . . .	405
16.9.2	DAC software trigger register (DAC_SWTRIGR) . . . . .	407
16.9.3	DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . .	407
16.9.4	DAC channel1 12-bit left-aligned data holding register (DAC_DHR12L1) . . . . .	408
16.9.5	DAC channel1 8-bit right-aligned data holding register (DAC_DHR8R1) . . . . .	408

- 16.9.6 DAC channel1 data output register (DAC_DOR1) . . . . . 408
- 16.9.7 DAC status register (DAC_SR) . . . . . 409
- 16.9.8 DAC register map . . . . . 410

17 Comparator (COMP) . . . . . 411
- 17.1 Introduction . . . . . 411
- 17.2 COMP main features . . . . . 411
- 17.3 COMP functional description . . . . . 412
  - 17.3.1 COMP block diagram . . . . . 412
  - 17.3.2 COMP pins and internal signals . . . . . 412
  - 17.3.3 COMP reset and clocks . . . . . 414
  - 17.3.4 Comparator LOCK mechanism . . . . . 414
  - 17.3.5 Hysteresis (STM32F302xBxC only) . . . . . 415
  - 17.3.6 Comparator output blanking function . . . . . 415
  - 17.3.7 Power mode (STM32F302xB/C only) . . . . . 416
- 17.4 COMP interrupts . . . . . 416
- 17.5 COMP registers . . . . . 416
  - 17.5.1 COMP1 control and status register (COMP1_CSR) . . . . . 416
  - 17.5.2 COMP2 control and status register (COMP2_CSR) . . . . . 418
  - 17.5.3 COMP4 control and status register (COMP4_CSR) . . . . . 420
  - 17.5.4 COMP6 control and status register (COMP6_CSR) . . . . . 423
  - 17.5.5 COMP register map . . . . . 425

18 Operational amplifier (OPAMP) . . . . . 426
- 18.1 OPAMP introduction . . . . . 426
- 18.2 OPAMP main features . . . . . 426
- 18.3 OPAMP functional description . . . . . 426
  - 18.3.1 General description . . . . . 426
  - 18.3.2 Clock . . . . . 427
  - 18.3.3 Operational amplifiers and comparators interconnections . . . . . 427
  - 18.3.4 Using the OPAMP outputs as ADC inputs . . . . . 428
  - 18.3.5 Calibration . . . . . 428
  - 18.3.6 Timer controlled Multiplexer mode . . . . . 429
  - 18.3.7 OPAMP modes . . . . . 430
- 18.4 OPAMP registers . . . . . 434
  - 18.4.1 OPAMP1 control register (OPAMP1_CSR) . . . . . 434

18.4.2	OPAMP2 control register (OPAMP2_CSR) . . . . .	436
18.4.3	OPAMP register map . . . . .	439
19	Touch sensing controller (TSC) . . . . .	440
19.1	Introduction . . . . .	440
19.2	TSC main features . . . . .	440
19.3	TSC functional description . . . . .	441
19.3.1	TSC block diagram . . . . .	441
19.3.2	Surface charge transfer acquisition overview . . . . .	441
19.3.3	Reset and clocks . . . . .	443
19.3.4	Charge transfer acquisition sequence . . . . .	444
19.3.5	Spread spectrum feature . . . . .	445
19.3.6	Max count error . . . . .	445
19.3.7	Sampling capacitor I/O and channel I/O mode selection . . . . .	446
19.3.8	Acquisition mode . . . . .	447
19.3.9	I/O hysteresis and analog switch control . . . . .	447
19.4	TSC low-power modes . . . . .	448
19.5	TSC interrupts . . . . .	448
19.6	TSC registers . . . . .	449
19.6.1	TSC control register (TSC_CR) . . . . .	449
19.6.2	TSC interrupt enable register (TSC_IER) . . . . .	451
19.6.3	TSC interrupt clear register (TSC_ICR) . . . . .	452
19.6.4	TSC interrupt status register (TSC_ISR) . . . . .	453
19.6.5	TSC I/O hysteresis control register (TSC_IOHCR) . . . . .	453
19.6.6	TSC I/O analog switch control register (TSC_IOASCR) . . . . .	454
19.6.7	TSC I/O sampling control register (TSC_IOSCR) . . . . .	454
19.6.8	TSC I/O channel control register (TSC_IOCCR) . . . . .	455
19.6.9	TSC I/O group control status register (TSC_IOGCSR) . . . . .	455
19.6.10	TSC I/O group x counter register (TSC_IOGxCR) . . . . .	456
19.6.11	TSC register map . . . . .	457
20	Advanced-control timer (TIM1) . . . . .	459
20.1	TIM1 introduction . . . . .	459
20.2	TIM1 main features . . . . .	460
20.3	TIM1 functional description . . . . .	463
20.3.1	Time-base unit . . . . .	463

20.3.2	Counter modes . . . . .	465
20.3.3	Repetition counter . . . . .	476
20.3.4	External trigger input . . . . .	478
20.3.5	Clock selection . . . . .	479
20.3.6	Capture/compare channels . . . . .	483
20.3.7	Input capture mode . . . . .	486
20.3.8	PWM input mode . . . . .	487
20.3.9	Forced output mode . . . . .	487
20.3.10	Output compare mode . . . . .	488
20.3.11	PWM mode . . . . .	489
20.3.12	Asymmetric PWM mode . . . . .	492
20.3.13	Combined PWM mode . . . . .	493
20.3.14	Combined 3-phase PWM mode . . . . .	494
20.3.15	Complementary outputs and dead-time insertion . . . . .	495
20.3.16	Using the break function . . . . .	497
20.3.17	Clearing the OCxREF signal on an external event . . . . .	502
20.3.18	6-step PWM generation . . . . .	504
20.3.19	One-pulse mode . . . . .	505
20.3.20	Retriggerable one pulse mode . . . . .	506
20.3.21	Encoder interface mode . . . . .	507
20.3.22	UIF bit remapping . . . . .	509
20.3.23	Timer input XOR function . . . . .	510
20.3.24	Interfacing with Hall sensors . . . . .	510
20.3.25	Timer synchronization . . . . .	513
20.3.26	ADC synchronization . . . . .	517
20.3.27	DMA burst mode . . . . .	517
20.3.28	Debug mode . . . . .	518
20.4	TIM1 registers . . . . .	519
20.4.1	TIM1 control register 1 (TIM1_CR1) . . . . .	519
20.4.2	TIM1 control register 2 (TIM1_CR2) . . . . .	520
20.4.3	TIM1 slave mode control register (TIM1_SMCR) . . . . .	523
20.4.4	TIM1 DMA/interrupt enable register (TIM1_DIER) . . . . .	525
20.4.5	TIM1 status register (TIM1_SR) . . . . .	527
20.4.6	TIM1 event generation register (TIM1_EGR) . . . . .	529
20.4.7	TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) . . . . .	530

20.4.8	TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) . . . . .	531
20.4.9	TIM1 capture/compare mode register 2 [alternate] (TIM1_CCMR2) . . . . .	534
20.4.10	TIM1 capture/compare mode register 2 [alternate] (TIM1_CCMR2) . . . . .	535
20.4.11	TIM1 capture/compare enable register (TIM1_CCER) . . . . .	537
20.4.12	TIM1 counter (TIM1_CNT) . . . . .	540
20.4.13	TIM1 prescaler (TIM1_PSC) . . . . .	540
20.4.14	TIM1 auto-reload register (TIM1_ARR) . . . . .	540
20.4.15	TIM1 repetition counter register (TIM1_RCR) . . . . .	541
20.4.16	TIM1 capture/compare register 1 (TIM1_CCR1) . . . . .	541
20.4.17	TIM1 capture/compare register 2 (TIM1_CCR2) . . . . .	542
20.4.18	TIM1 capture/compare register 3 (TIM1_CCR3) . . . . .	542
20.4.19	TIM1 capture/compare register 4 (TIM1_CCR4) . . . . .	543
20.4.20	TIM1 break and dead-time register (TIM1_BDTR) . . . . .	543
20.4.21	TIM1 DMA control register (TIM1_DCR) . . . . .	546
20.4.22	TIM1 DMA address for full transfer (TIM1_DMAR) . . . . .	547
20.4.23	TIM1 option registers (TIM1_OR) . . . . .	548
20.4.24	TIM1 capture/compare mode register 3 (TIM1_CCMR3) . . . . .	548
20.4.25	TIM1 capture/compare register 5 (TIM1_CCR5) . . . . .	549
20.4.26	TIM1 capture/compare register 6 (TIM1_CCR6) . . . . .	550
20.4.27	TIM1 register map . . . . .	551
21	General-purpose timers (TIM2/TIM3/TIM4) . . . . .	554
21.1	TIM2/TIM3/TIM4 introduction . . . . .	554
21.2	TIM2/TIM3/TIM4 main features . . . . .	554
21.3	TIM2/TIM3/TIM4 functional description . . . . .	556
21.3.1	Time-base unit . . . . .	556
21.3.2	Counter modes . . . . .	558
21.3.3	Clock selection . . . . .	568
21.3.4	Capture/Compare channels . . . . .	572
21.3.5	Input capture mode . . . . .	574
21.3.6	PWM input mode . . . . .	575
21.3.7	Forced output mode . . . . .	576

21.3.8	Output compare mode . . . . .	577
21.3.9	PWM mode . . . . .	578
21.3.10	Asymmetric PWM mode . . . . .	581
21.3.11	Combined PWM mode . . . . .	582
21.3.12	Clearing the OCxREF signal on an external event . . . . .	583
21.3.13	One-pulse mode . . . . .	585
21.3.14	Retriggerable one pulse mode . . . . .	586
21.3.15	Encoder interface mode . . . . .	587
21.3.16	UIF bit remapping . . . . .	589
21.3.17	Timer input XOR function . . . . .	589
21.3.18	Timers and external trigger synchronization . . . . .	590
21.3.19	Timer synchronization . . . . .	593
21.3.20	DMA burst mode . . . . .	598
21.3.21	Debug mode . . . . .	599
21.4	TIM2/TIM3/TIM4 registers . . . . .	600
21.4.1	TIMx control register 1 (TIMx_CR1)(x = 2 to 4) . . . . .	600
21.4.2	TIMx control register 2 (TIMx_CR2)(x = 2 to 4) . . . . .	601
21.4.3	TIMx slave mode control register (TIMx_SMCR)(x = 2 to 4) . . . . .	603
21.4.4	TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 4) . . . . .	606
21.4.5	TIMx status register (TIMx_SR)(x = 2 to 4) . . . . .	607
21.4.6	TIMx event generation register (TIMx_EGR)(x = 2 to 4) . . . . .	608
21.4.7	TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 4) . . . . .	609
21.4.8	TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 4) . . . . .	611
21.4.9	TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2) (x = 2 to 4) . . . . .	613
21.4.10	TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2) (x = 2 to 4) . . . . .	614
21.4.11	TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 4) . . . . .	615
21.4.12	TIMx counter [alternate] (TIMx_CNT)(x = 2 to 4) . . . . .	616
21.4.13	TIMx counter [alternate] (TIMx_CNT)(x = 2 to 4) . . . . .	617
21.4.14	TIMx prescaler (TIMx_PSC)(x = 2 to 4) . . . . .	617
21.4.15	TIMx auto-reload register (TIMx_ARR)(x = 2 to 4) . . . . .	618
21.4.16	TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 4) . . . . .	618
21.4.17	TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 4) . . . . .	619
21.4.18	TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 4) . . . . .	619

21.4.19	TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 4) . . . . .	620
21.4.20	TIMx DMA control register (TIMx_DCR)(x = 2 to 4) . . . . .	621
21.4.21	TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 4) . . . . .	621
21.4.22	TIMx register map . . . . .	622
22	General-purpose timers (TIM15/TIM16/TIM17) . . . . .	624
22.1	TIM15/TIM16/TIM17 introduction . . . . .	624
22.2	TIM15 main features . . . . .	624
22.3	TIM16/TIM17 main features . . . . .	625
22.4	TIM15/TIM16/TIM17 functional description . . . . .	628
22.4.1	Time-base unit . . . . .	628
22.4.2	Counter modes . . . . .	630
22.4.3	Repetition counter . . . . .	634
22.4.4	Clock selection . . . . .	635
22.4.5	Capture/compare channels . . . . .	637
22.4.6	Input capture mode . . . . .	639
22.4.7	PWM input mode (only for TIM15) . . . . .	640
22.4.8	Forced output mode . . . . .	641
22.4.9	Output compare mode . . . . .	642
22.4.10	PWM mode . . . . .	643
22.4.11	Combined PWM mode (TIM15 only) . . . . .	644
22.4.12	Complementary outputs and dead-time insertion . . . . .	645
22.4.13	Using the break function . . . . .	647
22.4.14	One-pulse mode . . . . .	651
22.4.15	Retriggerable one pulse mode (TIM15 only) . . . . .	653
22.4.16	UIF bit remapping . . . . .	653
22.4.17	Timer input XOR function (TIM15 only) . . . . .	655
22.4.18	External trigger synchronization (TIM15 only) . . . . .	656
22.4.19	Slave mode – combined reset + trigger mode (TIM15 only) . . . . .	658
22.4.20	DMA burst mode . . . . .	658
22.4.21	Timer synchronization (TIM15) . . . . .	660
22.4.22	Using timer output as trigger for other timers (TIM16/TIM17) . . . . .	660
22.4.23	Debug mode . . . . .	660
22.5	TIM15 registers . . . . .	661
22.5.1	TIM15 control register 1 (TIM15_CR1) . . . . .	661
22.5.2	TIM15 control register 2 (TIM15_CR2) . . . . .	662
22.5.3	TIM15 slave mode control register (TIM15_SMCR) . . . . .	664

22.5.4	TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .	665
22.5.5	TIM15 status register (TIM15_SR) . . . . .	666
22.5.6	TIM15 event generation register (TIM15_EGR) . . . . .	668
22.5.7	TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) . . . . .	669
22.5.8	TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) . . . . .	670
22.5.9	TIM15 capture/compare enable register (TIM15_CCER) . . . . .	673
22.5.10	TIM15 counter (TIM15_CNT) . . . . .	676
22.5.11	TIM15 prescaler (TIM15_PSC) . . . . .	676
22.5.12	TIM15 auto-reload register (TIM15_ARR) . . . . .	676
22.5.13	TIM15 repetition counter register (TIM15_RCR) . . . . .	677
22.5.14	TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .	677
22.5.15	TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .	678
22.5.16	TIM15 break and dead-time register (TIM15_BDTR) . . . . .	678
22.5.17	TIM15 DMA control register (TIM15_DCR) . . . . .	680
22.5.18	TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .	681
22.5.19	TIM15 register map . . . . .	681
22.6	TIM16/TIM17 registers . . . . .	684
22.6.1	TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .	684
22.6.2	TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .	685
22.6.3	TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .	686
22.6.4	TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .	687
22.6.5	TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .	688
22.6.6	TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 16 to 17) . . . . .	689
22.6.7	TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 16 to 17) . . . . .	690
22.6.8	TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . .	692
22.6.9	TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .	694
22.6.10	TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .	695
22.6.11	TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . .	695
22.6.12	TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .	696
22.6.13	TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .	696
22.6.14	TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . .	697
22.6.15	TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .	699
22.6.16	TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . .	699
22.6.17	TIM16 option register (TIM16_OR) . . . . .	700

22.6.18	TIM16/TIM17 register map .....	701
23	Basic timers (TIM6) .....	703
23.1	TIM6 introduction .....	703
23.2	TIM6 main features .....	703
23.3	TIM6 functional description .....	704
23.3.1	Time-base unit .....	704
23.3.2	Counting mode .....	706
23.3.3	UIF bit remapping .....	709
23.3.4	Clock source .....	709
23.3.5	Debug mode .....	710
23.4	TIM6 registers .....	710
23.4.1	TIM6 control register 1 (TIM6_CR1) .....	710
23.4.2	TIM6 control register 2 (TIM6_CR2) .....	712
23.4.3	TIM6 DMA/Interrupt enable register (TIM6_DIER) .....	712
23.4.4	TIM6 status register (TIM6_SR) .....	713
23.4.5	TIM6 event generation register (TIM6_EGR) .....	713
23.4.6	TIM6 counter (TIM6_CNT) .....	713
23.4.7	TIM6 prescaler (TIM6_PSC) .....	714
23.4.8	TIM6 auto-reload register (TIM6_ARR) .....	714
23.4.9	TIM6 register map .....	715
24	Infrared interface (IRTIM) .....	716
25	System window watchdog (WWDG) .....	717
25.1	Introduction .....	717
25.2	WWDG main features .....	717
25.3	WWDG functional description .....	717
25.3.1	WWDG block diagram .....	718
25.3.2	Enabling the watchdog .....	718
25.3.3	Controlling the down-counter .....	718
25.3.4	How to program the watchdog timeout .....	718
25.3.5	Debug mode .....	719
25.4	WWDG interrupts .....	720
25.5	WWDG registers .....	720
25.5.1	WWDG control register (WWDG_CR) .....	720

- 25.5.2 WWDG configuration register (WWDG_CFR) . . . . . 721
- 25.5.3 WWDG status register (WWDG_SR) . . . . . 721
- 25.5.4 WWDG register map . . . . . 721

26 Independent watchdog (IWDG) . . . . . 723
- 26.1 Introduction . . . . . 723
- 26.2 IWDG main features . . . . . 723
- 26.3 IWDG functional description . . . . . 723
  - 26.3.1 IWDG block diagram . . . . . 723
  - 26.3.2 Window option . . . . . 724
  - 26.3.3 Hardware watchdog . . . . . 725
  - 26.3.4 Register access protection . . . . . 725
  - 26.3.5 Debug mode . . . . . 725
- 26.4 IWDG registers . . . . . 726
  - 26.4.1 IWDG key register (IWDG_KR) . . . . . 726
  - 26.4.2 IWDG prescaler register (IWDG_PR) . . . . . 727
  - 26.4.3 IWDG reload register (IWDG_RLR) . . . . . 728
  - 26.4.4 IWDG status register (IWDG_SR) . . . . . 729
  - 26.4.5 IWDG window register (IWDG_WINR) . . . . . 730
  - 26.4.6 IWDG register map . . . . . 731

27 Real-time clock (RTC) . . . . . 732
- 27.1 Introduction . . . . . 732
- 27.2 RTC main features . . . . . 733
- 27.3 RTC functional description . . . . . 734
  - 27.3.1 RTC block diagram . . . . . 734
  - 27.3.2 GPIOs controlled by the RTC . . . . . 735
  - 27.3.3 Clock and prescalers . . . . . 737
  - 27.3.4 Real-time clock and calendar . . . . . 737
  - 27.3.5 Programmable alarms . . . . . 738
  - 27.3.6 Periodic auto-wakeup . . . . . 738
  - 27.3.7 RTC initialization and configuration . . . . . 739
  - 27.3.8 Reading the calendar . . . . . 740
  - 27.3.9 Resetting the RTC . . . . . 741
  - 27.3.10 RTC synchronization . . . . . 742
  - 27.3.11 RTC reference clock detection . . . . . 742

27.3.12	RTC smooth digital calibration . . . . .	743
27.3.13	Time-stamp function . . . . .	745
27.3.14	Tamper detection . . . . .	746
27.3.15	Calibration clock output . . . . .	747
27.3.16	Alarm output . . . . .	748
27.4	RTC low-power modes . . . . .	748
27.5	RTC interrupts . . . . .	748
27.6	RTC registers . . . . .	749
27.6.1	RTC time register (RTC_TR) . . . . .	749
27.6.2	RTC date register (RTC_DR) . . . . .	750
27.6.3	RTC control register (RTC_CR) . . . . .	752
27.6.4	RTC initialization and status register (RTC_ISR) . . . . .	755
27.6.5	RTC prescaler register (RTC_PRER) . . . . .	758
27.6.6	RTC wakeup timer register (RTC_WUTR) . . . . .	759
27.6.7	RTC alarm A register (RTC_ALRMAR) . . . . .	760
27.6.8	RTC alarm B register (RTC_ALRMBR) . . . . .	761
27.6.9	RTC write protection register (RTC_WPR) . . . . .	762
27.6.10	RTC sub second register (RTC_SSR) . . . . .	762
27.6.11	RTC shift control register (RTC_SHIFTR) . . . . .	763
27.6.12	RTC timestamp time register (RTC_TSTR) . . . . .	764
27.6.13	RTC timestamp date register (RTC_TSDR) . . . . .	765
27.6.14	RTC time-stamp sub second register (RTC_TSSSR) . . . . .	766
27.6.15	RTC calibration register (RTC_CALR) . . . . .	767
27.6.16	RTC tamper and alternate function configuration register (RTC_TAFCR) . . . . .	768
27.6.17	RTC alarm A sub second register (RTC_ALRMASSR) . . . . .	771
27.6.18	RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .	772
27.6.19	RTC backup registers (RTC_BKPxR) . . . . .	773
27.6.20	RTC register map . . . . .	773
28	Inter-integrated circuit (I2C) interface . . . . .	776
28.1	Introduction . . . . .	776
28.2	I2C main features . . . . .	776
28.3	I2C implementation . . . . .	777
28.4	I2C functional description . . . . .	777
28.4.1	I2C block diagram . . . . .	778
28.4.2	I2C pins and internal signals . . . . .	779

28.4.3 I2C clock requirements ..... 779
28.4.4 Mode selection ..... 779
28.4.5 I2C initialization ..... 780
28.4.6 Software reset ..... 785
28.4.7 Data transfer ..... 786
28.4.8 I2C slave mode ..... 788
28.4.9 I2C master mode ..... 797
28.4.10 I2C_TIMINGR register configuration examples ..... 809
28.4.11 SMBus specific features ..... 810
28.4.12 SMBus initialization ..... 813
28.4.13 SMBus: I2C_TIMEOUTR register configuration examples ..... 815
28.4.14 SMBus slave mode ..... 815
28.4.15 Wakeup from Stop mode on address match ..... 823
28.4.16 Error conditions ..... 823
28.4.17 DMA requests ..... 825
28.4.18 Debug mode ..... 826
28.5 I2C low-power modes ..... 826
28.6 I2C interrupts ..... 827
28.7 I2C registers ..... 828
- 28.7.1 I2C control register 1 (I2C_CR1) ..... 828
- 28.7.2 I2C control register 2 (I2C_CR2) ..... 831
- 28.7.3 I2C own address 1 register (I2C_OAR1) ..... 833
- 28.7.4 I2C own address 2 register (I2C_OAR2) ..... 834
- 28.7.5 I2C timing register (I2C_TIMINGR) ..... 835
- 28.7.6 I2C timeout register (I2C_TIMEOUTR) ..... 836
- 28.7.7 I2C interrupt and status register (I2C_ISR) ..... 837
- 28.7.8 I2C interrupt clear register (I2C_ICR) ..... 839
- 28.7.9 I2C PEC register (I2C_PECR) ..... 840
- 28.7.10 I2C receive data register (I2C_RXDR) ..... 841
- 28.7.11 I2C transmit data register (I2C_TXDR) ..... 841
- 28.7.12 I2C register map ..... 842
29 Universal synchronous/asynchronous receiver transmitter (USART/UART) ..... 844
- 29.1 Introduction ..... 844
- 29.2 USART main features ..... 844
- 29.3 USART extended features ..... 845

29.4	USART implementation . . . . .	846
29.5	USART functional description . . . . .	847
29.5.1	USART character description . . . . .	849
29.5.2	USART transmitter . . . . .	851
29.5.3	USART receiver . . . . .	853
29.5.4	USART baud rate generation . . . . .	860
29.5.5	Tolerance of the USART receiver to clock deviation . . . . .	862
29.5.6	USART auto baud rate detection . . . . .	863
29.5.7	Multiprocessor communication using USART . . . . .	864
29.5.8	Modbus communication using USART . . . . .	866
29.5.9	USART parity control . . . . .	867
29.5.10	USART LIN (local interconnection network) mode . . . . .	868
29.5.11	USART synchronous mode . . . . .	870
29.5.12	USART Single-wire Half-duplex communication . . . . .	873
29.5.13	USART Smartcard mode . . . . .	873
29.5.14	USART IrDA SIR ENDEC block . . . . .	878
29.5.15	USART continuous communication in DMA mode . . . . .	880
29.5.16	RS232 hardware flow control and RS485 driver enable using USART . . . . .	882
29.5.17	Wakeup from Stop mode using USART . . . . .	884
29.6	USART in low-power modes . . . . .	886
29.7	USART interrupts . . . . .	886
29.8	USART registers . . . . .	888
29.8.1	USART control register 1 (USART_CR1) . . . . .	888
29.8.2	USART control register 2 (USART_CR2) . . . . .	891
29.8.3	USART control register 3 (USART_CR3) . . . . .	895
29.8.4	USART baud rate register (USART_BRR) . . . . .	899
29.8.5	USART guard time and prescaler register (USART_GTPR) . . . . .	899
29.8.6	USART receiver timeout register (USART_RTOR) . . . . .	900
29.8.7	USART request register (USART_RQR) . . . . .	901
29.8.8	USART interrupt and status register (USART_ISR) . . . . .	902
29.8.9	USART interrupt flag clear register (USART_ICR) . . . . .	907
29.8.10	USART receive data register (USART_RDR) . . . . .	908
29.8.11	USART transmit data register (USART_TDR) . . . . .	908
29.8.12	USART register map . . . . .	909

Serial peripheral interface / integrated interchip sound (SPI/I2S) . . .

911

30.1 Introduction .....911
30.2 SPI main features .....911
30.3 I2S main features ..... 912
30.4 SPI/I2S implementation ..... 912
30.5 SPI functional description ..... 913
- 30.5.1 General description ..... 913
- 30.5.2 Communications between one master and one slave ..... 914
- 30.5.3 Standard multi-slave communication ..... 916
- 30.5.4 Multi-master communication ..... 917
- 30.5.5 Slave select (NSS) pin management ..... 918
- 30.5.6 Communication formats ..... 919
- 30.5.7 Configuration of SPI ..... 921
- 30.5.8 Procedure for enabling SPI ..... 922
- 30.5.9 Data transmission and reception procedures ..... 922
- 30.5.10 SPI status flags ..... 932
- 30.5.11 SPI error flags ..... 933
- 30.5.12 NSS pulse mode ..... 934
- 30.5.13 TI mode ..... 934
- 30.5.14 CRC calculation ..... 935
30.6 SPI interrupts ..... 937
30.7 I2S functional description ..... 938
- 30.7.1 I2S general description ..... 938
- 30.7.2 I2S full duplex ..... 939
- 30.7.3 Supported audio protocols ..... 940
- 30.7.4 Start-up description ..... 946
- 30.7.5 Clock generator ..... 948
- 30.7.6 I ²S master mode ..... 950
- 30.7.7 I ²S slave mode ..... 952
- 30.7.8 I2S status flags ..... 954
- 30.7.9 I2S error flags ..... 955
- 30.7.10 DMA features ..... 956
30.8 I2S interrupts ..... 956
30.9 SPI and I2S registers ..... 957
- 30.9.1 SPI control register 1 (SPIx_CR1) ..... 957
- 30.9.2 SPI control register 2 (SPIx_CR2) ..... 959
- 30.9.3 SPI status register (SPIx_SR) ..... 961

30.9.4	SPI data register (SPIx_DR) .....	963
30.9.5	SPI CRC polynomial register (SPIx_CRCPR) .....	963
30.9.6	SPI Rx CRC register (SPIx_RXCRCR) .....	963
30.9.7	SPI Tx CRC register (SPIx_TXCRCR) .....	964
30.9.8	SPIx_I2S configuration register (SPIx_I2SCFGR) .....	964
30.9.9	SPIx_I2S prescaler register (SPIx_I2SPR) .....	966
30.9.10	SPI/I2S register map .....	967
31	Controller area network (bxCAN) .....	968
31.1	Introduction .....	968
31.2	bxCAN main features .....	968
31.3	bxCAN general description .....	968
31.3.1	CAN 2.0B active core .....	969
31.3.2	Control, status and configuration registers .....	969
31.3.3	Tx mailboxes .....	969
31.3.4	Acceptance filters .....	969
31.4	bxCAN operating modes .....	970
31.4.1	Initialization mode .....	970
31.4.2	Normal mode .....	971
31.4.3	Sleep mode (low-power) .....	971
31.5	Test mode .....	972
31.5.1	Silent mode .....	972
31.5.2	Loop back mode .....	973
31.5.3	Loop back combined with silent mode .....	973
31.6	Behavior in debug mode .....	974
31.7	bxCAN functional description .....	974
31.7.1	Transmission handling .....	974
31.7.2	Time triggered communication mode .....	976
31.7.3	Reception handling .....	976
31.7.4	Identifier filtering .....	977
31.7.5	Message storage .....	981
31.7.6	Error management .....	983
31.7.7	Bit timing .....	983
31.8	bxCAN interrupts .....	986
31.9	CAN registers .....	987
31.9.1	Register access protection .....	987

31.9.2 CAN control and status registers . . . . . 987

31.9.3 CAN mailbox registers . . . . . 997

31.9.4 CAN filter registers . . . . . 1002

31.9.5 bxCAN register map . . . . . 1006

32 Universal serial bus full-speed device interface (USB) . . . . . 1010

32.1 Introduction . . . . . 1010

32.2 USB main features . . . . . 1010

32.3 USB implementation . . . . . 1010

32.4 USB functional description . . . . . 1011

32.4.1 Description of USB blocks . . . . . 1012

32.5 Programming considerations . . . . . 1013

32.5.1 Generic USB device programming . . . . . 1014

32.5.2 System and power-on reset . . . . . 1014

32.5.3 Double-buffered endpoints . . . . . 1019

32.5.4 Isochronous transfers . . . . . 1021

32.5.5 Suspend/Resume events . . . . . 1023

32.6 USB and USB SRAM registers . . . . . 1025

32.6.1 Common registers . . . . . 1025

32.6.2 Buffer descriptor table . . . . . 1037

32.6.3 USB register map . . . . . 1041

33 Debug support (DBG) . . . . . 1043

33.1 Overview . . . . . 1043

33.2 Reference Arm documentation . . . . . 1044

33.3 SWJ debug port (serial wire and JTAG) . . . . . 1044

33.3.1 Mechanism to select the JTAG-DP or the SW-DP . . . . . 1045

33.4 Pinout and debug port pins . . . . . 1045

33.4.1 SWJ debug port pins . . . . . 1046

33.4.2 Flexible SWJ-DP pin assignment . . . . . 1046

33.4.3 Internal pull-up and pull-down on JTAG pins . . . . . 1047

33.4.4 Using serial wire and releasing the unused debug pins as GPIOs . . . . . 1048

33.5 STM32F302xx JTAG TAP connection . . . . . 1048

33.6 ID codes and locking mechanism . . . . . 1049

33.6.1 MCU device ID code . . . . . 1049

33.6.2 Boundary scan TAP . . . . . 1050

33.6.3	Cortex-M4 ^®F TAP . . . . .	1050
33.6.4	Cortex-M4 ^®F JEDEC-106 ID code . . . . .	1050
33.7	JTAG debug port . . . . .	1050
33.8	SW debug port . . . . .	1052
33.8.1	SW protocol introduction . . . . .	1052
33.8.2	SW protocol sequence . . . . .	1052
33.8.3	SW-DP state machine (reset, idle states, ID code) . . . . .	1053
33.8.4	DP and AP read/write accesses . . . . .	1054
33.8.5	SW-DP registers . . . . .	1054
33.8.6	SW-AP registers . . . . .	1055
33.9	AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP . . . . .	1055
33.10	Core debug . . . . .	1056
33.11	Capability of the debugger host to connect under system reset . . . . .	1057
33.12	FPB (Flash patch breakpoint) . . . . .	1057
33.13	DWT (data watchpoint trigger) . . . . .	1057
33.14	MCU debug component (DBGMCU) . . . . .	1058
33.14.1	Debug support for low-power modes . . . . .	1058
33.14.2	Debug support for timers, watchdog, bxCAN and I ²C . . . . .	1058
33.14.3	Debug MCU configuration register . . . . .	1059
33.14.4	Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . .	1061
33.14.5	Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) . . . . .	1063
33.15	TPIU (trace port interface unit) . . . . .	1064
33.15.1	Introduction . . . . .	1064
33.15.2	TRACE pin assignment . . . . .	1064
33.15.3	TPUI formatter . . . . .	1066
33.15.4	TPUI frame synchronization packets . . . . .	1067
33.15.5	Transmission of the synchronization frame packet . . . . .	1067
33.15.6	Synchronous mode . . . . .	1067
33.15.7	Asynchronous mode . . . . .	1068
33.15.8	TRACECLKIN connection inside the STM32F302xx . . . . .	1068
33.15.9	TPIU registers . . . . .	1069
33.15.10	Example of configuration . . . . .	1070
33.16	DBG register map . . . . .	1070
34	Device electronic signature . . . . .	1071

34.1	Unique device ID register (96 bits) .....	1071
34.2	Flash memory size data register .....	1072
35	Revision history .....	1073

List of tables

Table 1.	Available features related to each product . . . . .	43
Table 2.	STM32F302xB/C peripheral register boundary addresses. . . . .	52
Table 3.	STM32F302xD/E peripheral register boundary addresses. . . . .	55
Table 4.	STM32F302x6/x8 peripheral register boundary addresses . . . . .	58
Table 5.	Boot modes. . . . .	61
Table 6.	Flash module organization . . . . .	63
Table 7.	Flash memory read protection status . . . . .	72
Table 8.	Access status versus protection level and execution modes . . . . .	73
Table 9.	Flash interrupt request . . . . .	74
Table 10.	Flash interface - register map and reset values . . . . .	80
Table 11.	Option byte format . . . . .	82
Table 12.	Option byte organization. . . . .	82
Table 13.	Description of the option bytes . . . . .	83
Table 14.	CRC internal input/output signals . . . . .	86
Table 15.	CRC register map and reset values . . . . .	91
Table 16.	STM32F302xx peripherals interconnect matrix . . . . .	92
Table 17.	VREFOPAMPx to ADC channel . . . . .	96
Table 18.	OPAMP output to ADC input . . . . .	96
Table 19.	Comparator outputs to timer inputs . . . . .	97
Table 20.	Timer output selection as comparator blanking source . . . . .	98
Table 21.	Timer synchronization. . . . .	100
Table 22.	Timer and EXTI signals triggering DAC1 conversions . . . . .	101
Table 23.	Low-power mode summary . . . . .	106
Table 24.	Sleep-now . . . . .	108
Table 25.	Sleep-on-exit. . . . .	108
Table 26.	Stop mode . . . . .	110
Table 27.	Standby mode. . . . .	111
Table 28.	PWR register map and reset values. . . . .	115
Table 29.	RCC register map and reset values . . . . .	155
Table 30.	Port bit configuration table . . . . .	160
Table 31.	GPIO register map and reset values . . . . .	173
Table 32.	SYSCFG register map and reset values. . . . .	184
Table 33.	DMA1 and DMA2 implementation . . . . .	186
Table 34.	DMA requests for each channel on STM32F302x6/8. . . . .	188
Table 35.	DMA1 requests for each channel on STM32F302xB/C/D/E devices . . . . .	190
Table 36.	DMA2 requests for each channel on STM32F302xB/C/D/E devices . . . . .	191
Table 37.	Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .	198
Table 38.	DMA interrupt requests. . . . .	199
Table 39.	DMA register map and reset values . . . . .	208
Table 40.	STM32F302xB/C/D/E vector table . . . . .	211
Table 41.	STM32F302x6/8 vector table . . . . .	214
Table 42.	External interrupt/event controller register map and reset values. . . . .	229
Table 43.	NOR/PSRAM bank selection . . . . .	235
Table 44.	NOR/PSRAM External memory address . . . . .	235
Table 45.	NAND/PC Card memory mapping and timing registers . . . . .	236
Table 46.	NAND bank selection . . . . .	236
Table 47.	Programmable NOR/PSRAM access parameters . . . . .	238
Table 48.	Non-multiplexed I/O NOR Flash memory . . . . .	238

Table 49.	16-bit multiplexed I/O NOR Flash memory . . . . .	239
Table 50.	Non-multiplexed I/Os PSRAM/SRAM . . . . .	239
Table 51.	16-Bit multiplexed I/O PSRAM . . . . .	239
Table 52.	NOR Flash/PSRAM: example of supported memories and transactions . . . . .	240
Table 53.	FMC_BCRx bitfields (mode 1) . . . . .	243
Table 54.	FMC_BTRx bitfields (mode 1) . . . . .	244
Table 55.	FMC_BCRx bitfields (mode A) . . . . .	246
Table 56.	FMC_BTRx bitfields (mode A) . . . . .	246
Table 57.	FMC_BWTRx bitfields (mode A) . . . . .	247
Table 58.	FMC_BCRx bitfields (mode 2/B) . . . . .	249
Table 59.	FMC_BTRx bitfields (mode 2/B) . . . . .	249
Table 60.	FMC_BWTRx bitfields (mode 2/B) . . . . .	250
Table 61.	FMC_BCRx bitfields (mode C) . . . . .	251
Table 62.	FMC_BTRx bitfields (mode C) . . . . .	252
Table 63.	FMC_BWTRx bitfields (mode C) . . . . .	252
Table 64.	FMC_BCRx bitfields (mode D) . . . . .	254
Table 65.	FMC_BTRx bitfields (mode D) . . . . .	254
Table 66.	FMC_BWTRx bitfields (mode D) . . . . .	255
Table 67.	FMC_BCRx bitfields (Muxed mode) . . . . .	256
Table 68.	FMC_BTRx bitfields (Muxed mode) . . . . .	257
Table 69.	FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .	262
Table 70.	FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .	263
Table 71.	FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .	264
Table 72.	FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .	265
Table 73.	Programmable NAND Flash/PC Card access parameters . . . . .	274
Table 74.	8-bit NAND Flash . . . . .	274
Table 75.	16-bit NAND Flash . . . . .	275
Table 76.	16-bit PC Card . . . . .	275
Table 77.	Supported memories and transactions . . . . .	276
Table 78.	16-bit PC-Card signals and access type . . . . .	281
Table 79.	ECC result relevant bits . . . . .	288
Table 80.	FMC register map . . . . .	289
Table 81.	ADC external channels mapping . . . . .	292
Table 82.	ADC internal channels summary . . . . .	293
Table 83.	ADC internal signals . . . . .	295
Table 84.	ADC pins . . . . .	295
Table 85.	Configuring the trigger polarity for regular external triggers . . . . .	310
Table 86.	Configuring the trigger polarity for injected external triggers . . . . .	311
Table 87.	ADC1 (master) & 2 (slave) - External triggers for regular channels . . . . .	312
Table 88.	ADC1 & ADC2 - External trigger for injected channels . . . . .	312
Table 89.	TSAR timings depending on resolution . . . . .	324
Table 90.	Offset computation versus data resolution . . . . .	327
Table 91.	Analog watchdog channel selection . . . . .	337
Table 92.	Analog watchdog 1 comparison . . . . .	338
Table 93.	Analog watchdog 2 and 3 comparison . . . . .	338
Table 94.	ADC interrupts per each ADC . . . . .	359
Table 95.	DELAY bits versus ADC resolution . . . . .	392
Table 96.	ADC global register map . . . . .	393
Table 97.	ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC, x=1..2) . . . . .	394
Table 98.	ADC register map and reset values (master and slave ADC common registers) offset =0x300, x=1 or 34) . . . . .	396

Table 99.	DACx pins . . . . .	398
Table 100.	External triggers (DAC1) . . . . .	401
Table 101.	DAC register map and reset values . . . . .	410
Table 102.	STM32F302xB/C/D/E comparator input/outputs summary . . . . .	413
Table 103.	STM32F302x6/8 comparator input/outputs summary . . . . .	414
Table 104.	COMP register map and reset values . . . . .	425
Table 105.	Connections with dedicated I/O . . . . .	426
Table 106.	OPAMP register map and reset values . . . . .	439
Table 107.	Acquisition sequence summary . . . . .	443
Table 108.	Spread spectrum deviation versus AHB clock frequency . . . . .	445
Table 109.	I/O state depending on its mode and IODEF bit value . . . . .	446
Table 110.	Effect of low-power modes on TSC . . . . .	448
Table 111.	Interrupt control bits . . . . .	448
Table 112.	TSC register map and reset values . . . . .	457
Table 113.	Behavior of timer outputs versus BRK/BRK2 inputs . . . . .	501
Table 114.	Counting direction versus encoder signals . . . . .	508
Table 115.	TIM1 internal trigger connection . . . . .	525
Table 116.	Output control bits for complementary OCx and OCxN channels with break feature . . . . .	539
Table 117.	TIM1 register map and reset values . . . . .	551
Table 118.	Counting direction versus encoder signals . . . . .	588
Table 119.	TIMx internal trigger connection . . . . .	606
Table 120.	Output control bit for standard OCx channels . . . . .	616
Table 121.	TIM2/TIM3/TIM4 register map and reset values . . . . .	622
Table 122.	TIMx Internal trigger connection . . . . .	665
Table 123.	Output control bits for complementary OCx and OCxN channels with break feature (TIM15) . . . . .	675
Table 124.	TIM15 register map and reset values . . . . .	681
Table 125.	Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) . . . . .	694
Table 126.	TIM16/TIM17 register map and reset values . . . . .	701
Table 127.	TIM6 register map and reset values . . . . .	715
Table 128.	WWDG register map and reset values . . . . .	722
Table 129.	IWDG register map and reset values . . . . .	731
Table 130.	RTC pin PC13 configuration . . . . .	736
Table 131.	LSE pin PC14 configuration . . . . .	736
Table 132.	LSE pin PC15 configuration . . . . .	736
Table 133.	Effect of low-power modes on RTC . . . . .	748
Table 134.	Interrupt control bits . . . . .	749
Table 135.	RTC register map and reset values . . . . .	773
Table 136.	STM32F302xx I2C implementation . . . . .	777
Table 137.	I2C input/output pins . . . . .	779
Table 138.	I2C internal input/output signals . . . . .	779
Table 139.	Comparison of analog vs. digital filters . . . . .	781
Table 140.	I2C-SMBus specification data setup and hold times . . . . .	784
Table 141.	I2C configuration . . . . .	788
Table 142.	I2C-SMBus specification clock timings . . . . .	799
Table 143.	Examples of timing settings for f _I2CCLK= 8 MHz . . . . .	809
Table 144.	Examples of timings settings for f _I2CCLK= 16 MHz . . . . .	809
Table 145.	Examples of timings settings for f _I2CCLK= 48 MHz . . . . .	810
Table 146.	SMBus timeout specifications . . . . .	812
Table 147.	SMBus with PEC configuration . . . . .	814
Table 148.	Examples of TIMEOUTA settings for various I2CCLK frequencies

	(max $t_{\text{TIMEOUT}} = 25 \text{ ms}$ ) . . . . .	815
Table 149.	Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . .	815
Table 150.	Examples of TIMEOUTA settings for various I2CCLK frequencies (max $t_{\text{IDLE}} = 50 \text{ } \mu\text{s}$ ) . . . . .	815
Table 151.	Effect of low-power modes on the I2C . . . . .	826
Table 152.	I2C Interrupt requests . . . . .	827
Table 153.	I2C register map and reset values . . . . .	842
Table 154.	STM32F302xx USART features . . . . .	846
Table 155.	Noise detection from sampled data . . . . .	858
Table 156.	Error calculation for programmed baud rates at $f_{\text{CK}} = 72\text{MHz}$ in both cases of oversampling by 16 or by 8. . . . .	861
Table 157.	Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .	863
Table 158.	Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . .	863
Table 159.	Frame formats . . . . .	867
Table 160.	Effect of low-power modes on the USART . . . . .	886
Table 161.	USART interrupt requests. . . . .	886
Table 162.	USART register map and reset values . . . . .	909
Table 163.	STM32F302x6/8 SPI/I2S implementation. . . . .	912
Table 164.	STM32F302xB/C/D/E SPI and SPI/I2S implementation. . . . .	913
Table 165.	SPI interrupt requests . . . . .	937
Table 166.	Audio-frequency precision using standard 8 MHz HSE . . . . .	950
Table 167.	I2S interrupt requests . . . . .	956
Table 168.	SPI/I2S register map and reset values . . . . .	967
Table 169.	Transmit mailbox mapping . . . . .	982
Table 170.	Receive mailbox mapping. . . . .	982
Table 171.	bxCAN register map and reset values . . . . .	1006
Table 172.	STM32F302xx USB implementation. . . . .	1010
Table 173.	Double-buffering buffer flag definition. . . . .	1020
Table 174.	Bulk double-buffering memory buffers usage . . . . .	1020
Table 175.	Isochronous memory buffers usage . . . . .	1022
Table 176.	Resume event detection . . . . .	1024
Table 177.	Reception status encoding . . . . .	1035
Table 178.	Endpoint type encoding . . . . .	1035
Table 179.	Endpoint kind meaning . . . . .	1035
Table 180.	Transmission status encoding . . . . .	1036
Table 181.	Definition of allocated buffer memory . . . . .	1039
Table 182.	USB register map and reset values . . . . .	1041
Table 183.	SWJ debug port pins . . . . .	1046
Table 184.	Flexible SWJ-DP pin assignment . . . . .	1046
Table 185.	JTAG debug port data registers . . . . .	1050
Table 186.	32-bit debug port registers addressed through the shifted value A[3:2] . . . . .	1051
Table 187.	Packet request (8-bits) . . . . .	1052
Table 188.	ACK response (3 bits). . . . .	1053
Table 189.	DATA transfer (33 bits). . . . .	1053
Table 190.	SW-DP registers . . . . .	1054
Table 191.	Cortex-M4 ^®F AHB-AP registers . . . . .	1056
Table 192.	Core debug registers . . . . .	1056
Table 193.	Asynchronous TRACE pin assignment. . . . .	1064
Table 194.	Synchronous TRACE pin assignment . . . . .	1065
Table 195.	Flexible TRACE pin assignment. . . . .	1065
Table 196.	Important TPIU registers. . . . .	1069

Table 197. DBG register map and reset values . . . . .	1070
Table 198. Document revision history . . . . .	1073

List of figures

Figure 1.	STM32F302xB/C system architecture . . . . .	48
Figure 2.	STM32F302x6/8 system architecture . . . . .	48
Figure 3.	STM32F302xD/E system architecture . . . . .	49
Figure 4.	Programming procedure . . . . .	67
Figure 5.	Flash memory Page Erase procedure . . . . .	69
Figure 6.	Flash memory Mass Erase procedure . . . . .	70
Figure 7.	CRC calculation unit block diagram . . . . .	86
Figure 8.	Power supply overview . . . . .	102
Figure 9.	Power on reset/power down reset waveform . . . . .	105
Figure 10.	PVD thresholds . . . . .	106
Figure 11.	Simplified diagram of the reset circuit . . . . .	117
Figure 12.	STM32F302xB/C clock tree . . . . .	119
Figure 13.	STM32F302xD/E clock tree . . . . .	120
Figure 14.	STM32F302x6/8 clock tree . . . . .	121
Figure 15.	HSE/ LSE clock sources . . . . .	122
Figure 16.	Frequency measurement with TIM16 in capture mode . . . . .	128
Figure 17.	Basic structure of an I/O port bit . . . . .	159
Figure 18.	Basic structure of a 5-Volt tolerant I/O port bit . . . . .	159
Figure 19.	Input floating/pull up/pull down configurations . . . . .	164
Figure 20.	Output configuration . . . . .	165
Figure 21.	Alternate function configuration . . . . .	166
Figure 22.	High impedance-analog configuration . . . . .	166
Figure 23.	DMA request mapping on STM32F302x6/8 . . . . .	187
Figure 24.	DMA1 request mapping on STM32F302xB/C/D/E . . . . .	189
Figure 25.	DMA2 request mapping on STM32F302xB/C/D/E . . . . .	190
Figure 26.	DMA block diagram . . . . .	192
Figure 27.	External interrupt/event block diagram . . . . .	219
Figure 28.	External interrupt/event GPIO mapping . . . . .	221
Figure 29.	FMC block diagram . . . . .	232
Figure 30.	FMC memory banks . . . . .	235
Figure 31.	Mode 1 read access waveforms . . . . .	242
Figure 32.	Mode 1 write access waveforms . . . . .	243
Figure 33.	Mode A read access waveforms . . . . .	245
Figure 34.	Mode A write access waveforms . . . . .	245
Figure 35.	Mode 2 and mode B read access waveforms . . . . .	247
Figure 36.	Mode 2 write access waveforms . . . . .	248
Figure 37.	Mode B write access waveforms . . . . .	248
Figure 38.	Mode C read access waveforms . . . . .	250
Figure 39.	Mode C write access waveforms . . . . .	251
Figure 40.	Mode D read access waveforms . . . . .	253
Figure 41.	Mode D write access waveforms . . . . .	253
Figure 42.	Muxed read access waveforms . . . . .	255
Figure 43.	Muxed write access waveforms . . . . .	256
Figure 44.	Asynchronous wait during a read access waveforms . . . . .	258
Figure 45.	Asynchronous wait during a write access waveforms . . . . .	259
Figure 46.	Wait configuration waveforms . . . . .	261
Figure 47.	Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . .	262
Figure 48.	Synchronous multiplexed write mode waveforms - PSRAM (CRAM) . . . . .	264
Figure 49.	NAND Flash/PC Card controller waveforms for common memory access . . . . .	277
Figure 50.	Access to non 'CE don't care' NAND-Flash . . . . .	278

Figure 51.	ADC block diagram . . . . .	294
Figure 52.	ADC clock scheme . . . . .	296
Figure 53.	ADC1 and ADC2 connectivity . . . . .	298
Figure 54.	ADC calibration. . . . .	301
Figure 55.	Updating the ADC calibration factor . . . . .	302
Figure 56.	Mixing single-ended and differential channels . . . . .	302
Figure 57.	Enabling / Disabling the ADC . . . . .	303
Figure 58.	Analog to digital conversion time . . . . .	308
Figure 59.	Stopping ongoing regular conversions . . . . .	309
Figure 60.	Stopping ongoing regular and injected conversions . . . . .	310
Figure 61.	Triggers are shared between ADC master & ADC slave . . . . .	311
Figure 62.	Injected conversion latency . . . . .	314
Figure 63.	Example of JSQR queue of context (sequence change) . . . . .	317
Figure 64.	Example of JSQR queue of context (trigger change) . . . . .	317
Figure 65.	Example of JSQR queue of context with overflow before conversion . . . . .	318
Figure 66.	Example of JSQR queue of context with overflow during conversion . . . . .	318
Figure 67.	Example of JSQR queue of context with empty queue (case JQM=0). . . . .	319
Figure 68.	Example of JSQR queue of context with empty queue (case JQM=1). . . . .	320
Figure 69.	Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion. . . . .	320
Figure 70.	Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs during an ongoing conversion and a new trigger occurs. . . . .	321
Figure 71.	Flushing JSQR queue of context by setting JADSTP=1 (JQM=0). Case when JADSTP occurs outside an ongoing conversion . . . . .	321
Figure 72.	Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . .	322
Figure 73.	Flushing JSQR queue of context by setting ADDIS=1 (JQM=0). . . . .	322
Figure 74.	Flushing JSQR queue of context by setting ADDIS=1 (JQM=1). . . . .	323
Figure 75.	Example of JSQR queue of context when changing SW and HW triggers. . . . .	323
Figure 76.	Single conversions of a sequence, software trigger . . . . .	325
Figure 77.	Continuous conversion of a sequence, software trigger. . . . .	325
Figure 78.	Single conversions of a sequence, hardware trigger . . . . .	326
Figure 79.	Continuous conversions of a sequence, hardware trigger . . . . .	326
Figure 80.	Right alignment (offset disabled, unsigned value) . . . . .	328
Figure 81.	Right alignment (offset enabled, signed value). . . . .	328
Figure 82.	Left alignment (offset disabled, unsigned value) . . . . .	329
Figure 83.	Left alignment (offset enabled, signed value). . . . .	329
Figure 84.	Example of overrun (OVR) . . . . .	330
Figure 85.	AUTODLY=1, regular conversion in continuous mode, software trigger . . . . .	333
Figure 86.	AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=0; JDISCEN=0) . . . . .	334
Figure 87.	AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=1, JDISCEN=1) . . . . .	335
Figure 88.	AUTODLY=1, regular continuous conversions interrupted by injected conversions . . . . .	336
Figure 89.	AUTODLY=1 in auto- injected mode (JAUTO=1). . . . .	336
Figure 90.	Analog watchdog's guarded area . . . . .	337
Figure 91.	ADC _y_AWD _x_OUT signal generation (on all regular channels). . . . .	339
Figure 92.	ADC _y_AWD _x_OUT signal generation (AWD _xflag not cleared by SW) . . . . .	340
Figure 93.	ADC _y_AWD _x_OUT signal generation (on a single regular channel) . . . . .	340
Figure 94.	ADC _y_AWD _x_OUT signal generation (on all injected channels) . . . . .	340
Figure 95.	Dual ADC block diagram ⁽¹⁾. . . . .	342
Figure 96.	Injected simultaneous mode on 4 channels: dual ADC mode . . . . .	343

Figure 97.	Regular simultaneous mode on 16 channels: dual ADC mode . . . . .	345
Figure 98.	Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode. . . . .	347
Figure 99.	Interleaved mode on 1 channel in single conversion mode: dual ADC mode. . . . .	347
Figure 100.	Interleaved conversion with injection . . . . .	348
Figure 101.	Alternate trigger: injected group of each ADC . . . . .	349
Figure 102.	Alternate trigger: 4 injected channels (each ADC) in discontinuous mode. . . . .	350
Figure 103.	Alternate + regular simultaneous . . . . .	351
Figure 104.	Case of trigger occurring during injected conversion . . . . .	351
Figure 105.	DMA Requests in regular simultaneous mode when MDMA=0b00 . . . . .	352
Figure 106.	DMA requests in regular simultaneous mode when MDMA=0b10 . . . . .	353
Figure 107.	DMA requests in interleaved mode when MDMA=0b10 . . . . .	353
Figure 108.	Temperature sensor channel block diagram . . . . .	355
Figure 109.	VBAT channel block diagram . . . . .	357
Figure 110.	VREFINT channel block diagram . . . . .	357
Figure 111.	DAC1 block diagram . . . . .	398
Figure 112.	Data registers in single DAC channel mode. . . . .	399
Figure 113.	Timing diagram for conversion with trigger disabled TEN = 0 . . . . .	400
Figure 114.	DAC LFSR register calculation algorithm . . . . .	402
Figure 115.	DAC conversion (SW trigger enabled) with LFSR wave generation. . . . .	402
Figure 116.	DAC triangle wave generation . . . . .	403
Figure 117.	DAC conversion (SW trigger enabled) with triangle wave generation . . . . .	403
Figure 118.	Comparator 1 and 2 block diagrams . . . . .	412
Figure 119.	Comparator output blanking . . . . .	415
Figure 120.	STM32F302xB/C/D/E comparator and operational amplifier connections . . . . .	427
Figure 121.	STM32F302x6/8 comparator and operational amplifier connections . . . . .	428
Figure 122.	Timer controlled Multiplexer mode . . . . .	430
Figure 123.	Standalone mode: external gain setting mode . . . . .	431
Figure 124.	Follower configuration. . . . .	432
Figure 125.	PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . .	433
Figure 126.	PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for filtering . . . . .	433
Figure 127.	TSC block diagram . . . . .	441
Figure 128.	Surface charge transfer analog I/O group structure . . . . .	442
Figure 129.	Sampling capacitor voltage variation . . . . .	443
Figure 130.	Charge transfer acquisition sequence . . . . .	444
Figure 131.	Spread spectrum variation principle . . . . .	445
Figure 132.	Advanced-control timer block diagram . . . . .	461
Figure 133.	Counter timing diagram with prescaler division change from 1 to 2 . . . . .	464
Figure 134.	Counter timing diagram with prescaler division change from 1 to 4 . . . . .	464
Figure 135.	Counter timing diagram, internal clock divided by 1 . . . . .	466
Figure 136.	Counter timing diagram, internal clock divided by 2 . . . . .	466
Figure 137.	Counter timing diagram, internal clock divided by 4 . . . . .	467
Figure 138.	Counter timing diagram, internal clock divided by N. . . . .	467
Figure 139.	Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .	468
Figure 140.	Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .	468
Figure 141.	Counter timing diagram, internal clock divided by 1 . . . . .	470
Figure 142.	Counter timing diagram, internal clock divided by 2 . . . . .	470
Figure 143.	Counter timing diagram, internal clock divided by 4 . . . . .	471
Figure 144.	Counter timing diagram, internal clock divided by N. . . . .	471
Figure 145.	Counter timing diagram, update event when repetition counter is not used. . . . .	472
Figure 146.	Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .	473

Figure 147. Counter timing diagram, internal clock divided by 2 . . . . .	474
Figure 148. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	474
Figure 149. Counter timing diagram, internal clock divided by N . . . . .	475
Figure 150. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .	475
Figure 151. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .	476
Figure 152. Update rate examples depending on mode and TIMx_RCR register settings . . . . .	477
Figure 153. External trigger input block . . . . .	478
Figure 154. Control circuit in normal mode, internal clock divided by 1 . . . . .	479
Figure 155. TI2 external clock connection example . . . . .	480
Figure 156. Control circuit in external clock mode 1 . . . . .	481
Figure 157. External trigger input block . . . . .	481
Figure 158. Control circuit in external clock mode 2 . . . . .	482
Figure 159. Capture/compare channel (example: channel 1 input stage) . . . . .	483
Figure 160. Capture/compare channel 1 main circuit . . . . .	484
Figure 161. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .	484
Figure 162. Output stage of capture/compare channel (channel 4) . . . . .	485
Figure 163. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .	485
Figure 164. PWM input mode timing . . . . .	487
Figure 165. Output compare mode, toggle on OC1 . . . . .	489
Figure 166. Edge-aligned PWM waveforms (ARR=8) . . . . .	490
Figure 167. Center-aligned PWM waveforms (ARR=8) . . . . .	491
Figure 168. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .	493
Figure 169. Combined PWM mode on channel 1 and 3 . . . . .	494
Figure 170. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .	495
Figure 171. Complementary output with dead-time insertion . . . . .	496
Figure 172. Dead-time waveforms with delay greater than the negative pulse . . . . .	496
Figure 173. Dead-time waveforms with delay greater than the positive pulse . . . . .	497
Figure 174. Various output behavior in response to a break event on BKIN (OSSI = 1) . . . . .	500
Figure 175. PWM output state following BKIN and BKIN2 pins assertion (OSSI=1) . . . . .	501
Figure 176. PWM output state following BKIN assertion (OSSI=0) . . . . .	502
Figure 177. Clearing TIMx_OCxREF . . . . .	503
Figure 178. 6-step generation, COM example (OSSR=1) . . . . .	504
Figure 179. Example of one pulse mode . . . . .	505
Figure 180. Retriggerable one pulse mode . . . . .	507
Figure 181. Example of counter operation in encoder interface mode . . . . .	508
Figure 182. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .	509
Figure 183. Measuring time interval between edges on 3 signals . . . . .	510
Figure 184. Example of Hall sensor interface . . . . .	512
Figure 185. Control circuit in reset mode . . . . .	513
Figure 186. Control circuit in Gated mode . . . . .	514
Figure 187. Control circuit in trigger mode . . . . .	515
Figure 188. Control circuit in external clock mode 2 + trigger mode . . . . .	516
Figure 189. General-purpose timer block diagram . . . . .	555
Figure 190. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	557
Figure 191. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	557
Figure 192. Counter timing diagram, internal clock divided by 1 . . . . .	558
Figure 193. Counter timing diagram, internal clock divided by 2 . . . . .	559
Figure 194. Counter timing diagram, internal clock divided by 4 . . . . .	559
Figure 195. Counter timing diagram, internal clock divided by N . . . . .	560
Figure 196. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	560
Figure 197. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	561
Figure 198. Counter timing diagram, internal clock divided by 1 . . . . .	562

Figure 199.	Counter timing diagram, internal clock divided by 2 . . . . .	562
Figure 200.	Counter timing diagram, internal clock divided by 4 . . . . .	563
Figure 201.	Counter timing diagram, internal clock divided by N . . . . .	563
Figure 202.	Counter timing diagram, Update event when repetition counter is not used . . . . .	564
Figure 203.	Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .	565
Figure 204.	Counter timing diagram, internal clock divided by 2 . . . . .	566
Figure 205.	Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	566
Figure 206.	Counter timing diagram, internal clock divided by N . . . . .	567
Figure 207.	Counter timing diagram, Update event with ARPE=1 (counter underflow) . . . . .	567
Figure 208.	Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .	568
Figure 209.	Control circuit in normal mode, internal clock divided by 1 . . . . .	569
Figure 210.	TI2 external clock connection example . . . . .	569
Figure 211.	Control circuit in external clock mode 1 . . . . .	570
Figure 212.	External trigger input block . . . . .	571
Figure 213.	Control circuit in external clock mode 2 . . . . .	572
Figure 214.	Capture/Compare channel (example: channel 1 input stage) . . . . .	573
Figure 215.	Capture/Compare channel 1 main circuit . . . . .	573
Figure 216.	Output stage of Capture/Compare channel (channel 1) . . . . .	574
Figure 217.	PWM input mode timing . . . . .	576
Figure 218.	Output compare mode, toggle on OC1 . . . . .	578
Figure 219.	Edge-aligned PWM waveforms (ARR=8) . . . . .	579
Figure 220.	Center-aligned PWM waveforms (ARR=8) . . . . .	580
Figure 221.	Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .	581
Figure 222.	Combined PWM mode on channels 1 and 3 . . . . .	583
Figure 223.	Clearing TIMx_OCxREF . . . . .	584
Figure 224.	Example of one-pulse mode . . . . .	585
Figure 225.	Retriggerable one-pulse mode . . . . .	587
Figure 226.	Example of counter operation in encoder interface mode . . . . .	588
Figure 227.	Example of encoder interface mode with TI1FP1 polarity inverted . . . . .	589
Figure 228.	Control circuit in reset mode . . . . .	590
Figure 229.	Control circuit in gated mode . . . . .	591
Figure 230.	Control circuit in trigger mode . . . . .	592
Figure 231.	Control circuit in external clock mode 2 + trigger mode . . . . .	593
Figure 232.	Master/Slave timer example . . . . .	594
Figure 233.	Master/slave connection example with 1 channel only timers . . . . .	594
Figure 234.	Gating TIM2 with OC1REF of TIM3 . . . . .	595
Figure 235.	Gating TIM2 with Enable of TIM3 . . . . .	596
Figure 236.	Triggering TIM2 with update of TIM3 . . . . .	597
Figure 237.	Triggering TIM2 with Enable of TIM3 . . . . .	597
Figure 238.	Triggering TIM3 and TIM2 with TIM3 TI1 input . . . . .	598
Figure 239.	TIM15 block diagram . . . . .	626
Figure 240.	TIM16/TIM17 block diagram . . . . .	627
Figure 241.	Counter timing diagram with prescaler division change from 1 to 2 . . . . .	629
Figure 242.	Counter timing diagram with prescaler division change from 1 to 4 . . . . .	629
Figure 243.	Counter timing diagram, internal clock divided by 1 . . . . .	631
Figure 244.	Counter timing diagram, internal clock divided by 2 . . . . .	631
Figure 245.	Counter timing diagram, internal clock divided by 4 . . . . .	632
Figure 246.	Counter timing diagram, internal clock divided by N . . . . .	632
Figure 247.	Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	633
Figure 248.	Counter timing diagram, update event when ARPE=1 (TIMx_ARR

preloaded). . . . .	633
Figure 249. Update rate examples depending on mode and TIMx_RCR register settings . . . . .	635
Figure 250. Control circuit in normal mode, internal clock divided by 1 . . . . .	636
Figure 251. TI2 external clock connection example. . . . .	636
Figure 252. Control circuit in external clock mode 1 . . . . .	637
Figure 253. Capture/compare channel (example: channel 1 input stage) . . . . .	638
Figure 254. Capture/compare channel 1 main circuit . . . . .	638
Figure 255. Output stage of capture/compare channel (channel 1). . . . .	639
Figure 256. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .	639
Figure 257. PWM input mode timing . . . . .	641
Figure 258. Output compare mode, toggle on OC1 . . . . .	643
Figure 259. Edge-aligned PWM waveforms (ARR=8) . . . . .	644
Figure 260. Combined PWM mode on channel 1 and 2 . . . . .	645
Figure 261. Complementary output with dead-time insertion. . . . .	646
Figure 262. Dead-time waveforms with delay greater than the negative pulse. . . . .	646
Figure 263. Dead-time waveforms with delay greater than the positive pulse. . . . .	647
Figure 264. Output behavior in response to a break . . . . .	650
Figure 265. Example of one pulse mode . . . . .	652
Figure 266. Retriggerable one pulse mode . . . . .	653
Figure 267. Measuring time interval between edges on 2 signals . . . . .	655
Figure 268. Control circuit in reset mode . . . . .	656
Figure 269. Control circuit in gated mode . . . . .	657
Figure 270. Control circuit in trigger mode . . . . .	658
Figure 271. Basic timer block diagram. . . . .	703
Figure 272. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	705
Figure 273. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	705
Figure 274. Counter timing diagram, internal clock divided by 1 . . . . .	706
Figure 275. Counter timing diagram, internal clock divided by 2 . . . . .	707
Figure 276. Counter timing diagram, internal clock divided by 4 . . . . .	707
Figure 277. Counter timing diagram, internal clock divided by N . . . . .	708
Figure 278. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .	708
Figure 279. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .	709
Figure 280. Control circuit in normal mode, internal clock divided by 1 . . . . .	710
Figure 281. IRTIM internal hardware connections with TIM16 and TIM17 . . . . .	716
Figure 282. Watchdog block diagram . . . . .	718
Figure 283. Window watchdog timing diagram . . . . .	719
Figure 284. Independent watchdog block diagram . . . . .	723
Figure 285. RTC block diagram . . . . .	734
Figure 286. I2C block diagram . . . . .	778
Figure 287. I2C bus protocol . . . . .	780
Figure 288. Setup and hold timings . . . . .	782
Figure 289. I2C initialization flowchart . . . . .	785
Figure 290. Data reception . . . . .	786
Figure 291. Data transmission . . . . .	787
Figure 292. Slave initialization flowchart . . . . .	790
Figure 293. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH= 0 . . . . .	792
Figure 294. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH= 1 . . . . .	793
Figure 295. Transfer bus diagrams for I2C slave transmitter. . . . .	794

Figure 296.	Transfer sequence flowchart for slave receiver with NOSTRETCH=0	795
Figure 297.	Transfer sequence flowchart for slave receiver with NOSTRETCH=1	796
Figure 298.	Transfer bus diagrams for I2C slave receiver	796
Figure 299.	Master clock generation	798
Figure 300.	Master initialization flowchart	800
Figure 301.	10-bit address read access with HEAD10R=0	800
Figure 302.	10-bit address read access with HEAD10R=1	801
Figure 303.	Transfer sequence flowchart for I2C master transmitter for N≤255 bytes	802
Figure 304.	Transfer sequence flowchart for I2C master transmitter for N>255 bytes	803
Figure 305.	Transfer bus diagrams for I2C master transmitter	804
Figure 306.	Transfer sequence flowchart for I2C master receiver for N≤255 bytes	806
Figure 307.	Transfer sequence flowchart for I2C master receiver for N >255 bytes	807
Figure 308.	Transfer bus diagrams for I2C master receiver	808
Figure 309.	Timeout intervals for $t_{LOW:SEXT}$ , $t_{LOW:MEXT}$	812
Figure 310.	Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC	816
Figure 311.	Transfer bus diagrams for SMBus slave transmitter (SBC=1)	817
Figure 312.	Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC	818
Figure 313.	Bus transfer diagrams for SMBus slave receiver (SBC=1)	819
Figure 314.	Bus transfer diagrams for SMBus master transmitter	820
Figure 315.	Bus transfer diagrams for SMBus master receiver	822
Figure 316.	USART block diagram	848
Figure 317.	Word length programming	850
Figure 318.	Configurable stop bits	852
Figure 319.	TC/TXE behavior when transmitting	853
Figure 320.	Start bit detection when oversampling by 16 or 8	854
Figure 321.	Data sampling when oversampling by 16	858
Figure 322.	Data sampling when oversampling by 8	858
Figure 323.	Mute mode using Idle line detection	865
Figure 324.	Mute mode using address mark detection	866
Figure 325.	Break detection in LIN mode (11-bit break length - LBDL bit is set)	869
Figure 326.	Break detection in LIN mode vs. Framing error detection	870
Figure 327.	USART example of synchronous transmission	871
Figure 328.	USART data clock timing diagram (M bits = 00)	871
Figure 329.	USART data clock timing diagram (M bits = 01)	872
Figure 330.	RX data setup/hold time	872
Figure 331.	ISO 7816-3 asynchronous protocol	874
Figure 332.	Parity error detection using the 1.5 stop bits	875
Figure 333.	IrDA SIR ENDEC- block diagram	879
Figure 334.	IrDA data modulation (3/16) -Normal Mode	880
Figure 335.	Transmission using DMA	881
Figure 336.	Reception using DMA	882
Figure 337.	Hardware flow control between 2 USARTs	882
Figure 338.	RS232 RTS flow control	883
Figure 339.	RS232 CTS flow control	884
Figure 340.	USART interrupt mapping diagram	887
Figure 341.	SPI block diagram	913
Figure 342.	Full-duplex single master/ single slave application	914
Figure 343.	Half-duplex single master/ single slave application	915
Figure 344.	Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode)	916
Figure 345.	Master and three independent slaves	917
Figure 346.	Multi-master application	918

Figure 347. Hardware/software slave select management . . . . .	919
Figure 348. Data clock timing diagram . . . . .	920
Figure 349. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .	921
Figure 350. Packing data in FIFO for transmission and reception . . . . .	925
Figure 351. Master full-duplex communication . . . . .	928
Figure 352. Slave full-duplex communication . . . . .	929
Figure 353. Master full-duplex communication with CRC . . . . .	930
Figure 354. Master full-duplex communication in packed mode . . . . .	931
Figure 355. NSSP pulse generation in Motorola SPI master mode . . . . .	934
Figure 356. TI mode transfer . . . . .	935
Figure 357. I2S block diagram . . . . .	938
Figure 358. I2S full-duplex block diagram . . . . .	939
Figure 359. I ²S Philips protocol waveforms (16/32-bit full accuracy). . . . .	941
Figure 360. I ²S Philips standard waveforms (24-bit frame) . . . . .	941
Figure 361. Transmitting 0x8EAA33 . . . . .	941
Figure 362. Receiving 0x8EAA33 . . . . .	942
Figure 363. I ²S Philips standard (16-bit extended to 32-bit packet frame) . . . . .	942
Figure 364. Example of 16-bit data frame extended to 32-bit channel frame . . . . .	942
Figure 365. MSB Justified 16-bit or 32-bit full-accuracy length . . . . .	943
Figure 366. MSB justified 24-bit frame length . . . . .	943
Figure 367. MSB justified 16-bit extended to 32-bit packet frame . . . . .	943
Figure 368. LSB justified 16-bit or 32-bit full-accuracy . . . . .	944
Figure 369. LSB justified 24-bit frame length . . . . .	944
Figure 370. Operations required to transmit 0x3478AE. . . . .	944
Figure 371. Operations required to receive 0x3478AE . . . . .	945
Figure 372. LSB justified 16-bit extended to 32-bit packet frame . . . . .	945
Figure 373. Example of 16-bit data frame extended to 32-bit channel frame . . . . .	945
Figure 374. PCM standard waveforms (16-bit) . . . . .	946
Figure 375. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . .	946
Figure 376. Start sequence in master mode . . . . .	947
Figure 377. Audio sampling frequency definition . . . . .	948
Figure 378. I ²S clock generator architecture . . . . .	948
Figure 379. CAN network topology . . . . .	969
Figure 380. Single-CAN block diagram . . . . .	970
Figure 381. bxCAN operating modes. . . . .	972
Figure 382. bxCAN in silent mode . . . . .	973
Figure 383. bxCAN in loop back mode . . . . .	973
Figure 384. bxCAN in combined mode . . . . .	974
Figure 385. Transmit mailbox states . . . . .	975
Figure 386. Receive FIFO states . . . . .	976
Figure 387. Filter bank scale configuration - Register organization. . . . .	979
Figure 388. Example of filter numbering . . . . .	980
Figure 389. Filtering mechanism example . . . . .	981
Figure 390. CAN error state diagram. . . . .	982
Figure 391. Bit timing . . . . .	984
Figure 392. CAN frames . . . . .	985
Figure 393. Event flags and interrupt generation. . . . .	986
Figure 394. CAN mailbox registers . . . . .	997
Figure 395. USB peripheral block diagram . . . . .	1011
Figure 396. Packet buffer areas with examples of buffer description table locations . . . . .	1016
Figure 397. Block diagram of STM32 MCU and Cortex-M4 ^®F-level debug support . . . . .	1043

Figure 398. SWJ debug port . . . . . 1045
Figure 399. JTAG TAP connections . . . . . 1049
Figure 400. TPIU block diagram . . . . . 1064

RM0365-STM32F302xB-C-D-E-302x6-8

Introduction

Contents

List of tables

List of figures

Chapters

RM0365-STM32F302xB-C-D-E-302x6-8

Introduction

Related documents

Contents

List of tables

List of figures

Chapters