RM0364-STM32F334

This reference manual targets application developers. It provides complete information on how to use the STM32F334xx microcontroller memory and peripherals.

The STM32F334xx is a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics refer to the STM32F334x4/x6/x8 datasheet.

For information on the Arm ^®Cortex ^®-M4 core with FPU, refer to the STM32 Cortex ^®-M4 MCUs and MPUs programming manual (PM0214).

Available from STMicroelectronics web site www.st.com :

• STM32F334x4/x6/x8 datasheet
• STM32 Cortex ^®-M4 MCUs and MPUs programming manual (PM0214)

1 Documentation conventions . . . . . 43
- 1.1 General information . . . . . 43
- 1.2 List of abbreviations for registers . . . . . 43
- 1.3 Glossary . . . . . 44
- 1.4 Availability of peripherals . . . . . 44
2 System and memory overview . . . . . 45
- 2.1 System architecture . . . . . 45
  - 2.1.1 S0: I-bus . . . . . 46
  - 2.1.2 S1: D-bus . . . . . 46
  - 2.1.3 S2: S-bus . . . . . 46
  - 2.1.4 S3: DMA-bus . . . . . 46
  - 2.1.5 BusMatrix . . . . . 46
- 2.2 Memory organization . . . . . 47
  - 2.2.1 Introduction . . . . . 47
  - 2.2.2 Memory map and register boundary addresses . . . . . 48
  - 2.2.3 Parity check . . . . . 51
  - 2.2.4 CCM SRAM write protection . . . . . 51
- 2.3 Embedded SRAM . . . . . 51
- 2.4 Flash memory overview . . . . . 52
- 2.5 Boot configuration . . . . . 52
  - 2.5.1 Embedded boot loader . . . . . 53
3 Embedded Flash memory . . . . . 54
- 3.1 Flash main features . . . . . 54
- 3.2 Flash memory functional description . . . . . 54
  - 3.2.1 Flash memory organization . . . . . 54
  - 3.2.2 Read operations . . . . . 55
  - 3.2.3 Flash program and erase operations . . . . . 57
- 3.3 Memory protection . . . . . 63
  - 3.3.1 Read protection . . . . . 63
  - 3.3.2 Write protection . . . . . 65
  - 3.3.3 Option byte block write protection . . . . . 65

3.4	Flash interrupts . . . . .	65
3.5	Flash register description . . . . .	66
3.5.1	Flash access control register (FLASH_ACR) . . . . .	66
3.5.2	Flash key register (FLASH_KEYR) . . . . .	66
3.5.3	Flash option key register (FLASH_OPTKEYR) . . . . .	67
3.5.4	Flash status register (FLASH_SR) . . . . .	67
3.5.5	Flash control register (FLASH_CR) . . . . .	68
3.5.6	Flash address register (FLASH_AR) . . . . .	69
3.5.7	Option byte register (FLASH_OBR) . . . . .	70
3.5.8	Write protection register (FLASH_WRP) . . . . .	71
3.6	Flash register map . . . . .	71
4	Option byte description . . . . .	73
5	Cyclic redundancy check calculation unit (CRC) . . . . .	76
5.1	Introduction . . . . .	76
5.2	CRC main features . . . . .	76
5.3	CRC functional description . . . . .	77
5.3.1	CRC block diagram . . . . .	77
5.3.2	CRC internal signals . . . . .	77
5.3.3	CRC operation . . . . .	77
5.4	CRC registers . . . . .	79
5.4.1	CRC data register (CRC_DR) . . . . .	79
5.4.2	CRC independent data register (CRC_IDR) . . . . .	79
5.4.3	CRC control register (CRC_CR) . . . . .	80
5.4.4	CRC initial value (CRC_INIT) . . . . .	80
5.4.5	CRC polynomial (CRC_POL) . . . . .	81
5.4.6	CRC register map . . . . .	81
6	Power control (PWR) . . . . .	82
6.1	Power supplies . . . . .	82
6.1.1	Independent A/D and D/A converter supply and reference voltage . . . . .	83
6.1.2	Battery Backup domain . . . . .	83
6.1.3	Voltage regulator . . . . .	84
6.2	Power supply supervisor . . . . .	84
6.2.1	Power on reset (POR)/power down reset (PDR) . . . . .	84

6.2.2	Programmable voltage detector (PVD) .....	85
6.3	Low-power modes .....	86
6.3.1	Slowing down system clocks .....	87
6.3.2	Peripheral clock gating .....	87
6.3.3	Sleep mode .....	87
6.3.4	Stop mode .....	88
6.3.5	Standby mode .....	90
6.3.6	Auto-wakeup from low-power mode .....	92
6.4	Power control registers .....	93
6.4.1	Power control register (PWR_CR) .....	93
6.4.2	Power control/status register (PWR_CSR) .....	94
6.4.3	PWR register map .....	95
7	Peripheral interconnect matrix .....	96
7.1	Introduction .....	96
7.2	Connection summary .....	96
7.3	Interconnection details .....	97
7.3.1	DMA interconnections .....	97
7.3.2	From ADC to ADC .....	97
7.3.3	From ADC to TIM .....	97
7.3.4	From TIM and EXTI to ADC .....	98
7.3.5	From OPAMP to ADC .....	98
7.3.6	From TS to ADC .....	98
7.3.7	From VBAT to ADC .....	98
7.3.8	From VREFINT to ADC .....	98
7.3.9	From COMP to TIM .....	98
7.3.10	From TIM to COMP .....	99
7.3.11	From DAC to COMP .....	100
7.3.12	From VREFINT to COMP .....	100
7.3.13	From TIM to OPAMP .....	100
7.3.14	From TIM to TIM .....	100
7.3.15	From system errors to TIM .....	101
7.3.16	From HSE, HSI, LSE, LSI, MCO, RTC to TIM .....	101
7.3.17	From TIM and EXTI to DAC .....	102
7.3.18	From TIM to IRTIM .....	102
7.3.19	From ADC to HRTIM1 .....	102
7.3.20	From system faults to HRTIM1 .....	102

7.3.21	From COMP to HRTIM1 .....	102
7.3.22	From OPAMP to HRTIM1 .....	103
7.3.23	From TIM to HRTIM1 .....	103
7.3.24	From HRTIM1 to ADC .....	103
7.3.25	From HRTIM1 to DAC .....	103
8	Reset and clock control (RCC) .....	104
8.1	Reset .....	104
8.1.1	Power reset .....	104
8.1.2	System reset .....	104
8.1.3	RTC domain reset .....	105
8.2	Clocks .....	106
8.2.1	HSE clock .....	108
8.2.2	HSI clock .....	109
8.2.3	PLL .....	110
8.2.4	LSE clock .....	110
8.2.5	LSI clock .....	111
8.2.6	System clock (SYSCLK) selection .....	111
8.2.7	Clock security system (CSS) .....	111
8.2.8	ADC clock .....	112
8.2.9	RTC clock .....	112
8.2.10	Timers (TIMx) clock .....	112
8.2.11	High-resolution timer (HRTIM) clock .....	113
8.2.12	Watchdog clock .....	113
8.2.13	Clock-out capability .....	113
8.2.14	Internal/external clock measurement with TIM16 .....	114
8.3	Low-power modes .....	115
8.4	RCC registers .....	116
8.4.1	Clock control register (RCC_CR) .....	116
8.4.2	Clock configuration register (RCC_CFGR) .....	118
8.4.3	Clock interrupt register (RCC_CIR) .....	120
8.4.4	APB2 peripheral reset register (RCC_APB2RSTR) .....	123
8.4.5	APB1 peripheral reset register (RCC_APB1RSTR) .....	124
8.4.6	AHB peripheral clock enable register (RCC_AHBENR) .....	126
8.4.7	APB2 peripheral clock enable register (RCC_APB2ENR) .....	127
8.4.8	APB1 peripheral clock enable register (RCC_APB1ENR) .....	129
8.4.9	RTC domain control register (RCC_BDCR) .....	131

8.4.10	Control/status register (RCC_CSR) . . . . .	132
8.4.11	AHB peripheral reset register (RCC_AHBRSTR) . . . . .	134
8.4.12	Clock configuration register 2 (RCC_CFGR2) . . . . .	135
8.4.13	Clock configuration register 3 (RCC_CFGR3) . . . . .	136
8.4.14	RCC register map . . . . .	137
9	General-purpose I/Os (GPIO) . . . . .	139
9.1	Introduction . . . . .	139
9.2	GPIO main features . . . . .	139
9.3	GPIO functional description . . . . .	139
9.3.1	General-purpose I/O (GPIO) . . . . .	142
9.3.2	I/O pin alternate function multiplexer and mapping . . . . .	142
9.3.3	I/O port control registers . . . . .	143
9.3.4	I/O port data registers . . . . .	143
9.3.5	I/O data bitwise handling . . . . .	143
9.3.6	GPIO locking mechanism . . . . .	144
9.3.7	I/O alternate function input/output . . . . .	144
9.3.8	External interrupt/wakeup lines . . . . .	144
9.3.9	Input configuration . . . . .	144
9.3.10	Output configuration . . . . .	145
9.3.11	Alternate function configuration . . . . .	146
9.3.12	Analog configuration . . . . .	147
9.3.13	Using the HSE or LSE oscillator pins as GPIOs . . . . .	148
9.3.14	Using the GPIO pins in the RTC supply domain . . . . .	148
9.4	GPIO registers . . . . .	148
9.4.1	GPIO port mode register (GPIOx_MODER) (x =A to D and F) . . . . .	148
9.4.2	GPIO port output type register (GPIOx_OTYPER) (x = A to D and F) . . . . .	149
9.4.3	GPIO port output speed register (GPIOx_OSPEEDR) (x = A to D and F) . . . . .	149
9.4.4	GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to D and F) . . . . .	150
9.4.5	GPIO port input data register (GPIOx_IDR) (x = A to D and F) . . . . .	150
9.4.6	GPIO port output data register (GPIOx_ODR) (x = A to D and F) . . . . .	151
9.4.7	GPIO port bit set/reset register (GPIOx_BSRR) (x = A to D and F) . . . . .	151

9.4.8	GPIO port configuration lock register (GPIOx_LCKR) (x = A to E and F) . . . . .	151
9.4.9	GPIO alternate function low register (GPIOx_AFRL) (x = A to D and F) . . . . .	153
9.4.10	GPIO alternate function high register (GPIOx_AFRH) (x = A to D and F) . . . . .	153
9.4.11	GPIO port bit reset register (GPIOx_BRR) (x = A to D and F) . . . . .	154
9.4.12	GPIO register map . . . . .	155
10	System configuration controller (SYSCFG) . . . . .	157
10.1	SYSCFG registers . . . . .	157
10.1.1	SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .	157
10.1.2	SYSCFG CCM SRAM protection register (SYSCFG_RCR) . . . . .	159
10.1.3	SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . .	160
10.1.4	SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) . . . . .	161
10.1.5	SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) . . . . .	163
10.1.6	SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) . . . . .	164
10.1.7	SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .	165
10.1.8	SYSCFG configuration register 3 (SYSCFG_CFGR3) . . . . .	167
10.1.9	SYSCFG register map . . . . .	168
11	Direct memory access controller (DMA) . . . . .	170
11.1	Introduction . . . . .	170
11.2	DMA main features . . . . .	170
11.3	DMA implementation . . . . .	171
11.3.1	DMA . . . . .	171
11.3.2	DMA request mapping . . . . .	171
11.4	DMA functional description . . . . .	173
11.4.1	DMA block diagram . . . . .	173
11.4.2	DMA transfers . . . . .	174
11.4.3	DMA arbitration . . . . .	175
11.4.4	DMA channels . . . . .	176
11.4.5	DMA data width, alignment and endianness . . . . .	180
11.4.6	DMA error management . . . . .	181
11.5	DMA interrupts . . . . .	182

11.6	DMA registers . . . . .	182
11.6.1	DMA interrupt status register (DMA_ISR) . . . . .	182
11.6.2	DMA interrupt flag clear register (DMA_IFCR) . . . . .	185
11.6.3	DMA channel x configuration register (DMA_CCRx) . . . . .	186
11.6.4	DMA channel x number of data to transfer register (DMA_CNDTRx) . . . . .	189
11.6.5	DMA channel x peripheral address register (DMA_CPARx) . . . . .	189
11.6.6	DMA channel x memory address register (DMA_CMARx) . . . . .	190
11.6.7	DMA register map . . . . .	190
12	Interrupts and events . . . . .	193
12.1	Nested vectored interrupt controller (NVIC) . . . . .	193
12.1.1	NVIC main features . . . . .	193
12.1.2	SysTick calibration value register . . . . .	193
12.1.3	Interrupt and exception vectors . . . . .	193
12.2	Extended interrupts and events controller (EXTI) . . . . .	196
12.2.1	Main features . . . . .	197
12.2.2	Block diagram . . . . .	197
12.2.3	Wakeup event management . . . . .	198
12.2.4	Asynchronous Internal Interrupts . . . . .	198
12.2.5	Functional description . . . . .	198
12.2.6	External and internal interrupt/event line mapping . . . . .	200
12.3	EXTI registers . . . . .	201
12.3.1	Interrupt mask register (EXTI_IMR1) . . . . .	201
12.3.2	Event mask register (EXTI_EMR1) . . . . .	202
12.3.3	Rising trigger selection register (EXTI_RTSR1) . . . . .	202
12.3.4	Falling trigger selection register (EXTI_FTSR1) . . . . .	203
12.3.5	Software interrupt event register (EXTI_SWIER1) . . . . .	204
12.3.6	Pending register (EXTI_PR1) . . . . .	205
12.3.7	Interrupt mask register (EXTI_IMR2) . . . . .	206
12.3.8	Event mask register (EXTI_EMR2) . . . . .	206
12.3.9	Rising trigger selection register (EXTI_RTSR2) . . . . .	206
12.3.10	Falling trigger selection register (EXTI_FTSR2) . . . . .	207
12.3.11	Software interrupt event register (EXTI_SWIER2) . . . . .	207
12.3.12	Pending register (EXTI_PR2) . . . . .	208
12.3.13	EXTI register map . . . . .	208
13	Analog-to-digital converters (ADC) . . . . .	211

13.1	Introduction .....	211
13.2	ADC main features .....	212
13.3	ADC functional description .....	214
13.3.1	ADC block diagram .....	214
13.3.2	Pins and internal signals .....	215
13.3.3	Clocks .....	215
13.3.4	ADC1/2 connectivity .....	218
13.3.5	Slave AHB interface .....	219
13.3.6	ADC voltage regulator (ADVREGEN) .....	219
13.3.7	Single-ended and differential input channels .....	219
13.3.8	Calibration (ADCAL, ADCALDIF, ADCx_CALFACT) .....	220
13.3.9	ADC on-off control (ADEN, ADDIS, ADRDY) .....	223
13.3.10	Constraints when writing the ADC control bits .....	224
13.3.11	Channel selection (SQRx, JSQRx) .....	224
13.3.12	Channel-wise programmable sampling time (SMPR1, SMPR2) .....	225
13.3.13	Single conversion mode (CONT=0) .....	226
13.3.14	Continuous conversion mode (CONT=1) .....	226
13.3.15	Starting conversions (ADSTART, JADSTART) .....	227
13.3.16	Timing .....	228
13.3.17	Stopping an ongoing conversion (ADSTP, JADSTP) .....	228
13.3.18	Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) .....	230
13.3.19	Injected channel management .....	233
13.3.20	Discontinuous mode (DISCEN, DISCNUM, JDISCEN) .....	234
13.3.21	Queue of context for injected conversions .....	235
13.3.22	Programmable resolution (RES) - fast conversion mode .....	244
13.3.23	End of conversion, end of sampling phase (EOC, JEOC, EOSMP) ..	244
13.3.24	End of conversion sequence (EOS, JEOS) .....	245
13.3.25	Timing diagrams example (single/continuous modes, hardware/software triggers) .....	245
13.3.26	Data management .....	246
13.3.27	Dynamic low-power features .....	252
13.3.28	Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) .....	257
13.3.29	Dual ADC modes .....	261
13.3.30	Temperature sensor .....	274
13.3.31	VBAT supply monitoring .....	276
13.3.32	Monitoring the internal voltage reference .....	277

13.4	ADC interrupts .....	279
13.5	ADC registers (for each ADC) .....	280
13.5.1	ADC interrupt and status register (ADCx_ISR, x=1..2) .....	280
13.5.2	ADC interrupt enable register (ADCx_IER, x=1..2) .....	282
13.5.3	ADC control register (ADCx_CR, x=1..2) .....	284
13.5.4	ADC configuration register (ADCx_CFGR, x=1..2) .....	287
13.5.5	ADC sample time register 1 (ADCx_SMPR1, x=1..2) .....	291
13.5.6	ADC sample time register 2 (ADCx_SMPR2, x=1..2) .....	293
13.5.7	ADC watchdog threshold register 1 (ADCx_TR1, x=1..2) .....	293
13.5.8	ADC watchdog threshold register 2 (ADCx_TR2, x = 1..2) .....	294
13.5.9	ADC watchdog threshold register 3 (ADCx_TR3, x=1..2) .....	295
13.5.10	ADC regular sequence register 1 (ADCx_SQR1, x=1..2) .....	296
13.5.11	ADC regular sequence register 2 (ADCx_SQR2, x=1..2) .....	297
13.5.12	ADC regular sequence register 3 (ADCx_SQR3, x=1..2) .....	299
13.5.13	ADC regular sequence register 4 (ADCx_SQR4, x=1..2) .....	300
13.5.14	ADC regular Data Register (ADCx_DR, x=1..2) .....	301
13.5.15	ADC injected sequence register (ADCx_JSQR, x=1..2) .....	302
13.5.16	ADC offset register (ADCx_OF Ry, x=1..2) (y=1..4) .....	304
13.5.17	ADC injected data register (ADCx_JDRy, x=1..2, y= 1..4) .....	305
13.5.18	ADC Analog Watchdog 2 Configuration Register (ADCx_AWD2CR, x=1..2) .....	305
13.5.19	ADC Analog Watchdog 3 Configuration Register (ADCx_AWD3CR, x=1..2) .....	306
13.5.20	ADC Differential Mode Selection Register (ADCx_DIFSEL, x=1..2) ..	306
13.5.21	ADC Calibration Factors (ADCx_CALFACT, x=1..2) .....	307
13.6	ADC common registers .....	308
13.6.1	ADC Common status register (ADCx_CSR, x=12) .....	308
13.6.2	ADC common control register (ADCx_CCR, x=12) .....	310
13.6.3	ADC common regular data register for dual mode (ADCx_CDR, x=12) .....	313
13.7	ADC register map .....	313
14	Digital-to-analog converter (DAC1 and DAC2) .....	317
14.1	Introduction .....	317
14.2	DAC1/2 main features .....	317
14.3	DAC output buffer enable/DAC output switch .....	319
14.4	DAC channel enable .....	320

14.5	Single mode functional description . . . . .	320
14.5.1	DAC data format . . . . .	320
14.5.2	DAC channel conversion . . . . .	320
14.5.3	DAC output voltage . . . . .	322
14.5.4	DAC trigger selection . . . . .	322
14.6	Dual-mode functional description . . . . .	323
14.6.1	DAC data format . . . . .	323
14.6.2	DAC channel conversion in dual mode . . . . .	324
14.6.3	Description of dual conversion modes . . . . .	324
14.6.4	DAC output voltage . . . . .	327
14.6.5	DAC trigger selection . . . . .	328
14.7	Noise generation . . . . .	328
14.8	Triangle-wave generation . . . . .	329
14.9	DMA request . . . . .	330
14.10	DAC registers . . . . .	331
14.10.1	DAC control register (DAC_CR) . . . . .	331
14.10.2	DAC software trigger register (DAC_SWTRIGR) . . . . .	335
14.10.3	DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) . . . . .	335
14.10.4	DAC channel1 12-bit left-aligned data holding register (DAC_DHR12L1) . . . . .	336
14.10.5	DAC channel1 8-bit right-aligned data holding register (DAC_DHR8R1) . . . . .	336
14.10.6	DAC channel2 12-bit right-aligned data holding register (DAC_DHR12R2) . . . . .	336
14.10.7	DAC channel2 12-bit left-aligned data holding register (DAC_DHR12L2) . . . . .	337
14.10.8	DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) . . . . .	337
14.10.9	Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) . . . . .	338
14.10.10	Dual DAC 12-bit left-aligned data holding register (DAC_DHR12LD) . . . . .	338
14.10.11	Dual DAC 8-bit right-aligned data holding register (DAC_DHR8RD) . . . . .	338
14.10.12	DAC channel1 data output register (DAC_DOR1) . . . . .	339
14.10.13	DAC channel2 data output register (DAC_DOR2) . . . . .	339
14.10.14	DAC status register (DAC_SR) . . . . .	339
14.10.15	DAC register map . . . . .	341

15 Comparator (COMP) . . . . . 343

15.1 Introduction . . . . . 343

15.2 COMP main features . . . . . 343

15.3 COMP functional description . . . . . 344

15.3.1 COMP block diagram . . . . . 344

15.3.2 COMP pins and internal signals . . . . . 344

15.3.3 COMP reset and clocks . . . . . 345

15.3.4 Comparator LOCK mechanism . . . . . 345

15.3.5 Comparator output blanking function . . . . . 346

15.4 COMP interrupts . . . . . 347

15.5 COMP registers . . . . . 347

15.5.1 COMP2 control and status register (COMP2_CSR) . . . . . 347

15.5.2 COMP4 control and status register (COMP4_CSR) . . . . . 348

15.5.3 COMP6 control and status register (COMP6_CSR) . . . . . 350

15.5.4 COMP register map . . . . . 352

16 Operational amplifier (OPAMP) . . . . . 353

16.1 OPAMP introduction . . . . . 353

16.2 OPAMP main features . . . . . 353

16.3 OPAMP functional description . . . . . 353

16.3.1 General description . . . . . 353

16.3.2 Clock . . . . . 353

16.3.3 Operational amplifiers and comparators interconnections . . . . . 354

16.3.4 Using the OPAMP outputs as ADC inputs . . . . . 354

16.3.5 Calibration . . . . . 354

16.3.6 Timer controlled Multiplexer mode . . . . . 355

16.3.7 OPAMP modes . . . . . 356

16.4 OPAMP registers . . . . . 360

16.4.1 OPAMP2 control register (OPAMP2_CSR) . . . . . 360

16.4.2 OPAMP register map . . . . . 363

17 Touch sensing controller (TSC) . . . . . 364

17.1 Introduction . . . . . 364

17.2 TSC main features . . . . . 364

17.3 TSC functional description . . . . . 365

17.3.1 TSC block diagram . . . . . 365

17.3.2	Surface charge transfer acquisition overview . . . . .	365
17.3.3	Reset and clocks . . . . .	367
17.3.4	Charge transfer acquisition sequence . . . . .	368
17.3.5	Spread spectrum feature . . . . .	369
17.3.6	Max count error . . . . .	369
17.3.7	Sampling capacitor I/O and channel I/O mode selection . . . . .	370
17.3.8	Acquisition mode . . . . .	371
17.3.9	I/O hysteresis and analog switch control . . . . .	371
17.4	TSC low-power modes . . . . .	372
17.5	TSC interrupts . . . . .	372
17.6	TSC registers . . . . .	373
17.6.1	TSC control register (TSC_CR) . . . . .	373
17.6.2	TSC interrupt enable register (TSC_IER) . . . . .	375
17.6.3	TSC interrupt clear register (TSC_ICR) . . . . .	376
17.6.4	TSC interrupt status register (TSC_ISR) . . . . .	377
17.6.5	TSC I/O hysteresis control register (TSC_IOHCR) . . . . .	377
17.6.6	TSC I/O analog switch control register (TSC_IOASCR) . . . . .	378
17.6.7	TSC I/O sampling control register (TSC_IOSCR) . . . . .	378
17.6.8	TSC I/O channel control register (TSC_IOCCR) . . . . .	379
17.6.9	TSC I/O group control status register (TSC_IOGCSR) . . . . .	379
17.6.10	TSC I/O group x counter register (TSC_IOGxCR) . . . . .	380
17.6.11	TSC register map . . . . .	381
18	Advanced-control timer (TIM1) . . . . .	383
18.1	TIM1 introduction . . . . .	383
18.2	TIM1 main features . . . . .	384
18.3	TIM1 functional description . . . . .	387
18.3.1	Time-base unit . . . . .	387
18.3.2	Counter modes . . . . .	389
18.3.3	Repetition counter . . . . .	400
18.3.4	External trigger input . . . . .	402
18.3.5	Clock selection . . . . .	403
18.3.6	Capture/compare channels . . . . .	407
18.3.7	Input capture mode . . . . .	410
18.3.8	PWM input mode . . . . .	411
18.3.9	Forced output mode . . . . .	411

18.3.10	Output compare mode . . . . .	412
18.3.11	PWM mode . . . . .	413
18.3.12	Asymmetric PWM mode . . . . .	416
18.3.13	Combined PWM mode . . . . .	417
18.3.14	Combined 3-phase PWM mode . . . . .	418
18.3.15	Complementary outputs and dead-time insertion . . . . .	419
18.3.16	Using the break function . . . . .	421
18.3.17	Clearing the OCxREF signal on an external event . . . . .	426
18.3.18	6-step PWM generation . . . . .	428
18.3.19	One-pulse mode . . . . .	429
18.3.20	Retriggerable one pulse mode . . . . .	430
18.3.21	Encoder interface mode . . . . .	431
18.3.22	UIF bit remapping . . . . .	433
18.3.23	Timer input XOR function . . . . .	434
18.3.24	Interfacing with Hall sensors . . . . .	434
18.3.25	Timer synchronization . . . . .	437
18.3.26	ADC synchronization . . . . .	441
18.3.27	DMA burst mode . . . . .	441
18.3.28	Debug mode . . . . .	442
18.4	TIM1 registers . . . . .	443
18.4.1	TIM1 control register 1 (TIM1_CR1) . . . . .	443
18.4.2	TIM1 control register 2 (TIM1_CR2) . . . . .	444
18.4.3	TIM1 slave mode control register (TIM1_SMCR) . . . . .	447
18.4.4	TIM1 DMA/interrupt enable register (TIM1_DIER) . . . . .	449
18.4.5	TIM1 status register (TIM1_SR) . . . . .	451
18.4.6	TIM1 event generation register (TIM1_EGR) . . . . .	453
18.4.7	TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) . . . . .	454
18.4.8	TIM1 capture/compare mode register 1 [alternate] (TIM1_CCMR1) . . . . .	455
18.4.9	TIM1 capture/compare mode register 2 [alternate] (TIM1_CCMR2) . . . . .	458
18.4.10	TIM1 capture/compare mode register 2 [alternate] (TIM1_CCMR2) . . . . .	459
18.4.11	TIM1 capture/compare enable register (TIM1_CCER) . . . . .	461
18.4.12	TIM1 counter (TIM1_CNT) . . . . .	464
18.4.13	TIM1 prescaler (TIM1_PSC) . . . . .	464

18.4.14	TIM1 auto-reload register (TIM1_ARR) . . . . .	464
18.4.15	TIM1 repetition counter register (TIM1_RCR) . . . . .	465
18.4.16	TIM1 capture/compare register 1 (TIM1_CCR1) . . . . .	465
18.4.17	TIM1 capture/compare register 2 (TIM1_CCR2) . . . . .	466
18.4.18	TIM1 capture/compare register 3 (TIM1_CCR3) . . . . .	466
18.4.19	TIM1 capture/compare register 4 (TIM1_CCR4) . . . . .	467
18.4.20	TIM1 break and dead-time register (TIM1_BDTR) . . . . .	467
18.4.21	TIM1 DMA control register (TIM1_DCR) . . . . .	470
18.4.22	TIM1 DMA address for full transfer (TIM1_DMAR) . . . . .	471
18.4.23	TIM1 option registers (TIM1_OR) . . . . .	472
18.4.24	TIM1 capture/compare mode register 3 (TIM1_CCMR3) . . . . .	472
18.4.25	TIM1 capture/compare register 5 (TIM1_CCR5) . . . . .	473
18.4.26	TIM1 capture/compare register 6 (TIM1_CCR6) . . . . .	474
18.4.27	TIM1 register map . . . . .	475
19	General-purpose timers (TIM2/TIM3) . . . . .	478
19.1	TIM2/TIM3 introduction . . . . .	478
19.2	TIM2/TIM3 main features . . . . .	478
19.3	TIM2/TIM3 functional description . . . . .	480
19.3.1	Time-base unit . . . . .	480
19.3.2	Counter modes . . . . .	482
19.3.3	Clock selection . . . . .	492
19.3.4	Capture/Compare channels . . . . .	496
19.3.5	Input capture mode . . . . .	498
19.3.6	PWM input mode . . . . .	499
19.3.7	Forced output mode . . . . .	500
19.3.8	Output compare mode . . . . .	501
19.3.9	PWM mode . . . . .	502
19.3.10	Asymmetric PWM mode . . . . .	505
19.3.11	Combined PWM mode . . . . .	506
19.3.12	Clearing the OCxREF signal on an external event . . . . .	507
19.3.13	One-pulse mode . . . . .	509
19.3.14	Retriggerable one pulse mode . . . . .	510
19.3.15	Encoder interface mode . . . . .	511
19.3.16	UIF bit remapping . . . . .	513

19.3.17	Timer input XOR function . . . . .	513
19.3.18	Timers and external trigger synchronization . . . . .	514
19.3.19	Timer synchronization . . . . .	517
19.3.20	DMA burst mode . . . . .	522
19.3.21	Debug mode . . . . .	523
19.4	TIM2/TIM3 registers . . . . .	524
19.4.1	TIMx control register 1 (TIMx_CR1)(x = 2 to 3) . . . . .	524
19.4.2	TIMx control register 2 (TIMx_CR2)(x = 2 to 3) . . . . .	525
19.4.3	TIMx slave mode control register (TIMx_SMCR)(x = 2 to 3) . . . . .	527
19.4.4	TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 3) . . . . .	530
19.4.5	TIMx status register (TIMx_SR)(x = 2 to 3) . . . . .	531
19.4.6	TIMx event generation register (TIMx_EGR)(x = 2 to 3) . . . . .	532
19.4.7	TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 3) . . . . .	533
19.4.8	TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 3) . . . . .	535
19.4.9	TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2) (x = 2 to 3) . . . . .	537
19.4.10	TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2) (x = 2 to 3) . . . . .	538
19.4.11	TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 3) . . . . .	539
19.4.12	TIMx counter [alternate] (TIMx_CNT)(x = 2 to 3) . . . . .	540
19.4.13	TIMx counter [alternate] (TIMx_CNT)(x = 2 to 3) . . . . .	541
19.4.14	TIMx prescaler (TIMx_PSC)(x = 2 to 3) . . . . .	541
19.4.15	TIMx auto-reload register (TIMx_ARR)(x = 2 to 3) . . . . .	542
19.4.16	TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 3) . . . . .	542
19.4.17	TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 3) . . . . .	543
19.4.18	TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 3) . . . . .	543
19.4.19	TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 3) . . . . .	544
19.4.20	TIMx DMA control register (TIMx_DCR)(x = 2 to 3) . . . . .	545
19.4.21	TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 3) . . . . .	545
19.4.22	TIMx register map . . . . .	546
20	General-purpose timers (TIM15/TIM16/TIM17) . . . . .	548
20.1	TIM15/TIM16/TIM17 introduction . . . . .	548
20.2	TIM15 main features . . . . .	548
20.3	TIM16/TIM17 main features . . . . .	549

20.4	TIM15/TIM16/TIM17 functional description . . . . .	552
20.4.1	Time-base unit . . . . .	552
20.4.2	Counter modes . . . . .	554
20.4.3	Repetition counter . . . . .	558
20.4.4	Clock selection . . . . .	559
20.4.5	Capture/compare channels . . . . .	561
20.4.6	Input capture mode . . . . .	564
20.4.7	PWM input mode (only for TIM15) . . . . .	565
20.4.8	Forced output mode . . . . .	566
20.4.9	Output compare mode . . . . .	566
20.4.10	PWM mode . . . . .	567
20.4.11	Combined PWM mode (TIM15 only) . . . . .	568
20.4.12	Complementary outputs and dead-time insertion . . . . .	570
20.4.13	Using the break function . . . . .	572
20.4.14	One-pulse mode . . . . .	575
20.4.15	Retriggerable one pulse mode (TIM15 only) . . . . .	577
20.4.16	UIF bit remapping . . . . .	577
20.4.17	Timer input XOR function (TIM15 only) . . . . .	579
20.4.18	External trigger synchronization (TIM15 only) . . . . .	580
20.4.19	Slave mode – combined reset + trigger mode (TIM15 only) . . . . .	582
20.4.20	DMA burst mode . . . . .	582
20.4.21	Timer synchronization (TIM15) . . . . .	584
20.4.22	Using timer output as trigger for other timers (TIM16/TIM17) . . . . .	584
20.4.23	Debug mode . . . . .	584
20.5	TIM15 registers . . . . .	585
20.5.1	TIM15 control register 1 (TIM15_CR1) . . . . .	585
20.5.2	TIM15 control register 2 (TIM15_CR2) . . . . .	586
20.5.3	TIM15 slave mode control register (TIM15_SMCR) . . . . .	588
20.5.4	TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .	589
20.5.5	TIM15 status register (TIM15_SR) . . . . .	590
20.5.6	TIM15 event generation register (TIM15_EGR) . . . . .	592
20.5.7	TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) . . . . .	593
20.5.8	TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) . . . . .	594
20.5.9	TIM15 capture/compare enable register (TIM15_CCER) . . . . .	597
20.5.10	TIM15 counter (TIM15_CNT) . . . . .	600

20.5.11	TIM15 prescaler (TIM15_PSC) .....	600
20.5.12	TIM15 auto-reload register (TIM15_ARR) .....	600
20.5.13	TIM15 repetition counter register (TIM15_RCR) .....	601
20.5.14	TIM15 capture/compare register 1 (TIM15_CCR1) .....	601
20.5.15	TIM15 capture/compare register 2 (TIM15_CCR2) .....	602
20.5.16	TIM15 break and dead-time register (TIM15_BDTR) .....	602
20.5.17	TIM15 DMA control register (TIM15_DCR) .....	604
20.5.18	TIM15 DMA address for full transfer (TIM15_DMAR) .....	605
20.5.19	TIM15 register map .....	605
20.6	TIM16/TIM17 registers .....	608
20.6.1	TIMx control register 1 (TIMx_CR1)(x = 16 to 17) .....	608
20.6.2	TIMx control register 2 (TIMx_CR2)(x = 16 to 17) .....	609
20.6.3	TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) .....	610
20.6.4	TIMx status register (TIMx_SR)(x = 16 to 17) .....	611
20.6.5	TIMx event generation register (TIMx_EGR)(x = 16 to 17) .....	612
20.6.6	TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 16 to 17) .....	613
20.6.7	TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 16 to 17) .....	614
20.6.8	TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) ..	616
20.6.9	TIMx counter (TIMx_CNT)(x = 16 to 17) .....	618
20.6.10	TIMx prescaler (TIMx_PSC)(x = 16 to 17) .....	619
20.6.11	TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) .....	619
20.6.12	TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) .....	620
20.6.13	TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) .....	620
20.6.14	TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) .....	621
20.6.15	TIMx DMA control register (TIMx_DCR)(x = 16 to 17) .....	623
20.6.16	TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) .....	623
20.6.17	TIM16 option register (TIM16_OR) .....	624
20.6.18	TIM16/TIM17 register map .....	625
21	High-Resolution Timer (HRTIM) .....	627
21.1	Introduction .....	627
21.2	Main features .....	628
21.3	Functional description .....	629
21.3.1	General description .....	629
21.3.2	HRTIM pins and internal signals .....	630

21.3.3	Clocks .....	632
21.3.4	Timer A..E timing units .....	635
21.3.5	Master timer .....	653
21.3.6	Set/reset events priorities and narrow pulses management .....	654
21.3.7	External events global conditioning .....	657
21.3.8	External event filtering in timing units .....	661
21.3.9	Delayed Protection .....	666
21.3.10	Register preload and update management .....	672
21.3.11	Events propagation within or across multiple timers .....	675
21.3.12	Output management .....	679
21.3.13	Burst mode controller .....	681
21.3.14	Chopper .....	690
21.3.15	Fault protection .....	691
21.3.16	Auxiliary outputs .....	694
21.3.17	Synchronizing the HRTIM with other timers or HRTIM instances .....	697
21.3.18	ADC triggers .....	700
21.3.19	DAC triggers .....	701
21.3.20	HRTIM Interrupts .....	703
21.3.21	DMA .....	705
21.3.22	HRTIM initialization .....	709
21.3.23	Debug .....	710
21.4	Application use cases .....	711
21.4.1	Buck converter .....	711
21.4.2	Buck converter with synchronous rectification .....	712
21.4.3	Multiphase converters .....	712
21.4.4	Transition mode Power Factor Correction .....	714
21.5	HRTIM registers .....	716
21.5.1	HRTIM Master Timer Control Register (HRTIM_MCR) .....	716
21.5.2	HRTIM Master Timer Interrupt Status Register (HRTIM_MISR) .....	719
21.5.3	HRTIM Master Timer Interrupt Clear Register (HRTIM_MICR) .....	720
21.5.4	HRTIM Master Timer DMA / Interrupt Enable Register (HRTIM_MDIER) .....	721
21.5.5	HRTIM Master Timer Counter Register (HRTIM_MCNTR) .....	723
21.5.6	HRTIM Master Timer Period Register (HRTIM_MPER) .....	723
21.5.7	HRTIM Master Timer Repetition Register (HRTIM_MREP) .....	724
21.5.8	HRTIM Master Timer Compare 1 Register (HRTIM_MCMP1R) .....	724
21.5.9	HRTIM Master Timer Compare 2 Register (HRTIM_MCMP2R) .....	725

21.5.10	HRTIM Master Timer Compare 3 Register (HRTIM_MCMP3R) . . . . .	725
21.5.11	HRTIM Master Timer Compare 4 Register (HRTIM_MCMP4R) . . . . .	726
21.5.12	HRTIM Timerx Control Register (HRTIM_TIMxCR) . . . . .	727
21.5.13	HRTIM Timerx Interrupt Status Register (HRTIM_TIMxISR) . . . . .	731
21.5.14	HRTIM Timerx Interrupt Clear Register (HRTIM_TIMxICR) . . . . .	733
21.5.15	HRTIM Timerx DMA / Interrupt Enable Register (HRTIM_TIMxDIER) . . . . .	734
21.5.16	HRTIM Timerx Counter Register (HRTIM_CNTxR) . . . . .	737
21.5.17	HRTIM Timerx Period Register (HRTIM_PERxR) . . . . .	737
21.5.18	HRTIM Timerx Repetition Register (HRTIM_REPxR) . . . . .	738
21.5.19	HRTIM Timerx Compare 1 Register (HRTIM_CMP1xR) . . . . .	738
21.5.20	HRTIM Timerx Compare 1 Compound Register (HRTIM_CMP1CxR) . . . . .	739
21.5.21	HRTIM Timerx Compare 2 Register (HRTIM_CMP2xR) . . . . .	739
21.5.22	HRTIM Timerx Compare 3 Register (HRTIM_CMP3xR) . . . . .	740
21.5.23	HRTIM Timerx Compare 4 Register (HRTIM_CMP4xR) . . . . .	740
21.5.24	HRTIM Timerx Capture 1 Register (HRTIM_CPT1xR) . . . . .	741
21.5.25	HRTIM Timerx Capture 2 Register (HRTIM_CPT2xR) . . . . .	741
21.5.26	HRTIM Timerx Deadtime Register (HRTIM_DTxR) . . . . .	742
21.5.27	HRTIM Timerx Output1 Set Register (HRTIM_SETx1R) . . . . .	744
21.5.28	HRTIM Timerx Output1 Reset Register (HRTIM_RSTx1R) . . . . .	746
21.5.29	HRTIM Timerx Output2 Set Register (HRTIM_SETx2R) . . . . .	746
21.5.30	HRTIM Timerx Output2 Reset Register (HRTIM_RSTx2R) . . . . .	747
21.5.31	HRTIM Timerx External Event Filtering Register 1 (HRTIM_EEFxR1) . . . . .	748
21.5.32	HRTIM Timerx External Event Filtering Register 2 (HRTIM_EEFxR2) . . . . .	750
21.5.33	HRTIM Timerx Reset Register (HRTIM_RSTxR) . . . . .	751
21.5.34	HRTIM Timerx Chopper Register (HRTIM_CHPxR) . . . . .	754
21.5.35	HRTIM Timerx Capture 1 Control Register (HRTIM_CPT1xCR) . . . . .	756
21.5.36	HRTIM Timerx Capture 2 Control Register (HRTIM_CPT2xCR) . . . . .	757
21.5.37	HRTIM Timerx Output Register (HRTIM_OUTxR) . . . . .	760
21.5.38	HRTIM Timerx Fault Register (HRTIM_FLTxR) . . . . .	763
21.5.39	HRTIM Control Register 1 (HRTIM_CR1) . . . . .	764
21.5.40	HRTIM Control Register 2 (HRTIM_CR2) . . . . .	766
21.5.41	HRTIM Interrupt Status Register (HRTIM_ISR) . . . . .	767
21.5.42	HRTIM Interrupt Clear Register (HRTIM_ICR) . . . . .	768
21.5.43	HRTIM Interrupt Enable Register (HRTIM_IER) . . . . .	769

21.5.44	HRTIM Output Enable Register (HRTIM_OENR) .....	770
21.5.45	HRTIM Output Disable Register (HRTIM_ODISR) .....	771
21.5.46	HRTIM Output Disable Status Register (HRTIM_ODSR) .....	772
21.5.47	HRTIM Burst Mode Control Register (HRTIM_BMCR) .....	773
21.5.48	HRTIM Burst Mode Trigger Register (HRTIM_BMTRGR) .....	775
21.5.49	HRTIM Burst Mode Compare Register (HRTIM_BMCMPR) .....	777
21.5.50	HRTIM Burst Mode Period Register (HRTIM_BMPER) .....	777
21.5.51	HRTIM Timer External Event Control Register 1 (HRTIM_EECR1) ..	778
21.5.52	HRTIM Timer External Event Control Register 2 (HRTIM_EECR2) ..	780
21.5.53	HRTIM Timer External Event Control Register 3 (HRTIM_EECR3) ..	781
21.5.54	HRTIM ADC Trigger 1 Register (HRTIM_ADC1R) .....	782
21.5.55	HRTIM ADC Trigger 2 Register (HRTIM_ADC2R) .....	783
21.5.56	HRTIM ADC Trigger 3 Register (HRTIM_ADC3R) .....	784
21.5.57	HRTIM ADC Trigger 4 Register (HRTIM_ADC4R) .....	786
21.5.58	HRTIM DLL Control Register (HRTIM_DLLCR) .....	788
21.5.59	HRTIM Fault Input Register 1 (HRTIM_FLTINR1) .....	789
21.5.60	HRTIM Fault Input Register 2 (HRTIM_FLTINR2) .....	791
21.5.61	HRTIM Burst DMA Master timer update Register (HRTIM_BDMUPR) .....	793
21.5.62	HRTIM Burst DMA Timerx update Register (HRTIM_BDTxUPR) .....	794
21.5.63	HRTIM Burst DMA Data Register (HRTIM_BDMADR) .....	795
21.5.64	HRTIM register map .....	796
22	Infrared interface (IRTIM) .....	805
23	Basic timers (TIM6/TIM7) .....	806
23.1	TIM6/TIM7 introduction .....	806
23.2	TIM6/TIM7 main features .....	806
23.3	TIM6/TIM7 functional description .....	807
23.3.1	Time-base unit .....	807
23.3.2	Counting mode .....	809
23.3.3	UIF bit remapping .....	812
23.3.4	Clock source .....	812
23.3.5	Debug mode .....	813
23.4	TIM6/TIM7 registers .....	813
23.4.1	TIMx control register 1 (TIMx_CR1)(x = 6 to 7) .....	813
23.4.2	TIMx control register 2 (TIMx_CR2)(x = 6 to 7) .....	815

- 23.4.3 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . . 815
- 23.4.4 TIMx status register (TIMx_SR)(x = 6 to 7) . . . . . 816
- 23.4.5 TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . . 816
- 23.4.6 TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . . 816
- 23.4.7 TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . . 817
- 23.4.8 TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . . 817
- 23.4.9 TIMx register map . . . . . 818
24 Independent watchdog (IWDG) . . . . . 819
- 24.1 Introduction . . . . . 819
- 24.2 IWDG main features . . . . . 819
- 24.3 IWDG functional description . . . . . 819
  - 24.3.1 IWDG block diagram . . . . . 819
  - 24.3.2 Window option . . . . . 820
  - 24.3.3 Hardware watchdog . . . . . 821
  - 24.3.4 Register access protection . . . . . 821
  - 24.3.5 Debug mode . . . . . 821
- 24.4 IWDG registers . . . . . 822
  - 24.4.1 IWDG key register (IWDG_KR) . . . . . 822
  - 24.4.2 IWDG prescaler register (IWDG_PR) . . . . . 823
  - 24.4.3 IWDG reload register (IWDG_RLR) . . . . . 824
  - 24.4.4 IWDG status register (IWDG_SR) . . . . . 825
  - 24.4.5 IWDG window register (IWDG_WINR) . . . . . 826
  - 24.4.6 IWDG register map . . . . . 827
25 System window watchdog (WWDG) . . . . . 828
- 25.1 Introduction . . . . . 828
- 25.2 WWDG main features . . . . . 828
- 25.3 WWDG functional description . . . . . 828
  - 25.3.1 WWDG block diagram . . . . . 829
  - 25.3.2 Enabling the watchdog . . . . . 829
  - 25.3.3 Controlling the down-counter . . . . . 829
  - 25.3.4 How to program the watchdog timeout . . . . . 829
  - 25.3.5 Debug mode . . . . . 831
- 25.4 WWDG interrupts . . . . . 831
- 25.5 WWDG registers . . . . . 831

25.5.1	WWDG control register (WWDG_CR) .....	831
25.5.2	WWDG configuration register (WWDG_CFR) .....	832
25.5.3	WWDG status register (WWDG_SR) .....	832
25.5.4	WWDG register map .....	833
26	Real-time clock (RTC) .....	834
26.1	Introduction .....	834
26.2	RTC main features .....	835
26.3	RTC functional description .....	836
26.3.1	RTC block diagram .....	836
26.3.2	GPIOs controlled by the RTC .....	837
26.3.3	Clock and prescalers .....	839
26.3.4	Real-time clock and calendar .....	839
26.3.5	Programmable alarms .....	840
26.3.6	Periodic auto-wakeup .....	840
26.3.7	RTC initialization and configuration .....	841
26.3.8	Reading the calendar .....	842
26.3.9	Resetting the RTC .....	843
26.3.10	RTC synchronization .....	844
26.3.11	RTC reference clock detection .....	844
26.3.12	RTC smooth digital calibration .....	845
26.3.13	Time-stamp function .....	847
26.3.14	Tamper detection .....	848
26.3.15	Calibration clock output .....	849
26.3.16	Alarm output .....	850
26.4	RTC low-power modes .....	850
26.5	RTC interrupts .....	850
26.6	RTC registers .....	851
26.6.1	RTC time register (RTC_TR) .....	851
26.6.2	RTC date register (RTC_DR) .....	852
26.6.3	RTC control register (RTC_CR) .....	854
26.6.4	RTC initialization and status register (RTC_ISR) .....	857
26.6.5	RTC prescaler register (RTC_PRER) .....	860
26.6.6	RTC wakeup timer register (RTC_WUTR) .....	861
26.6.7	RTC alarm A register (RTC_ALRMAR) .....	862
26.6.8	RTC alarm B register (RTC_ALRMBR) .....	863

26.6.9	RTC write protection register (RTC_WPR) . . . . .	864
26.6.10	RTC sub second register (RTC_SSR) . . . . .	864
26.6.11	RTC shift control register (RTC_SHIFTR) . . . . .	865
26.6.12	RTC timestamp time register (RTC_TSTR) . . . . .	866
26.6.13	RTC timestamp date register (RTC_TSDR) . . . . .	867
26.6.14	RTC time-stamp sub second register (RTC_TSSSR) . . . . .	868
26.6.15	RTC calibration register (RTC_CALR) . . . . .	869
26.6.16	RTC tamper and alternate function configuration register (RTC_TAFCR) . . . . .	870
26.6.17	RTC alarm A sub second register (RTC_ALRMASSR) . . . . .	873
26.6.18	RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .	874
26.6.19	RTC backup registers (RTC_BKPxR) . . . . .	875
26.6.20	RTC register map . . . . .	875
27	Inter-integrated circuit (I2C) interface . . . . .	878
27.1	Introduction . . . . .	878
27.2	I2C main features . . . . .	878
27.3	I2C implementation . . . . .	879
27.4	I2C functional description . . . . .	879
27.4.1	I2C block diagram . . . . .	880
27.4.2	I2C pins and internal signals . . . . .	881
27.4.3	I2C clock requirements . . . . .	881
27.4.4	Mode selection . . . . .	881
27.4.5	I2C initialization . . . . .	882
27.4.6	Software reset . . . . .	887
27.4.7	Data transfer . . . . .	888
27.4.8	I2C slave mode . . . . .	890
27.4.9	I2C master mode . . . . .	899
27.4.10	I2C_TIMINGR register configuration examples . . . . .	911
27.4.11	SMBus specific features . . . . .	912
27.4.12	SMBus initialization . . . . .	915
27.4.13	SMBus: I2C_TIMEOUTR register configuration examples . . . . .	917
27.4.14	SMBus slave mode . . . . .	918
27.4.15	Wakeup from Stop mode on address match . . . . .	926
27.4.16	Error conditions . . . . .	926
27.4.17	DMA requests . . . . .	928
27.4.18	Debug mode . . . . .	929

27.5	I2C low-power modes . . . . .	929
27.6	I2C interrupts . . . . .	930
27.7	I2C registers . . . . .	931
27.7.1	I2C control register 1 (I2C_CR1) . . . . .	931
27.7.2	I2C control register 2 (I2C_CR2) . . . . .	934
27.7.3	I2C own address 1 register (I2C_OAR1) . . . . .	937
27.7.4	I2C own address 2 register (I2C_OAR2) . . . . .	938
27.7.5	I2C timing register (I2C_TIMINGR) . . . . .	939
27.7.6	I2C timeout register (I2C_TIMEOUTR) . . . . .	940
27.7.7	I2C interrupt and status register (I2C_ISR) . . . . .	941
27.7.8	I2C interrupt clear register (I2C_ICR) . . . . .	943
27.7.9	I2C PEC register (I2C_PECR) . . . . .	944
27.7.10	I2C receive data register (I2C_RXDR) . . . . .	945
27.7.11	I2C transmit data register (I2C_TXDR) . . . . .	945
27.7.12	I2C register map . . . . .	946
28	Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .	948
28.1	Introduction . . . . .	948
28.2	USART main features . . . . .	948
28.3	USART extended features . . . . .	949
28.4	USART implementation . . . . .	950
28.5	USART functional description . . . . .	950
28.5.1	USART character description . . . . .	953
28.5.2	USART transmitter . . . . .	955
28.5.3	USART receiver . . . . .	957
28.5.4	USART baud rate generation . . . . .	964
28.5.5	Tolerance of the USART receiver to clock deviation . . . . .	966
28.5.6	USART auto baud rate detection . . . . .	967
28.5.7	Multiprocessor communication using USART . . . . .	968
28.5.8	Modbus communication using USART . . . . .	970
28.5.9	USART parity control . . . . .	971
28.5.10	USART LIN (local interconnection network) mode . . . . .	972
28.5.11	USART synchronous mode . . . . .	974
28.5.12	USART Single-wire Half-duplex communication . . . . .	977
28.5.13	USART Smartcard mode . . . . .	977

- 28.5.14 USART IrDA SIR ENDEC block . . . . . 982
- 28.5.15 USART continuous communication in DMA mode . . . . . 984
- 28.5.16 RS232 hardware flow control and RS485 driver enable using USART . . . . . 986
- 28.5.17 Wakeup from Stop mode using USART . . . . . 988
28.6 USART low-power modes . . . . . 990
28.7 USART interrupts . . . . . 990
28.8 USART registers . . . . . 992
- 28.8.1 USART control register 1 (USART_CR1) . . . . . 992
- 28.8.2 USART control register 2 (USART_CR2) . . . . . 995
- 28.8.3 USART control register 3 (USART_CR3) . . . . . 999
- 28.8.4 USART baud rate register (USART_BRR) . . . . . 1003
- 28.8.5 USART guard time and prescaler register (USART_GTPR) . . . . . 1003
- 28.8.6 USART receiver timeout register (USART_RTOR) . . . . . 1004
- 28.8.7 USART request register (USART_RQR) . . . . . 1005
- 28.8.8 USART interrupt and status register (USART_ISR) . . . . . 1006
- 28.8.9 USART interrupt flag clear register (USART_ICR) . . . . . 1011
- 28.8.10 USART receive data register (USART_RDR) . . . . . 1012
- 28.8.11 USART transmit data register (USART_TDR) . . . . . 1012
- 28.8.12 USART register map . . . . . 1013

29 Serial peripheral interface (SPI) . . . . . 1015

29.1 Introduction . . . . . 1015
29.2 SPI main features . . . . . 1015
29.3 SPI implementation . . . . . 1015
29.4 SPI functional description . . . . . 1016
- 29.4.1 General description . . . . . 1016
- 29.4.2 Communications between one master and one slave . . . . . 1017
- 29.4.3 Standard multi-slave communication . . . . . 1019
- 29.4.4 Multi-master communication . . . . . 1020
- 29.4.5 Slave select (NSS) pin management . . . . . 1021
- 29.4.6 Communication formats . . . . . 1022
- 29.4.7 Configuration of SPI . . . . . 1024
- 29.4.8 Procedure for enabling SPI . . . . . 1025
- 29.4.9 Data transmission and reception procedures . . . . . 1025
- 29.4.10 SPI status flags . . . . . 1035
- 29.4.11 SPI error flags . . . . . 1036

29.4.12	NSS pulse mode .....	1037
29.4.13	TI mode .....	1037
29.4.14	CRC calculation .....	1038
29.5	SPI interrupts .....	1040
29.6	SPI registers .....	1041
29.6.1	SPI control register 1 (SPIx_CR1) .....	1041
29.6.2	SPI control register 2 (SPIx_CR2) .....	1043
29.6.3	SPI status register (SPIx_SR) .....	1045
29.6.4	SPI data register (SPIx_DR) .....	1046
29.6.5	SPI CRC polynomial register (SPIx_CRCPR) .....	1047
29.6.6	SPI Rx CRC register (SPIx_RXCRCR) .....	1047
29.6.7	SPI Tx CRC register (SPIx_TXCRCR) .....	1047
29.6.8	SPI register map .....	1049
30	Controller area network (bxCAN) .....	1050
30.1	Introduction .....	1050
30.2	bxCAN main features .....	1050
30.3	bxCAN general description .....	1050
30.3.1	CAN 2.0B active core .....	1051
30.3.2	Control, status and configuration registers .....	1051
30.3.3	Tx mailboxes .....	1051
30.3.4	Acceptance filters .....	1051
30.4	bxCAN operating modes .....	1052
30.4.1	Initialization mode .....	1052
30.4.2	Normal mode .....	1053
30.4.3	Sleep mode (low-power) .....	1053
30.5	Test mode .....	1054
30.5.1	Silent mode .....	1054
30.5.2	Loop back mode .....	1055
30.5.3	Loop back combined with silent mode .....	1055
30.6	Behavior in debug mode .....	1056
30.7	bxCAN functional description .....	1056
30.7.1	Transmission handling .....	1056
30.7.2	Time triggered communication mode .....	1058
30.7.3	Reception handling .....	1058
30.7.4	Identifier filtering .....	1059

- 30.7.5 Message storage . . . . . 1063
- 30.7.6 Error management . . . . . 1065
- 30.7.7 Bit timing . . . . . 1065
30.8 bxCAN interrupts . . . . . 1068
30.9 CAN registers . . . . . 1069
- 30.9.1 Register access protection . . . . . 1069
- 30.9.2 CAN control and status registers . . . . . 1069
- 30.9.3 CAN mailbox registers . . . . . 1079
- 30.9.4 CAN filter registers . . . . . 1086
- 30.9.5 bxCAN register map . . . . . 1090

31 Debug support (DBG) . . . . . 1094

31.1 Overview . . . . . 1094
31.2 Reference Arm documentation . . . . . 1095
31.3 SWJ debug port (serial wire and JTAG) . . . . . 1095
- 31.3.1 Mechanism to select the JTAG-DP or the SW-DP . . . . . 1096
31.4 Pinout and debug port pins . . . . . 1096
- 31.4.1 SWJ debug port pins . . . . . 1097
- 31.4.2 Flexible SWJ-DP pin assignment . . . . . 1097
- 31.4.3 Internal pull-up and pull-down on JTAG pins . . . . . 1098
- 31.4.4 Using serial wire and releasing the unused debug pins as GPIOs . . . . . 1099
31.5 STM32F334xx JTAG TAP connection . . . . . 1099
31.6 ID codes and locking mechanism . . . . . 1100
- 31.6.1 MCU device ID code . . . . . 1100
- 31.6.2 Boundary scan TAP . . . . . 1101
- 31.6.3 Cortex ^®-M4 TAP . . . . . 1101
- 31.6.4 Cortex ^®-M4 JEDEC-106 ID code . . . . . 1101
31.7 JTAG debug port . . . . . 1101
31.8 SW debug port . . . . . 1103
- 31.8.1 SW protocol introduction . . . . . 1103
- 31.8.2 SW protocol sequence . . . . . 1103
- 31.8.3 SW-DP state machine (reset, idle states, ID code) . . . . . 1104
- 31.8.4 DP and AP read/write accesses . . . . . 1105
- 31.8.5 SW-DP registers . . . . . 1105
- 31.8.6 SW-AP registers . . . . . 1106

31.9	AHB-AP (AHB access port) - valid for both JTAG-DP and SW-DP . . . . .	1106
31.10	Core debug . . . . .	1107
31.11	Capability of the debugger host to connect under system reset . . . . .	1108
31.12	FPB (Flash patch breakpoint) . . . . .	1108
31.13	DWT (data watchpoint trigger) . . . . .	1108
31.14	ITM (instrumentation trace macrocell) . . . . .	1109
31.14.1	General description . . . . .	1109
31.14.2	Time stamp packets, synchronization and overflow packets . . . . .	1109
31.15	MCU debug component (DBGMCU) . . . . .	1111
31.15.1	Debug support for low-power modes . . . . .	1111
31.15.2	Debug support for timers, watchdog, bxCAN and I ²C . . . . .	1111
31.15.3	Debug MCU configuration register . . . . .	1111
31.15.4	Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . .	1113
31.15.5	Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) . . . . .	1114
31.16	TPIU (trace port interface unit) . . . . .	1115
31.16.1	Introduction . . . . .	1115
31.17	DBG register map . . . . .	1116
32	Device electronic signature . . . . .	1117
32.1	Unique device ID register (96 bits) . . . . .	1117
32.2	Flash memory size data register . . . . .	1118
33	Revision history . . . . .	1119

List of tables

Table 1. STM32F334xx peripheral register boundary addresses . . . . . 48

Table 2. CCM SRAM organization . . . . . 51

Table 3. Boot modes . . . . . 52

Table 4. Flash module organization . . . . . 54

Table 5. Flash memory read protection status . . . . . 63

Table 6. Access status versus protection level and execution modes . . . . . 64

Table 7. Flash interrupt request . . . . . 65

Table 8. Flash interface - register map and reset values . . . . . 71

Table 9. Option byte format . . . . . 73

Table 10. Option byte organization. . . . . 73

Table 11. Description of the option bytes . . . . . 74

Table 12. CRC internal input/output signals . . . . . 77

Table 13. CRC register map and reset values . . . . . 81

Table 14. Low-power mode summary . . . . . 86

Table 15. Sleep-now . . . . . 88

Table 16. Sleep-on-exit. . . . . 88

Table 17. Stop mode . . . . . 90

Table 18. Standby mode. . . . . 91

Table 19. PWR register map and reset values . . . . . 95

Table 20. STM32F334 peripherals interconnect matrix . . . . . 96

Table 21. Comparator outputs to timer inputs . . . . . 99

Table 22. Timer output selection as comparator blanking source . . . . . 99

Table 23. DAC output selection as comparator inverting input. . . . . 100

Table 24. Timer synchronization. . . . . 101

Table 25. Timer and EXTI signals triggering DAC conversions . . . . . 102

Table 26. RCC register map and reset values . . . . . 137

Table 27. Port bit configuration table . . . . . 141

Table 28. GPIO register map and reset values . . . . . 155

Table 29. SYSCFG register map and reset values. . . . . 168

Table 30. DMA implementation . . . . . 171

Table 31. DMA requests for each channel . . . . . 173

Table 32. Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . 180

Table 33. DMA interrupt requests. . . . . 182

Table 34. DMA register map and reset values . . . . . 190

Table 35. STM32F334xx vector table. . . . . 193

Table 36. External interrupt/event controller register map and reset values. . . . . 208

Table 37. ADC internal signals . . . . . 215

Table 38. ADC pins. . . . . 215

Table 39. Configuring the trigger polarity for regular external triggers . . . . . 230

Table 40. ADC1 (master) & 2 (slave) - External triggers for regular channels . . . . . 231

Table 41. ADC1 & ADC2 - External trigger for injected channels. . . . . 232

Table 42. TSAR timings depending on resolution . . . . . 244

Table 43. Offset computation versus data resolution . . . . . 247

Table 44. Analog watchdog channel selection . . . . . 257

Table 45. Analog watchdog 1 comparison . . . . . 258

Table 46. Analog watchdog 2 and 3 comparison . . . . . 258

Table 47. ADC interrupts per each ADC. . . . . 279

Table 48. DELAY bits versus ADC resolution. . . . . 312

Table 49.	ADC global register map. . . . .	313
Table 50.	ADC register map and reset values for each ADC (offset=0x000 for master ADC, 0x100 for slave ADC, x=1..2) . . . . .	314
Table 51.	ADC register map and reset values (master and slave ADC common registers) offset =0x300, x=1) . . . . .	316
Table 52.	DACx pins. . . . .	319
Table 53.	External triggers (DAC1). . . . .	322
Table 54.	External triggers (DAC2). . . . .	322
Table 55.	DAC register map and reset values . . . . .	341
Table 56.	STM32F334xx comparator input/outputs summary . . . . .	345
Table 57.	COMP register map and reset values. . . . .	352
Table 58.	Connections with dedicated I/O . . . . .	353
Table 59.	OPAMP register map and reset values . . . . .	363
Table 60.	Acquisition sequence summary . . . . .	367
Table 61.	Spread spectrum deviation versus AHB clock frequency. . . . .	369
Table 62.	I/O state depending on its mode and IODEF bit value . . . . .	370
Table 63.	Effect of low-power modes on TSC . . . . .	372
Table 64.	Interrupt control bits . . . . .	372
Table 65.	TSC register map and reset values . . . . .	381
Table 66.	Behavior of timer outputs versus BRK/BRK2 inputs. . . . .	425
Table 67.	Counting direction versus encoder signals. . . . .	432
Table 68.	TIM1 internal trigger connection . . . . .	449
Table 69.	Output control bits for complementary OCx and OCxN channels with break feature. . . . .	463
Table 70.	TIM1 register map and reset values . . . . .	475
Table 71.	Counting direction versus encoder signals. . . . .	512
Table 72.	TIMx internal trigger connection . . . . .	530
Table 73.	Output control bit for standard OCx channels. . . . .	540
Table 74.	TIM2/TIM3 register map and reset values . . . . .	546
Table 75.	TIMx Internal trigger connection . . . . .	589
Table 76.	Output control bits for complementary OCx and OCxN channels with break feature (TIM15). . . . .	599
Table 77.	TIM15 register map and reset values . . . . .	605
Table 78.	Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) . . . . .	618
Table 79.	TIM16/TIM17 register map and reset values . . . . .	625
Table 80.	HRTIM Input/output summary. . . . .	630
Table 81.	Timer resolution and min. PWM frequency for $f_{HRTIM} = 144$ MHz . . . . .	632
Table 82.	Period and Compare registers min and max values. . . . .	635
Table 83.	Timer operating modes. . . . .	636
Table 84.	Events mapping across Timer A to E . . . . .	642
Table 85.	Deadtime resolution and max absolute values. . . . .	651
Table 86.	External events mapping and associated features . . . . .	658
Table 87.	Output set/reset latency and jitter vs external event operating mode. . . . .	659
Table 88.	Filtering signals mapping per time . . . . .	662
Table 89.	Windowing signals mapping per timer (EEFLTR[3:0] = 1111) . . . . .	664
Table 90.	HRTIM preloadable control registers and associated update sources . . . . .	673
Table 91.	Update enable inputs and sources . . . . .	674
Table 92.	Master timer update event propagation . . . . .	676
Table 93.	TIMx update event propagation . . . . .	676
Table 94.	Reset events able to generate an update. . . . .	677
Table 95.	Update event propagation for a timer reset . . . . .	678
Table 96.	Output state programming, x= A..E, y = 1 or 2 . . . . .	679

Table 97.	Timer output programming for burst mode . . . . .	682
Table 98.	Burst mode clock sources from general purpose timer. . . . .	684
Table 99.	Fault inputs . . . . .	692
Table 100.	Sampling rate and filter length vs FLTFxF[3:0] and clock setting . . . . .	693
Table 101.	Effect of sync event vs timer operating modes . . . . .	698
Table 102.	HRTIM interrupt summary . . . . .	704
Table 103.	HRTIM DMA request summary . . . . .	705
Table 104.	RTIM global register map . . . . .	796
Table 105.	HRTIM Register map and reset values: Master timer. . . . .	796
Table 106.	HRTIM Register map and reset values: TIMx (x= A..E) . . . . .	798
Table 107.	HRTIM Register map and reset values: Common functions. . . . .	802
Table 108.	TIMx register map and reset values . . . . .	818
Table 109.	IWDG register map and reset values . . . . .	827
Table 110.	WWDG register map and reset values . . . . .	833
Table 111.	RTC pin PC13 configuration . . . . .	838
Table 112.	LSE pin PC14 configuration . . . . .	838
Table 113.	LSE pin PC15 configuration . . . . .	838
Table 114.	Effect of low-power modes on RTC . . . . .	850
Table 115.	Interrupt control bits . . . . .	851
Table 116.	RTC register map and reset values . . . . .	875
Table 117.	STM32F334xx I2C implementation . . . . .	879
Table 118.	I2C input/output pins. . . . .	881
Table 119.	I2C internal input/output signals . . . . .	881
Table 120.	Comparison of analog vs. digital filters . . . . .	883
Table 121.	I2C-SMBus specification data setup and hold times . . . . .	886
Table 122.	I2C configuration. . . . .	890
Table 123.	I2C-SMBus specification clock timings . . . . .	901
Table 124.	Examples of timing settings for f _I2CCLK= 8 MHz . . . . .	911
Table 125.	Examples of timings settings for f _I2CCLK= 16 MHz . . . . .	911
Table 126.	Examples of timings settings for f _I2CCLK= 48 MHz . . . . .	912
Table 127.	SMBus timeout specifications . . . . .	914
Table 128.	SMBus with PEC configuration . . . . .	916
Table 129.	Examples of TIMEOUTA settings for various I2CCLK frequencies (max t _TIMEOUT= 25 ms) . . . . .	917
Table 130.	Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . .	917
Table 131.	Examples of TIMEOUTA settings for various I2CCLK frequencies (max t _IDLE= 50 µs) . . . . .	918
Table 132.	Effect of low-power modes on the I2C . . . . .	929
Table 133.	I2C Interrupt requests . . . . .	930
Table 134.	I2C register map and reset values . . . . .	946
Table 135.	STM32F334xx USART features . . . . .	950
Table 136.	Noise detection from sampled data . . . . .	962
Table 137.	Error calculation for programmed baud rates at f _CK= 72MHz in both cases of oversampling by 16 or by 8. . . . .	965
Table 138.	Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .	967
Table 139.	Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . .	967
Table 140.	Frame formats . . . . .	971
Table 141.	Effect of low-power modes on the USART . . . . .	990
Table 142.	USART interrupt requests. . . . .	990
Table 143.	USART register map and reset values . . . . .	1013
Table 144.	STM32F334xx SPI implementation . . . . .	1016
Table 145.	SPI interrupt requests . . . . .	1040

Table 146.	SPI register map and reset values . . . . .	1049
Table 147.	Transmit mailbox mapping . . . . .	1064
Table 148.	Receive mailbox mapping. . . . .	1064
Table 149.	bxCAN register map and reset values . . . . .	1090
Table 150.	SWJ debug port pins . . . . .	1097
Table 151.	Flexible SWJ-DP pin assignment . . . . .	1097
Table 152.	JTAG debug port data registers . . . . .	1101
Table 153.	32-bit debug port registers addressed through the shifted value A[3:2] . . . . .	1102
Table 154.	Packet request (8-bits) . . . . .	1103
Table 155.	ACK response (3 bits). . . . .	1104
Table 156.	DATA transfer (33 bits). . . . .	1104
Table 157.	SW-DP registers . . . . .	1105
Table 158.	Cortex ^®-M4 AHB-AP registers . . . . .	1107
Table 159.	Core debug registers . . . . .	1107
Table 160.	Main ITM registers . . . . .	1110
Table 161.	Flexible TRACE pin assignment. . . . .	1115
Table 162.	DBG register map and reset values . . . . .	1116
Table 163.	Document revision history . . . . .	1119

List of figures

Figure 1. System architecture . . . . . 45

Figure 2. Programming procedure . . . . . 58

Figure 3. Flash memory Page Erase procedure . . . . . 60

Figure 4. Flash memory Mass Erase procedure . . . . . 61

Figure 5. CRC calculation unit block diagram . . . . . 77

Figure 6. Power supply overview . . . . . 82

Figure 7. Power on reset/power down reset waveform . . . . . 85

Figure 8. PVD thresholds . . . . . 86

Figure 9. Simplified diagram of the reset circuit . . . . . 105

Figure 10. STM32F334xx clock tree . . . . . 107

Figure 11. HSE/ LSE clock sources . . . . . 108

Figure 12. Frequency measurement with TIM16 in capture mode . . . . . 114

Figure 13. Basic structure of an I/O port bit . . . . . 140

Figure 14. Basic structure of a 5-Volt tolerant I/O port bit . . . . . 140

Figure 15. Input floating/pull up/pull down configurations . . . . . 145

Figure 16. Output configuration . . . . . 146

Figure 17. Alternate function configuration . . . . . 147

Figure 18. High impedance-analog configuration . . . . . 147

Figure 19. DMA request mapping . . . . . 172

Figure 20. DMA block diagram . . . . . 174

Figure 21. External interrupt/event block diagram . . . . . 197

Figure 22. External interrupt/event GPIO mapping . . . . . 200

Figure 23. ADC block diagram . . . . . 214

Figure 24. ADC clock scheme . . . . . 216

Figure 25. ADC1 and ADC2 connectivity . . . . . 218

Figure 26. ADC calibration . . . . . 221

Figure 27. Updating the ADC calibration factor . . . . . 222

Figure 28. Mixing single-ended and differential channels . . . . . 222

Figure 29. Enabling / Disabling the ADC . . . . . 223

Figure 30. Analog to digital conversion time . . . . . 228

Figure 31. Stopping ongoing regular conversions . . . . . 229

Figure 32. Stopping ongoing regular and injected conversions . . . . . 230

Figure 33. Triggers are shared between ADC master & ADC slave . . . . . 231

Figure 34. Injected conversion latency . . . . . 234

Figure 35. Example of JSQR queue of context (sequence change) . . . . . 237

Figure 36. Example of JSQR queue of context (trigger change) . . . . . 237

Figure 37. Example of JSQR queue of context with overflow before conversion . . . . . 238

Figure 38. Example of JSQR queue of context with overflow during conversion . . . . . 238

Figure 39. Example of JSQR queue of context with empty queue (case JQM=0). . . . . 239

Figure 40. Example of JSQR queue of context with empty queue (case JQM=1). . . . . 240

Figure 41. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion. . . . . 240

Figure 42. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . . 241

Figure 43. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs outside an ongoing conversion . . . . . 241

Figure 44. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . . 242

Figure 45.	Flushing JSQR queue of context by setting ADDIS=1 (JQM=0).	242
Figure 46.	Flushing JSQR queue of context by setting ADDIS=1 (JQM=1).	243
Figure 47.	Example of JSQR queue of context when changing SW and HW triggers.	243
Figure 48.	Single conversions of a sequence, software trigger	245
Figure 49.	Continuous conversion of a sequence, software trigger	245
Figure 50.	Single conversions of a sequence, hardware trigger	246
Figure 51.	Continuous conversions of a sequence, hardware trigger	246
Figure 52.	Right alignment (offset disabled, unsigned value)	248
Figure 53.	Right alignment (offset enabled, signed value)	248
Figure 54.	Left alignment (offset disabled, unsigned value)	249
Figure 55.	Left alignment (offset enabled, signed value)	249
Figure 56.	Example of overrun (OVR)	250
Figure 57.	AUTODLY=1, regular conversion in continuous mode, software trigger	253
Figure 58.	AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=0; JDISCEN=0)	254
Figure 59.	AUTODLY=1, regular HW conversions interrupted by injected conversions (DISCEN=1, JDISCEN=1)	255
Figure 60.	AUTODLY=1, regular continuous conversions interrupted by injected conversions	256
Figure 61.	AUTODLY=1 in auto- injected mode (JAUTO=1)	256
Figure 62.	Analog watchdog's guarded area	257
Figure 63.	ADC _y_AWD _x_OUT signal generation (on all regular channels)	259
Figure 64.	ADC _y_AWD _x_OUT signal generation (AWD _xflag not cleared by SW)	260
Figure 65.	ADC _y_AWD _x_OUT signal generation (on a single regular channel)	260
Figure 66.	ADC _y_AWD _x_OUT signal generation (on all injected channels)	260
Figure 67.	Dual ADC block diagram ⁽¹⁾	262
Figure 68.	Injected simultaneous mode on 4 channels: dual ADC mode	263
Figure 69.	Regular simultaneous mode on 16 channels: dual ADC mode	265
Figure 70.	Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode.	267
Figure 71.	Interleaved mode on 1 channel in single conversion mode: dual ADC mode.	267
Figure 72.	Interleaved conversion with injection	268
Figure 73.	Alternate trigger: injected group of each ADC	269
Figure 74.	Alternate trigger: 4 injected channels (each ADC) in discontinuous mode.	270
Figure 75.	Alternate + regular simultaneous	271
Figure 76.	Case of trigger occurring during injected conversion	271
Figure 77.	DMA Requests in regular simultaneous mode when MDMA=0b00	272
Figure 78.	DMA requests in regular simultaneous mode when MDMA=0b10	273
Figure 79.	DMA requests in interleaved mode when MDMA=0b10	273
Figure 80.	Temperature sensor channel block diagram	275
Figure 81.	VBAT channel block diagram	277
Figure 82.	V _REFINTchannel block diagram	277
Figure 83.	DAC1 block diagram	318
Figure 84.	DAC2 block diagram	319
Figure 85.	Data registers in single DAC channel mode	320
Figure 86.	Timing diagram for conversion with trigger disabled TEN = 0	321
Figure 87.	Data registers in dual DAC channel mode	323
Figure 88.	DAC LFSR register calculation algorithm	328
Figure 89.	DAC conversion (SW trigger enabled) with LFSR wave generation.	328
Figure 90.	DAC triangle wave generation	329
Figure 91.	DAC conversion (SW trigger enabled) with triangle wave generation	329
Figure 92.	Comparator 2 block diagram	344
Figure 93.	Comparator output blanking	346
Figure 94.	STM32F334xx comparator and operational amplifier

connections	354
Figure 95. Timer controlled Multiplexer mode	356
Figure 96. Standalone mode: external gain setting mode	357
Figure 97. Follower configuration	358
Figure 98. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used	359
Figure 99. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for filtering	359
Figure 100. TSC block diagram	365
Figure 101. Surface charge transfer analog I/O group structure	366
Figure 102. Sampling capacitor voltage variation	367
Figure 103. Charge transfer acquisition sequence	368
Figure 104. Spread spectrum variation principle	369
Figure 105. Advanced-control timer block diagram	385
Figure 106. Counter timing diagram with prescaler division change from 1 to 2	388
Figure 107. Counter timing diagram with prescaler division change from 1 to 4	388
Figure 108. Counter timing diagram, internal clock divided by 1	390
Figure 109. Counter timing diagram, internal clock divided by 2	390
Figure 110. Counter timing diagram, internal clock divided by 4	391
Figure 111. Counter timing diagram, internal clock divided by N	391
Figure 112. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded)	392
Figure 113. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)	392
Figure 114. Counter timing diagram, internal clock divided by 1	394
Figure 115. Counter timing diagram, internal clock divided by 2	394
Figure 116. Counter timing diagram, internal clock divided by 4	395
Figure 117. Counter timing diagram, internal clock divided by N	395
Figure 118. Counter timing diagram, update event when repetition counter is not used	396
Figure 119. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6	397
Figure 120. Counter timing diagram, internal clock divided by 2	398
Figure 121. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36	398
Figure 122. Counter timing diagram, internal clock divided by N	399
Figure 123. Counter timing diagram, update event with ARPE=1 (counter underflow)	399
Figure 124. Counter timing diagram, Update event with ARPE=1 (counter overflow)	400
Figure 125. Update rate examples depending on mode and TIMx_RCR register settings	401
Figure 126. External trigger input block	402
Figure 127. Control circuit in normal mode, internal clock divided by 1	403
Figure 128. TI2 external clock connection example	404
Figure 129. Control circuit in external clock mode 1	405
Figure 130. External trigger input block	405
Figure 131. Control circuit in external clock mode 2	406
Figure 132. Capture/compare channel (example: channel 1 input stage)	407
Figure 133. Capture/compare channel 1 main circuit	408
Figure 134. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3)	408
Figure 135. Output stage of capture/compare channel (channel 4)	409
Figure 136. Output stage of capture/compare channel (channel 5, idem ch. 6)	409
Figure 137. PWM input mode timing	411
Figure 138. Output compare mode, toggle on OC1	413
Figure 139. Edge-aligned PWM waveforms (ARR=8)	414
Figure 140. Center-aligned PWM waveforms (ARR=8)	415
Figure 141. Generation of 2 phase-shifted PWM signals with 50% duty cycle	417
Figure 142. Combined PWM mode on channel 1 and 3	418
Figure 143. 3-phase combined PWM signals with multiple trigger pulses per period	419
Figure 144. Complementary output with dead-time insertion	420

Figure 145. Dead-time waveforms with delay greater than the negative pulse . . . . .	420
Figure 146. Dead-time waveforms with delay greater than the positive pulse. . . . .	421
Figure 147. Various output behavior in response to a break event on BKIN (OSSI = 1). . . . .	424
Figure 148. PWM output state following BKIN and BKIN2 pins assertion (OSSI=1). . . . .	425
Figure 149. PWM output state following BKIN assertion (OSSI=0). . . . .	426
Figure 150. Clearing TIMx_OCxREF . . . . .	427
Figure 151. 6-step generation, COM example (OSSR=1). . . . .	428
Figure 152. Example of one pulse mode. . . . .	429
Figure 153. Retriggerable one pulse mode . . . . .	431
Figure 154. Example of counter operation in encoder interface mode. . . . .	432
Figure 155. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .	433
Figure 156. Measuring time interval between edges on 3 signals . . . . .	434
Figure 157. Example of Hall sensor interface . . . . .	436
Figure 158. Control circuit in reset mode . . . . .	437
Figure 159. Control circuit in Gated mode . . . . .	438
Figure 160. Control circuit in trigger mode . . . . .	439
Figure 161. Control circuit in external clock mode 2 + trigger mode . . . . .	440
Figure 162. General-purpose timer block diagram . . . . .	479
Figure 163. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	481
Figure 164. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	481
Figure 165. Counter timing diagram, internal clock divided by 1 . . . . .	482
Figure 166. Counter timing diagram, internal clock divided by 2 . . . . .	483
Figure 167. Counter timing diagram, internal clock divided by 4 . . . . .	483
Figure 168. Counter timing diagram, internal clock divided by N. . . . .	484
Figure 169. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .	484
Figure 170. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .	485
Figure 171. Counter timing diagram, internal clock divided by 1 . . . . .	486
Figure 172. Counter timing diagram, internal clock divided by 2 . . . . .	486
Figure 173. Counter timing diagram, internal clock divided by 4 . . . . .	487
Figure 174. Counter timing diagram, internal clock divided by N. . . . .	487
Figure 175. Counter timing diagram, Update event when repetition counter is not used . . . . .	488
Figure 176. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .	489
Figure 177. Counter timing diagram, internal clock divided by 2 . . . . .	490
Figure 178. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	490
Figure 179. Counter timing diagram, internal clock divided by N. . . . .	491
Figure 180. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .	491
Figure 181. Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .	492
Figure 182. Control circuit in normal mode, internal clock divided by 1 . . . . .	493
Figure 183. TI2 external clock connection example. . . . .	493
Figure 184. Control circuit in external clock mode 1 . . . . .	494
Figure 185. External trigger input block . . . . .	495
Figure 186. Control circuit in external clock mode 2 . . . . .	496
Figure 187. Capture/Compare channel (example: channel 1 input stage) . . . . .	497
Figure 188. Capture/Compare channel 1 main circuit . . . . .	497
Figure 189. Output stage of Capture/Compare channel (channel 1). . . . .	498
Figure 190. PWM input mode timing . . . . .	500
Figure 191. Output compare mode, toggle on OC1. . . . .	502
Figure 192. Edge-aligned PWM waveforms (ARR=8). . . . .	503
Figure 193. Center-aligned PWM waveforms (ARR=8). . . . .	504
Figure 194. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .	505
Figure 195. Combined PWM mode on channels 1 and 3 . . . . .	507

Figure 196. Clearing TIMx_OCxREF . . . . .	508
Figure 197. Example of one-pulse mode. . . . .	509
Figure 198. Retriggerable one-pulse mode. . . . .	511
Figure 199. Example of counter operation in encoder interface mode . . . . .	512
Figure 200. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .	513
Figure 201. Control circuit in reset mode . . . . .	514
Figure 202. Control circuit in gated mode . . . . .	515
Figure 203. Control circuit in trigger mode . . . . .	516
Figure 204. Control circuit in external clock mode 2 + trigger mode . . . . .	517
Figure 205. Master/Slave timer example . . . . .	518
Figure 206. Master/slave connection example with 1 channel only timers . . . . .	518
Figure 207. Gating TIM2 with OC1REF of TIM3 . . . . .	519
Figure 208. Gating TIM2 with Enable of TIM3 . . . . .	520
Figure 209. Triggering TIM2 with update of TIM3 . . . . .	521
Figure 210. Triggering TIM2 with Enable of TIM3 . . . . .	521
Figure 211. Triggering TIM3 and TIM2 with TIM3 TI1 input. . . . .	522
Figure 212. TIM15 block diagram . . . . .	550
Figure 213. TIM16/TIM17 block diagram . . . . .	551
Figure 214. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	553
Figure 215. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	553
Figure 216. Counter timing diagram, internal clock divided by 1 . . . . .	555
Figure 217. Counter timing diagram, internal clock divided by 2 . . . . .	555
Figure 218. Counter timing diagram, internal clock divided by 4 . . . . .	556
Figure 219. Counter timing diagram, internal clock divided by N . . . . .	556
Figure 220. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .	557
Figure 221. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .	557
Figure 222. Update rate examples depending on mode and TIMx_RCR register settings . . . . .	559
Figure 223. Control circuit in normal mode, internal clock divided by 1 . . . . .	560
Figure 224. TI2 external clock connection example. . . . .	560
Figure 225. Control circuit in external clock mode 1 . . . . .	561
Figure 226. Capture/compare channel (example: channel 1 input stage) . . . . .	562
Figure 227. Capture/compare channel 1 main circuit . . . . .	562
Figure 228. Output stage of capture/compare channel (channel 1). . . . .	563
Figure 229. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .	563
Figure 230. PWM input mode timing . . . . .	565
Figure 231. Output compare mode, toggle on OC1 . . . . .	567
Figure 232. Edge-aligned PWM waveforms (ARR=8) . . . . .	568
Figure 233. Combined PWM mode on channel 1 and 2 . . . . .	569
Figure 234. Complementary output with dead-time insertion. . . . .	570
Figure 235. Dead-time waveforms with delay greater than the negative pulse. . . . .	571
Figure 236. Dead-time waveforms with delay greater than the positive pulse. . . . .	571
Figure 237. Output behavior in response to a break . . . . .	574
Figure 238. Example of one pulse mode . . . . .	576
Figure 239. Retriggerable one pulse mode . . . . .	577
Figure 240. Measuring time interval between edges on 2 signals. . . . .	579
Figure 241. Control circuit in reset mode . . . . .	580
Figure 242. Control circuit in gated mode . . . . .	581
Figure 243. Control circuit in trigger mode . . . . .	582
Figure 244. High-resolution timer block diagram . . . . .	630
Figure 245. Counter and capture register format vs clock prescaling factor . . . . .	633

Figure 246. Timer A..E overview . . . . .	635
Figure 247. Continuous timer operation. . . . .	637
Figure 248. Single-shot timer operation. . . . .	637
Figure 249. Timer reset resynchronization (prescaling ratio above 32). . . . .	639
Figure 250. Repetition rate vs HRTIM_REPxR content in continuous mode. . . . .	640
Figure 251. Repetition counter behavior in single-shot mode . . . . .	640
Figure 252. Compare events action on outputs: set on compare 1, reset on compare 2 . . . . .	642
Figure 253. Timing unit capture circuitry . . . . .	644
Figure 254. Auto-delayed overview (Compare 2 only). . . . .	645
Figure 255. Auto-delayed compare . . . . .	646
Figure 256. Push-pull mode block diagram . . . . .	648
Figure 257. Push-pull mode example . . . . .	649
Figure 258. Complementary outputs with deadtime insertion . . . . .	649
Figure 259. Deadtime insertion vs deadtime sign (1 indicates negative deadtime). . . . .	650
Figure 260. Complementary outputs for low pulse width (SDTRx = SDTFx = 0). . . . .	651
Figure 261. Complementary outputs for low pulse width (SDTRx = SDTFx = 1). . . . .	651
Figure 262. Complementary outputs for low pulse width (SDTRx = 0, SDTFx = 1). . . . .	652
Figure 263. Complementary outputs for low pulse width (SDTRx = 1, SDTFx=0). . . . .	652
Figure 264. Master timer overview. . . . .	653
Figure 265. Short distance set/reset management for narrow pulse generation . . . . .	655
Figure 266. External event conditioning overview (1 channel represented) . . . . .	657
Figure 267. Latency to external events falling edge (counter reset and output set) . . . . .	660
Figure 268. Latency to external events (output reset on external event). . . . .	661
Figure 269. Event blanking mode . . . . .	661
Figure 270. Event postpone mode. . . . .	662
Figure 271. External trigger blanking with edge-sensitive trigger . . . . .	663
Figure 272. External trigger blanking, level sensitive triggering. . . . .	663
Figure 273. Event windowing mode. . . . .	664
Figure 274. External trigger windowing with edge-sensitive trigger. . . . .	665
Figure 275. External trigger windowing, level sensitive triggering . . . . .	665
Figure 276. Delayed Idle mode entry. . . . .	667
Figure 277. Burst mode and delayed protection priorities (DIDL = 0) . . . . .	668
Figure 278. Burst mode and delayed protection priorities (DIDL = 1) . . . . .	669
Figure 279. Balanced Idle protection example. . . . .	670
Figure 280. Output management overview . . . . .	680
Figure 281. HRTIM output states and transitions . . . . .	680
Figure 282. Burst mode operation example. . . . .	682
Figure 283. Burst mode trigger on external event . . . . .	684
Figure 284. Delayed burst mode entry with deadtime enabled and IDLESx = 1 . . . . .	686
Figure 285. Delayed Burst mode entry during deadtime . . . . .	687
Figure 286. Burst mode exit when the deadtime generator is enabled . . . . .	688
Figure 287. Burst mode emulation example . . . . .	690
Figure 288. Carrier frequency signal insertion . . . . .	690
Figure 289. HRTIM outputs with Chopper mode enabled . . . . .	691
Figure 290. Fault protection circuitry (FAULT1 fully represented, FAULT2..5 partially). . . . .	692
Figure 291. Fault signal filtering (FLTxF[3:0]= 0010: f _SAMPLING= f _HRTIM, N = 4) . . . . .	693
Figure 292. Auxiliary outputs . . . . .	695
Figure 293. Auxiliary and main outputs during burst mode (DIDLx = 0) . . . . .	696
Figure 294. Deadtime distortion on auxiliary output when exiting burst mode. . . . .	696
Figure 295. Counter behavior in synchronized start mode . . . . .	700
Figure 296. ADC trigger selection overview . . . . .	701
Figure 297. Combining several updates on a single DACtrigOutx output . . . . .	702

Figure 298. DMA burst overview . . . . .	706
Figure 299. Burst DMA operation flowchart . . . . .	707
Figure 300. Registers update following DMA burst transfer . . . . .	708
Figure 301. Buck converter topology . . . . .	711
Figure 302. Dual Buck converter management . . . . .	711
Figure 303. Synchronous rectification depending on output current . . . . .	712
Figure 304. Buck with synchronous rectification . . . . .	712
Figure 305. 3-phase interleaved buck converter . . . . .	713
Figure 306. 3-phase interleaved buck converter control . . . . .	714
Figure 307. Transition mode PFC . . . . .	714
Figure 308. Transition mode PFC waveforms . . . . .	715
Figure 309. IRTIM internal hardware connections with TIM16 and TIM17 . . . . .	805
Figure 310. Basic timer block diagram. . . . .	806
Figure 311. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	808
Figure 312. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	808
Figure 313. Counter timing diagram, internal clock divided by 1 . . . . .	809
Figure 314. Counter timing diagram, internal clock divided by 2 . . . . .	810
Figure 315. Counter timing diagram, internal clock divided by 4 . . . . .	810
Figure 316. Counter timing diagram, internal clock divided by N . . . . .	811
Figure 317. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .	811
Figure 318. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .	812
Figure 319. Control circuit in normal mode, internal clock divided by 1 . . . . .	813
Figure 320. Independent watchdog block diagram . . . . .	819
Figure 321. Watchdog block diagram . . . . .	829
Figure 322. Window watchdog timing diagram . . . . .	830
Figure 323. RTC block diagram . . . . .	836
Figure 324. I2C block diagram . . . . .	880
Figure 325. I2C bus protocol . . . . .	882
Figure 326. Setup and hold timings . . . . .	884
Figure 327. I2C initialization flowchart . . . . .	887
Figure 328. Data reception . . . . .	888
Figure 329. Data transmission . . . . .	889
Figure 330. Slave initialization flowchart . . . . .	892
Figure 331. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH= 0 . . . . .	894
Figure 332. Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH= 1 . . . . .	895
Figure 333. Transfer bus diagrams for I2C slave transmitter. . . . .	896
Figure 334. Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . .	897
Figure 335. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . .	898
Figure 336. Transfer bus diagrams for I2C slave receiver . . . . .	898
Figure 337. Master clock generation . . . . .	900
Figure 338. Master initialization flowchart . . . . .	902
Figure 339. 10-bit address read access with HEAD10R=0 . . . . .	902
Figure 340. 10-bit address read access with HEAD10R=1 . . . . .	903
Figure 341. Transfer sequence flowchart for I2C master transmitter for N≤255 bytes . . . . .	904
Figure 342. Transfer sequence flowchart for I2C master transmitter for N>255 bytes . . . . .	905
Figure 343. Transfer bus diagrams for I2C master transmitter . . . . .	906
Figure 344. Transfer sequence flowchart for I2C master receiver for N≤255 bytes . . . . .	908
Figure 345. Transfer sequence flowchart for I2C master receiver for N >255 bytes . . . . .	909

Figure 346. Transfer bus diagrams for I2C master receiver . . . . .	910
Figure 347. Timeout intervals for $t_{LOW:SEXT}$ , $t_{LOW:MEXT}$ . . . . .	915
Figure 348. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . .	919
Figure 349. Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . .	919
Figure 350. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . .	921
Figure 351. Bus transfer diagrams for SMBus slave receiver (SBC=1). . . . .	922
Figure 352. Bus transfer diagrams for SMBus master transmitter. . . . .	923
Figure 353. Bus transfer diagrams for SMBus master receiver. . . . .	925
Figure 354. USART block diagram . . . . .	952
Figure 355. Word length programming . . . . .	954
Figure 356. Configurable stop bits. . . . .	956
Figure 357. TC/TXE behavior when transmitting. . . . .	957
Figure 358. Start bit detection when oversampling by 16 or 8. . . . .	958
Figure 359. Data sampling when oversampling by 16. . . . .	962
Figure 360. Data sampling when oversampling by 8. . . . .	962
Figure 361. Mute mode using Idle line detection . . . . .	969
Figure 362. Mute mode using address mark detection . . . . .	970
Figure 363. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .	973
Figure 364. Break detection in LIN mode vs. Framing error detection. . . . .	974
Figure 365. USART example of synchronous transmission. . . . .	975
Figure 366. USART data clock timing diagram (M bits = 00). . . . .	975
Figure 367. USART data clock timing diagram (M bits = 01) . . . . .	976
Figure 368. RX data setup/hold time . . . . .	976
Figure 369. ISO 7816-3 asynchronous protocol . . . . .	978
Figure 370. Parity error detection using the 1.5 stop bits . . . . .	979
Figure 371. IrDA SIR ENDEC- block diagram . . . . .	983
Figure 372. IrDA data modulation (3/16) -Normal Mode . . . . .	984
Figure 373. Transmission using DMA . . . . .	985
Figure 374. Reception using DMA. . . . .	986
Figure 375. Hardware flow control between 2 USARTs . . . . .	986
Figure 376. RS232 RTS flow control . . . . .	987
Figure 377. RS232 CTS flow control . . . . .	988
Figure 378. USART interrupt mapping diagram . . . . .	991
Figure 379. SPI block diagram. . . . .	1016
Figure 380. Full-duplex single master/ single slave application. . . . .	1017
Figure 381. Half-duplex single master/ single slave application . . . . .	1018
Figure 382. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . .	1019
Figure 383. Master and three independent slaves. . . . .	1020
Figure 384. Multi-master application . . . . .	1021
Figure 385. Hardware/software slave select management . . . . .	1022
Figure 386. Data clock timing diagram . . . . .	1023
Figure 387. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .	1024
Figure 388. Packing data in FIFO for transmission and reception. . . . .	1028
Figure 389. Master full-duplex communication . . . . .	1031
Figure 390. Slave full-duplex communication . . . . .	1032
Figure 391. Master full-duplex communication with CRC . . . . .	1033
Figure 392. Master full-duplex communication in packed mode . . . . .	1034
Figure 393. NSSP pulse generation in Motorola SPI master mode. . . . .	1037
Figure 394. TI mode transfer . . . . .	1038
Figure 395. CAN network topology . . . . .	1051
Figure 396. Single-CAN block diagram . . . . .	1052

Figure 397. bxCAN operating modes. . . . .	1054
Figure 398. bxCAN in silent mode . . . . .	1055
Figure 399. bxCAN in loop back mode . . . . .	1055
Figure 400. bxCAN in combined mode . . . . .	1056
Figure 401. Transmit mailbox states . . . . .	1057
Figure 402. Receive FIFO states . . . . .	1058
Figure 403. Filter bank scale configuration - register organization . . . . .	1061
Figure 404. Example of filter numbering . . . . .	1062
Figure 405. Filtering mechanism - example. . . . .	1063
Figure 406. CAN error state diagram. . . . .	1064
Figure 407. Bit timing . . . . .	1066
Figure 408. CAN frames . . . . .	1067
Figure 409. Event flags and interrupt generation. . . . .	1068
Figure 410. CAN mailbox registers . . . . .	1079
Figure 411. Block diagram of STM32 MCU and Cortex ^®-M4-level debug support . . . . .	1094
Figure 412. SWJ debug port . . . . .	1096
Figure 413. JTAG TAP connections . . . . .	1100

RM0364-STM32F334

Contents

List of tables

List of figures

Chapters

RM0364-STM32F334

Related documents

Contents

List of tables

List of figures

Chapters