15. Basic timer (TIM6/TIM7)

The block diagram illustrates the internal architecture of the basic timer TIM6/TIM7. The main components are:

• TIMxCLK from RCC : The input clock signal that feeds into the Trigger controller .
• Internal clock (CK_INT) : The output of the Trigger controller.
• Trigger controller : A block that receives TIMxCLK and provides Reset, enable, Count signals to the counter.
• CK_PSC : The clock signal for the prescaler.
• PSC prescaler : A block that divides the CK_PSC frequency to produce CK_CNT .
• CNT counter : A 16-bit upcounter that receives CK_CNT and control signals from the Trigger controller.
• Auto-reload register : A register that provides the reload value to the counter. It has a U (Update) input and a UI (Update Interrupt) output.
• Stop, clear or up : Control signals from the counter to the Auto-reload register.

Notes:

• Reg : Preload registers transferred to active registers on U event according to control bit.
• Event : Indicated by a lightning bolt symbol.
• Interrupt & DMA output : Indicated by a jagged line symbol.

MS32645V1

This timing diagram illustrates the behavior of a basic timer when the prescaler division is changed from 1 to 2. The signals shown are:

• CK_PSC : Prescaler clock signal, a continuous square wave.
• CEN : Counter enable signal, which goes high to enable counting.
• Timerclock = CK_CNT : The clock signal for the counter, derived from CK_PSC. Its frequency changes when the prescaler division changes.
• Counter register : Shows hexadecimal values F7, F8, F9, FA, FB, FC, followed by 00, 01, 02, 03. The counter rolls over from FC to 00 when the Update event (UEV) occurs.
• Update event (UEV) : A pulse generated when the counter reaches its maximum value (FC) and rolls over to 00.
• Prescaler control register : Shows a value of 0 initially. An arrow labeled "Write a new value in TIMx_PSC" points to a change to value 1.
• Prescaler buffer : A buffer register that latches the new prescaler value (1) from the control register.
• Prescaler counter : A counter that divides the CK_PSC frequency. It counts from 0 to 1 (which corresponds to a division of 2) after the prescaler value is updated.

The diagram shows that after writing a new value (1) to the prescaler control register, the prescaler buffer updates to 1, and the prescaler counter begins counting from 0 to 1. The timerclock (CK_CNT) frequency is halved after the update. The counter register continues to count from 00 upwards. The identifier MS31076V2 is present in the bottom right corner.

This timing diagram illustrates the behavior of a basic timer when the prescaler division is changed from 1 to 4. The signals shown are:

• CK_PSC : Prescaler clock signal, a continuous square wave.
• CEN : Counter enable signal, which goes high to enable counting.
• Timerclock = CK_CNT : The clock signal for the counter, derived from CK_PSC. Its frequency changes when the prescaler division changes.
• Counter register : Shows hexadecimal values F7, F8, F9, FA, FB, FC, followed by 00, 01. The counter rolls over from FC to 00 when the Update event (UEV) occurs.
• Update event (UEV) : A pulse generated when the counter reaches its maximum value (FC) and rolls over to 00.
• Prescaler control register : Shows a value of 0 initially. An arrow labeled "Write a new value in TIMx_PSC" points to a change to value 3.
• Prescaler buffer : A buffer register that latches the new prescaler value (3) from the control register.
• Prescaler counter : A counter that divides the CK_PSC frequency. It counts from 0 to 3 (which corresponds to a division of 4) after the prescaler value is updated.

The diagram shows that after writing a new value (3) to the prescaler control register, the prescaler buffer updates to 3, and the prescaler counter begins counting from 0 to 3. The timerclock (CK_CNT) frequency is divided by 4 after the update. The counter register continues to count from 00 upwards. The identifier MS31077V2 is present in the bottom right corner.

The timing diagram illustrates the operation of a basic timer. The top signal, CK_PSC, is a periodic square wave representing the prescaler clock. Below it, CNT_EN is a signal that goes high to enable the counter. When CNT_EN is high, the Timerclock = CK_CNT signal is a square wave with a frequency that is a fraction of CK_PSC. The Counter register is shown as a sequence of values: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. The counter increments by 1 at each rising edge of CK_CNT. When the counter reaches 36 (0x24), it overflows to 00. This overflow generates a pulse on the Counter overflow signal. Simultaneously, an Update event (UEV) is generated, shown as a pulse. Finally, the Update interrupt flag (UIF) is set, shown as a signal that goes high at the overflow point.

This timing diagram illustrates the operation of a basic timer with the internal clock divided by 2. The top signal, CK_PSC, is a periodic square wave. Below it, CNT_EN is a high-level enable signal. The Timerclock (CK_CNT) is derived from CK_PSC and has a frequency half that of CK_PSC. The Counter register shows a sequence of values: 0034, 0035, 0036, 0000, 0001, 0002, and 0003. Vertical dashed lines indicate key timing points: the first at the rising edge of CK_PSC when CNT_EN goes high; the second at the rising edge of CK_CNT following the count of 0036; and the third at the subsequent rising edge of CK_CNT. At the second dashed line, the Counter overflow, Update event (UEV), and Update interrupt flag (UIF) signals all transition from low to high. These signals remain high until the third dashed line, where they all transition back to low.

This timing diagram illustrates the operation of a basic timer with the internal clock divided by 4. The signals CK_PSC, CNT_EN, Counter register, Counter overflow, Update event (UEV), and Update interrupt flag (UIF) follow similar patterns to Figure 143. However, the Timerclock (CK_CNT) has a frequency one-quarter that of CK_PSC. The Counter register shows values 0035, 0036, 0000, and 0001. Vertical dashed lines indicate key timing points: the first at the rising edge of CK_PSC when CNT_EN goes high; the second at the rising edge of CK_CNT following the count of 0036; and the third at the subsequent rising edge of CK_CNT. At the second dashed line, the Counter overflow, Update event (UEV), and Update interrupt flag (UIF) signals all transition from low to high and remain high until the third dashed line, where they transition back to low.

This timing diagram illustrates the operation of a basic timer with an internal clock divided by N. The top signal is CK_PSC, a periodic square wave. Below it, Timerclock = CK_CNT is shown as a series of pulses, with a break indicating a change in frequency. The Counter register is shown in three states: 1F, 20, and 00. Vertical dashed lines indicate the relationship between the clock and the counter values. The Counter overflow signal is a pulse that occurs when the counter reaches 00. The Update event (UEV) and Update interrupt flag (UIF) are also shown as pulses that coincide with the counter overflow. The diagram is labeled MS31081V2 in the bottom right corner.

This timing diagram shows the counter operation when ARPE = 0 and the TIMx_ARR register is not preloaded. The signals shown are CK_PSC, CEN (Counter Enable), Timerclock = CK_CNT, Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), and Auto-reload preload register. The counter register values are shown as 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. The Counter overflow and Update event (UEV) occur when the counter reaches 36. The Update interrupt flag (UIF) is set at this time. The Auto-reload preload register is shown with values FF and 36. A note indicates that a new value should be written in TIMx_ARR. The diagram is labeled MS31082V2 in the bottom right corner.

The timing diagram illustrates the operation of a basic timer (TIM6/TIM7) when ARPE=1 and the auto-reload register (TIMx_ARR) is preloaded. The diagram shows the following signals and their timing relationships:

• CK_PSC: Prescaler clock signal, shown as a continuous square wave.
• CEN: Counter Enable signal. It is initially low and goes high at the first vertical dashed line.
• Timerclock = CK_CNT: The clock signal for the counter, which is derived from CK_PSC. It starts at the first vertical dashed line.
• Counter register: Shows the sequence of counter values: F0, F1, F2, F3, F4, F5, 00, 01, 02, 03, 04, 05, 06, 07. The values F0 through F5 are shown before the first vertical dashed line. The values 00 through 07 are shown after the second vertical dashed line.
• Counter overflow: A signal that goes high when the counter reaches 00 (at the second vertical dashed line).
• Update event (UEV): A signal that goes high when the counter reaches 00 (at the second vertical dashed line).
• Update interrupt flag (UIF): A signal that goes high when the counter reaches 00 (at the second vertical dashed line).
• Auto-reload preload register: Shows the value F5 before the first vertical dashed line. At the first vertical dashed line, a new value of 36 is written. This value remains until the second vertical dashed line.
• Auto-reload shadow register: Shows the value F5 before the first vertical dashed line. At the first vertical dashed line, the value F5 is updated. At the second vertical dashed line, the value 36 is loaded into the shadow register.

An arrow labeled "Write a new value in TIMx_ARR" points to the transition of the Auto-reload preload register at the first vertical dashed line. The diagram is identified by the code MS31083V2 in the bottom right corner.

The diagram illustrates the timing relationships between several signals over time. The 'Internal clock' is a continuous square wave. The 'CEN=CNT_EN' signal is initially low and transitions to high at a certain point. The 'UG' signal is initially low and transitions to high after the CEN signal goes high. The 'CNT_INIT' signal is initially high and transitions to low after the UG signal goes high. The 'Counter clock = CK_CNT = CK_PSC' signal is initially low and transitions to a square wave after the CEN signal goes high. The 'Counter register' shows a sequence of values: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. Vertical dashed lines indicate the timing of the signal transitions and counter increments.

MS31085V2