12. Analog-to-digital converter (ADC)

12.1 Introduction

The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 18 multiplexed channels allowing it to measure signals from 16 external and 2 internal sources. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit data register.

The analog watchdog feature allows the application to detect if the input voltage goes outside the user-defined higher or lower thresholds.

An efficient low-power mode is implemented to allow very low consumption at low frequency.

12.2 ADC main features

• High performance
- – 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
- – ADC conversion time: 1.0 µs for 12-bit resolution (1 MHz), 0.93 µs conversion time for 10-bit resolution, faster conversion times can be obtained by lowering resolution.
- – Self-calibration
- – Programmable sampling time
- – Data alignment with built-in data coherency
- – DMA support
• Low-power
- – The application can reduce PCLK frequency for low-power operation while still keeping optimum ADC performance. For example, 1.0 µs conversion time is kept, whatever the PCLK frequency
- – Wait mode: prevents ADC overrun in applications with low PCLK frequency
- – Auto off mode: ADC is automatically powered off except during the active conversion phase. This dramatically reduces the power consumption of the ADC.
• Analog input channels
- – 16 external analog inputs
- – 1 channel for internal temperature sensor ( $V_{\text{SENSE}}$ )
- – 1 channel for internal reference voltage ( $V_{\text{REFINT}}$ )
• Start-of-conversion can be initiated:
- – By software
- – By hardware triggers with configurable polarity (timer events)
• Conversion modes
- – Can convert a single channel or can scan a sequence of channels.
- – Single mode converts selected inputs once per trigger
- – Continuous mode converts selected inputs continuously
- – Discontinuous mode
• Interrupt generation at the end of sampling, end of conversion, end of sequence conversion, and in case of analog watchdog or overrun events
• Analog watchdog
• ADC input range: $V_{\text{SSA}} \leq V_{\text{IN}} \leq V_{\text{DDA}}$

12.3 ADC functional description

Figure 23 shows the ADC block diagram and Table 33 gives the ADC pin description.

Figure 23. ADC block diagram

The block diagram illustrates the internal architecture of the ADC. At the core is the SAR ADC, which receives analog input from ADC_IN[15:0] through an input selection & scan control block. This block also takes V_REF and V_TS as inputs. The SAR ADC is controlled by a Start & Stop control block (with ADSTART S/W trigger and AUTLDLY auto-delayed conv. ADSTP) and a sampling time control (SMP[2:0]). The ADC output is DATA[11:0], which is sent to an APB interface. The APB interface connects to an IRQ CPU and a DMA via master/slave interfaces. The APB interface also includes control signals like AREADY, EOSMP, EOEQ, EOC, OVR, and AWD. The AWD (Analog Watchdog) is connected to an AWDx Analog watchdog block with inputs AWDxEN, AWDxSGL, AWDCHx[4:0], LTx[11:0], and HTx[11:0]. The SAR ADC also receives configuration from OVRMOD, ALIGN, and RSE[1:0] (12, 10, 8, 6 bits). The ADC is powered by VDDA (Analog supply 2.4 V to 3.6 V) and VSSA. The diagram also shows various internal signals like SCANDIR, CH_SEL[18:0], CONT, ADEN/ADDIS, AUTOFF, ADCAL, and DISCEN. External triggers for the ADC are provided by TIM1_TRGO, TIM1_CC4, TIM2_TRGO, TIM3_TRGO, and TIM15_TRGO, which are processed through an EXTEN[1:0] trigger enable and edge selection block and an EXTSEL[2:0] trigger selection block.

ADC block diagram showing internal components like SAR ADC, input selection, start & stop control, and external connections to CPU, DMA, and watchdog.

12.3.1 ADC pins and internal signals

Table 33. ADC input/output pins

Name	Signal type	Remarks
VDDA	Input, analog power supply	Analog power supply and positive reference voltage for the ADC
VSSA	Input, analog supply ground	Ground for analog power supply
ADC_INx	Analog input signals	16 external analog input channels

Table 34. ADC internal input/output signals

Internal signal name	Signal type	Description
V _IN[x]	Analog Input channels	Connected either to internal channels or to ADC_INi external channels
TRGx	Input	ADC conversion triggers
V _SENSE	Input	Internal temperature sensor output voltage
V _REFINT	Input	Internal voltage reference output voltage
ADC_AWDx_OUT	Output	Internal analog watchdog output signal connected to on-chip timers (x = Analog watchdog number = 1)

Table 35. External triggers

Name	Source	EXTSEL[2:0]
TRG0	TIM1_TRGO	000
TRG1	TIM1_CC4	001
TRG2	TIM2_TRGO	010
TRG3	TIM3_TRGO	011
TRG4	TIM15_TRGO	100
TRG5	Reserved	101
TRG6	Reserved	110
TRG7	Reserved	111

12.3.2 Calibration (ADCAL)

The ADC has a calibration feature. During the calibration phase, the ADC calculates a calibration factor which is internally applied to the ADC until the next ADC power-off. The application must not use the ADC during calibration and must wait until it is complete.

Calibration should be performed before starting A/D conversion. It removes the offset error which may vary from chip to chip due to process variation.

The calibration is initiated by software by setting ADCAL bit to 1. It can only be initiated when the ADC is disabled (when ADEN = 0). ADCAL bit stays at 1 during the whole calibration sequence. It is then cleared by hardware as soon as the calibration completes. After this, the calibration factor can be read from the ADC_DR register (from bits 6 to 0).

The internal analog calibration is kept if the ADC is disabled (ADEN = 0). When the ADC operating conditions change (V _DDAchanges are the main contributor to ADC offset variations and temperature change to a lesser extent), it is recommended to re-run a calibration cycle.

The calibration factor is lost each time power is removed from the ADC (for example when the product enters Standby mode).

Calibration software procedure

1. Ensure that ADEN = 0 and DMAEN = 0.
2. Set ADCAL = 1.
3. Wait until ADCAL = 0.
4. The calibration factor can be read from bits 6:0 of ADC_DR .

For code example refer to the Appendix section A.7.1: ADC calibration .

Figure 24. ADC calibration

The diagram shows the timing relationship for ADC calibration. It includes three signals: ADCAL , ADC State , and ADC_DR[6:0] . ADCAL is set high by S/W and cleared by H/W. The ADC State transitions from OFF to Startup, then to CALIBRATE, and finally back to OFF. The ADC_DR[6:0] register holds 0x00 until the end of the CALIBRATE state, where it is updated with the CALIBRATION FACTOR. The duration from the rising edge of ADCAL to the end of the CALIBRATE state is labeled $t_{CAB}$ .

Figure 24: ADC calibration timing diagram

12.3.3 ADC on-off control (ADEN, ADDIS, ADRDY)

At power-up, the ADC is disabled and put in power-down mode ( ADEN = 0).

As shown in Figure 25 , the ADC needs a stabilization time of $t_{STAB}$ before it starts converting accurately.

Two control bits are used to enable or disable the ADC:

• Set ADEN = 1 to enable the ADC. The ADRDY flag is set as soon as the ADC is ready for operation.
• Set ADDIS = 1 to disable the ADC and put the ADC in power down mode. The ADEN and ADDIS bits are then automatically cleared by hardware as soon as the ADC is fully disabled.

Conversion can then start either by setting ADSTART to 1 (refer to Section 12.4: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) on page 193 ) or when an external trigger event occurs if triggers are enabled.

Follow this procedure to enable the ADC:

1. Clear the ADRDY bit in ADC_ISR register by programming this bit to 1.
2. Set ADEN = 1 in the ADC_CR register.
3. Wait until ADRDY = 1 in the ADC_ISR register and continue to write ADEN = 1 ( ADRDY is set after the ADC startup time). This can be handled by interrupt if the interrupt is enabled by setting the ADRDYIE bit in the ADC_IER register.

For code example refer to the Appendix section A.7.2: ADC enable sequence .

Follow this procedure to disable the ADC:

1. Check that ADSTART = 0 in the ADC_CR register to ensure that no conversion is ongoing. If required, stop any ongoing conversion by writing 1 to the ADSTP bit in the ADC_CR register and waiting until this bit is read at 0.
2. Set ADDIS = 1 in the ADC_CR register.
3. If required by the application, wait until ADEN = 0 in the ADC_CR register, indicating that the ADC is fully disabled (ADDIS is automatically reset once ADEN = 0).
4. Clear the ADRDY bit in ADC_ISR register by programming this bit to 1 (optional).

For code example refer to the Appendix section A.7.3: ADC disable sequence .

Caution: ADEN bit cannot be set when ADCAL = 1 and during four ADC clock cycles after the ADCAL bit is cleared by hardware (end of calibration).

Figure 25. Enabling/disabling the ADC

The diagram illustrates the timing for enabling and disabling the ADC. It shows four signal lines: ADEN, ADRDY, ADDIS, and ADC stat.
- ADEN : Set by software (S/W) to enable the ADC.
- ADRDY : Set by hardware (H/W) to indicate the ADC is ready. A time interval $t_{STAB}$ is shown between the rising edge of ADEN and the rising edge of ADRDY.
- ADDIS : Set by software to disable the ADC.
- ADC stat : Shows the state of the ADC: OFF, Startup, RDY, CONVERTING CH, RDY, REQ-OF, and OFF.
The diagram is labeled MS30264V2.

Timing diagram showing the sequence of events for enabling and disabling the ADC. The diagram plots four signals over time: ADEN, ADRDY, ADDIS, and ADC stat. ADEN is set by software (S/W) to enable the ADC. ADRDY is set by hardware (H/W) to indicate the ADC is ready. ADDIS is set by software to disable the ADC. The ADC stat shows phases: OFF, Startup, RDY, CONVERTING CH, RDY, REQ-OF, and OFF. A time interval tSTAB is shown between ADEN and ADRDY. The diagram is labeled MS30264V2.

Note: In Auto-off mode (AUTOFF = 1) the power-on/off phases are performed automatically, by hardware and the ADRDY flag is not set.

When the bus clock is much faster than the analog ADC_CK clock, a minimum delay of ten analog ADC_CK cycles must be respected between ADEN and ADDIS bit settings.

12.3.4 ADC clock (CKMODE)

The ADC has a dual clock-domain architecture, so that the ADC can be fed with a clock (ADC asynchronous clock) independent from the APB clock (PCLK).

Figure 26. ADC clock scheme

Figure 26. ADC clock scheme diagram. The diagram shows the RCC (Reset & Clock Controller) providing two clock inputs to the ADC: PCLK and an ADC asynchronous clock. The PCLK is connected to the APB interface and also to a divider block labeled '/2 or /4'. The output of this divider is connected to a multiplexer labeled 'Others'. The ADC asynchronous clock is also connected to this multiplexer. The multiplexer is controlled by bits CKMODE[1:0] of the ADC_CFGR2 register. The output of the multiplexer is labeled 'Analog ADC_CK' and is connected to the Analog ADC block. The APB interface is also connected to the ADC_CFGR2 register. The diagram is labeled MSv31473V2 in the bottom right corner.

1. Refer to Section Reset and clock control (RCC) for how the PCLK clock and ADC asynchronous clock are enabled.

The input clock of the analog ADC can be selected between two different clock sources (see Figure 26: ADC clock scheme to see how the PCLK clock and the ADC asynchronous clock are enabled):

a) The ADC clock can be a specific clock source, named “ADC asynchronous clock” which is independent and asynchronous with the APB clock.

Refer to RCC Section for more information on generating this clock source.

To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be reset.

For code example refer to the Appendix section A.7.4: ADC clock selection .

b) The ADC clock can be derived from the APB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4) according to bits CKMODE[1:0].

To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be different from “00”.

Option a) has the advantage of reaching the maximum ADC clock frequency whatever the APB clock scheme selected.

Option b) has the advantage of bypassing the clock domain resynchronizations. This can be useful when the ADC is triggered by a timer and if the application requires that the ADC is precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is added by the resynchronizations between the two clock domains).

Table 36. Latency between trigger and start of conversion ⁽¹⁾

ADC clock source	CKMODE[1:0]	Latency between the trigger event and the start of conversion
Dedicated 14MHz clock	00	Latency is not deterministic (jitter)
PCLK divided by 2	01	Latency is deterministic (no jitter) and equal to 2.75 ADC clock cycles
PCLK divided by 4	10	Latency is deterministic (no jitter) and equal to 2.625 ADC clock cycles

1. Refer to the device datasheet for the maximum ADC_CLK frequency.

12.3.5 Configuring the ADC

The software must write the ADCAL and ADEN bits in the ADC_CR register only when the ADC is disabled (ADEN cleared).

The software must only write to the ADSTART and ADDIS bits in the ADC_CR register only if the ADC is enabled and there is no pending request to disable the ADC (ADEN = 1 and ADDIS = 0).

For all the other control bits in the ADC_IER, ADC_CFGRi, ADC_SMPR, ADC_TR, ADC_CHSELR and ADC_CCR registers, refer to the description of the corresponding control bit in Section 12.10: ADC registers .

The software must only write to the ADSTP bit in the ADC_CR register if the ADC is enabled (and possibly converting) and there is no pending request to disable the ADC (ADSTART = 1 and ADDIS = 0).

Note: There is no hardware protection preventing software from making write operations forbidden by the above rules. If such a forbidden write access occurs, the ADC may enter an undefined state. To recover correct operation in this case, the ADC must be disabled (clear ADEN = 0 and all the bits in the ADC_CR register).

12.3.6 Channel selection (CHSEL, SCANDIR)

There are up to 18 multiplexed channels:

• 16 analog inputs from GPIO pins (ADC_INx)
• 2 internal analog inputs (temperature sensor, internal reference voltage)

It is possible to convert a single channel or a sequence of channels.

The sequence of the channels to be converted can be programmed in the ADC_CHSELR channel selection register: each analog input channel has a dedicated selection bit (CHSELx).

The order in which the channels is scanned can be configured by programming the bit SCANDIR bit in the ADC_CFGR1 register:

• SCANDIR = 0: forward scan Channel 0 to Channel 17
• SCANDIR = 1: backward scan Channel 17 to Channel 0

Temperature sensor, V _REFINTinternal channels

The temperature sensor is connected to channel ADC V _IN[16].

The internal voltage reference $V_{REFINT}$ is connected to channel ADC $V_{IN}[17]$ .

12.3.7 Programmable sampling time (SMP)

Before starting a conversion, the ADC needs to establish a direct connection between the voltage source to be measured and the embedded sampling capacitor of the ADC. This sampling time must be enough for the input voltage source to charge the sample and hold capacitor to the input voltage level.

Having a programmable sampling time allows the conversion speed to be trimmed according to the input resistance of the input voltage source.

The ADC samples the input voltage for a number of ADC clock cycles that can be modified using the SMP[2:0] bits in the ADC_SMPR register.

This programmable sampling time is common to all channels. If required by the application, the software can change and adapt this sampling time between each conversions.

The total conversion time is calculated as follows:

t_{CONV} = \text{Sampling time} + 12.5 \times \text{ADC clock cycles}

Example:

With $ADC\_CLK = 14$ MHz and a sampling time of 1.5 ADC clock cycles:

t_{CONV} = 1.5 + 12.5 = 14 \text{ ADC clock cycles} = 1 \mu\text{s}

The ADC indicates the end of the sampling phase by setting the EOSMP flag.

12.3.8 Single conversion mode (CONT = 0)

In Single conversion mode, the ADC performs a single sequence of conversions, converting all the channels once. This mode is selected when $$ CONT = 0 $$ in the ADC_CFGR1 register. Conversion is started by either:

• Setting the ADSTART bit in the ADC_CR register
• Hardware trigger event

Inside the sequence, after each conversion is complete:

• The converted data are stored in the 16-bit ADC_DR register
• The EOC (end of conversion) flag is set
• An interrupt is generated if the EOCIE bit is set

After the sequence of conversions is complete:

• The EOS (end of sequence) flag is set
• An interrupt is generated if the EOSIE bit is set

Then the ADC stops until a new external trigger event occurs or the ADSTART bit is set again.

Note: To convert a single channel, program a sequence with a length of 1.

12.3.9 Continuous conversion mode (CONT = 1)

In continuous conversion mode, when a software or hardware trigger event occurs, the ADC performs a sequence of conversions, converting all the channels once and then automatically re-starts and continuously performs the same sequence of conversions. This mode is selected when CONT = 1 in the ADC_CFGR1 register. Conversion is started by either:

• Setting the ADSTART bit in the ADC_CR register
• Hardware trigger event

Inside the sequence, after each conversion is complete:

• The converted data are stored in the 16-bit ADC_DR register
• The EOC (end of conversion) flag is set
• An interrupt is generated if the EOCIE bit is set

After the sequence of conversions is complete:

• The EOS (end of sequence) flag is set
• An interrupt is generated if the EOSIE bit is set

Then, a new sequence restarts immediately and the ADC continuously repeats the conversion sequence.

Note: To convert a single channel, program a sequence with a length of 1.

It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.

12.3.10 Starting conversions (ADSTART)

Software starts ADC conversions by setting ADSTART = 1.

When ADSTART is set, the conversion:

• Starts immediately if EXTEN = 00 (software trigger)
• At the next active edge of the selected hardware trigger if EXTEN ≠ 00

The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing. It is possible to re-configure the ADC while ADSTART = 0, indicating that the ADC is idle.

The ADSTART bit is cleared by hardware:

• In single mode with software trigger (CONT = 0, EXTEN = 00)
- – At any end of conversion sequence (EOS = 1)
• In discontinuous mode with software trigger (CONT = 0, DISCEN = 1, EXTEN = 00)
- – At end of conversion (EOC = 1)
• In all cases (CONT = x, EXTEN = XX)
- – After execution of the ADSTP procedure invoked by software (see Section 12.3.12: Stopping an ongoing conversion (ADSTP) on page 193 )

Note: In continuous mode (CONT = 1), the ADSTART bit is not cleared by hardware when the EOS flag is set because the sequence is automatically relaunched.

When hardware trigger is selected in single mode (CONT = 0 and EXTEN = 01), ADSTART is not cleared by hardware when the EOS flag is set (except if DMAEN = 1 and DMACFG = 0 in which case ADSTART is cleared at end of the DMA transfer). This avoids

the need for software having to set the ADSTART bit again and ensures the next trigger event is not missed.

12.3.11 Timings

The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution:

t_{CONV} = t_{SMPL} + t_{SAR} = [1.5 \text{ } \mu\text{s}_{min} + 12.5 \text{ } \mu\text{s}_{12bit}] \times t_{ADC\_CLK}

t_{CONV} = t_{SMPL} + t_{SAR} = 107.1 \text{ ns}_{min} + 892.8 \text{ ns}_{12bit} = 1 \text{ } \mu\text{s}_{min} \text{ (for } f_{ADC\_CLK} = 14 \text{ MHz)}

Figure 27. Analog to digital conversion time

The diagram shows the timing of an ADC conversion. The ADC state transitions from RDY to SAMPLING CH(N), then to CONVERTING CH(N), and finally to SAMPLING CH(N+1). The Analog channel is shown for CH(N) and CH(N+1). The Internal S/H signal shows Sample AIN(N+1) and Hold AIN(N) phases. ADSTART is set by software. EOSMP is set by hardware and cleared by software. EOC is set by hardware and cleared by software. ADC_DR shows DATA N-1 and DATA N. Notes: (1) t _SMPLdepends on SMP[2:0]; (2) t _SARdepends on RES[2:0]. MS30336V1

Timing diagram for Figure 27 showing ADC state, Analog channel, Internal S/H, ADSTART, EOSMP, EOC, and ADC_DR signals over time. It illustrates the sampling and converting phases for channels N and N+1.

Figure 28. ADC conversion timings

The diagram shows the timing of ADC conversions. ADSTART ⁽¹⁾is shown with a trigger latency ⁽²⁾to the start of the first conversion. The ADC state sequence is Ready, S0, Conversion 0, S1, Conversion 1, S2, Conversion 2, S3, Conversion 3. ADC_DR shows Data 0, Data 1, and Data 2 with write latency ⁽³⁾W _LATENCY. MSV33174V1

Timing diagram for Figure 28 showing ADSTART, ADC state, and ADC_DR signals. It details the latency from ADSTART to the start of conversion and the write latency for the ADC_DR register.

1. EXTEN = 00 or EXTEN ≠ 00
2. Trigger latency (refer to datasheet for more details)
3. ADC_DR register write latency (refer to datasheet for more details)

12.3.12 Stopping an ongoing conversion (ADSTP)

The software can decide to stop any ongoing conversions by setting ADSTP = 1 in the ADC_CR register.

This resets the ADC operation and the ADC is idle, ready for a new operation.

When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is discarded (ADC_DR register is not updated with the current conversion).

The scan sequence is also aborted and reset (meaning that restarting the ADC would restart a new sequence).

Once this procedure is complete, the ADSTP and ADSTART bits are both cleared by hardware and the software must wait until ADSTART=0 before starting new conversions.

Figure 29. Stopping an ongoing conversion

The diagram illustrates the timing for stopping an ongoing conversion. The top line represents the ADC state, which transitions from RDY to SAMPLING CH(N), then to CONVERTING CH(N), and finally back to RDY. The ADSTART signal is set by software at the beginning of the sequence and is cleared by hardware when the ADC returns to the RDY state. The ADSTOP signal is set by software while the ADC is in the CONVERTING CH(N) state and is also cleared by hardware when the ADC returns to the RDY state. The ADC_DR register holds the data from the previous conversion (DATA N-1) during the current conversion process.

Timing diagram showing the sequence of events to stop an ongoing conversion. The diagram shows four horizontal lines: ADC state, ADSTART, ADSTOP, and ADC_DR. The ADC state starts at RDY, goes to SAMPLING CH(N), then CONVERTING CH(N), and returns to RDY. ADSTART is set by software at the start of the conversion sequence and cleared by hardware when the ADC returns to RDY. ADSTOP is set by software while the ADC is in the CONVERTING CH(N) state and is cleared by hardware when the ADC returns to RDY. The ADC_DR register contains DATA N-1 during the conversion.

12.4 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN)

A conversion or a sequence of conversion can be triggered either by software or by an external event (for example timer capture). If the EXTEN[1:0] control bits are not equal to “0b00”, then external events are able to trigger a conversion with the selected polarity. The trigger selection is effective once software has set bit ADSTART = 1.

Any hardware triggers which occur while a conversion is ongoing are ignored.

If bit ADSTART = 0, any hardware triggers which occur are ignored.

Table 37 provides the correspondence between the EXTEN[1:0] values and the trigger polarity.

Table 37. Configuring the trigger polarity

Source	EXTEN[1:0]
Trigger detection disabled	00
Detection on rising edge	01
Detection on falling edge	10
Detection on both rising and falling edges	11

Note: The polarity of the external trigger can be changed only when the ADC is not converting (ADSTART = 0).

The EXTSEL[2:0] control bits are used to select which of 8 possible events can trigger conversions.

Refer to Table 35: External triggers in Section 12.3.1: ADC pins and internal signals for the list of all the external triggers that can be used for regular conversion.

The software source trigger events can be generated by setting the ADSTART bit in the ADC_CR register.

Note: The trigger selection can be changed only when the ADC is not converting (ADSTART = 0).

12.4.1 Discontinuous mode (DISCEN)

This mode is enabled by setting the DISCEN bit in the ADC_CFGR1 register.

In this mode (DISCEN = 1), a hardware or software trigger event is required to start each conversion defined in the sequence. On the contrary, if DISCEN = 0, a single hardware or software trigger event successively starts all the conversions defined in the sequence.

Example:

• DISCEN = 1, channels to be converted = 0, 3, 7, 10
- – 1st trigger: channel 0 is converted and an EOC event is generated
- – 2nd trigger: channel 3 is converted and an EOC event is generated
- – 3rd trigger: channel 7 is converted and an EOC event is generated
- – 4th trigger: channel 10 is converted and both EOC and EOS events are generated.
- – 5th trigger: channel 0 is converted an EOC event is generated
- – 6th trigger: channel 3 is converted and an EOC event is generated
- – ...
• DISCEN = 0, channels to be converted = 0, 3, 7, 10
- – 1st trigger: the complete sequence is converted: channel 0, then 3, 7 and 10. Each conversion generates an EOC event and the last one also generates an EOS event.
- – Any subsequent trigger events restarts the complete sequence.

Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.

12.4.2 Programmable resolution (RES) - Fast conversion mode

It is possible to obtain faster conversion times ( $t_{SAR}$ ) by reducing the ADC resolution.

The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the RES[1:0] bits in the ADC_CFGR1 register. Lower resolution allows faster conversion times for applications where high data precision is not required.

Note: The RES[1:0] bit must only be changed when the ADEN bit is reset.

The result of the conversion is always 12 bits wide and any unused LSB bits are read as zeros.

Lower resolution reduces the conversion time needed for the successive approximation steps as shown in Table 38 .

Table 38.

t_{SAR}

timings depending on resolution

RES[1:0] bits	$t_{SAR}$ (ADC clock cycles)	$t_{SAR}$ (ns) at $f_{ADC} = 14$ MHz	$t_{SMPL}$ (min) (ADC clock cycles)	$t_{CONV}$ (ADC clock cycles) (with min. $t_{SMPL}$ )	$t_{CONV}$ (ns) at $f_{ADC} = 14$ MHz
12	12.5	893	1.5	14	1000
10	11.5	821	1.5	13	928
8	9.5	678	1.5	11	785
6	7.5	535	1.5	9	643

12.4.3 End of conversion, end of sampling phase (EOC, EOSMP flags)

The ADC indicates each end of conversion (EOC) event.

The ADC sets the EOC flag in the ADC_ISR register as soon as a new conversion data result is available in the ADC_DR register. An interrupt can be generated if the EOCIE bit is set in the ADC_IER register. The EOC flag is cleared by software either by writing 1 to it, or by reading the ADC_DR register.

The ADC also indicates the end of sampling phase by setting the EOSMP flag in the ADC_ISR register. The EOSMP flag is cleared by software by writing 1 to it. An interrupt can be generated if the EOSMPIE bit is set in the ADC_IER register.

The aim of this interrupt is to allow the processing to be synchronized with the conversions. Typically, an analog multiplexer can be accessed in hidden time during the conversion phase, so that the multiplexer is positioned when the next sampling starts.

Note: As there is only a very short time left between the end of the sampling and the end of the conversion, it is recommenced to use polling or a WFE instruction rather than an interrupt and a WFI instruction.

12.4.4 End of conversion sequence (EOS flag)

The ADC notifies the application of each end of sequence (EOS) event.

The ADC sets the EOS flag in the ADC_ISR register as soon as the last data result of a conversion sequence is available in the ADC_DR register. An interrupt can be generated if the EOSIE bit is set in the ADC_IER register. The EOS flag is cleared by software by writing 1 to it.

12.4.5 Example timing diagrams (single/continuous modes hardware/software triggers)

Figure 30. Single conversions of a sequence, software trigger

Timing diagram for Figure 30: Single conversions of a sequence, software trigger. Shows ADSTART(1), EOC, EOS, SCANDIR, ADC state(2), and ADC_DR. ADSTART is triggered by software (up arrow) and hardware (down arrow). EOC pulses for each conversion. EOS pulses after the last conversion in a sequence. SCANDIR changes state. ADC state transitions through RDY, CH0, CH9, CH10, CH17, RDY, CH17, CH10, CH9, CH0, RDY. ADC_DR captures data D0, D9, D10, D17, D17, D10, D9, D0.

1. EXTEN = 00, CONT = 0
2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0

For code example refer to the Appendix section A.7.5: Single conversion sequence - software trigger .

Figure 31. Continuous conversion of a sequence, software trigger

Timing diagram for Figure 31: Continuous conversion of a sequence, software trigger. Shows ADSTART(1), EOC, EOS, ADSTP, SCANDIR, ADC state(2), and ADC_DR. ADSTART is triggered by software. EOC pulses for each conversion. EOS pulses after each full sequence. ADSTP is used to stop conversion. ADC state transitions through RDY, CH0, CH9, CH10, CH17, CH0, CH9, CH10, STP, RDY, CH17, CH10. ADC_DR captures data D0, D9, D10, D17, D0, D9, D17.

1. EXTEN = 00, CONT = 1,
2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0

For code example refer to the Appendix section A.7.6: Continuous conversion sequence - software trigger .

Figure 32. Single conversions of a sequence, hardware trigger

Timing diagram for single conversions of a sequence with hardware trigger. The diagram shows the relationship between ADSTART, EOC, EOS, TRGx, ADC state, and ADC_DR signals over time. ADSTART is a software trigger (rising edge). EOC pulses for each conversion. EOS pulses at the end of the sequence. TRGx is a hardware trigger (rising edge) that starts the sequence. ADC state shows RDY, CH0, CH1, CH2, CH3, RDY, CH0, CH1, CH2, CH3, RDY. ADC_DR shows data D0, D1, D2, D3, D0, D1, D2, D3.

Timing diagram for single conversions of a sequence, hardware trigger. The diagram shows the relationship between ADSTART, EOC, EOS, TRGx, ADC state, and ADC_DR signals over time.

ADSTART ⁽¹⁾: Software trigger (rising edge).
EOC : End of Conversion pulses for each conversion.
EOS : End of Sequence pulses at the end of the sequence.
TRGx ⁽¹⁾: Hardware trigger (rising edge) that starts the sequence.
ADC state ⁽²⁾: Shows the sequence of conversions: RDY, CH0, CH1, CH2, CH3, RDY, CH0, CH1, CH2, CH3, RDY.
ADC_DR : Data register showing D0, D1, D2, D3, D0, D1, D2, D3.

Legend:

by S/W (Software): rising edge
by H/W (Hardware): rising edge
triggered: rising edge
ignored: falling edge

MSv30340V2

Timing diagram for single conversions of a sequence with hardware trigger. The diagram shows the relationship between ADSTART, EOC, EOS, TRGx, ADC state, and ADC_DR signals over time. ADSTART is a software trigger (rising edge). EOC pulses for each conversion. EOS pulses at the end of the sequence. TRGx is a hardware trigger (rising edge) that starts the sequence. ADC state shows RDY, CH0, CH1, CH2, CH3, RDY, CH0, CH1, CH2, CH3, RDY. ADC_DR shows data D0, D1, D2, D3, D0, D1, D2, D3.

1. EXTSEL = TRGx (over-frequency), EXTEN = 01 (rising edge), CONT = 0
2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0

For code example refer to the Appendix section A.7.7: Single conversion sequence - hardware trigger .

Figure 33. Continuous conversions of a sequence, hardware trigger

Timing diagram for continuous conversions of a sequence with hardware trigger. The diagram shows the relationship between ADSTART, EOC, EOS, ADSTP, TRGx, ADC state, and ADC_DR signals over time. ADSTART is a software trigger (rising edge). EOC pulses for each conversion. EOS pulses at the end of the sequence. ADSTP is a software stop (falling edge). TRGx is a hardware trigger (falling edge) that starts the sequence. ADC state shows RDY, CH0, CH1, CH2, CH3, CH0, CH1, CH2, CH3, CH0, STOP, RDY. ADC_DR shows data D0, D1, D2, D3, D0, D1, D2, D3.

Timing diagram for continuous conversions of a sequence, hardware trigger. The diagram shows the relationship between ADSTART, EOC, EOS, ADSTP, TRGx, ADC state, and ADC_DR signals over time.

ADSTART ⁽¹⁾: Software trigger (rising edge).
EOC : End of Conversion pulses for each conversion.
EOS : End of Sequence pulses at the end of the sequence.
ADSTP : Software stop (falling edge).
TRGx ⁽¹⁾: Hardware trigger (falling edge) that starts the sequence.
ADC state ⁽²⁾: Shows the sequence of conversions: RDY, CH0, CH1, CH2, CH3, CH0, CH1, CH2, CH3, CH0, STOP, RDY.
ADC_DR : Data register showing D0, D1, D2, D3, D0, D1, D2, D3.

Legend:

by S/W (Software): rising edge
by H/W (Hardware): falling edge
triggered: rising edge
ignored: falling edge

MSv30341V2

Timing diagram for continuous conversions of a sequence with hardware trigger. The diagram shows the relationship between ADSTART, EOC, EOS, ADSTP, TRGx, ADC state, and ADC_DR signals over time. ADSTART is a software trigger (rising edge). EOC pulses for each conversion. EOS pulses at the end of the sequence. ADSTP is a software stop (falling edge). TRGx is a hardware trigger (falling edge) that starts the sequence. ADC state shows RDY, CH0, CH1, CH2, CH3, CH0, CH1, CH2, CH3, CH0, STOP, RDY. ADC_DR shows data D0, D1, D2, D3, D0, D1, D2, D3.

1. EXTSEL = TRGx, EXTEN = 10 (falling edge), CONT = 1
2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0

For code example refer to the Appendix section A.7.8: Continuous conversion sequence - hardware trigger .

12.5 Data management

12.5.1 Data register and data alignment (ADC_DR, ALIGN)

At the end of each conversion (when an EOC event occurs), the result of the converted data is stored in the ADC_DR data register which is 16-bit wide.

The format of the ADC_DR depends on the configured data alignment and resolution.

The ALIGN bit in the ADC_CFGR1 register selects the alignment of the data stored after conversion. Data can be right-aligned (ALIGN = 0) or left-aligned (ALIGN = 1) as shown in Figure 34.

Figure 34. Data alignment and resolution

ALIGN	RES	14	13	12	11	10	9	5	4	3	2	1	0
0	0x0	0x0						DR[11:0]
	0x1		0x00						DR[9:0]
	0x2			0x00						DR[7:0]
	0x3				0x00						DR[5:0]
1	0x0				DR[11:0]								0x0
	0x1					DR[9:0]						0x00
	0x2						DR[7:0]					0x00
	0x3					0x00		DR[5:0]					0x0

MS30342V1

12.5.2 ADC overrun (OVR, OVRMOD)

The overrun flag (OVR) indicates a data overrun event, when the converted data was not read in time by the CPU or the DMA, before the data from a new conversion is available.

The OVR flag is set in the ADC_ISR register if the EOC flag is still at '1' at the time when a new conversion completes. An interrupt can be generated if the OVRRIE bit is set in the ADC_IER register.

When an overrun condition occurs, the ADC keeps operating and can continue to convert unless the software decides to stop and reset the sequence by setting the ADSTP bit in the ADC_CR register.

The OVR flag is cleared by software by writing 1 to it.

It is possible to configure if the data is preserved or overwritten when an overrun event occurs by programming the OVRMOD bit in the ADC_CFGR1 register:

• OVRMOD = 0
- – An overrun event preserves the data register from being overwritten: the old data is maintained and the new conversion is discarded. If OVR remains at 1, further conversions can be performed but the resulting data is discarded.
• OVRMOD = 1
- – The data register is overwritten with the last conversion result and the previous unread data is lost. If OVR remains at 1, further conversions can be performed and the ADC_DR register always contains the data from the latest conversion.

Figure 35. Example of overrun (OVR)

Timing diagram illustrating an overrun (OVR) event in an ADC. The diagram shows the relationship between ADSTART, EOC, EOS, OVR, ADSTP, TRGx, ADC state, ADC_DR read access, and ADC_DR data for two different OVRMOD settings. An overrun occurs when a new conversion starts before the previous one is read, causing the OVR flag to be set and data to be lost or overwritten.

The timing diagram shows the following signals and states over time:

ADSTART ⁽¹⁾: A software trigger signal that goes high to start the ADC sequence and low to stop it.
EOC : End of Conversion flag, which pulses high when each conversion in the sequence is complete.
EOS : End of Sequence flag, which goes high when the last conversion in the sequence is complete.
OVR : Overrun flag, which goes high if a new conversion starts before the previous data in the ADC_DR register has been read.
ADSTP : A hardware trigger signal that goes high to stop the ADC sequence.
TRGx ⁽¹⁾: A hardware trigger signal that goes high to start the ADC sequence.
ADC state ⁽²⁾: The state of the ADC, showing the sequence of conversions: RDY, CH0, CH1, CH2, CH0, CH1, CH2, CH0, STOP, RDY.
ADC_DR read access : Software read accesses to the ADC_DR register. An overrun is indicated when a read access occurs while the OVR flag is still high from a previous conversion.
ADC_DR (OVRMOD=0) : The data register when OVRMOD is 0. It shows data D0, D1, D2, and then D0 again. The second D0 is lost due to the overrun.
ADC_DR (OVRMOD=1) : The data register when OVRMOD is 1. It shows data D0, D1, D2, and then D0, D1, and finally D2. In this mode, the overrun does not prevent further conversions, and the register contains the latest conversion data (D2).

Legend:

by S/W (software): rising edge
by H/W (hardware): rising edge
triggered: falling edge

MSV30343V3

Timing diagram illustrating an overrun (OVR) event in an ADC. The diagram shows the relationship between ADSTART, EOC, EOS, OVR, ADSTP, TRGx, ADC state, ADC_DR read access, and ADC_DR data for two different OVRMOD settings. An overrun occurs when a new conversion starts before the previous one is read, causing the OVR flag to be set and data to be lost or overwritten.

12.5.3 Managing a sequence of data converted without using the DMA

If the conversions are slow enough, the conversion sequence can be handled by software. In this case the software must use the EOC flag and its associated interrupt to handle each data result. Each time a conversion is complete, the EOC bit is set in the ADC_ISR register and the ADC_DR register can be read. The OVRMOD bit in the ADC_CFGR1 register should be configured to 0 to manage overrun events as an error.

12.5.4 Managing converted data without using the DMA without overrun

It may be useful to let the ADC convert one or more channels without reading the data after each conversion. In this case, the OVRMOD bit must be configured at 1 and the OVR flag should be ignored by the software. When OVRMOD = 1, an overrun event does not prevent the ADC from continuing to convert and the ADC_DR register always contains the latest conversion data.

12.5.5 Managing converted data using the DMA

Since all converted channel values are stored in a single data register, it is efficient to use DMA when converting more than one channel. This avoids losing the conversion data results stored in the ADC_DR register.

When DMA mode is enabled (DMAEN bit set in the ADC_CFGR1 register), a DMA request is generated after the conversion of each channel. This allows the transfer of the converted data from the ADC_DR register to the destination location selected by the software.

Note: The DMAEN bit in the ADC_CFGR1 register must be set after the ADC calibration phase.

Despite this, if an overrun occurs (OVR = 1) because the DMA could not serve the DMA transfer request in time, the ADC stops generating DMA requests and the data corresponding to the new conversion is not transferred by the DMA. Which means that all the data transferred to the RAM can be considered as valid.

Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten (refer to Section 12.5.2: ADC overrun (OVR, OVRMOD) on page 198 ).

The DMA transfer requests are blocked until the software clears the OVR bit.

Two different DMA modes are proposed depending on the application use and are configured with bit DMACFG in the ADC_CFGR1 register:

• DMA one shot mode (DMACFG = 0).
This mode should be selected when the DMA is programmed to transfer a fixed number of data words.
• DMA circular mode (DMACFG = 1)
This mode should be selected when programming the DMA in circular mode or double buffer mode.

DMA one shot mode (DMACFG = 0)

In this mode, the ADC generates a DMA transfer request each time a new conversion data word is available and stops generating DMA requests once the DMA has reached the last DMA transfer (when a transfer complete interrupt occurs, see Section 10: Direct memory access controller (DMA) ) even if a conversion has been started again.

For code example refer to the Appendix section A.7.9: DMA one shot mode sequence .

When the DMA transfer is complete (all the transfers configured in the DMA controller have been done):

• The content of the ADC data register is frozen.
• Any ongoing conversion is aborted and its partial result discarded
• No new DMA request is issued to the DMA controller. This avoids generating an overrun error if there are still conversions which are started.
• The scan sequence is stopped and reset
• The DMA is stopped

DMA circular mode (DMACFG = 1)

In this mode, the ADC generates a DMA transfer request each time a new conversion data word is available in the data register, even if the DMA has reached the last DMA transfer. This allows the DMA to be configured in circular mode to handle a continuous analog input data stream.

For code example refer to the Appendix section A.7.10: DMA circular mode sequence .

12.6 Low-power features

12.6.1 Wait mode conversion

Wait mode conversion can be used to simplify the software as well as optimizing the performance of applications clocked at low frequency where there might be a risk of ADC overrun occurring.

When the WAIT bit is set in the ADC_CFGR1 register, a new conversion can start only if the previous data has been treated, once the ADC_DR register has been read or if the EOC bit has been cleared.

This is a way to automatically adapt the speed of the ADC to the speed of the system that reads the data.

Note: Any hardware triggers which occur while a conversion is ongoing or during the wait time preceding the read access are ignored.

Figure 36. Wait mode conversion (continuous mode, software trigger)

The diagram illustrates the timing sequence for a continuous mode ADC conversion with software triggers and wait mode. The signals shown are:

ADSTART: Software trigger (S/W) that starts the conversion sequence.
EOC: End of Conversion signal, which pulses high when a conversion is complete.
EOS: End of Sequence signal, which pulses high when the sequence of conversions is complete.
ADSTP: Stop signal, which pulses high to stop the conversion sequence.
ADC_DR Read access: Software read access to the ADC_DR register.
ADC state: The sequence of states: RDY, CH1, DLY, CH2, DLY, CH3, DLY, CH1, DLY, STOP, RDY.
ADC_DR: The data values: D1, D2, D3, D1.

A legend indicates that rising edges are by S/W (Software) and falling edges are by H/W (Hardware).

MSv30344V2

Timing diagram for Figure 36: Wait mode conversion (continuous mode, software trigger). The diagram shows the relationship between ADSTART, EOC, EOS, ADSTP, ADC_DR Read access, ADC state, and ADC_DR over time. ADSTART is a software trigger (S/W) that starts the conversion. EOC (End of Conversion) pulses high when a conversion is complete. EOS (End of Sequence) pulses high when the sequence of conversions is complete. ADSTP (Stop) pulses high to stop the conversion sequence. ADC_DR Read access shows the software reading the data. ADC state shows the sequence: RDY, CH1, DLY, CH2, DLY, CH3, DLY, CH1, DLY, STOP, RDY. ADC_DR shows the data values: D1, D2, D3, D1. A legend indicates that rising edges are by S/W and falling edges are by H/W.

1. EXTEN = 00, CONT = 1
2. CHSEL = 0x3, SCANDIR = 0, WAIT = 1, AUTOFF = 0

For code example refer to the Appendix section A.7.11: Wait mode sequence .

12.6.2 Auto-off mode (AUTOFF)

The ADC has an automatic power management feature which is called auto-off mode, and is enabled by setting AUTOFF = 1 in the ADC_CFGR1 register.

When AUTOFF = 1, the ADC is always powered off when not converting and automatically wakes-up when a conversion is started (by software or hardware trigger). A startup-time is automatically inserted between the trigger event which starts the conversion and the sampling time of the ADC. The ADC is then automatically disabled once the sequence of conversions is complete.

Auto-off mode can cause a dramatic reduction in the power consumption of applications which need relatively few conversions or when conversion requests are timed far enough apart (for example with a low frequency hardware trigger) to justify the extra power and extra time used for switching the ADC on and off.

Auto-off mode can be combined with the wait mode conversion (WAIT = 1) for applications clocked at low frequency. This combination can provide significant power savings if the ADC is automatically powered-off during the wait phase and restarted as soon as the ADC_DR register is read by the application (see Figure 38: Behavior with WAIT = 1, AUTOFF = 1 ).

Note: Refer to the Section Reset and clock control (RCC) for the description of how to manage the dedicated 14 MHz internal oscillator. The ADC interface can automatically switch ON/OFF the 14 MHz internal oscillator to save power.

Figure 37. Behavior with WAIT = 0, AUTOFF = 1

Timing diagram showing the behavior of the ADC in auto-off mode (AUTOFF = 1) with no wait mode (WAIT = 0). The diagram illustrates the relationship between the trigger signal (TRGx), end of conversion (EOC), end of sequence (EOS), ADC state, and data register (ADC_DR).

The timing diagram shows the following signals and states over time:

TRGx: Trigger signal. It shows two rising edges. The first rising edge is labeled 'by S/W triggered' and starts the conversion sequence. The second rising edge occurs after the ADC has returned to the OFF state and starts another conversion sequence.
EOC: End of Conversion signal. It pulses high for each conversion (CH1, CH2, CH3, CH4) and then goes low when the sequence is complete.
EOS: End of Sequence signal. It goes high when the last conversion (CH4) is complete and goes low when the ADC state becomes OFF.
ADC_DR Read access: Shows the software reading the data register. The read occurs after each EOC pulse, corresponding to data D1, D2, D3, and D4.
ADC state: The state transitions are: RDY → Startup → CH1 → CH2 → CH3 → CH4 → OFF → Startup (upon the second trigger).
ADC_DR: The data register contains the conversion results: D1, D2, D3, and D4, which are read out sequentially.

A legend indicates that a rising edge labeled 'by S/W triggered' is a software trigger, and a rising edge labeled 'by H/W' is a hardware trigger.

MSv30345V2

Timing diagram showing the behavior of the ADC in auto-off mode (AUTOFF = 1) with no wait mode (WAIT = 0). The diagram illustrates the relationship between the trigger signal (TRGx), end of conversion (EOC), end of sequence (EOS), ADC state, and data register (ADC_DR).

EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 1

For code example refer to the Appendix section A.7.12: Auto Off and no wait mode sequence .

Figure 38. Behavior with WAIT = 1, AUTOFF = 1

Timing diagram showing the behavior of the ADC with WAIT=1 and AUTOFF=1. The diagram illustrates the sequence of events starting from a TRGx trigger (rising edge) to the conversion of multiple channels (CH1, CH2, CH3) and the resulting data (D1, D2, D3, D4). The ADC state transitions between RDY, Startup, CH1, OFF, CH2, CH3, and OFF. The EOC (End of Conversion) and EOS (End of Sequence) signals are shown. The ADC_DR Read access is indicated. A legend defines the trigger types: by S/W (Software), by H/W (Hardware), and triggered.

The diagram shows the following signal levels and states over time:

TRGx: A rising edge triggers the start of the conversion sequence.
EOC: End of Conversion signal. It pulses high when a conversion is complete (after CH1, CH2, and CH3) and returns low when the next conversion starts.
EOS: End of Sequence signal. It pulses high when the end of the sequence is reached (after CH3) and returns low when the sequence restarts.
ADC_DR Read access: Indicates when the data register is read. It is shown as a low pulse during the conversion of CH2 and CH3.
ADC state: The state of the ADC. It starts at RDY, goes to Startup, then CH1, then OFF, then Startup, then CH2, then OFF, then Startup, then CH3, then OFF, then Startup, then CH1, then OFF, then Startup, then CH2.
ADC_DR: The data register. It contains the converted data for each channel: D1 (after CH1), D2 (after CH2), D3 (after CH3), and D4 (after CH2).

Legend for triggers:

by S/W: Software trigger (rising edge)
by H/W: Hardware trigger (rising edge)
triggered: Triggered (rising edge)

MSv30346V2

Timing diagram showing the behavior of the ADC with WAIT=1 and AUTOFF=1. The diagram illustrates the sequence of events starting from a TRGx trigger (rising edge) to the conversion of multiple channels (CH1, CH2, CH3) and the resulting data (D1, D2, D3, D4). The ADC state transitions between RDY, Startup, CH1, OFF, CH2, CH3, and OFF. The EOC (End of Conversion) and EOS (End of Sequence) signals are shown. The ADC_DR Read access is indicated. A legend defines the trigger types: by S/W (Software), by H/W (Hardware), and triggered.

1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1, AUTOFF = 1

For code example refer to the Appendix section A.7.13: Auto Off and wait mode sequence .

12.7 Analog window watchdog

12.7.1 Description of the analog watchdog

The AWD analog watchdog is enabled by setting the AWDEN bit in the ADC_CFGR1 register. It is used to monitor that either one selected channel or all enabled channels (see Table 40: Analog watchdog channel selection ) remain within a configured voltage range (window) as shown in Figure 39 .

The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold. These thresholds are programmed in HT[11:0] and LT[11:0] bit of ADC_TR register. An interrupt can be enabled by setting the AWDIE bit in the ADC_IER register.

The AWD flag is cleared by software by programming it to it.

When converting data with a resolution of less than 12-bit (according to bits RES[1:0]), the LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data (left aligned).

For code example refer to the Appendix section A.7.14: Analog watchdog .

Table 39 describes how the comparison is performed for all the possible resolutions.

Table 39. Analog watchdog comparison

Resolution bits RES[1:0]	Analog watchdog comparison between:		Comments
Resolution bits RES[1:0]	Raw converted data, left aligned ⁽¹⁾	Thresholds	Comments
00: 12-bit	DATA[11:0]	LT[11:0] and HT[11:0]	-
01: 10-bit	DATA[11:2],00	LT[11:0] and HT[11:0]	The user must configure LT1[1:0] and HT1[1:0] to “00”
10: 8-bit	DATA[11:4],0000	LT[11:0] and HT[11:0]	The user must configure LT1[3:0] and HT1[3:0] to “0000”
11: 6-bit	DATA[11:6],000000	LT[11:0] and HT[11:0]	The user must configure LT1[5:0] and HT1[5:0] to “000000”

1. The watchdog comparison is performed on the raw converted data before any alignment calculation.

Table 40 shows how to configure the AWDSGL and AWDEN bits in the ADC_CFGR1 register to enable the analog watchdog on one or more channels.

Figure 39. Analog watchdog guarded area

Diagram showing the analog watchdog guarded area between a lower threshold (LTx) and a higher threshold (HTx) on an analog voltage scale. The area between the thresholds is shaded and labeled 'Guarded area'. The diagram includes a vertical axis for 'Analog voltage' and labels for 'Higher threshold' (HTx) and 'Lower threshold' (LTx). A small code 'MS45396V1' is in the bottom right corner.

Table 40. Analog watchdog channel selection

Channels guarded by the analog watchdog	AWDSGL bit	AWDEN bit
None	x	0
All channels	0	1
Single ⁽¹⁾channel	1	1

1. Selected by the AWDCH[4:0] bits

12.7.2 ADC_AWD1_OUT output signal generation

The analog watchdog is associated to an internal hardware signal, ADC_AWD1_OUT that is directly connected to the ETR input (external trigger) of some on-chip timers (refer to the timers section for details on how to select the ADC_AWD1_OUT signal as ETR).

ADC_AWD1_OUT is activated when the analog watchdog is enabled:

• ADC_AWD1_OUT is set when a guarded conversion is outside the programmed thresholds.
• ADC_AWD1_OUT is reset after the end of the next guarded conversion which is inside the programmed thresholds. It remains at 1 if the next guarded conversions are still outside the programmed thresholds.
• ADC_AWD1_OUT is also reset when disabling the ADC (when setting ADDIS to 1). Note that stopping conversions (ADSTP set), might clear the ADC_AWD1_OUT state.
• ADC_AWD1_OUT state does not change when the ADC converts the none-guarded channel (see Figure 40 )

AWD flag is set by hardware and reset by software: AWD flag has no influence on the generation of ADC_AWD1_OUT (as an example, ADC_AWD1_OUT can toggle while AWD flag remains at 1 if the software has not cleared the flag).

The ADC_AWD1_OUT signal is generated by the ADC_CLK domain. This signal can be generated even the APB clock is stopped.

The AWD comparison is performed at the end of each ADC conversion. The ADC_AWD1_OUT rising edge and falling edge occurs two ADC_CLK clock cycles after the comparison.

As ADC_AWD1_OUT is generated by the ADC_CLK domain and AWD flag is generated by the APB clock domain, the rising edges of these signals are not synchronized.

Figure 40. ADC_AWD1_OUT signal generation

Timing diagram showing ADC STATE, EOC FLAG, AWD FLAG, and ADC_AWD1_OUT signals over seven conversions. The diagram illustrates how the AWD flag is set and cleared by software based on whether conversions are 'inside' or 'outside' thresholds, and how the ADC_AWD1_OUT signal toggles based on these conditions.

The timing diagram shows four signals over a sequence of conversions:

ADC STATE: Shows the sequence: RDY, Conversion1 (inside), Conversion2 (outside), Conversion3 (inside), Conversion4 (outside), Conversion5 (outside), Conversion6 (outside), Conversion7 (inside).
EOC FLAG: Pulses at the end of each conversion (Conversion1 through Conversion7).
AWD FLAG: Set by hardware at the end of Conversion2 (outside) and Conversion4 (outside). It is cleared by software (SW) at the end of Conversion3 (inside), Conversion5 (outside), Conversion6 (outside), and Conversion7 (inside).
ADC_AWD1_OUT: This signal toggles based on the AWD flag and the conversion status. It is set (goes high) when a guarded conversion is outside the thresholds (e.g., at the end of Conversion2) and reset (goes low) when the next guarded conversion is inside the thresholds (e.g., at the end of Conversion3). It remains high if consecutive guarded conversions are outside the thresholds (Conversions 4 and 5).

Legend:

- Converted channels: 1,2,3,4,5,6,7
- Guarded converted channels: 1,2,3,4,5,6,7

MSV65326V1

Timing diagram showing ADC STATE, EOC FLAG, AWD FLAG, and ADC_AWD1_OUT signals over seven conversions. The diagram illustrates how the AWD flag is set and cleared by software based on whether conversions are 'inside' or 'outside' thresholds, and how the ADC_AWD1_OUT signal toggles based on these conditions.

Figure 41. ADC_AWD1_OUT signal generation (AWD flag not cleared by software)

Timing diagram for Figure 41 showing ADC STATE, EOC FLAG, AWD FLAG, and ADC_AWD1_OUT signals over seven conversions. The AWD FLAG is set at the end of Conversion2 and remains high because it is not cleared by software, causing the ADC_AWD1_OUT signal to go high at the end of Conversion2 and stay high until the end of Conversion7.

ADC STATE: RDY, Conversion1 (inside), Conversion2 (outside), Conversion3 (inside), Conversion4 (outside), Conversion5 (outside), Conversion6 (outside), Conversion7 (inside)

EOC FLAG: Pulses at the end of each conversion.

AWD FLAG: Goes high at the end of Conversion2 and remains high (not cleared by SW).

ADC_AWD1_OUT: Goes high at the end of Conversion2 and remains high until the end of Conversion7.

Legend:
- Converted channels: 1,2,3,4,5,6,7
- Guarded converted channels: 1,2,3,4,5,6,7

MSv65327V1

Timing diagram for Figure 41 showing ADC STATE, EOC FLAG, AWD FLAG, and ADC_AWD1_OUT signals over seven conversions. The AWD FLAG is set at the end of Conversion2 and remains high because it is not cleared by software, causing the ADC_AWD1_OUT signal to go high at the end of Conversion2 and stay high until the end of Conversion7.

Figure 42. ADC1_AWD_OUT signal generation (on a single channel)

Timing diagram for Figure 42 showing ADC STATE, EOC FLAG, EOS FLAG, AWD FLAG, and ADCy_AWD1_OUT signals over four sets of Conversion1 and Conversion2. Only Conversion1 is guarded. The AWD FLAG is cleared by software after the first Conversion1. The ADCy_AWD1_OUT signal goes high at the end of the first Conversion1 (outside) and low at the end of the second Conversion1 (inside).

ADC STATE: Conversion1 (outside), Conversion2, Conversion1 (inside), Conversion2, Conversion1 (outside), Conversion2, Conversion1 (outside), Conversion2

EOC FLAG: Pulses at the end of each conversion.

EOS FLAG: Pulses at the end of each set of conversions.

AWD FLAG: Goes high at the end of the first Conversion1, then is cleared by software. It goes high again at the end of the third Conversion1 and is cleared by software again.

ADCy_AWD1_OUT: Goes high at the end of the first Conversion1 (outside) and low at the end of the second Conversion1 (inside).

Legend:
- Converted channels: 1 and 2
- Only channel 1 is guarded

MSv65328V1

Timing diagram for Figure 42 showing ADC STATE, EOC FLAG, EOS FLAG, AWD FLAG, and ADCy_AWD1_OUT signals over four sets of Conversion1 and Conversion2. Only Conversion1 is guarded. The AWD FLAG is cleared by software after the first Conversion1. The ADCy_AWD1_OUT signal goes high at the end of the first Conversion1 (outside) and low at the end of the second Conversion1 (inside).

12.7.3 Analog watchdog threshold control

LT[11:0] and HT[11:0] can be changed during an analog-to-digital conversion (that is between the start of the conversion and the end of conversion of the ADC internal state). If LT and HT bits are programmed during the ADC guarded channel conversion, the watchdog function is masked for this conversion. This mask is cleared when starting a new conversion, and the resulting new AWD threshold is applied starting the next ADC conversion result. AWD comparison is performed at each end of conversion. If the current ADC data are out of the new threshold interval, this does not generate any interrupt or an ADC_AWD1_OUT signal. The Interrupt and the ADC_AWD1_OUT generation only occurs at the end of the ADC conversion that started after the threshold update. If ADC_AWD1_OUT is already asserted, programming the new threshold does not deactivate the ADC_AWD1_OUT signal.

Figure 43. Analog watchdog threshold update

Figure 43: Analog watchdog threshold update diagram. The diagram shows three horizontal timelines. The top timeline, labeled 'ADC state', shows four 'Conversion' blocks. The middle timeline, labeled 'LT, HT', shows three threshold values: 'XXXX', 'XXXY', and 'XXXZ'. An arrow labeled 'Threshold updated' points from the first 'Conversion' block to the 'XXXY' threshold. The bottom timeline, labeled 'Comparison', shows three states: 'Active' (under the first 'Conversion'), 'Masked' (under the 'XXXY' threshold), and 'Active' (under the 'XXXZ' threshold). The diagram is labeled 'MSv65329V1' in the bottom right corner.

12.8 Temperature sensor and internal reference voltage

The temperature sensor can be used to measure the junction temperature ( $$ T_J $$ ) of the device. The temperature sensor is internally connected to the ADC $V_{IN}[16]$ input channel which is used to convert the sensor's output voltage to a digital value. The sampling time for the temperature sensor analog pin must be greater than the minimum $T_{S\_temp}$ value specified in the datasheet. When not in use, the sensor can be put in power down mode.

The temperature sensor output voltage changes linearly with temperature, however its characteristics may vary significantly from chip to chip due to the process variations. To improve the accuracy of the temperature sensor (especially for absolute temperature measurement), calibration values are individually measured for each part by ST during production test and stored in the system memory area. Refer to the specific device datasheet for additional information.

The internal voltage reference ( $V_{REFINT}$ ) provides a stable (bandgap) voltage output for the ADC and comparators. $V_{REFINT}$ is internally connected to the ADC $V_{IN}[17]$ input channel. The precise voltage of $V_{REFINT}$ is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Figure 44 shows the block diagram of connections between the temperature sensor, the internal voltage reference and the ADC.

The TSEN bit must be set to enable the conversion of ADC $V_{IN}[16]$ (temperature sensor) and the VREFEN bit must be set to enable the conversion of ADC $V_{IN}[17]$ ( $V_{REFINT}$ ).

Main features

Linearity: $\pm 2\text{ }^{\circ}\text{C}$ max., precision depending on calibration

Figure 44. Temperature sensor and V _REFINTchannel block diagram

Figure 44. Temperature sensor and VREFINT channel block diagram. The diagram shows two input sources connected to an ADC. The first source is a 'Temperature sensor' connected to a multiplexer controlled by the 'TSEN control bit'. The output of this multiplexer is labeled 'VSENSE' and is connected to the 'ADC V_IN[16]' input. The second source is an 'Internal power block' connected to another multiplexer controlled by the 'VREFEN control bit'. The output of this multiplexer is labeled 'VREFINT' and is connected to the 'ADC V_IN[17]' input. Both ADC inputs are part of a larger 'ADC' block. The 'ADC' block outputs 'converted data' to an 'Address/data bus'. The identifier 'ai16065c' is present in the bottom right corner of the diagram.

Reading the temperature

1. Select the ADC V _IN[16] input channel.
2. Select an appropriate sampling time specified in the device datasheet (T _{S_temp}).
3. Set the TSEN bit in the ADC_CCR register to wake up the temperature sensor from power down mode and wait for its stabilization time (t _START).
For code example refer to the Appendix section A.7.15: Temperature configuration .
4. Start the ADC conversion by setting the ADSTART bit in the ADC_CR register (or by external trigger).
5. Read the resulting V _SENSEdata in the ADC_DR register.
6. Calculate the temperature using the following formula

\text{Temperature (in } ^{\circ}\text{C)} = \frac{\text{Sense\_DATA} - \text{TS\_CAL1}}{\text{Avg\_Slope\_Code}} + \text{TS\_CAL1\_TEMP}

\text{Avg\_Slope\_Code} = \text{Avg\_Slope} \times 4096 / 3300

\text{Sense\_DATA} = \text{TS\_DATA} \times V_{\text{DDA}} / 3.3

Where:

• TS_CAL1 is the temperature sensor calibration value acquired at TS_CAL1_TEMP (refer to the datasheet for TS_CAL1 value)
• TS_DATA is the actual temperature sensor output value converted by ADC
Refer to the specific device datasheet for more information about TS_CAL1 calibration point.
• Avg_Slope is the coefficient of the temperature sensor output voltage expressed in mV/°C (refer to the datasheet for Avg_Slope value).

For code example refer to the A.7.16: Temperature computation .

Note: The sensor has a startup time after waking from power down mode before it can output V _SENSEat the correct level. The ADC also has a startup time after power-on, so to minimize the delay, the ADEN and TSEN bits should be set at the same time.

Calculating the actual V _DDAvoltage using the internal reference voltage

The V _DDApower supply voltage applied to the device may be subject to variation or not precisely known. The embedded internal voltage reference (V _REFINT) and its calibration data, acquired by the ADC during the manufacturing process at V _{DDA_Charac}, can be used to evaluate the actual V _DDAvoltage level.

The following formula gives the actual V _DDAvoltage supplying the device:

V_{DDA} = V_{DDA\_Charac} \times VREFINT\_CAL / VREFINT\_DATA

Where:

• V _{DDA_Chac}is the value of V _DDAvoltage characterized at V _REFINTduring the manufacturing process. It is specified in the device datasheet.
• VREFINT_CAL is the VREFINT calibration value
• VREFINT_DATA is the actual VREFINT output value converted by ADC

Converting a supply-relative ADC measurement to an absolute voltage value

The ADC is designed to deliver a digital value corresponding to the ratio between the analog power supply and the voltage applied on the converted channel. For most application use cases, it is necessary to convert this ratio into a voltage independent of V _DDA. For applications where V _DDAis known and ADC converted values are right-aligned you can use the following formula to get this absolute value:

V_{CHANNELx} = \frac{V_{DDA}}{NUM\_CODES} \times ADC\_DATA_x

For applications where V _DDAvalue is not known, you must use the internal voltage reference and V _DDAcan be replaced by the expression provided in Section : Calculating the actual V _DDAvoltage using the internal reference voltage , resulting in the following formula:

V_{CHANNELx} = \frac{V_{DDA\_Charac} \times VREFINT\_CAL \times ADC\_DATA_x}{VREFINT\_DATA \times NUM\_CODES}

Where:

• $V_{DDA\_Charac}$ is the value of $V_{DDA}$ voltage characterized at $V_{REFINT}$ during the manufacturing process. It is specified in the device datasheet.
• $VREFINT\_CAL$ is the $$ VREFINT $$ calibration value
• $ADC\_DATA_x$ is the value measured by the ADC on channelx (right-aligned)
• $VREFINT\_DATA$ is the actual $$ VREFINT $$ output value converted by the ADC
• $NUM\_CODES$ is the number of ADC output codes. For example with 12-bit resolution, it is $2^{12} = 4096$ or with 8-bit resolution, $$ 2^8 = 256 $$ .

Note: If ADC measurements are done using an output format other than 12 bit right-aligned, all the parameters must first be converted to a compatible format before the calculation is done.

12.9 ADC interrupts

An interrupt can be generated by any of the following events:

• ADC power-up, when the ADC is ready (ADRDY flag)
• End of any conversion (EOC flag)
• End of a sequence of conversions (EOS flag)
• When an analog watchdog detection occurs (AWD flag)
• When the end of sampling phase occurs (EOSMP flag)
• when a data overrun occurs (OVR flag)

Separate interrupt enable bits are available for flexibility.

Table 41. ADC interrupts

Interrupt event	Event flag	Enable control bit
ADC ready	ADRDY	ADRDYIE
End of conversion	EOC	EOCIE
End of sequence of conversions	EOS	EOSIE
Analog watchdog status bit is set	AWD	AWDIE
End of sampling phase	EOSMP	EOSMPIE
Overrun	OVR	OVRIE

12.10 ADC registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.

12.10.1 ADC interrupt and status register (ADC_ISR)

Address offset: 0x00

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	AWD	Res.	Res.	OVR	EOS	EOC	EOSMP	ADRDY
								rc_w1			rc_w1	rc_w1	rc_w1	rc_w1	rc_w1

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:10 Reserved, must be kept at reset value.

Bits 9:8 Reserved, must be kept at reset value.

Bit 7 AWD : Analog watchdog flag

This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR register. It is cleared by software by programming it to 1.

0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software)

1: Analog watchdog event occurred

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 OVR : ADC overrun

This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it.

0: No overrun occurred (or the flag event was already acknowledged and cleared by software)

1: Overrun has occurred

Bit 3 EOS : End of sequence flag

This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it.

0: Conversion sequence not complete (or the flag event was already acknowledged and cleared by software)

1: Conversion sequence complete

Bit 2 EOC : End of conversion flag

This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register.

0: Channel conversion not complete (or the flag event was already acknowledged and cleared by software)
1: Channel conversion complete

Bit 1 EOSMP : End of sampling flag

This bit is set by hardware during the conversion, at the end of the sampling phase. It is cleared by software by programming it to '1'.

0: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)
1: End of sampling phase reached

Bit 0 ADRDY : ADC ready

This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests.

It is cleared by software writing 1 to it.

0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)
1: ADC is ready to start conversion

Note: In auto-off mode (AUTOFF = 1) the power-on/off phases are performed automatically, by hardware and the ADRDY flag is not set.

12.10.2 ADC interrupt enable register (ADC_IER)

Address offset: 0x04

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	AWDIE	Res.	Res.	OVRIE	EOSIE	EOCIE	EOSMP IE	ADRDY IE
								rw			rw	rw	rw	rw	rw

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:10 Reserved, must be kept at reset value.

Bits 9:8 Reserved, must be kept at reset value.

Bit 7 AWDIE : Analog watchdog interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog interrupt.

0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled

Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bits 6:5 Reserved, must be kept at reset value.

Bit 4 OVRIE: Overrun interrupt enable

This bit is set and cleared by software to enable/disable the overrun interrupt.

0: Overrun interrupt disabled

1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 3 EOSIE: End of conversion sequence interrupt enable

This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt.

0: EOS interrupt disabled

1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 2 EOCIE: End of conversion interrupt enable

This bit is set and cleared by software to enable/disable the end of conversion interrupt.

0: EOC interrupt disabled

1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 1 EOSMPIE: End of sampling flag interrupt enable

This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt.

0: EOSMP interrupt disabled.

1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 0 ADRDYIE: ADC ready interrupt enable

This bit is set and cleared by software to enable/disable the ADC Ready interrupt.

0: ADRDY interrupt disabled.

1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

12.10.3 ADC control register (ADC_CR)

Address offset: 0x08

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADCAL	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ADSTP	Res.	ADSTA RT	ADDIS	ADEN
											rs		rs	rs	rs

Bit 31 ADCAL: ADC calibration

This bit is set by software to start the calibration of the ADC.

It is cleared by hardware after calibration is complete.

0: Calibration complete

1: Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.

Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0, AUTOFF = 0, and ADEN = 0).

Bits 30:28 Reserved, must be kept at reset value.

Bits 27:5 Reserved, must be kept at reset value.

Bit 4 ADSTP: ADC stop conversion command

This bit is set by software to stop and discard an ongoing conversion (ADSTP Command).

It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command.

0: No ADC stop conversion command ongoing

1: Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.

Note: Setting ADSTP to '1' is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and may be converting and there is no pending request to disable the ADC)

Bit 3 Reserved, must be kept at reset value.

Bit 2 ADSTART: ADC start conversion command

This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration).

It is cleared by hardware:

– In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag.
– In discontinuous conversion mode (CONT = 0, DISCEN = 1), when the software trigger is selected (EXTEN = 00): at the assertion of the end of Conversion (EOC) flag.
– In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware.

0: No ADC conversion is ongoing.

1: Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.

Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC).

Bit 1 ADDIS: ADC disable command

This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state).

It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time).

0: No ADDIS command ongoing

1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.

Note: Setting ADDIS to '1' is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no conversion is ongoing)

Bit 0 ADEN: ADC enable command

This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the ADRDY flag has been set.

It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.

0: ADC is disabled (OFF state)

1: Write 1 to enable the ADC.

Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, ADSTP = 0, ADSTART = 0, ADDIS = 0 and ADEN = 0)

12.10.4 ADC configuration register 1 (ADC_CFGR1)

Address offset: 0x0C

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	AWDCH[4:0]					Res.	Res.	AWDEN	AWDSGL	Res.	Res.	Res.	Res.	Res.	DISCE
	rw	rw	rw	rw	rw			rw	rw						rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AUTOF	WAIT	CONT	OVRMOD	EXTEN[1:0]		Res.	EXTSEL[2:0]			ALIGN	RES[1:0]		SCANDIR	DMACFG	DMAEN
rw	rw	rw	rw	rw	rw		rw	rw	rw	rw	rw	rw	rw	rw	rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:26 AWDCH[4:0] : Analog watchdog channel selection

These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog.

00000: ADC analog input Channel 0 monitored by AWD

00001: ADC analog input Channel 1 monitored by AWD

.....

10001: ADC analog input Channel 17 monitored by AWD

Others: Reserved

Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register.

The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bits 25:24 Reserved, must be kept at reset value.

Bit 23 AWDEN : Analog watchdog enable

This bit is set and cleared by software.

0: Analog watchdog disabled

1: Analog watchdog enabled

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 22 AWDSGL : Enable the watchdog on a single channel or on all channels

This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels

0: Analog watchdog enabled on all channels

1: Analog watchdog enabled on a single channel

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bits 21:17 Reserved, must be kept at reset value.

Bit 16 DISCEN: Discontinuous mode

This bit is set and cleared by software to enable/disable discontinuous mode.

0: Discontinuous mode disabled

1: Discontinuous mode enabled

Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.

The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 15 AUTOFF: Auto-off mode

This bit is set and cleared by software to enable/disable auto-off mode.

0: Auto-off mode disabled

1: Auto-off mode enabled

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 14 WAIT: Wait conversion mode

This bit is set and cleared by software to enable/disable wait conversion mode.

0: Wait conversion mode off

1: Wait conversion mode on

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 13 CONT: Single / continuous conversion mode

This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared.

0: Single conversion mode

1: Continuous conversion mode

Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN = 1 and CONT = 1.

The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 12 OVRMOD: Overrun management mode

This bit is set and cleared by software and configure the way data overruns are managed.

0: ADC_DR register is preserved with the old data when an overrun is detected.

1: ADC_DR register is overwritten with the last conversion result when an overrun is detected.

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection

These bits are set and cleared by software to select the external trigger polarity and enable the trigger.

00: Hardware trigger detection disabled (conversions can be started by software)

01: Hardware trigger detection on the rising edge

10: Hardware trigger detection on the falling edge

11: Hardware trigger detection on both the rising and falling edges

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 9 Reserved, must be kept at reset value.

Bits 8:6 EXTSEL[2:0] : External trigger selection

These bits select the external event used to trigger the start of conversion (refer to Table 35: External triggers for details):

000: TRG0

001: TRG1

010: TRG2

011: TRG3

100: TRG4

101: TRG5

110: TRG6

111: TRG7

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 5 ALIGN : Data alignment

This bit is set and cleared by software to select right or left alignment. Refer to Figure 34: Data alignment and resolution on page 198

0: Right alignment

1: Left alignment

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bits 4:3 RES[1:0] : Data resolution

These bits are written by software to select the resolution of the conversion.

00: 12 bits

01: 10 bits

10: 8 bits

11: 6 bits

Bit 2 SCANDIR: Scan sequence direction

This bit is set and cleared by software to select the direction in which the channels is scanned in the sequence.

0: Upward scan (from CHSEL0 to CHSEL17)

1: Backward scan (from CHSEL17 to CHSEL0)

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 1 DMACFG: Direct memory access configuration

This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1.

0: DMA one shot mode selected

1: DMA circular mode selected

For more details, refer to Section 12.5.5: Managing converted data using the DMA on page 199 .

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

Bit 0 DMAEN: Direct memory access enable

This bit is set and cleared by software to enable the generation of DMA requests. This allows the DMA controller to be used to manage automatically the converted data. For more details, refer to Section 12.5.5: Managing converted data using the DMA on page 199 .

0: DMA disabled

1: DMA enabled

Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no conversion is ongoing).

12.10.5 ADC configuration register 2 (ADC_CFGR2)

Address offset: 0x10

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CKMODE[1:0]	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

Bits 31:30 CKMODE[1:0] : ADC clock mode

These bits are set and cleared by software to define how the analog ADC is clocked:

00: ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)

01: PCLK/2 (Synchronous clock mode)

10: PCLK/4 (Synchronous clock mode)

11: Reserved

In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion.

Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

Bits 29:10 Reserved, must be kept at reset value.

Bits 9:0 Reserved, must be kept at reset value.

12.10.6 ADC sampling time register (ADC_SMPR)

Address offset: 0x14

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	SMP[2:0]
													rw	rw	rw

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 SMP[2:0] : Sampling time selection

These bits are written by software to select the sampling time that applies to all channels.

000: 1.5 ADC clock cycles

001: 7.5 ADC clock cycles

010: 13.5 ADC clock cycles

011: 28.5 ADC clock cycles

100: 41.5 ADC clock cycles

101: 55.5 ADC clock cycles

110: 71.5 ADC clock cycles

111: 239.5 ADC clock cycles

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

12.10.7 ADC watchdog threshold register (ADC_TR)

Address offset: 0x20

Reset value: 0x0FFF 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	HT[11:0]
				rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	LT[11:0]
				rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HT[11:0] : Analog watchdog higher threshold

These bits are written by software to define the higher threshold for the analog watchdog. Refer to Section 12.7: Analog window watchdog on page 203

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bits 15:12 Reserved, must be kept at reset value.

Bits 11:0 LT[11:0] : Analog watchdog lower threshold

These bits are written by software to define the lower threshold for the analog watchdog.

Refer to Section 12.7: Analog window watchdog on page 203 .

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

12.10.8 ADC channel selection register (ADC_CHSELR)

Address offset: 0x28

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	CHSEL 17	CHSEL 16
														rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CHSEL 15	CHSEL 14	CHSEL 13	CHSEL 12	CHSEL 11	CHSEL 10	CHSEL 9	CHSEL 8	CHSEL 7	CHSEL 6	CHSEL 5	CHSEL 4	CHSEL 3	CHSEL 2	CHSEL 1	CHSEL 0
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 31:18 Reserved, must be kept at reset value.

Bits 17:0 CHSELx : Channel-x selection

These bits are written by software and define which channels are part of the sequence of channels to be converted.

0: Input Channel-x is not selected for conversion

1: Input Channel-x is selected for conversion

Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

12.10.9 ADC data register (ADC_DR)

Address offset: 0x40

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.
DATA[15:0]
r	r	r	r	r	r	r	r	r	r	r	r	r	r	r	r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 DATA[15:0] : Converted data

These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in Figure 34: Data alignment and resolution on page 198 .

Just after a calibration is complete, DATA[6:0] contains the calibration factor.

12.10.10 ADC common configuration register (ADC_CCR)

Address offset: 0x308

Reset value: 0x0000 0000

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	TSEN	VREFEN	Res.				Res.	Res.
								rw	rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 Reserved, must be kept at reset value.

Bit 23 TSEN : Temperature sensor enable

This bit is set and cleared by software to enable/disable the temperature sensor.

0: Temperature sensor disabled

1: Temperature sensor enabled

Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bit 22 VREFEN : V _REFINTenable

This bit is set and cleared by software to enable/disable the V _REFINT.

0: V _REFINTdisabled

1: V _REFINTenabled

Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).

Bits 21:0 Reserved, must be kept at reset value.

12.11 ADC register map

The following table summarizes the ADC registers.

Table 42. ADC register map and reset values

Offset	Register name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	ADC_ISR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	AWD	Res.	Res.	Res.	OVR	EOS	EOC	EOSMP
0x00	Reset value																									0				0	0	0	0
0x04	ADC_IER	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	AWDIE	Res.	Res.	Res.	OVRIE	EOSIE	EOCIE	EOSMPIE
0x04	Reset value																									0				0	0	0	0
0x08	ADC_CR	ADCAL	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ADSTP	ADSTART	ADDIS	ADEN
0x08	Reset value	0																												0	0	0	0

Table 42. ADC register map and reset values (continued)

Offset	Register name	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x0C	ADC_CFGR1	Res	AWDCH[4:0]					Res	Res	AWDEN	AWDSGL	Res	Res	Res	Res	Res	DISCEN	AUTOFF	WAIT	CONT	OVRMOD	EXTEN[1:0]	Res	Res	EXTSEL [2:0]		ALIGN	RES [1:0]	SCANDIR	DMACFG	DMAEN
0x0C	Reset value		0	0	0	0	0			0	0						0	0	0	0	0	0	0		0	0	0	0	0	0	0	0	0
0x10	ADC_CFGR2	CKMODE[1:0]		Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res		Res		Res		Res	Res
0x10	Reset value	0	0
0x14	ADC_SMPR	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	SMP [2:0]
0x14	Reset value																														0	0	0
0x18	Reserved	Reserved
0x1C	Reserved	Reserved
0x20	ADC_TR	Res	Res	Res	Res	HT[11:0]
0x20	Reset value					1	1	1	1	1	1	1	1	1	1	1	1					0	0	0	0	0	0	0	0	0	0	0	0
0x24	Reserved	Reserved
0x28	ADC_CHSELR	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	CHSEL17	CHSEL16	CHSEL15	CHSEL14	CHSEL13	CHSEL12	CHSEL11	CHSEL10	CHSEL9	CHSEL8	CHSEL7	CHSEL6	CHSEL5	CHSEL4	CHSEL3	CHSEL2	CHSEL1	CHSEL0
0x28	Reset value															0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x2C 0x30 0x34 0x38 0x3C	Reserved	Reserved
0x40	ADC_DR	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	DATA[15:0]
0x40	Reset value																	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
...	Reserved	Reserved
...	Reserved	Reserved
...	Reserved	Reserved
0x308	ADC_CCR	Res	Res	Res	Res	Res	Res	Res	Res	TSENA	VREFEN	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res	Res
0x308	Reset value									0	0

Refer to Section 2.2 for the register boundary addresses.

12. Analog-to-digital converter (ADC)

12.1 Introduction

12.2 ADC main features

12.3 ADC functional description

12.3.1 ADC pins and internal signals

12.3.2 Calibration (ADCAL)

12.3.3 ADC on-off control (ADEN, ADDIS, ADRDY)

12.3.4 ADC clock (CKMODE)

12.3.5 Configuring the ADC

12.3.6 Channel selection (CHSEL, SCANDIR)

Temperature sensor, V REFINT internal channels

12.3.7 Programmable sampling time (SMP)

12.3.8 Single conversion mode (CONT = 0)

12.3.9 Continuous conversion mode (CONT = 1)

12.3.10 Starting conversions (ADSTART)

12.3.11 Timings

12.3.12 Stopping an ongoing conversion (ADSTP)

12.4 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN)

12.4.1 Discontinuous mode (DISCEN)

12.4.2 Programmable resolution (RES) - Fast conversion mode

12.4.3 End of conversion, end of sampling phase (EOC, EOSMP flags)

12.4.4 End of conversion sequence (EOS flag)

12.4.5 Example timing diagrams (single/continuous modes hardware/software triggers)

12.5 Data management

12.5.1 Data register and data alignment (ADC_DR, ALIGN)

12.5.2 ADC overrun (OVR, OVRMOD)

12.5.3 Managing a sequence of data converted without using the DMA

12.5.4 Managing converted data without using the DMA without overrun

12.5.5 Managing converted data using the DMA

DMA one shot mode (DMACFG = 0)

DMA circular mode (DMACFG = 1)

12.6 Low-power features

12.6.1 Wait mode conversion

12.6.2 Auto-off mode (AUTOFF)

12.7 Analog window watchdog

12.7.1 Description of the analog watchdog

12.7.2 ADC_AWD1_OUT output signal generation

12.7.3 Analog watchdog threshold control

12.8 Temperature sensor and internal reference voltage

Main features

Reading the temperature

Calculating the actual V DDA voltage using the internal reference voltage

Converting a supply-relative ADC measurement to an absolute voltage value

12.9 ADC interrupts

12.10 ADC registers

12.10.1 ADC interrupt and status register (ADC_ISR)

12.10.3 ADC control register (ADC_CR)

12.10.4 ADC configuration register 1 (ADC_CFGR1)

12.10.5 ADC configuration register 2 (ADC_CFGR2)

12.10.6 ADC sampling time register (ADC_SMPR)

12.10.7 ADC watchdog threshold register (ADC_TR)

12.10.8 ADC channel selection register (ADC_CHSELR)

12.10.9 ADC data register (ADC_DR)

12.10.10 ADC common configuration register (ADC_CCR)

12.11 ADC register map

Temperature sensor, V _REFINTinternal channels

Calculating the actual V _DDAvoltage using the internal reference voltage