2. System and memory overview

2.1 System architecture

The main system consists of:

• • Two masters:
  • – Arm ^® Cortex ^® -M0 core
  • – General-purpose DMA
• • Four slaves:
  • – Internal SRAM
  • – Internal flash memory
  • – AHB1 with AHB to APB bridge, which connects all the APB peripherals
  • – AHB2 dedicated to GPIO ports

These are interconnected using a multilayer AHB bus architecture, as shown in Figure 1 :

Figure 1. System architecture

System bus

This bus connects the system bus of the Arm ^® Cortex ^® -M0 core (peripherals bus) to a BusMatrix which manages the arbitration between the core and the DMA.

DMA bus

This bus connects the AHB master interface of the DMA to the BusMatrix which manages the access of CPU and DMA to SRAM, flash memory and peripherals.

BusMatrix

The BusMatrix manages the access arbitration between the core system bus and the DMA master bus. The arbitration uses a Round Robin algorithm. The BusMatrix is composed of two masters (CPU, DMA) and four slaves (FLITF, SRAM, AHB1 with AHB to APB bridge and AHB2).

AHB peripherals are connected on system bus through a BusMatrix to allow DMA access.

AHB to APB bridge (APB)

The AHB to APB bridge provides full synchronous connections between the AHB and the APB bus.

Refer to Section 2.2.2: Memory map and register boundary addresses for the address mapping of the peripherals connected to this bridge.

After each device reset, all peripheral clocks are disabled (except for the SRAM and flash). Before using a peripheral you have to enable its clock in the RCC_AHBENR, RCC_APB2ENR or RCC_APB1ENR register.

Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

2.2 Memory organization

2.2.1 Introduction

Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space.

The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word's least significant byte and the highest numbered byte the most significant.

The addressable memory space is divided into eight main blocks, of 512 Mbytes each.

2.2.2 Memory map and register boundary addresses

Figure 2. Memory map

All the memory map areas not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, refer to the following table, which gives the boundary addresses of the available peripherals.

Table 1. STM32F0x0 memory boundary addresses

1. Limited to 16 KB on STM32F030x4 devices.

Table 2. STM32F0x0 peripheral register boundary addresses (continued)

2.3 Embedded SRAM

STM32F030x4 and STM32F030x6 devices feature 4 Kbytes of SRAM. STM32F030x8 devices feature 8 Kbytes of SRAM. STM32F030xC devices feature 32 Kbytes of SRAM. STM32F070x6 devices feature 6 Kbytes of SRAM. STM32F070xB devices feature 16 Kbytes of SRAM.

The SRAM can be accessed by bytes, half-words (16 bits) or full words (32 bits), at maximum system clock frequency without wait state and thus by both CPU and DMA.

Parity check

The user can enable the parity check using the option bit RAM_PARITY_CHECK in the user option byte (refer to Section 4: Option bytes ).

The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in order to increase memory robustness, as required for instance by Class B or SIL norms.

The parity bits are computed and stored when writing into the SRAM. Then, they are automatically checked when reading. If one bit fails, an NMI is generated. In addition, to get the SRAM parity error at the same cycle time that it is occurring, a bus error is generated (triggering a HardFault exception) together with the NMI. This avoids the use of corrupted data by the application, but with the side effect of having both NMI and HardFault interrupts generated. The same error can also be linked to the BRK_IN Break input of TIM1/15/16/17, with the SRAM_PARITY_LOCK control bit in the SYSCFG configuration register 2 (SYSCFG_CFGR2) . The SRAM Parity Error flag (SRAM_PEF) is available in the SYSCFG configuration register 2 (SYSCFG_CFGR2) .

Note: When enabling the RAM parity check, it is advised to initialize by software the whole RAM memory at the beginning of the code, to avoid getting parity errors when reading non-initialized locations.

2.4 Flash memory overview

The flash memory is composed of two distinct physical areas:

• • The main flash memory block. It contains the application program and user data if necessary.
• • The information block. It is composed of two parts:
  • – option bytes for hardware and memory protection user configuration
  • – system memory which contains the proprietary boot loader code (refer to Section 3: Embedded flash memory for more details.)

The flash interface implements instruction access and data access based on the AHB protocol. It implements the prefetch buffer that speeds up CPU code execution. It also implements the logic necessary to carry out the flash memory operations (Program/Erase) controlled through the flash registers.

2.5 Boot configuration

In the STM32F0x0, three different boot modes can be selected through the BOOT0 pin and boot configuration bits nBOOT1 in the User option byte, as shown in the following table.

Table 3. Boot modes

1. For STM32F070x6 and STM32F030xC devices, see also Empty check description.

The boot mode configuration is latched on the 4th rising edge of SYSCLK after a reset. It is up to the user to set boot mode configuration related to the required boot mode.

The boot mode configuration is also re-sampled when exiting from Standby mode. Consequently they must be kept in the required Boot mode configuration in Standby mode. After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.

Depending on the selected boot mode, main flash memory, system memory or SRAM is accessible as follows:

• • Boot from main flash memory: the main flash memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x0800 0000). In other words, the flash memory contents can be accessed starting from address 0x0000 0000 or 0x0800 0000.
• • Boot from system memory: the system memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x1FFF EC00 on STM32F030x4, STM32F030x6 and STM32F030x8 devices, 0x1FFF C400 on STM32F070x6 devices, 0x1FFF C800 on STM32F070xB and 0x1FFF D800 on STM32F030xC devices).
• • Boot from the embedded SRAM: the SRAM is aliased in the boot memory space (0x0000 0000), but it is still accessible from its original memory space (0x2000 0000).

Empty check

On STM32F070x6 and STM32F030xC devices only, internal empty check flag is implemented to allow easy programming of virgin devices by the boot loader. This flag is used when BOOT0 pin is defining Main flash memory as the target boot area. When the flag is set, the device is considered as empty and System memory (boot loader) is selected instead of the main flash as a boot area to allow user to program the flash memory.

Therefore, some of the GPIOs are reconfigured from the High-Z state. Refer to AN2606 for more details concerning the boot loader and GPIO configuration in System memory boot mode. It is possible to disable this feature by configuring the option bytes, to force boot from the Main flash memory (nSWBOOT0 = 0, nBOOT0 = 1).

The empty check flag is updated only during the loading of option bytes: it is set when the content of the address 0x0800 0000 is read as 0xFFFF FFFF, otherwise it is cleared. It

means a power reset or setting of OBL_LAUNCH bit in FLASH_CR register is needed to clear this flag after programming of a virgin device to execute user code after System reset.

Note: If the device is programmed for a first time but the option bytes are not reloaded, the device still selects System memory as a boot area after a System reset. In the STM32F070x6, the boot loader code is able to detect this situation. It then changes the boot memory mapping to main flash and performs a jump to user code programmed there. In the STM32F030xC, a POR must be performed or the Option bytes reloaded before applying the system reset.

Physical remap

Once the boot mode is selected, the application software can modify the memory accessible in the code area. This modification is performed by programming the MEM_MODE bits in the SYSCFG configuration register 1 (SYSCFG_CFGR1) . Unlike Cortex ^® M3 and M4, the M0 CPU does not support the vector table relocation. For application code which is located in a different address than 0x0800 0000, some additional code must be added in order to be able to serve the application interrupts. A solution is to relocate by software the vector table to the internal SRAM:

• • Copy the vector table from the flash (mapped at the base of the application load address) to the base address of the SRAM at 0x2000 0000.
• • Remap SRAM at address 0x0000 0000, using SYSCFG configuration register 1.
• • Then once an interrupt occurs, the Cortex ^® -M0 processor fetches the interrupt handler start address from the relocated vector table in SRAM, then it jumps to execute the interrupt handler located in the flash.

This operation should be done at the initialization phase of the application. Please refer to AN4065 and attached IAP code from www.st.com for more details.

Embedded boot loader

The embedded boot loader is located in the System memory, programmed by ST during production. It is used to reprogram the flash memory using one of the following serial interfaces:

• • USART on pins PA14/PA15 or PA9/PA10
• • I2C on pins PB6/PB7 (STM32F070xx and STM32F030xC devices only)
• • USB DFU interface (STM32F070xx devices only)

For further details, refer to the application note AN2606.