RM0360-STM32F030x4-x6-x8-xC-070x6-xB

Introduction

This reference manual targets application developers. It provides complete information on how to use the STM32F030x4/x6/x8/xC and STM32F070x6/xB microcontroller memory and peripherals.

It applies to STM32F030x4/x6/x8/xC and STM32F070x6/xB devices.

For the purpose of this manual, STM32F030x4/x6/x8/xC and STM32F070x6/xB microcontrollers are referred to as STM32F0x0.

The STM32F0x0 is a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics, please refer to the corresponding datasheet.

For information on the Arm ^®Cortex ^®-M0 core, please refer to the Arm ^®Cortex ^®-M0 technical reference manual .

STM32F030x4/x6/x8/xC and STM32F070x6/xB microcontrollers include ST state-of-the-art patented technology.

• Arm ^®Cortex ^®-M0 technical reference manual, available from Arm website at www.arm.com
• STM32F0xx Cortex-M0 programming manual (PM0215)
• STM32F030x4/x6/x8/xC and STM32F070x6/xB datasheets available from STMicroelectronics website at www.st.com
• STM32F030x4/x6/x8/xC and STM32F070x6/xB errata sheets available from STMicroelectronics website at www.st.com

1 Documentation conventions . . . . . 33
- 1.1 General information . . . . . 33
- 1.2 List of abbreviations for registers . . . . . 33
- 1.3 Glossary . . . . . 34
- 1.4 Availability of peripherals . . . . . 34
2 System and memory overview . . . . . 35
- 2.1 System architecture . . . . . 35
- 2.2 Memory organization . . . . . 37
  - 2.2.1 Introduction . . . . . 37
  - 2.2.2 Memory map and register boundary addresses . . . . . 38
- 2.3 Embedded SRAM . . . . . 42
- 2.4 Flash memory overview . . . . . 43
- 2.5 Boot configuration . . . . . 44
3 Embedded flash memory . . . . . 46
- 3.1 Flash main features . . . . . 46
- 3.2 Flash memory functional description . . . . . 46
  - 3.2.1 Flash memory organization . . . . . 46
  - 3.2.2 Flash program and erase operations . . . . . 49
- 3.3 Memory protection . . . . . 56
  - 3.3.1 Read protection . . . . . 56
  - 3.3.2 Write protection . . . . . 58
  - 3.3.3 Option byte write protection . . . . . 58
- 3.4 Flash interrupts . . . . . 58
- 3.5 Flash register description . . . . . 59
  - 3.5.1 Flash access control register (FLASH_ACR) . . . . . 59
  - 3.5.2 Flash key register (FLASH_KEYR) . . . . . 59
  - 3.5.3 Flash option key register (FLASH_OPTKEYR) . . . . . 60
  - 3.5.4 Flash status register (FLASH_SR) . . . . . 61
  - 3.5.5 Flash control register (FLASH_CR) . . . . . 61
  - 3.5.6 Flash address register (FLASH_AR) . . . . . 63
  - 3.5.7 Flash Option byte register (FLASH_OBR) . . . . . 63

3.5.8	Write protection register (FLASH_WRPR) . . . . .	64
3.5.9	Flash register map . . . . .	65
4	Option bytes . . . . .	66
4.1	Option byte description . . . . .	67
4.1.1	User and read protection option byte . . . . .	67
4.1.2	User data option byte . . . . .	68
4.1.3	Write protection option byte . . . . .	68
4.1.4	Option byte map . . . . .	69
5	Cyclic redundancy check calculation unit (CRC) . . . . .	70
5.1	Introduction . . . . .	70
5.2	CRC main features . . . . .	70
5.3	CRC functional description . . . . .	71
5.3.1	CRC block diagram . . . . .	71
5.3.2	CRC internal signals . . . . .	71
5.3.3	CRC operation . . . . .	71
5.4	CRC registers . . . . .	72
5.4.1	CRC data register (CRC_DR) . . . . .	72
5.4.2	CRC independent data register (CRC_IDR) . . . . .	73
5.4.3	CRC control register (CRC_CR) . . . . .	73
5.4.4	CRC initial value (CRC_INIT) . . . . .	74
5.4.5	CRC register map . . . . .	75
6	Power control (PWR) . . . . .	76
6.1	Power supplies . . . . .	76
6.1.1	Independent A/D converter supply and reference voltage . . . . .	76
6.1.2	Voltage regulator . . . . .	77
6.2	Power supply supervisor . . . . .	77
6.2.1	Power on reset (POR) / power down reset (PDR) . . . . .	77
6.3	Low-power modes . . . . .	78
6.3.1	Slowing down system clocks . . . . .	79
6.3.2	Peripheral clock gating . . . . .	80
6.3.3	Sleep mode . . . . .	80
6.3.4	Stop mode . . . . .	81
6.3.5	Standby mode . . . . .	83

6.3.6	RTC wakeup from low-power mode . . . . .	84
6.4	Power control registers . . . . .	85
6.4.1	Power control register (PWR_CR) . . . . .	85
6.4.2	Power control/status register (PWR_CSR) . . . . .	86
6.4.3	PWR register map . . . . .	87
7	Reset and clock control (RCC) . . . . .	88
7.1	Reset . . . . .	88
7.1.1	Power reset . . . . .	88
7.1.2	System reset . . . . .	88
7.1.3	RTC domain reset . . . . .	89
7.2	Clocks . . . . .	90
7.2.1	HSE clock . . . . .	93
7.2.2	HSI clock . . . . .	94
7.2.3	PLL . . . . .	95
7.2.4	LSE clock . . . . .	95
7.2.5	LSI clock . . . . .	96
7.2.6	System clock (SYSCLK) selection . . . . .	96
7.2.7	Clock security system (CSS) . . . . .	96
7.2.8	ADC clock . . . . .	97
7.2.9	RTC clock . . . . .	97
7.2.10	Independent watchdog clock . . . . .	97
7.2.11	Clock-out capability . . . . .	97
7.2.12	Internal/external clock measurement with TIM14 . . . . .	98
7.3	Low-power modes . . . . .	99
7.4	RCC registers . . . . .	100
7.4.1	Clock control register (RCC_CR) . . . . .	100
7.4.2	Clock configuration register (RCC_CFGR) . . . . .	101
7.4.3	Clock interrupt register (RCC_CIR) . . . . .	104
7.4.4	APB peripheral reset register 2 (RCC_APB2RSTR) . . . . .	107
7.4.5	APB peripheral reset register 1 (RCC_APB1RSTR) . . . . .	108
7.4.6	AHB peripheral clock enable register (RCC_AHBENR) . . . . .	110
7.4.7	APB peripheral clock enable register 2 (RCC_APB2ENR) . . . . .	111
7.4.8	APB peripheral clock enable register 1 (RCC_APB1ENR) . . . . .	113
7.4.9	RTC domain control register (RCC_BDCR) . . . . .	115
7.4.10	Control/status register (RCC_CSR) . . . . .	116
7.4.11	AHB peripheral reset register (RCC_AHBRSTR) . . . . .	118

7.4.12	Clock configuration register 2 (RCC_CFGR2) .....	119
7.4.13	Clock configuration register 3 (RCC_CFGR3) .....	120
7.4.14	Clock control register 2 (RCC_CR2) .....	121
7.4.15	RCC register map .....	123
8	General-purpose I/Os (GPIO) .....	125
8.1	Introduction .....	125
8.2	GPIO main features .....	125
8.3	GPIO functional description .....	125
8.3.1	General-purpose I/O (GPIO) .....	127
8.3.2	I/O pin alternate function multiplexer and mapping .....	127
8.3.3	I/O port control registers .....	128
8.3.4	I/O port data registers .....	128
8.3.5	I/O data bitwise handling .....	128
8.3.6	GPIO locking mechanism .....	129
8.3.7	I/O alternate function input/output .....	129
8.3.8	External interrupt/wake-up lines .....	129
8.3.9	Input configuration .....	130
8.3.10	Output configuration .....	130
8.3.11	Alternate function configuration .....	131
8.3.12	Analog configuration .....	132
8.3.13	Using the HSE or LSE oscillator pins as GPIOs .....	133
8.3.14	Using the GPIO pins in the RTC supply domain .....	133
8.4	GPIO registers .....	134
8.4.1	GPIO port mode register (GPIOx_MODER) (x =A to D, F) .....	134
8.4.2	GPIO port output type register (GPIOx_OTYPER) (x = A to D, F) .....	134
8.4.3	GPIO port output speed register (GPIOx_OSPEEDR) (x = A to D, F) .....	135
8.4.4	GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to ,D, F) .....	135
8.4.5	GPIO port input data register (GPIOx_IDR) (x = A to D, F) .....	136
8.4.6	GPIO port output data register (GPIOx_ODR) (x = A to D, F) .....	136
8.4.7	GPIO port bit set/reset register (GPIOx_BSRR) (x = A to D, F) .....	137

8.4.8	GPIO port configuration lock register (GPIOx_LCKR) (x = A to B) . . . . .	137
8.4.9	GPIO alternate function low register (GPIOx_AFRL) (x = A to D, ) . . . . .	138
8.4.10	GPIO alternate function high register (GPIOx_AFRH) (x = A to D, F) . . . . .	139
8.4.11	GPIO port bit reset register (GPIOx_BRR) (x = A to D, F) . . . . .	139
8.4.12	GPIO register map . . . . .	140
9	System configuration controller (SYSCFG) . . . . .	142
9.1	SYSCFG registers . . . . .	142
9.1.1	SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .	142
9.1.2	SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . .	144
9.1.3	SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) . . . . .	145
9.1.4	SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) . . . . .	145
9.1.5	SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) . . . . .	146
9.1.6	SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .	147
9.1.7	SYSCFG register maps . . . . .	148
10	Direct memory access controller (DMA) . . . . .	149
10.1	Introduction . . . . .	149
10.2	DMA main features . . . . .	149
10.3	DMA implementation . . . . .	150
10.3.1	DMA . . . . .	150
10.3.2	DMA request mapping . . . . .	150
10.4	DMA functional description . . . . .	153
10.4.1	DMA block diagram . . . . .	153
10.4.2	DMA transfers . . . . .	154
10.4.3	DMA arbitration . . . . .	155
10.4.4	DMA channels . . . . .	155
10.4.5	DMA data width, alignment and endianness . . . . .	159
10.4.6	DMA error management . . . . .	160
10.5	DMA interrupts . . . . .	161
10.6	DMA registers . . . . .	161

10.6.1	DMA interrupt status register (DMA_ISR) . . . . .	161
10.6.2	DMA interrupt flag clear register (DMA_IFCR) . . . . .	163
10.6.3	DMA channel x configuration register (DMA_CCRx) . . . . .	164
10.6.4	DMA channel x number of data to transfer register (DMA_CNDTRx) . . . . .	166
10.6.5	DMA channel x peripheral address register (DMA_CPARx) . . . . .	167
10.6.6	DMA channel x memory address register (DMA_CMARx) . . . . .	168
10.6.7	DMA channel selection register (DMA_CSELR) . . . . .	168
10.6.8	DMA register map . . . . .	169
11	Interrupts and events . . . . .	171
11.1	Nested vectored interrupt controller (NVIC) . . . . .	171
11.1.1	NVIC main features . . . . .	171
11.1.2	SysTick calibration value register . . . . .	171
11.1.3	Interrupt and exception vectors . . . . .	171
11.2	Extended interrupts and events controller (EXTI) . . . . .	173
11.2.1	Main features . . . . .	173
11.2.2	Block diagram . . . . .	174
11.2.3	Event management . . . . .	174
11.2.4	Functional description . . . . .	174
11.2.5	External and internal interrupt/event line mapping . . . . .	176
11.3	EXTI registers . . . . .	177
11.3.1	Interrupt mask register (EXTI_IMR) . . . . .	177
11.3.2	Event mask register (EXTI_EMR) . . . . .	177
11.3.3	Rising trigger selection register (EXTI_RTSR) . . . . .	177
11.3.4	Falling trigger selection register (EXTI_FTSR) . . . . .	178
11.3.5	Software interrupt event register (EXTI_SWIER) . . . . .	179
11.3.6	Pending register (EXTI_PR) . . . . .	179
11.3.7	EXTI register map . . . . .	181
12	Analog-to-digital converter (ADC) . . . . .	182
12.1	Introduction . . . . .	182
12.2	ADC main features . . . . .	183
12.3	ADC functional description . . . . .	184
12.3.1	ADC pins and internal signals . . . . .	184
12.3.2	Calibration (ADCAL) . . . . .	185
12.3.3	ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .	186
12.3.4	ADC clock (CKMODE) . . . . .	188

12.3.5	Configuring the ADC . . . . .	189
12.3.6	Channel selection (CHSEL, SCANDIR) . . . . .	189
12.3.7	Programmable sampling time (SMP) . . . . .	190
12.3.8	Single conversion mode (CONT = 0) . . . . .	190
12.3.9	Continuous conversion mode (CONT = 1) . . . . .	191
12.3.10	Starting conversions (ADSTART) . . . . .	191
12.3.11	Timings . . . . .	192
12.3.12	Stopping an ongoing conversion (ADSTP) . . . . .	193
12.4	Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . . . . .	193
12.4.1	Discontinuous mode (DISCEN) . . . . .	194
12.4.2	Programmable resolution (RES) - Fast conversion mode . . . . .	194
12.4.3	End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . .	195
12.4.4	End of conversion sequence (EOS flag) . . . . .	195
12.4.5	Example timing diagrams (single/continuous modes hardware/software triggers) . . . . .	196
12.5	Data management . . . . .	198
12.5.1	Data register and data alignment (ADC_DR, ALIGN) . . . . .	198
12.5.2	ADC overrun (OVR, OVRMOD) . . . . .	198
12.5.3	Managing a sequence of data converted without using the DMA . . . . .	199
12.5.4	Managing converted data without using the DMA without overrun . . . . .	199
12.5.5	Managing converted data using the DMA . . . . .	199
12.6	Low-power features . . . . .	201
12.6.1	Wait mode conversion . . . . .	201
12.6.2	Auto-off mode (AUTOFF) . . . . .	202
12.7	Analog window watchdog . . . . .	203
12.7.1	Description of the analog watchdog . . . . .	203
12.7.2	ADC_AWD1_OUT output signal generation . . . . .	204
12.7.3	Analog watchdog threshold control . . . . .	206
12.8	Temperature sensor and internal reference voltage . . . . .	207
12.9	ADC interrupts . . . . .	210
12.10	ADC registers . . . . .	211
12.10.1	ADC interrupt and status register (ADC_ISR) . . . . .	211
12.10.2	ADC interrupt enable register (ADC_IER) . . . . .	212
12.10.3	ADC control register (ADC_CR) . . . . .	214
12.10.4	ADC configuration register 1 (ADC_CFGR1) . . . . .	216
12.10.5	ADC configuration register 2 (ADC_CFGR2) . . . . .	220

12.10.6	ADC sampling time register (ADC_SMPR)	220
12.10.7	ADC watchdog threshold register (ADC_TR)	221
12.10.8	ADC channel selection register (ADC_CHSELR)	221
12.10.9	ADC data register (ADC_DR)	222
12.10.10	ADC common configuration register (ADC_CCR)	223
12.11	ADC register map	223
13	Advanced-control timers (TIM1)	225
13.1	TIM1 introduction	225
13.2	TIM1 main features	225
13.3	TIM1 functional description	227
13.3.1	Time-base unit	227
13.3.2	Counter modes	229
13.3.3	Repetition counter	239
13.3.4	Clock sources	241
13.3.5	Capture/compare channels	244
13.3.6	Input capture mode	247
13.3.7	PWM input mode	248
13.3.8	Forced output mode	249
13.3.9	Output compare mode	249
13.3.10	PWM mode	250
13.3.11	Complementary outputs and dead-time insertion	254
13.3.12	Using the break function	256
13.3.13	Clearing the OCxREF signal on an external event	259
13.3.14	6-step PWM generation	261
13.3.15	One-pulse mode	262
13.3.16	Encoder interface mode	263
13.3.17	Timer input XOR function	266
13.3.18	Interfacing with Hall sensors	266
13.3.19	TIMx and external trigger synchronization	268
13.3.20	Timer synchronization	271
13.3.21	Debug mode	271
13.4	TIM1 registers	272
13.4.1	TIM1 control register 1 (TIM1_CR1)	272
13.4.2	TIM1 control register 2 (TIM1_CR2)	273
13.4.3	TIM1 slave mode control register (TIM1_SMCR)	275
13.4.4	TIM1 DMA/interrupt enable register (TIM1_DIER)	278

13.4.5	TIM1 status register (TIM1_SR) .....	280
13.4.6	TIM1 event generation register (TIM1_EGR) .....	281
13.4.7	TIM1 capture/compare mode register 1 (TIM1_CCMR1) .....	283
13.4.8	TIM1 capture/compare mode register 2 (TIM1_CCMR2) .....	286
13.4.9	TIM1 capture/compare enable register (TIM1_CCER) .....	288
13.4.10	TIM1 counter (TIM1_CNT) .....	291
13.4.11	TIM1 prescaler (TIM1_PSC) .....	292
13.4.12	TIM1 auto-reload register (TIM1_ARR) .....	292
13.4.13	TIM1 repetition counter register (TIM1_RCR) .....	292
13.4.14	TIM1 capture/compare register 1 (TIM1_CCR1) .....	293
13.4.15	TIM1 capture/compare register 2 (TIM1_CCR2) .....	293
13.4.16	TIM1 capture/compare register 3 (TIM1_CCR3) .....	294
13.4.17	TIM1 capture/compare register 4 (TIM1_CCR4) .....	295
13.4.18	TIM1 break and dead-time register (TIM1_BDTR) .....	295
13.4.19	TIM1 DMA control register (TIM1_DCR) .....	297
13.4.20	TIM1 DMA address for full transfer (TIM1_DMAR) .....	298
13.4.21	TIM1 register map .....	299
14	General-purpose timers (TIM3) .....	301
14.1	TIM3 introduction .....	301
14.2	TIM3 main features .....	301
14.3	TIM3 functional description .....	302
14.3.1	Time-base unit .....	302
14.3.2	Counter modes .....	304
14.3.3	Clock sources .....	315
14.3.4	Capture/compare channels .....	318
14.3.5	Input capture mode .....	320
14.3.6	PWM input mode .....	322
14.3.7	Forced output mode .....	323
14.3.8	Output compare mode .....	323
14.3.9	PWM mode .....	324
14.3.10	One-pulse mode .....	328
14.3.11	Clearing the OCxREF signal on an external event .....	329
14.3.12	Encoder interface mode .....	330
14.3.13	Timer input XOR function .....	332
14.3.14	Timers and external trigger synchronization .....	333
14.3.15	Timer synchronization .....	336

14.3.16	Debug mode	342
14.4	TIM3 registers	343
14.4.1	TIM3 control register 1 (TIM3_CR1)	343
14.4.2	TIM3 control register 2 (TIM3_CR2)	345
14.4.3	TIM3 slave mode control register (TIM3_SMCR)	346
14.4.4	TIM3 DMA/Interrupt enable register (TIM3_DIER)	348
14.4.5	TIM3 status register (TIM3_SR)	349
14.4.6	TIM3 event generation register (TIM3_EGR)	352
14.4.7	TIM3 capture/compare mode register 1 (TIM3_CCMR1)	353
14.4.8	TIM3 capture/compare mode register 2 (TIM3_CCMR2)	356
14.4.9	TIM3 capture/compare enable register (TIM3_CCER)	357
14.4.10	TIM3 counter (TIM3_CNT)	359
14.4.11	TIM3 prescaler (TIM3_PSC)	359
14.4.12	TIM3 auto-reload register (TIM3_ARR)	359
14.4.13	TIM3 capture/compare register 1 (TIM3_CCR1)	360
14.4.14	TIM3 capture/compare register 2 (TIM3_CCR2)	360
14.4.15	TIM3 capture/compare register 3 (TIM3_CCR3)	360
14.4.16	TIM3 capture/compare register 4 (TIM3_CCR4)	362
14.4.17	TIM3 DMA control register (TIM3_DCR)	362
14.4.18	TIM3 DMA address for full transfer (TIM3_DMAR)	363
14.4.19	TIM3 register map	365
15	Basic timer (TIM6/TIM7)	367
15.1	TIM6/TIM7 introduction	367
15.2	TIM6/TIM7 main features	367
15.3	TIM6/TIM7 functional description	368
15.3.1	Time-base unit	368
15.3.2	Counter modes	370
15.3.3	Clock source	374
15.3.4	Debug mode	374
15.4	TIM6/TIM7 registers	375
15.4.1	TIM6/TIM7 control register 1 (TIMx_CR1)	375
15.4.2	TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER)	376
15.4.3	TIM6/TIM7 status register (TIMx_SR)	377
15.4.4	TIM6/TIM7 event generation register (TIMx_EGR)	377
15.4.5	TIM6/TIM7 counter (TIMx_CNT)	377
15.4.6	TIM6/TIM7 prescaler (TIMx_PSC)	378

15.4.7	TIM6/TIM7 auto-reload register (TIMx_ARR) .....	378
15.4.8	TIM6/TIM7 register map .....	379
16	General-purpose timer (TIM14) .....	380
16.1	TIM14 introduction .....	380
16.2	TIM14 main features .....	380
16.3	TIM14 functional description .....	381
16.3.1	Time-base unit .....	381
16.3.2	Counter operation .....	382
16.3.3	Clock source .....	385
16.3.4	Capture/compare channels .....	385
16.3.5	Input capture mode .....	387
16.3.6	Forced output mode .....	388
16.3.7	Output compare mode .....	388
16.3.8	PWM mode .....	390
16.3.9	Debug mode .....	391
16.4	TIM14 registers .....	391
16.4.1	TIM14 control register 1 (TIM14_CR1) .....	391
16.4.2	TIM14 interrupt enable register (TIM14_DIER) .....	392
16.4.3	TIM14 status register (TIM14_SR) .....	393
16.4.4	TIM14 event generation register (TIM14_EGR) .....	393
16.4.5	TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1) .....	394
16.4.6	TIM14 capture/compare mode register 1 [alternate] (TIM14_CCMR1) .....	395
16.4.7	TIM14 capture/compare enable register (TIM14_CCER) .....	396
16.4.8	TIM14 counter (TIM14_CNT) .....	397
16.4.9	TIM14 prescaler (TIM14_PSC) .....	398
16.4.10	TIM14 auto-reload register (TIM14_ARR) .....	398
16.4.11	TIM14 capture/compare register 1 (TIM14_CCR1) .....	398
16.4.12	TIM14 option register (TIM14_OR) .....	399
16.4.13	TIM14 register map .....	399
17	General-purpose timers (TIM15/16/17) .....	401
17.1	TIM15/16/17 introduction .....	401
17.2	TIM15 main features .....	401
17.3	TIM16 and TIM17 main features .....	403
17.4	TIM15/16/17 functional description .....	404

17.4.1	Time-base unit . . . . .	404
17.4.2	Counter operation . . . . .	406
17.4.3	Repetition counter . . . . .	410
17.4.4	Clock sources . . . . .	411
17.4.5	Capture/compare channels . . . . .	413
17.4.6	Input capture mode . . . . .	416
17.4.7	PWM input mode (only for TIM15) . . . . .	417
17.4.8	Forced output mode . . . . .	417
17.4.9	Output compare mode . . . . .	418
17.4.10	PWM mode . . . . .	419
17.4.11	Complementary outputs and dead-time insertion . . . . .	420
17.4.12	Using the break function . . . . .	422
17.4.13	One-pulse mode . . . . .	425
17.4.14	TIM15 external trigger synchronization . . . . .	426
17.4.15	Timer synchronization (TIM15) . . . . .	429
17.4.16	Debug mode . . . . .	429
17.5	TIM15 registers . . . . .	430
17.5.1	TIM15 control register 1 (TIM15_CR1) . . . . .	430
17.5.2	TIM15 control register 2 (TIM15_CR2) . . . . .	431
17.5.3	TIM15 slave mode control register (TIM15_SMCR) . . . . .	432
17.5.4	TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .	434
17.5.5	TIM15 status register (TIM15_SR) . . . . .	435
17.5.6	TIM15 event generation register (TIM15_EGR) . . . . .	437
17.5.7	TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) . . . . .	438
17.5.8	TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) . . . . .	439
17.5.9	TIM15 capture/compare enable register (TIM15_CCER) . . . . .	441
17.5.10	TIM15 counter (TIM15_CNT) . . . . .	444
17.5.11	TIM15 prescaler (TIM15_PSC) . . . . .	444
17.5.12	TIM15 auto-reload register (TIM15_ARR) . . . . .	444
17.5.13	TIM15 repetition counter register (TIM15_RCR) . . . . .	445
17.5.14	TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .	445
17.5.15	TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .	445
17.5.16	TIM15 break and dead-time register (TIM15_BDTR) . . . . .	446
17.5.17	TIM15 DMA control register (TIM15_DCR) . . . . .	448
17.5.18	TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .	449
17.5.19	TIM15 register map . . . . .	449
17.6	TIM16/TIM17 registers . . . . .	450

- 17.6.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . . 450
- 17.6.2 TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . . 452
- 17.6.3 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . . 452
- 17.6.4 TIMx status register (TIMx_SR)(x = 16 to 17) . . . . . 453
- 17.6.5 TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . . 454
- 17.6.6 TIMx capture/compare mode register 1 [alternate]
  (TIMx_CCMR1)(x = 16 to 17) . . . . . 455
- 17.6.7 TIMx capture/compare mode register 1 [alternate]
  (TIMx_CCMR1)(x = 16 to 17) . . . . . 456
- 17.6.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . . 458
- 17.6.9 TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . . 461
- 17.6.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . . 461
- 17.6.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . . 461
- 17.6.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . . 462
- 17.6.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . . 462
- 17.6.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . . 462
- 17.6.15 TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . . 464
- 17.6.16 TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . . 465
- 17.6.17 TIM16/TIM17 register map . . . . . 466
18 Infrared interface (IRTIM) . . . . . 468
19 Independent watchdog (IWDG) . . . . . 469
- 19.1 Introduction . . . . . 469
- 19.2 IWDG main features . . . . . 469
- 19.3 IWDG functional description . . . . . 469
  - 19.3.1 IWDG block diagram . . . . . 469
  - 19.3.2 Window option . . . . . 470
  - 19.3.3 Hardware watchdog . . . . . 471
  - 19.3.4 Register access protection . . . . . 471
  - 19.3.5 Debug mode . . . . . 471
- 19.4 IWDG registers . . . . . 472
  - 19.4.1 IWDG key register (IWDG_KR) . . . . . 472
  - 19.4.2 IWDG prescaler register (IWDG_PR) . . . . . 473
  - 19.4.3 IWDG reload register (IWDG_RLR) . . . . . 474
  - 19.4.4 IWDG status register (IWDG_SR) . . . . . 475
  - 19.4.5 IWDG window register (IWDG_WINR) . . . . . 476

19.4.6	IWDG register map .....	477
20	System window watchdog (WWDG) .....	478
20.1	Introduction .....	478
20.2	WWDG main features .....	478
20.3	WWDG functional description .....	478
20.3.1	WWDG block diagram .....	479
20.3.2	Enabling the watchdog .....	479
20.3.3	Controlling the down-counter .....	479
20.3.4	How to program the watchdog timeout .....	479
20.3.5	Debug mode .....	480
20.4	WWDG interrupts .....	481
20.5	WWDG registers .....	481
20.5.1	WWDG control register (WWDG_CR) .....	481
20.5.2	WWDG configuration register (WWDG_CFR) .....	482
20.5.3	WWDG status register (WWDG_SR) .....	482
20.5.4	WWDG register map .....	483
21	Real-time clock (RTC) .....	484
21.1	Introduction .....	484
21.2	RTC main features .....	485
21.3	RTC implementation .....	485
21.4	RTC functional description .....	486
21.4.1	RTC block diagram .....	486
21.4.2	GPIOs controlled by the RTC .....	488
21.4.3	Clock and prescalers .....	489
21.4.4	Real-time clock and calendar .....	490
21.4.5	Programmable alarm .....	490
21.4.6	Periodic auto-wake-up .....	491
21.4.7	RTC initialization and configuration .....	491
21.4.8	Reading the calendar .....	493
21.4.9	Resetting the RTC .....	494
21.4.10	RTC synchronization .....	494
21.4.11	RTC reference clock detection .....	495
21.4.12	RTC smooth digital calibration .....	496
21.4.13	Time-stamp function .....	498

- - 21.4.14 Tamper detection . . . . . 498
  - 21.4.15 Calibration clock output . . . . . 500
  - 21.4.16 Alarm output . . . . . 500
- 21.5 RTC low-power modes . . . . . 501
- 21.6 RTC interrupts . . . . . 501
- 21.7 RTC registers . . . . . 501
  - 21.7.1 RTC time register (RTC_TR) . . . . . 501
  - 21.7.2 RTC date register (RTC_DR) . . . . . 502
  - 21.7.3 RTC control register (RTC_CR) . . . . . 504
  - 21.7.4 RTC initialization and status register (RTC_ISR) . . . . . 507
  - 21.7.5 RTC prescaler register (RTC_PRER) . . . . . 509
  - 21.7.6 RTC wake-up timer register (RTC_WUTR) . . . . . 510
  - 21.7.7 RTC alarm A register (RTC_ALRMAR) . . . . . 511
  - 21.7.8 RTC write protection register (RTC_WPR) . . . . . 512
  - 21.7.9 RTC sub second register (RTC_SSR) . . . . . 512
  - 21.7.10 RTC shift control register (RTC_SHIFT) . . . . . 513
  - 21.7.11 RTC timestamp time register (RTC_TSTR) . . . . . 514
  - 21.7.12 RTC timestamp date register (RTC_TSDR) . . . . . 515
  - 21.7.13 RTC time-stamp sub second register (RTC_TSSSR) . . . . . 516
  - 21.7.14 RTC calibration register (RTC_CALR) . . . . . 517
  - 21.7.15 RTC tamper and alternate function configuration register
    (RTC_TAFCR) . . . . . 518
  - 21.7.16 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . 521
  - 21.7.17 RTC register map . . . . . 521
22 Inter-integrated circuit (I2C) interface . . . . . 524
- 22.1 Introduction . . . . . 524
- 22.2 I2C main features . . . . . 524
- 22.3 I2C implementation . . . . . 525
- 22.4 I2C functional description . . . . . 525
  - 22.4.1 I2C block diagram . . . . . 526
  - 22.4.2 I2C2 block diagram . . . . . 526
  - 22.4.3 I2C pins and internal signals . . . . . 527
  - 22.4.4 I2C clock requirements . . . . . 527
  - 22.4.5 Mode selection . . . . . 528
  - 22.4.6 I2C initialization . . . . . 529
  - 22.4.7 Software reset . . . . . 533

22.4.8	Data transfer . . . . .	534
22.4.9	I2C slave mode . . . . .	536
22.4.10	I2C master mode . . . . .	545
22.4.11	I2C_TIMINGR register configuration examples . . . . .	556
22.4.12	SMBus specific features . . . . .	558
22.4.13	SMBus initialization . . . . .	561
22.4.14	SMBus: I2C_TIMEOUTR register configuration examples . . . . .	563
22.4.15	SMBus slave mode . . . . .	563
22.4.16	Error conditions . . . . .	570
22.4.17	DMA requests . . . . .	572
22.4.18	Debug mode . . . . .	573
22.5	I2C low-power modes . . . . .	573
22.6	I2C interrupts . . . . .	574
22.7	I2C registers . . . . .	575
22.7.1	I2C control register 1 (I2C_CR1) . . . . .	575
22.7.2	I2C control register 2 (I2C_CR2) . . . . .	577
22.7.3	I2C own address 1 register (I2C_OAR1) . . . . .	579
22.7.4	I2C own address 2 register (I2C_OAR2) . . . . .	580
22.7.5	I2C timing register (I2C_TIMINGR) . . . . .	581
22.7.6	I2C timeout register (I2C_TIMEOUTR) . . . . .	582
22.7.7	I2C interrupt and status register (I2C_ISR) . . . . .	583
22.7.8	I2C interrupt clear register (I2C_ICR) . . . . .	585
22.7.9	I2C PEC register (I2C_PECR) . . . . .	586
22.7.10	I2C receive data register (I2C_RXDR) . . . . .	587
22.7.11	I2C transmit data register (I2C_TXDR) . . . . .	587
22.7.12	I2C register map . . . . .	588
23	Universal synchronous/asynchronous receiver transmitter (USART/UART) . . . . .	590
23.1	Introduction . . . . .	590
23.2	USART main features . . . . .	590
23.3	USART implementation . . . . .	592
23.4	USART functional description . . . . .	593
23.4.1	USART character description . . . . .	594
23.4.2	USART transmitter . . . . .	595
23.4.3	USART receiver . . . . .	598

23.4.4	USART baud rate generation . . . . .	604
23.4.5	Tolerance of the USART receiver to clock deviation . . . . .	606
23.4.6	USART auto baud rate detection . . . . .	607
23.4.7	Multiprocessor communication using USART . . . . .	607
23.4.8	USART parity control . . . . .	610
23.4.9	USART synchronous mode . . . . .	610
23.4.10	USART Single-wire Half-duplex communication . . . . .	613
23.4.11	USART continuous communication in DMA mode . . . . .	613
23.4.12	RS232 hardware flow control and RS485 driver enable using USART . . . . .	616
23.5	USART in low-power modes . . . . .	618
23.6	USART interrupts . . . . .	619
23.7	USART registers . . . . .	620
23.7.1	USART control register 1 (USART_CR1) . . . . .	620
23.7.2	USART control register 2 (USART_CR2) . . . . .	623
23.7.3	USART control register 3 (USART_CR3) . . . . .	626
23.7.4	USART baud rate register (USART_BRR) . . . . .	628
23.7.5	USART receiver timeout register (USART_RTOR) . . . . .	628
23.7.6	USART request register (USART_RQR) . . . . .	629
23.7.7	USART interrupt and status register (USART_ISR) . . . . .	630
23.7.8	USART interrupt flag clear register (USART_ICR) . . . . .	633
23.7.9	USART receive data register (USART_RDR) . . . . .	634
23.7.10	USART transmit data register (USART_TDR) . . . . .	635
23.7.11	USART register map . . . . .	635
24	Serial peripheral interface (SPI) . . . . .	637
24.1	Introduction . . . . .	637
24.2	SPI main features . . . . .	637
24.3	SPI implementation . . . . .	638
24.4	SPI functional description . . . . .	638
24.4.1	General description . . . . .	638
24.4.2	Communications between one master and one slave . . . . .	639
24.4.3	Standard multislave communication . . . . .	642
24.4.4	Multimaster communication . . . . .	642
24.4.5	Slave select (NSS) pin management . . . . .	643
24.4.6	Communication formats . . . . .	644
24.4.7	Configuration of SPI . . . . .	646

24.4.8	Procedure for enabling SPI .....	647
24.4.9	Data transmission and reception procedures .....	647
24.4.10	SPI status flags .....	657
24.4.11	SPI error flags .....	658
24.4.12	NSS pulse mode .....	659
24.4.13	TI mode .....	659
24.4.14	CRC calculation .....	660
24.5	SPI interrupts .....	662
24.6	SPI registers .....	663
24.6.1	SPI control register 1 (SPIx_CR1) .....	663
24.6.2	SPI control register 2 (SPIx_CR2) .....	665
24.6.3	SPI status register (SPIx_SR) .....	667
24.6.4	SPI data register (SPIx_DR) .....	668
24.6.5	SPI CRC polynomial register (SPIx_CRCPR) .....	669
24.6.6	SPI Rx CRC register (SPIx_RXCRCR) .....	669
24.6.7	SPI Tx CRC register (SPIx_TXCRCR) .....	669
24.6.8	SPI register map .....	671
25	Universal serial bus full-speed device interface (USB) .....	672
25.1	Introduction .....	672
25.2	USB main features .....	672
25.3	USB implementation .....	672
25.4	USB functional description .....	673
25.4.1	Description of USB blocks .....	674
25.5	Programming considerations .....	675
25.5.1	Generic USB device programming .....	675
25.5.2	System and power-on reset .....	676
25.5.3	Double-buffered endpoints .....	681
25.5.4	Isochronous transfers .....	683
25.5.5	Suspend/Resume events .....	684
25.6	USB and USB SRAM registers .....	687
25.6.1	Common registers .....	687
25.6.2	Buffer descriptor table .....	700
25.6.3	USB register map .....	703
26	Debug support (DBG) .....	705

26.1 Overview . . . . . 705
26.2 Reference Arm documentation . . . . . 706
26.3 Pinout and debug port pins . . . . . 706
- 26.3.1 SWD port pins . . . . . 707
- 26.3.2 SW-DP pin assignment . . . . . 707
- 26.3.3 Internal pull-up and pull-down on SWD pins . . . . . 707
26.4 ID codes and locking mechanism . . . . . 707
- 26.4.1 MCU device ID code . . . . . 708
26.5 SWD port . . . . . 708
- 26.5.1 SWD protocol introduction . . . . . 708
- 26.5.2 SWD protocol sequence . . . . . 709
- 26.5.3 SW-DP state machine (reset, idle states, ID code) . . . . . 710
- 26.5.4 DP and AP read/write accesses . . . . . 710
- 26.5.5 SW-DP registers . . . . . 711
- 26.5.6 SW-AP registers . . . . . 712
26.6 Core debug . . . . . 712
26.7 BPU (Break Point Unit) . . . . . 713
- 26.7.1 BPU functionality . . . . . 713
26.8 DWT (Data Watchpoint) . . . . . 713
- 26.8.1 DWT functionality . . . . . 713
- 26.8.2 DWT Program Counter Sample Register . . . . . 713
26.9 MCU debug component (DBGMCU) . . . . . 713
- 26.9.1 Debug support for low-power modes . . . . . 714
- 26.9.2 Debug support for timers, watchdog and I ²C . . . . . 714
- 26.9.3 Debug MCU configuration register (DBGMCU_CR) . . . . . 715
- 26.9.4 Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . . 716
- 26.9.5 Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) . . . . . 718
- 26.9.6 DBG register map . . . . . 718

27 Device electronic signature . . . . . 720

27.1 Flash memory size data register . . . . . 720

Appendix A Code examples. . . . . 721

A.1 Introduction . . . . . 721
A.2 FLASH operation code examples . . . . . 721
- A.2.1 Flash memory unlocking sequence . . . . . 721

A.2.2	Main flash memory programming sequence . . . . .	721
A.2.3	Page erase sequence . . . . .	722
A.2.4	Mass erase sequence . . . . .	723
A.2.5	Option byte unlocking sequence . . . . .	723
A.2.6	Option byte programming sequence . . . . .	724
A.2.7	Option byte erasing sequence . . . . .	724
A.3	Clock controller code examples . . . . .	725
A.3.1	HSE start sequence . . . . .	725
A.3.2	PLL configuration modification . . . . .	726
A.3.3	MCO selection . . . . .	726
A.3.4	Clock measurement configuration with TIM14 . . . . .	727
A.4	GPIO code examples . . . . .	728
A.4.1	Lock sequence . . . . .	728
A.4.2	Alternate function selection sequence . . . . .	728
A.4.3	Analog GPIO configuration . . . . .	729
A.5	DMA code examples . . . . .	729
A.5.1	DMA channel configuration sequence . . . . .	729
A.6	Interrupts and event code examples . . . . .	730
A.6.1	NVIC initialization . . . . .	730
A.6.2	External interrupt selection . . . . .	730
A.7	ADC code examples . . . . .	731
A.7.1	ADC calibration . . . . .	731
A.7.2	ADC enable sequence . . . . .	731
A.7.3	ADC disable sequence . . . . .	732
A.7.4	ADC clock selection . . . . .	732
A.7.5	Single conversion sequence - software trigger . . . . .	733
A.7.6	Continuous conversion sequence - software trigger . . . . .	733
A.7.7	Single conversion sequence - hardware trigger . . . . .	734
A.7.8	Continuous conversion sequence - hardware trigger . . . . .	734
A.7.9	DMA one shot mode sequence . . . . .	735
A.7.10	DMA circular mode sequence . . . . .	735
A.7.11	Wait mode sequence . . . . .	735
A.7.12	Auto Off and no wait mode sequence . . . . .	736
A.7.13	Auto Off and wait mode sequence . . . . .	736
A.7.14	Analog watchdog . . . . .	736
A.7.15	Temperature configuration . . . . .	737

A.7.16	Temperature computation . . . . .	737
A.8	Timers . . . . .	738
A.8.1	Upcounter on TI2 rising edge . . . . .	738
A.8.2	Up counter on each 2 ETR rising edges . . . . .	739
A.8.3	Input capture configuration . . . . .	739
A.8.4	Input capture data management . . . . .	740
A.8.5	PWM input configuration . . . . .	741
A.8.6	PWM input with DMA configuration . . . . .	741
A.8.7	Output compare configuration . . . . .	742
A.8.8	Edge-aligned PWM configuration example . . . . .	742
A.8.9	Center-aligned PWM configuration example . . . . .	743
A.8.10	ETR configuration to clear OCxREF . . . . .	744
A.8.11	Encoder interface . . . . .	744
A.8.12	Reset mode . . . . .	745
A.8.13	Gated mode . . . . .	745
A.8.14	Trigger mode . . . . .	746
A.8.15	External clock mode 2 + trigger mode . . . . .	746
A.8.16	One-Pulse mode . . . . .	747
A.8.17	Timer prescaling another timer . . . . .	747
A.8.18	Timer enabling another timer . . . . .	748
A.8.19	Master and slave synchronization . . . . .	749
A.8.20	Two timers synchronized by an external trigger . . . . .	750
A.8.21	DMA burst feature . . . . .	751
A.9	IRTIM code examples . . . . .	752
A.9.1	TIM16 and TIM17 configuration . . . . .	752
A.9.2	IRQHandler for IRTIM . . . . .	753
A.10	DBG code examples . . . . .	754
A.10.1	DBG read device ID . . . . .	754
A.10.2	DBG debug in Low-power mode . . . . .	754
A.11	I2C code examples . . . . .	754
A.11.1	I2C configured in master mode to receive . . . . .	754
A.11.2	I2C configured in master mode to transmit . . . . .	754
A.11.3	I2C configured in slave mode . . . . .	755
A.11.4	I2C master transmitter . . . . .	755
A.11.5	I2C master receiver . . . . .	755
A.11.6	I2C slave transmitter . . . . .	756
A.11.7	I2C slave receiver . . . . .	756

- A.11.8 I2C configured in master mode to transmit with DMA. . . . . 756
- A.11.9 I2C configured in slave mode to receive with DMA . . . . . 757
A.12 IWDG code examples . . . . . 757
- A.12.1 IWDG configuration . . . . . 757
- A.12.2 IWDG configuration with window . . . . . 758
A.13 RTC code examples . . . . . 758
- A.13.1 RTC calendar configuration . . . . . 758
- A.13.2 RTC alarm configuration. . . . . 759
- A.13.3 RTC WUT configuration . . . . . 759
- A.13.4 RTC read calendar . . . . . 759
- A.13.5 RTC calibration . . . . . 760
- A.13.6 RTC tamper and time stamp configuration. . . . . 760
- A.13.7 RTC tamper and time stamp. . . . . 761
- A.13.8 RTC clock output . . . . . 761
A.14 SPI code examples . . . . . 761
- A.14.1 SPI master configuration . . . . . 761
- A.14.2 SPI slave configuration. . . . . 762
- A.14.3 SPI full duplex communication . . . . . 762
- A.14.4 SPI interrupt . . . . . 762
- A.14.5 SPI master configuration with DMA . . . . . 762
- A.14.6 SPI slave configuration with DMA. . . . . 763
A.15 USART code examples . . . . . 763
- A.15.1 USART transmitter configuration . . . . . 763
- A.15.2 USART transmit byte . . . . . 763
- A.15.3 USART transfer complete. . . . . 763
- A.15.4 USART receiver configuration . . . . . 764
- A.15.5 USART receive byte . . . . . 764
- A.15.6 USART synchronous mode . . . . . 764
- A.15.7 USART DMA. . . . . 765
- A.15.8 USART hardware flow control. . . . . 765
A.16 WWDG code examples. . . . . 765
- A.16.1 WWDG configuration . . . . . 765

Important security notice . . . . . 766

Revision history . . . . . 767

List of tables

Table 1.	STM32F0x0 memory boundary addresses . . . . .	39
Table 2.	STM32F0x0 peripheral register boundary addresses. . . . .	40
Table 3.	Boot modes. . . . .	44
Table 4.	Flash memory organization (STM32F030x4, STM32F030x6, STM32F070x6 and STM32F030x8 devices). . . . .	47
Table 5.	Flash memory organization (STM32F070xB, STM32F030xC devices) . . . . .	48
Table 6.	Flash memory read protection status . . . . .	56
Table 7.	Access status versus protection level and execution modes . . . . .	57
Table 8.	Flash interrupt request . . . . .	58
Table 9.	Flash interface - Register map and reset values . . . . .	65
Table 10.	Option byte format . . . . .	66
Table 11.	Option byte organization. . . . .	66
Table 12.	Option byte map and ST production values . . . . .	69
Table 13.	CRC internal input/output signals . . . . .	71
Table 14.	CRC register map and reset values . . . . .	75
Table 15.	Low-power mode summary . . . . .	79
Table 16.	Sleep-now. . . . .	81
Table 17.	Sleep-on-exit. . . . .	81
Table 18.	Stop mode . . . . .	82
Table 19.	Standby mode. . . . .	83
Table 20.	PWR register map and reset values. . . . .	87
Table 21.	RCC register map and reset values . . . . .	123
Table 22.	Port bit configuration table . . . . .	126
Table 23.	GPIO register map and reset values . . . . .	140
Table 24.	SYSCFG register map and reset values. . . . .	148
Table 25.	DMA implementation . . . . .	150
Table 26.	DMA requests for each channel on STM32F030x4/x6/x8 and STM32F070x6/x8 devices . . . . .	151
Table 27.	DMA requests for each channel on STM32F030xC devices . . . . .	152
Table 28.	Programmable data width and endian behavior (when PINC = MINC = 1) . . . . .	159
Table 29.	DMA interrupt requests. . . . .	161
Table 30.	DMA register map and reset values . . . . .	169
Table 31.	Vector table. . . . .	171
Table 32.	External interrupt/event controller register map and reset values. . . . .	181
Table 33.	ADC input/output pins. . . . .	184
Table 34.	ADC internal input/output signals . . . . .	185
Table 35.	External triggers . . . . .	185
Table 36.	Latency between trigger and start of conversion . . . . .	189
Table 37.	Configuring the trigger polarity . . . . .	193
Table 38.	tSAR timings depending on resolution . . . . .	195
Table 39.	Analog watchdog comparison. . . . .	204
Table 40.	Analog watchdog channel selection . . . . .	204
Table 41.	ADC interrupts . . . . .	210
Table 42.	ADC register map and reset values . . . . .	223
Table 43.	Counting direction versus encoder signals. . . . .	264
Table 44.	TIMx Internal trigger connection . . . . .	277
Table 45.	Output control bits for complementary OCx and OCxN channels with break feature. . . . .	290

Table 46.	TIM1 register map and reset values . . . . .	299
Table 47.	Counting direction versus encoder signals . . . . .	331
Table 48.	TIM3 internal trigger connection . . . . .	348
Table 49.	Output control bit for standard OCx channels . . . . .	358
Table 50.	TIM3 register map and reset values . . . . .	365
Table 51.	TIM6/TIM7 register map and reset values . . . . .	379
Table 52.	Output control bit for standard OCx channels . . . . .	397
Table 53.	TIM14 register map and reset values . . . . .	399
Table 54.	TIMx Internal trigger connection . . . . .	433
Table 55.	Output control bits for complementary OCx and OCxN channels with break feature . . . . .	443
Table 56.	TIM15 register map and reset values . . . . .	449
Table 57.	Output control bits for complementary OCx and OCxN channels with break feature . . . . .	460
Table 58.	TIM16/TIM17 register map and reset values . . . . .	466
Table 59.	IWDG register map and reset values . . . . .	477
Table 60.	WWDG register map and reset values . . . . .	483
Table 61.	STM32F0x0 RTC implementation . . . . .	485
Table 62.	RTC pin PC13 configuration . . . . .	488
Table 63.	LSE pin PC14 configuration . . . . .	489
Table 64.	LSE pin PC15 configuration . . . . .	489
Table 65.	Effect of low-power modes on RTC . . . . .	501
Table 66.	Interrupt control bits . . . . .	501
Table 67.	RTC register map and reset values . . . . .	521
Table 68.	STM32F0x0 I2C implementation . . . . .	525
Table 69.	I2C input/output pins . . . . .	527
Table 70.	I2C internal input/output signals . . . . .	527
Table 71.	Comparison of analog vs. digital filters . . . . .	529
Table 72.	I2C-SMBus specification data setup and hold times . . . . .	532
Table 73.	I2C configuration . . . . .	536
Table 74.	I2C-SMBus specification clock timings . . . . .	547
Table 75.	Examples of timing settings for f _I2CCLK= 8 MHz . . . . .	557
Table 76.	Examples of timing settings for f _I2CCLK= 16 MHz . . . . .	557
Table 77.	Examples of timing settings for f _I2CCLK= 48 MHz . . . . .	558
Table 78.	SMBus timeout specifications . . . . .	560
Table 79.	SMBus with PEC configuration . . . . .	561
Table 80.	Examples of TIMEOUTA settings (max t _TIMEOUT= 25 ms) . . . . .	563
Table 81.	Examples of TIMEOUTB settings . . . . .	563
Table 82.	Examples of TIMEOUTA settings (max t _IDLE= 50 µs) . . . . .	563
Table 83.	Effect of low-power modes on the I2C . . . . .	573
Table 84.	I2C interrupt requests . . . . .	574
Table 85.	I2C register map and reset values . . . . .	588
Table 86.	STM32F0x0 USART features . . . . .	592
Table 87.	Noise detection from sampled data . . . . .	603
Table 88.	Error calculation for programmed baud rates at f _CK= 48 MHz in both cases of oversampling by 16 or by 8 . . . . .	605
Table 89.	Tolerance of the USART receiver when BRR [3:0] = 0000 . . . . .	606
Table 90.	Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . .	606
Table 91.	Frame formats . . . . .	610
Table 92.	Effect of low-power modes on the USART . . . . .	618
Table 93.	USART interrupt requests . . . . .	619
Table 94.	USART register map and reset values . . . . .	635
Table 95.	STM32F0x0 SPI implementation . . . . .	638
Table 96.	SPI interrupt requests . . . . .	662

Table 97. SPI register map and reset values . . . . . 671
Table 98. STM32F0x0 USB implementation . . . . . 672
Table 99. Double-buffering buffer flag definition . . . . . 682
Table 100. Bulk double-buffering memory buffers usage . . . . . 682
Table 101. Isochronous memory buffers usage . . . . . 684
Table 102. Resume event detection . . . . . 685
Table 103. Reception status encoding . . . . . 698
Table 104. Endpoint type encoding . . . . . 698
Table 105. Endpoint kind meaning . . . . . 698
Table 106. Transmission status encoding . . . . . 699
Table 107. Definition of allocated buffer memory . . . . . 702
Table 108. USB register map and reset values . . . . . 703
Table 109. SW debug port pins . . . . . 707
Table 110. DEV_ID and REV_ID field values . . . . . 708
Table 111. Packet request (8-bits) . . . . . 709
Table 112. ACK response (3 bits) . . . . . 709
Table 113. DATA transfer (33 bits) . . . . . 710
Table 114. SW-DP registers . . . . . 711
Table 115. 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . 712
Table 116. Core debug registers . . . . . 712
Table 117. DBG register map and reset values . . . . . 719
Table 118. Document revision history . . . . . 767

List of figures

Figure 1.	System architecture . . . . .	35
Figure 2.	Memory map . . . . .	38
Figure 3.	Programming procedure . . . . .	51
Figure 4.	Flash memory Page erase procedure . . . . .	53
Figure 5.	Flash memory mass erase procedure . . . . .	54
Figure 6.	CRC calculation unit block diagram . . . . .	71
Figure 7.	Power supply overview . . . . .	76
Figure 8.	Power on reset/power down reset waveform . . . . .	77
Figure 9.	Simplified diagram of the reset circuit . . . . .	89
Figure 10.	Clock tree (STM32F030x4, STM32F030x6 and STM32F030x8 devices) . . . . .	91
Figure 11.	Clock tree (STM32F070x6, STM32F070xB and STM32F030xC). . . . .	92
Figure 12.	HSE/ LSE clock sources . . . . .	93
Figure 13.	Frequency measurement with TIM14 in capture mode. . . . .	98
Figure 14.	Basic structure of an I/O port bit . . . . .	126
Figure 15.	Input floating / pull up / pull down configurations . . . . .	130
Figure 16.	Output configuration . . . . .	131
Figure 17.	Alternate function configuration . . . . .	132
Figure 18.	High impedance-analog configuration . . . . .	133
Figure 19.	DMA request mapping . . . . .	151
Figure 20.	DMA block diagram . . . . .	153
Figure 21.	Extended interrupts and events controller (EXTI) block diagram . . . . .	174
Figure 22.	External interrupt/event GPIO mapping . . . . .	176
Figure 23.	ADC block diagram . . . . .	184
Figure 24.	ADC calibration . . . . .	186
Figure 25.	Enabling/disabling the ADC . . . . .	187
Figure 26.	ADC clock scheme . . . . .	188
Figure 27.	Analog to digital conversion time . . . . .	192
Figure 28.	ADC conversion timings . . . . .	192
Figure 29.	Stopping an ongoing conversion . . . . .	193
Figure 30.	Single conversions of a sequence, software trigger . . . . .	196
Figure 31.	Continuous conversion of a sequence, software trigger. . . . .	196
Figure 32.	Single conversions of a sequence, hardware trigger . . . . .	197
Figure 33.	Continuous conversions of a sequence, hardware trigger . . . . .	197
Figure 34.	Data alignment and resolution . . . . .	198
Figure 35.	Example of overrun (OVR) . . . . .	199
Figure 36.	Wait mode conversion (continuous mode, software trigger). . . . .	201
Figure 37.	Behavior with WAIT = 0, AUTOFF = 1 . . . . .	202
Figure 38.	Behavior with WAIT = 1, AUTOFF = 1 . . . . .	203
Figure 39.	Analog watchdog guarded area . . . . .	204
Figure 40.	ADC_AWD1_OUT signal generation . . . . .	205
Figure 41.	ADC_AWD1_OUT signal generation (AWD flag not cleared by software) . . . . .	206
Figure 42.	ADC1_AWD_OUT signal generation (on a single channel) . . . . .	206
Figure 43.	Analog watchdog threshold update . . . . .	207
Figure 44.	Temperature sensor and VREFINT channel block diagram . . . . .	208
Figure 45.	Advanced-control timer block diagram . . . . .	226
Figure 46.	Counter timing diagram with prescaler division change from 1 to 2 . . . . .	228
Figure 47.	Counter timing diagram with prescaler division change from 1 to 4 . . . . .	228
Figure 48.	Counter timing diagram, internal clock divided by 1 . . . . .	230

Figure 49.	Counter timing diagram, internal clock divided by 2 . . . . .	230
Figure 50.	Counter timing diagram, internal clock divided by 4 . . . . .	231
Figure 51.	Counter timing diagram, internal clock divided by N . . . . .	231
Figure 52.	Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . .	232
Figure 53.	Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .	232
Figure 54.	Counter timing diagram, internal clock divided by 1 . . . . .	233
Figure 55.	Counter timing diagram, internal clock divided by 2 . . . . .	234
Figure 56.	Counter timing diagram, internal clock divided by 4 . . . . .	234
Figure 57.	Counter timing diagram, internal clock divided by N . . . . .	234
Figure 58.	Counter timing diagram, update event when repetition counter is not used. . . . .	235
Figure 59.	Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .	236
Figure 60.	Counter timing diagram, internal clock divided by 2 . . . . .	237
Figure 61.	Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	237
Figure 62.	Counter timing diagram, internal clock divided by N . . . . .	238
Figure 63.	Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .	238
Figure 64.	Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .	239
Figure 65.	Update rate examples depending on mode and TIMx_RCR register settings . . . . .	240
Figure 66.	Control circuit in normal mode, internal clock divided by 1 . . . . .	241
Figure 67.	TI2 external clock connection example. . . . .	242
Figure 68.	Control circuit in external clock mode 1 . . . . .	243
Figure 69.	External trigger input block . . . . .	243
Figure 70.	Control circuit in external clock mode 2 . . . . .	244
Figure 71.	Capture/compare channel (example: channel 1 input stage) . . . . .	245
Figure 72.	Capture/compare channel 1 main circuit . . . . .	245
Figure 73.	Output stage of capture/compare channel (channel 1 to 3) . . . . .	246
Figure 74.	Output stage of capture/compare channel (channel 4). . . . .	246
Figure 75.	PWM input mode timing . . . . .	248
Figure 76.	Output compare mode, toggle on OC1 . . . . .	250
Figure 77.	Edge-aligned PWM waveforms (ARR=8) . . . . .	252
Figure 78.	Center-aligned PWM waveforms (ARR=8). . . . .	253
Figure 79.	Complementary output with dead-time insertion. . . . .	255
Figure 80.	Dead-time waveforms with delay greater than the negative pulse. . . . .	255
Figure 81.	Dead-time waveforms with delay greater than the positive pulse. . . . .	255
Figure 82.	Output behavior in response to a break . . . . .	258
Figure 83.	Clearing TIMx_OCxREF . . . . .	260
Figure 84.	6-step generation, COM example (OSSR=1) . . . . .	261
Figure 85.	Example of one pulse mode . . . . .	262
Figure 86.	Example of counter operation in encoder interface mode. . . . .	265
Figure 87.	Example of encoder interface mode with TI1FP1 polarity inverted. . . . .	265
Figure 88.	Example of hall sensor interface . . . . .	267
Figure 89.	Control circuit in reset mode . . . . .	268
Figure 90.	Control circuit in gated mode . . . . .	269
Figure 91.	Control circuit in trigger mode . . . . .	270
Figure 92.	Control circuit in external clock mode 2 + trigger mode . . . . .	271
Figure 93.	General-purpose timer block diagram (TIM3) . . . . .	302
Figure 94.	Counter timing diagram with prescaler division change from 1 to 2 . . . . .	303
Figure 95.	Counter timing diagram with prescaler division change from 1 to 4 . . . . .	304
Figure 96.	Counter timing diagram, internal clock divided by 1 . . . . .	305
Figure 97.	Counter timing diagram, internal clock divided by 2 . . . . .	305
Figure 98.	Counter timing diagram, internal clock divided by 4 . . . . .	306

Figure 99.	Counter timing diagram, internal clock divided by N . . . . .	306
Figure 100.	Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .	307
Figure 101.	Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .	307
Figure 102.	Counter timing diagram, internal clock divided by 1 . . . . .	308
Figure 103.	Counter timing diagram, internal clock divided by 2 . . . . .	309
Figure 104.	Counter timing diagram, internal clock divided by 4 . . . . .	309
Figure 105.	Counter timing diagram, internal clock divided by N . . . . .	310
Figure 106.	Counter timing diagram, Update event when repetition counter is not used . . . . .	310
Figure 107.	Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .	312
Figure 108.	Counter timing diagram, internal clock divided by 2 . . . . .	312
Figure 109.	Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .	313
Figure 110.	Counter timing diagram, internal clock divided by N . . . . .	313
Figure 111.	Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . .	314
Figure 112.	Counter timing diagram, Update event with ARPE=1 (counter overflow). . . . .	314
Figure 113.	Control circuit in normal mode, internal clock divided by 1 . . . . .	315
Figure 114.	TI2 external clock connection example. . . . .	316
Figure 115.	Control circuit in external clock mode 1 . . . . .	317
Figure 116.	External trigger input block . . . . .	317
Figure 117.	Control circuit in external clock mode 2 . . . . .	318
Figure 118.	Capture/compare channel (example: channel 1 input stage). . . . .	319
Figure 119.	Capture/compare channel 1 main circuit . . . . .	319
Figure 120.	Output stage of capture/compare channel (channel 1). . . . .	320
Figure 121.	PWM input mode timing . . . . .	322
Figure 122.	Output compare mode, toggle on OC1 . . . . .	324
Figure 123.	Edge-aligned PWM waveforms (ARR=8). . . . .	325
Figure 124.	Center-aligned PWM waveforms (ARR=8). . . . .	327
Figure 125.	Example of one-pulse mode . . . . .	328
Figure 126.	Clearing TIMx_OCxREF . . . . .	330
Figure 127.	Example of counter operation in encoder interface mode . . . . .	332
Figure 128.	Example of encoder interface mode with TI1FP1 polarity inverted . . . . .	332
Figure 129.	Control circuit in reset mode . . . . .	333
Figure 130.	Control circuit in gated mode . . . . .	334
Figure 131.	Control circuit in trigger mode . . . . .	335
Figure 132.	Control circuit in external clock mode 2 + trigger mode . . . . .	336
Figure 133.	Master/Slave timer example . . . . .	337
Figure 134.	Gating timer 3 with OC1REF of timer 1 . . . . .	338
Figure 135.	Gating timer 3 with Enable of timer 1 . . . . .	339
Figure 136.	Triggering timer 3 with update of timer 1 . . . . .	340
Figure 137.	Triggering timer 3 with Enable of timer 1 . . . . .	341
Figure 138.	Triggering timer 1 and 3 with timer 1 TI1 input . . . . .	342
Figure 139.	Basic timer block diagram. . . . .	367
Figure 140.	Counter timing diagram with prescaler division change from 1 to 2 . . . . .	369
Figure 141.	Counter timing diagram with prescaler division change from 1 to 4 . . . . .	369
Figure 142.	Counter timing diagram, internal clock divided by 1 . . . . .	370
Figure 143.	Counter timing diagram, internal clock divided by 2 . . . . .	371
Figure 144.	Counter timing diagram, internal clock divided by 4 . . . . .	371
Figure 145.	Counter timing diagram, internal clock divided by N . . . . .	372
Figure 146.	Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .	372
Figure 147.	Counter timing diagram, update event when ARPE=1

(TIMx_ARR preloaded) . . . . .	373
Figure 148. Control circuit in normal mode, internal clock divided by 1 . . . . .	374
Figure 149. General-purpose timer block diagram (TIM14) . . . . .	381
Figure 150. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	382
Figure 151. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	382
Figure 152. Counter timing diagram, internal clock divided by 1 . . . . .	383
Figure 153. Counter timing diagram, internal clock divided by 2 . . . . .	383
Figure 154. Counter timing diagram, internal clock divided by 4 . . . . .	384
Figure 155. Counter timing diagram, internal clock divided by N . . . . .	384
Figure 156. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	384
Figure 157. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	385
Figure 158. Control circuit in normal mode, internal clock divided by 1 . . . . .	385
Figure 159. Capture/compare channel (example: channel 1 input stage) . . . . .	386
Figure 160. Capture/compare channel 1 main circuit . . . . .	386
Figure 161. Output stage of capture/compare channel (channel 1) . . . . .	387
Figure 162. Output compare mode, toggle on OC1 . . . . .	390
Figure 163. Edge-aligned PWM waveforms (ARR=8) . . . . .	391
Figure 164. TIM15 block diagram . . . . .	402
Figure 165. TIM16 and TIM17 block diagram . . . . .	404
Figure 166. Counter timing diagram with prescaler division change from 1 to 2 . . . . .	405
Figure 167. Counter timing diagram with prescaler division change from 1 to 4 . . . . .	406
Figure 168. Counter timing diagram, internal clock divided by 1 . . . . .	407
Figure 169. Counter timing diagram, internal clock divided by 2 . . . . .	408
Figure 170. Counter timing diagram, internal clock divided by 4 . . . . .	408
Figure 171. Counter timing diagram, internal clock divided by N . . . . .	409
Figure 172. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .	409
Figure 173. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .	410
Figure 174. Update rate examples depending on mode and TIMx_RCR register settings . . . . .	411
Figure 175. Control circuit in normal mode, internal clock divided by 1 . . . . .	412
Figure 176. TI2 external clock connection example . . . . .	412
Figure 177. Control circuit in external clock mode 1 . . . . .	413
Figure 178. Capture/compare channel (example: channel 1 input stage) . . . . .	414
Figure 179. Capture/compare channel 1 main circuit . . . . .	414
Figure 180. Output stage of capture/compare channel (channel 1) . . . . .	415
Figure 181. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .	415
Figure 182. PWM input mode timing . . . . .	417
Figure 183. Output compare mode, toggle on OC1 . . . . .	419
Figure 184. Edge-aligned PWM waveforms (ARR=8) . . . . .	420
Figure 185. Complementary output with dead-time insertion . . . . .	421
Figure 186. Dead-time waveforms with delay greater than the negative pulse . . . . .	421
Figure 187. Dead-time waveforms with delay greater than the positive pulse . . . . .	421
Figure 188. Output behavior in response to a break . . . . .	424
Figure 189. Example of One-pulse mode . . . . .	425
Figure 190. Control circuit in reset mode . . . . .	427
Figure 191. Control circuit in gated mode . . . . .	428
Figure 192. Control circuit in trigger mode . . . . .	429
Figure 193. IRTIM internal hardware connections . . . . .	468
Figure 194. Independent watchdog block diagram . . . . .	469

Figure 195. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 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Figure 242. RX data setup/hold time . . . . .	613
Figure 243. Transmission using DMA . . . . .	615
Figure 244. Reception using DMA . . . . .	616
Figure 245. Hardware flow control between 2 USARTs . . . . .	616
Figure 246. RS232 RTS flow control . . . . .	617
Figure 247. RS232 CTS flow control . . . . .	618
Figure 248. USART interrupt mapping diagram . . . . .	619
Figure 249. SPI block diagram. . . . .	639
Figure 250. Full-duplex single master/ single slave application. . . . .	640
Figure 251. Half-duplex single master/ single slave application . . . . .	640
Figure 252. Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . .	641
Figure 253. Master and three independent slaves. . . . .	642
Figure 254. Multimaster application. . . . .	643
Figure 255. Hardware/software slave select management . . . . .	644
Figure 256. Data clock timing diagram . . . . .	645
Figure 257. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .	646
Figure 258. Packing data in FIFO for transmission and reception. . . . .	650
Figure 259. Master full-duplex communication . . . . .	653
Figure 260. Slave full-duplex communication . . . . .	654
Figure 261. Master full-duplex communication with CRC . . . . .	655
Figure 262. Master full-duplex communication in packed mode . . . . .	656
Figure 263. NSSP pulse generation in Motorola SPI master mode. . . . .	659
Figure 264. TI mode transfer . . . . .	660
Figure 265. USB peripheral block diagram . . . . .	673
Figure 266. Packet buffer areas with examples of buffer description table locations . . . . .	677
Figure 267. Block diagram of STM32F0x0 MCU and Arm ^®Cortex ^®-M0-level debug support . . . . .	705

RM0360-STM32F030x4-x6-x8-xC-070x6-xB

Introduction

Contents

List of tables

List of figures

Chapters

RM0360-STM32F030x4-x6-x8-xC-070x6-xB

Introduction

Related documents

Contents

List of tables

List of figures

Chapters