51. Revision history

PWR

Updated Section 5.1: Power supplies .

Updated Section : Entering the Low-power run mode .

Updated Table 25: Sleep .

Updated Table 26: Low-power sleep .

Updated Table 27: Stop 0 mode .

Updated Table 29: Stop 2 mode .

Updated Table 27: Stop 0 mode .

Renamed bit EIWF into EIWUL in Section 5.4.3: Power control register 3 (PWR_CR3) .

GPIO

Updated OSPEEDy[1:0] definition in Section 8.4.3: GPIO port output speed register (GPIOx_OSPEEDR) (x = A to E, H) .

FMC

Updated Section : SRAM/NOR-flash chip-select timing register for bank x (FMC_BTRx) .

Updated Section : SRAM/NOR-flash write timing registers x (FMC_BWTRx) .

ADC

Updated Figure 70: ADC3 connectivity .

Updated Section 18.4.17: Stopping an ongoing conversion (ADSTP, JADSTP) .

Added formula in Bullet .

VREFBUF

Updated Table 142: VREF buffer modes .

DFSDM

Updated clock range in SPI data input format operation and Manchester coded data input format operation .

LCD

Updated Section 25.2: LCD main features .

TSC

Updated Table 171: Spread spectrum deviation versus AHB clock frequency .

Updated Table 173: Effect of low-power modes on TSC .

TIM2/TIM3/TIM4/TIM5

Updated Bullet in Table 31.3.13: One-pulse mode .

2C

Updated Section 39.4.5: I2C initialization , including Figure 392: Setup and hold timings .

Updated Section 39.9.5: I2C timing register (I2C_TIMINGR) .

ISPI

Updated Figure 458: Full-duplex single master/ single slave application , Figure 459: Half-duplex single master/ single slave application , Figure 460: Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) and Figure 461: Master and three independent slaves .

Notes updated and added below Figure 458: Full-duplex single master/ single slave application , Figure 459: Half-duplex single master/ single slave application , Figure 460: Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) .

Added Section 42.4.4: Multimaster communication .

UART

Updated The RTO counter starts counting: on page 1353 .

Added Determining the maximum USART baud rate allowing to wake up correctly from Stop mode when the USART clock source is the HSI clock .

Removed TXFRQ bit in Table 263: LPUART register map and reset values .

DEBUG

Updated DBGMCU_IDCODE .

In all the document:

• – Stop 1 with main regulator becomes Stop 0
• – Stop 1 with low-power regulator remains as Stop 1

MEM

Updated SAI1 and SAI2 base address in Table 2: STM32L49x/L4Ax devices memory map and peripheral register boundary addresses .

MMAP

Added Table 5: Memory mapping versus boot mode/physical remap .

FLASH

Added If the flash is attempted to be written in Fast programming mode while a read operation is on going in the same bank, the programming is aborted without any system notification (no error flag is set)..

PWR

Updated Table 23: Functionalities depending on the working mode .

RCC

Updated WWDGEN bit description and access mode in Section 6.4.19: APB1 peripheral clock enable register 1 (RCC_APB1ENR1) .

Removed bit CC2NE from Section 32.6.9: TIM15 capture/compare enable register (TIM15_CCER) .

Removed bit TIE from Section 32.7.3: TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) .

Removed bit TIF from Section 32.7.4: TIMx status register (TIMx_SR)(x = 16 to 17) .

Removed bit TG from Section 32.7.5: TIMx event generation register (TIMx_EGR)(x = 16 to 17) .

Updated reset value to 0xFFFF in Section 32.7.11: TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) .

TIM6/TIM7

Updated reset value to 0xFFFF in Section 33.4.8: TIMx auto-reload register (TIMx_ARR)(x = 6 to 7)

LPTIM

Added Section 34.5: LPTIM low-power modes .

RTC

Updated reference to TAMPTS bit in Section 38.3.13: Time-stamp function .

Updated Table 225: Effect of low-power modes on RTC .

I2C

Updated Table 244: Effect of low-power modes to I2C .

Updated Table 228: STM32L47x/L48x I2C implementation .

USART

Replaced nCTS by CTS - nRTS by RTS - SCLK by CK.

Replaced "w" by "rc_w1" in Section 40.8.9: USART interrupt flag clear register (USART_ICR) .

Updated Table 253: Effect of low-power modes on the USART .

Updated RTOF bit description in Section 40.8.8: USART interrupt and status register (USART_ISR) .

LPUART

Replaced nCTS by CTS - nRTS by RTS.

Updated Table 261: Effect of low-power modes on the LPUART .

SWPMI

Updated Table 276: Effect of low-power modes on SWPMI .

SDMMC

Updated limit from 48 to 50 MHz in Section 45.1: SDMMC main features , Section 45.3: SDMMC functional description , Section 45.8.1: SDMMC power control register (SDMMC_POWER) , Section 45.8.2: SDMMC clock control register (SDMMC_CLKCR) and in Section 45.8.4: SDMMC command register (SDMMC_CMD) .

Updated Section 16.6.5: NAND Flash prewait functionality .

Updated MEMHOLD bit description in Section : Common memory space timing register 2..4 (FMC_PMEM) .

ADC:
Replaced ADVREGRN by ADVREGEN in Section : Software procedure to enable the ADC and Section 18.4.9: ADC on-off control (ADEN, ADDIS, ADRDY) .

DAC:
Updated Section 19.2: DAC main features .
Updated Section 19.3.11: DAC channel buffer calibration .
Updated CAL_FLAG1 and CAL_FLAG2 bits description in Section 19.6.14: DAC x status register (DACx_SR) (x=1 to 2) .

DFSDM:
Replaced DFSDM by DFSDM1 when referring to DFSDM within other sections of the document.
Renamed DFSDM signal names in all the document.
Updated Section 24.2: DFSDM main features .
Updated Section 24.4.2: DFSDM pins and internal signals .
Updated entire Section 24: Digital filter for sigma delta modulators (DFSDM) to better differentiate the filter indexes (FLT _x ) from the channel indexes (CH _y ).

LCD:
Updated Section 25.3.5: Voltage generator and contrast control .
Updated Table 163: Remapping capability .
Updated LCDEN bit description in Section 25.6.2: LCD frame control register (LCD_FCR) .

TIM1/TIM8:
Added note 1 in Figure 225: Advanced-control timer block diagram
Updated Section 30.3.4: External trigger input .
Added note Note: on page 940 .
Updated Section 30.3.24: Timer input XOR function .
Updated Section 30.3.29: Debug mode .
Updated OC1CE bit description in Section 30.4.7: TIM1/TIM8 capture/compare mode register 1 (TIMx_CCMR1) .
Updated ETRSEL bit description in Section 30.4.26: TIM1 option register 2 (TIM1_OR2) , Section 30.4.27: TIM1 option register 3 (TIM1_OR3) and Section 30.4.28: TIM8 option register 2 (TIM8_OR2) .

TIM2/TIM3/TIM4/TIM5:
Updated Table 195: TIMx internal trigger connection .

Updated PCSC bit description in Section 31.4.11: TIMx prescaler (TIMx_PSC) .

Updated ETRSEL bit description in Section 31.4.21: TIM2 option register 2 (TIM2_OR2) , Section 31.4.22: TIM3 option register 2 (TIM3_OR2) .

TIM15/TIM16/TIM17

Added Section 32.5.21: Timer synchronization (TIM15) .

TIM6/TIM7:

Updated PCSC bit description in Section 33.4.7: TIM6/TIM7 prescaler (TIMx_PSC) .

WWDG:

Updated Section 36.3: IWDG functional description .

Updated T bit description in Section 37.4.1: Control register (WWDG_CR) .

RTC:

Updated Section 38.3.1: RTC block diagram .

Added Table 221: RTC functions over modes .

Updated Section 38.3.9: Resetting the RTC .

Updated Section 38.3.15: Calibration clock output .

Added Caution at the end of Section 38.6.3: RTC control register (RTC_CR) .

I2C:

Updated Section 39.4.1: I2C block diagram .

Updated Section : I2C timings .

Updated Section 39.4.8: I2C master mode .

Added note in Section 39.7.5: Timing register (I2C_TIMINGR)

USART:

Updated Section 40.5.5: Tolerance of the USART receiver to clock deviation .

Updated Section 40.5.10: USART LIN (local interconnection network) mode .

Updated Section : Using Mute mode with Stop mode .

Updated Section 40.5.17: Wakeup from Stop mode using USART .

Added bit UCESM in Section 40.8.3: Control register 3 (USART_CR3) .

LPUART:

Added Table 245: Tolerance of the USART receiver when BRR [3:0] = 0000 .

Added Section 41.4.5: Tolerance of the LPUART receiver to clock deviation .

Updated Section : Determining the maximum USART baud rate allowing to wakeup correctly from Stop mode when the USART clock source is the HSI clock .

Updated Section 41.4.11: Wakeup from Stop mode using LPUART .

Added bit UCESM in Section 41.7.3: Control register 3 (LPUART_CR3) .

SAI:
Replaced FLTH by FLVL in entire Section 43: Serial audio interface (SAI) .

SWPMI:
Updated Section 44.3.2: SWP initialization and activation .

USB:
Updated Section 47.1: Introduction .
Added Table 311: OTG_FS speeds supported .
Updated Section 47.8.1: Host SOFs .
Updated Section 47.8.2: Peripheral SOFs .
Updated Section 47.9: Power options .
Updated Section 47.11.3: FIFO RAM allocation .
Updated Table 313: Core global control and status registers (CSRs) .
Updated Table 317: Power and clock gating control and status registers .
Updated Section 47.15.1: OTG control and status register (OTG_GOTGCTL) .
Updated Section 47.15.5: OTG reset register (OTG_GRSTCTL) .
Updated Section 47.15.32: OTG device configuration register (OTG_DCFG) .
Updated Section 47.16.3: Device initialization .
Updated Section 47.16.5: Device programming model .

Update of the document to include support for STM32L4x5xx, STM32L496xx and STM32L4A6xx.

SYSTEM AND MEMORY OVERVIEW:
Updated Section 2.1: System architecture , Section 2.1.3: S2: S-bus , Section 2.1.4: S3, S4: DMA-bus , Section 2.1.6: BusMatrix , Section 2.4: Embedded SRAM , Table 3: SRAM2 organization , Section 2.6.1: Boot configuration for STM32L47x/L48x devices
Added Figure 2: System architecture for STM32L49x/L4Ax , Section 2.1.5: S5: DMA2D-bus , Figure 4: Memory map for STM32L49x/L4Ax devices , Table 2: STM32L49x/L4Ax devices memory map and peripheral register boundary addresses , Section 2.6.2: Boot configuration for STM32L49x/L4Ax devices

FLASH:
Updated Table 11: Number of wait states according to CPU clock (HCLK) frequency , Section : Fast programming , Section 3.4.1: Option bytes description , Section 3.7.8: Flash option register (FLASH_OPTR)

FIREWALL:
Updated Table 19: Segment granularity and area ranges , Section 4.4.5: Volatile data segment start address (FW_VDSSA)

PWR:
Updated Section 5: Power control (PWR) , Figure 9: Power supply overview , Section 5.1.8: Dynamic voltage scaling management , Table 23: Functionalities depending on the working mode
Added Section 5.1.7: VDD12 domain , Section 5.4.24: Power Port I pull-up control register (PWR_PUCRI) , Section 5.4.25: Power Port I pull-down control register (PWR_PDCRI)

RCC:
Updated Section 6.2: Clocks , Table 33: Clock source frequency , Section 6.4.2: Internal clock sources calibration register (RCC_ICSCR) , Section 6.4.3: Clock configuration register (RCC_CFGR) , Section 6.4.6: PLLSAI2 configuration register (RCC_PLLSAI2CFGR) , Section 6.4.7: Clock interrupt enable register (RCC_CIER) , Section 6.4.8: Clock interrupt flag register (RCC_CIFR) , Section 6.4.9: Clock interrupt clear register (RCC_CICR) , Section 6.4.10: AHB1 peripheral reset register (RCC_AHB1RSTR) , Section 6.4.11: AHB2 peripheral reset register (RCC_AHB2RSTR) , Section 6.4.13: APB1 peripheral reset register 1 (RCC_APB1RSTR1) , Section 6.4.14: APB1 peripheral reset register 2 (RCC_APB1RSTR2) , Section 6.4.16: AHB1 peripheral clock enable register (RCC_AHB1ENR) , Section 6.4.17: AHB2 peripheral clock enable register (RCC_AHB2ENR) , Section 6.4.19: APB1 peripheral clock enable register 1 (RCC_APB1ENR1) , Section 6.4.20: APB1 peripheral clock enable register 2 (RCC_APB1ENR2) , Section 6.4.23: AHB2 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB2SMENR) , Section 6.4.25: APB1 peripheral clocks enable in Sleep and Stop modes register 1 (RCC_APB1SMENR1) , Section 6.4.26: APB1 peripheral clocks enable in Sleep and Stop modes register 2 (RCC_APB1SMENR2) , Section 6.4.28: Peripherals independent clock configuration register (RCC_CCIPR) , Table 34: RCC register map and reset values
Added Figure 16: Clock tree (for STM32L49x/L4Ax devices) , Section 6.2.4: HSI48 clock (only valid for STM32L49x/L4Ax devices) , Section 6.2.11: Clock security system on LSE , Section 6.4.31: Clock recovery RC register (RCC_CRRRCR) , Section 6.4.32: Peripherals independent clock configuration register (RCC_CCIPR2)

CRS: added Section 7: Clock recovery system (CRS)

GPIO:
Updated Section 8.3.1: General-purpose I/O (GPIO)
Added Section 8.3.15: Using PH3 as GPIO

SYSCFG

Updated Section 9.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP) , Section 9.2.2: SYSCFG configuration register 1 (SYSCFG_CFGR1) , Section 9.2.3: SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) , Section 9.2.4: SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) , Section 9.2.5: SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) , Section 9.2.6: SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4)

Added Section 9.2.11: SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2)

PERIPHERAL INTERCONNECT MATRIX:

Update Table 42: STM32L47x/L48x/L49x/L4Ax peripherals interconnect matrix

Added Section 10.3.16: From ADC (ADC1/ADC2/ADC3) to DFSDM (only for STM32L49x/L4Ax devices)

DMA:

Updated Figure 31: DMA block diagram , Figure 29: DMA1 request mapping , Figure 30: DMA2 request mapping , Section 11.3.2: DMA request mapping

DMA2D: Updated Section 12: Chrom-ART Accelerator controller (DMA2D)

NVIC:

Updated Section 13.1: NVIC main features , Section 13.2: SysTick calibration value register , Table 58: STM32L47x/L48x/L49x/L4Ax vector table

EXTI:

Updated Table 14.1: Introduction , Table 14.2: EXTI main features , Table 14.4: EXTI interrupt/event line mapping , Figure 34: External interrupt/event GPIO mapping , Table 59: EXTI lines connections , Section 14.5.7: Interrupt mask register 2 (EXTI_IMR2) , Section 14.5.8: Event mask register 2 (EXTI_EMR2) , Table 60: Extended interrupt/event controller register map and reset values

CRC:

Updated Section 15.2: CRC main features

FMC:

updated Section 16.2: FMC main features , Section 16.3: FMC block diagram , Table 73: FMC_BCRx bitfields (mode 1) , Table 75: FMC_BCRx bitfields (mode A) , Figure 42: Mode 2 and mode B read access waveforms , Figure 43: Mode 2 write access waveforms , Table 78: FMC_BCRx bitfields (mode 2/B) , Table 81: FMC_BCRx bitfields (mode C) , Table 84: FMC_BCRx bitfields (mode D) , Table 87: FMC_BCRx bitfields (Muxed mode) , Table 89: FMC_BCRx bitfields (Synchronous multiplexed read mode) ,

Table 91: FMC_BCRx bitfields (Synchronous multiplexed write mode), Section 16.6.6: NOR/PSRAM controller registers

QUADSPI:
Updated Section 17.1: Introduction, Section 17.2: QUADSPI main features, Section 17.4.4: QUADSPI signal interface protocol modes, Section 17.4.7: QUADSPI memory-mapped mode, Section 17.6.1: QUADSPI control register (QUADSPI_CR), Table 102: QUADSPI register map and reset values
Added Section 17.3: QUADSPI implementation, Figure 59: QUADSPI block diagram when dual-flash mode is enabled, Section 17.4.2: QUADSPI pins, Section 17.4.5: QUADSPI indirect mode

ADC:
Updated Section 18.2: ADC main features, Figure 66: ADC block diagram, Table 105: ADC input/output pins, Section 18.4.3: ADC clocks, Section 18.4.12: Channel-wise programmable sampling time (SMPR1, SMPR2), Table 108: ADC1, ADC2 and ADC3 - External triggers for regular channels, Table 109: ADC1, ADC2 and ADC3 - External trigger for injected channels, Figure 80: Example of JSQR queue of context (sequence change), Figure 81: Example of JSQR queue of context (trigger change), Figure 84: Example of JSQR queue of context with empty queue (case JQM = 0), Figure 86: Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 0) Case when JADSTP occurs during an ongoing conversion, Section 18.4.26: Data management, Section 18.7.4: ADC configuration register (ADC_CFGR), Section 18.7.6: ADC sample time register 1 (ADC_SMPR1), Section 18.8.2: ADC common control register (ADC_CCR)
Added Section 18.3: ADC implementation, Section 18.4.27: Managing conversions using the DFSDM, Section : DFSDM mode in dual ADC interleaved mode, Section : DFSDM mode in dual ADC simultaneous mode

DAC:
Updated Section 19.1: Introduction, Section 19.4.1: DAC block diagram, Section 19.7.11: Dual DAC 8-bit right aligned data holding register (DAC_DHR8RD)
Added Table 125: DAC trigger selection

DCMI: Added Section 20: Digital camera interface (DCMI)

DFSDM:
Updated Section 24.1: Introduction, Table 157: DFSDM internal signals, Table 158: DFSDM triggers connection, Section 24.4.6: Parallel data inputs, Section 24.4.13: Data unit block

Added Section 24.3: DFSDM implementation , Table 159: DFSDM break connection , Figure 164: Input channel pins redirection

RNG:
Updated Section 27.3.5: RNG operation , Section 27.3.7: Error management , Section 27.7.1: RNG control register (RNG_CR) , Section 27.7.2: RNG status register (RNG_SR)
Added Section 27.3.1: RNG block diagram , Section 27.3.2: RNG internal signals , Section 27.3.3: Random number generation , Section 27.3.4: RNG initialization , Section 27.3.6: RNG clocking , Section 27.3.8: RNG low-power use , Section 27.4: RNG interrupts , Section 27.5: RNG processing time , Section 27.6: RNG entropy source validation

AES:
Updated Figure 201: 128-bit block construction according to the data type (continued) , Figure 205: Mode 4: key derivation and decryption with 128-bit key length , Figure 206: DMA requests and data transfers during Input phase (AES_IN) , Figure 218: DMA transfer of a 128-bit data block during output phase

HASH: added Section 29: Hash processor (HASH)

TIM15/TIM16/TIM17:
Updated Section 32.5.24: Debug mode , Table 207: Output control bits for complementary OCx and OCxN channels with break feature (TIM15) , Section 32.7.3: TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) , Table 209: Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) , Table 210: TIM16/TIM17 register map and reset values

RTC:
Updated Figure 389: RTC block diagram

I2C:
Updated Table 229: STM32L49x/L44x I2C implementation , Section : Master communication initialization (address phase) , Table 244: Effect of low-power modes to I2C , Section 39.9.2: I2C control register 2 (I2C_CR2) , Section 39.9.3: I2C own address 1 register (I2C_OAR1) , Section 39.9.4: I2C own address 2 register (I2C_OAR2)
Added Table 228: STM32L47x/L48x I2C implementation

USART:
Updated Section 40.4: USART implementation , Section 40.5.13: USART smartcard mode , Table 254: USART interrupt requests , Section 40.8.3: USART control register 3 (USART_CR3) , Section 40.8.8: USART interrupt and status register (USART_ISR) , Table 255: USART register map and reset values

LPUART:
Updated Section 41.4.11: Wake-up from Stop mode using LPUART

SPI:
Updated Section 42.4.7: Configuration of SPI , Section 42.4.14: CRC calculation , Section 42.6.6: SPI Rx CRC register (SPIx_RXCRCR) , Section 42.6.7: SPI Tx CRC register (SPIx_TXCRCR)

SAI:
Updated Figure 473: SAI functional block diagram , Section 43.3.8: SAI clock generator , Table 270: Example of possible audio frequency sampling range
Added Section 43.3.2: SAI pins and internal signals

BxCAN:
Updated Section 46.9.4: CAN filter registers , Table 316: bxCAN register map and reset values
Added Section : Dual CAN peripheral configuration , Figure 516: Dual-CAN block diagram

OTG_FS:
Updated Section 47.5.1: ID line detection , Figure 534: OTG_FS peripheral-only connection , Section 47.15.5: OTG reset register (OTG_GRSTCTL) , Section 47.15.16: OTG core ID register (OTG_CID) , Section 47.15.35: OTG device configuration register (OTG_DCFG) , Section 47.15.56: OTG power and clock gating control register (OTG_PCGCCTL) , Table 329: OTG_FS register map and reset values

DEBUG SUPPORT:
Updated Section 48.4.2: Flexible SWJ-DP pin assignment , Section 48.6.1: MCU device ID code , Section 48.16.4: Debug MCU APB1 freeze register1(DBGMCU_APB1FZR1) , Section 48.16.5: Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2) , Table 343: Synchronous TRACE pin assignment , Table 344: Flexible TRACE pin assignment , Table 346: DBG register map and reset values

DEVICE ELECTRONIC SIGNATURE:
Updated Section 49.3: Package data register .
Added note on cover page

System and memory overview:
Figure 3: Memory map for STM32L47x/L48x devices , Figure 4: Memory map for STM32L49x/L4Ax devices , Table 2: STM32L49x/L4Ax devices memory map and peripheral register boundary addresses
Updated: note on Section 2.6.1: Boot configuration for STM32L47x/L48x devices , Section : User and read protection option bytes , Section : Bank 1 PCROP End address option bytes , Section : Bank 2 WRP Area A address option bytes ,

Section : Bank 1 WRP Area B address option bytes, Section : Bank 2 PCROP Start address option bytes, Section : Bank 2 PCROP End address option bytes, Section : Bank 2 WRP Area A address option bytes, Section : Bank 2 WRP Area B address option bytes, Section 3.7.8: Flash option register (FLASH_OPTR), Section 3.7.9: Flash Bank 1 PCROP Start address register (FLASH_PCROP1SR), Section 3.7.10: Flash Bank 1 PCROP End address register (FLASH_PCROP1ER), Section 3.7.11: Flash Bank 1 WRP area A address register (FLASH_WRP1AR), Section 3.7.12: Flash Bank 1 WRP area B address register (FLASH_WRP1BR), Section 3.7.13: Flash Bank 2 PCROP Start address register (FLASH_PCROP2SR), Section 3.7.14: Flash Bank 2 PCROP End address register (FLASH_PCROP2ER), Section 3.7.15: Flash Bank 2 WRP area A address register (FLASH_WRP2AR), Section 3.7.16: Flash Bank 2 WRP area B address register (FLASH_WRP2BR)

Added: notes in Table 6: Boot modes

FIREWALL:
Updated Section 4.3.2: Functional requirements, Table 18: Segment accesses according to the Firewall state

PWR:
Updated Section 5.1.7: VDD12 domain, Section 5.1.8: Dynamic voltage scaling management, Figure 10: Internal main regulator overview, Section 5.2.2: Programmable voltage detector (PVD)

RCC:
Updated Figure 15: Clock tree (for STM32L47x/L48x devices), Figure 16: Clock tree (for STM32L49x/L4Ax devices), Table 33: Clock source frequency, Section 6.2.17: Clock-out capability, Section 6.4.1: Clock control register (RCC_CR), Section 6.4.2: Internal clock sources calibration register (RCC_ICSCR), Section 6.4.5: PLLSAI1 configuration register (RCC_PLLSAI1CFGR), Section 6.4.6: PLLSAI2 configuration register (RCC_PLLSAI2CFGR)

GPIO:
Updated Section 8.3.2: I/O pin alternate function multiplexer and mapping

SYSCFG:
Updated Section 9.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP)

DMA and DMA2D:
Updated Table 44: DMA1 requests for each channel, Table 45: DMA2 requests for each channel, Table 57: DMA2D register map and reset values.

Removed Section 12.5.21: IP version register (DMA2D_VERR) , Section 12.5.22: DMA2D IP identification register (DMA2D_IPIDR) , Section 12.2.23: DMA2D IP size identification register (DMA2D_SIDR)

NVIC:

Updated Section 13.2: SysTick calibration value register , Table 58: STM32L47x/L48x/L49x/L4Ax vector table , Figure 34: External interrupt/event GPIO mapping

CRC: Updated section Section 15.4.2: CRC independent data register (CRC_IDR) , Section 15.4.3: CRC control register (CRC_CR) , Section 15.4.4: CRC initial value (CRC_INIT)

QUADSPI:

Updated Section 17.6.1: QUADSPI control register (QUADSPI_CR) , Section 17.6.2: QUADSPI device configuration register (QUADSPI_DCR) , Section 17.6.4: QUADSPI flag clear register (QUADSPI_FCR)

ADC:

Updated Section 18.1: Introduction , Section 18.2: ADC main features , Figure 66: ADC block diagram , Table 104: ADC internal input/output signals , Table 105: ADC input/output pins , Figure 68: ADC1 connectivity , Figure 69: ADC2 connectivity , Figure 70: ADC3 connectivity , Section 18.4.7: Single-ended and differential input channels , Section 18.4.11: Channel selection (SQRx, JSQRx) , Section 18.4.18: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) , Figure 118: Dual ADC block diagram ⁽¹⁾ , Section : Interleaved mode with independent injected , Figure 121: Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode , Figure 122: Interleaved mode on 1 channel in single conversion mode: dual ADC mode , Section 18.4.32: Temperature sensor , Figure 136: VREFINT channel block diagram , Section 18.7.1: ADC interrupt and status register (ADC_ISR) , Section 18.7.4: ADC configuration register (ADC_CFGR) , Section 18.7.18: ADC injected channel y data register (ADC_JDRy) , Section 18.7.21: ADC differential mode selection register (ADC_DIFSEL) , Table 119: DELAY bits versus ADC resolution

Added Figure 44: Bulb mode timing diagram

DAC:

Updated Section 19.2: DAC main features , Section 19.4.7: DMA requests , Section 19.4.10: DAC channel modes , Section 19.4.12: Dual DAC channel conversion modes (if dual channels are available) , Section 19.7.18: DAC channel2 sample and hold sample time register (DAC_SHSR2) , Section 19.7.20: DAC sample and hold refresh time register (DAC_SHRR) .

Added Section 19.6: DAC interrupts

VREFBUF

Updated Section 21.2: VREFBUF functional description , Table 142: VREF buffer modes , Section 21.4.1: VREFBUF control and status register (VREFBUF_CSR)

COMP:

Updated Section 22.3.8: COMP power and speed modes

TSC:

Updated Table 170: Acquisition sequence summary

RNG:

Updated Section 27.3.7: Error management , Section 27.6.2: Validation conditions , Section 27.7.1: RNG control register (RNG_CR) , Table 178: RNG register map and reset map

AES:

Updated Section 28.1: Introduction , Section 28.2: AES main features , Section 28.4: AES functional description , all subsections of Section 28.7: AES registers , Table 179: AES registers

Added Section 28.3: AES implementation , all subsections of Section 28.4: AES functional description

Removed Section 28.4: Encryption and derivation keys , Section 28.9: Operating modes

Replaced Section 28.5: AES chaining algorithms with Section 28.4.8: AES basic chaining modes (ECB, CBC) , Section 28.4.9: AES counter (CTR) mode .

Replaced Section 28.6: Galois counter mode (GCM) with Section 28.4.10: AES Galois/counter mode (GCM)

Replaced Section 28.7: AES cipher message authentication code mode (CMAC) with Section 28.4.11: AES Galois message authentication code (GMAC)

Replaced Section 28.8: Data type with Section 28.4.13: AES data registers and data swapping

Replaced Section 28.10: AES DMA interface with Section 28.4.16: AES DMA interface

Replaced Section 28.13: AES interrupts with Section 28.5: AES interrupts

Advanced-control Timers(TIM1/TIM8):

Updated Figure 237: Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 , Section 30.3.22: Encoder interface mode , Section 30.3.23: Slave mode: external clock mode 2 + trigger mode , Section 30.3.27: ADC synchronization , Section 30.4.3: TIMx slave mode control register (TIMx_SMCR)(x = 1, 8) , Section 30.4.14: TIMx auto-reload register (TIMx_ARR)(x = 1, 8) , Section 30.4.14: TIMx auto-reload register (TIMx_ARR)(x = 1, 8)

General-purpose timers:

Updated Figure 298: Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 , Figure 32.2: TIM15 main features , Figure 32.5.22: Timer synchronization (TIM15) , Section 32.6.3: TIM15 slave mode control register (TIM15_SMCR) , Section 32.6.8: TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) , Section 32.7.17: TIM16 option register 1 (TIM16_OR1)

Added Figure 32.4: Implementation , Section 32.5.16: Retriggerable one pulse mode (TIM15 only)

LPTIMER:

Added Section 34.4.2: LPTIM trigger mapping

Updated Figure 380: LPTIM output waveform, single counting mode configuration , Figure 381: LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set) , Figure 382: LPTIM output waveform, Continuous counting mode configuration , Figure 383: Waveform generation , Section 34.4.10: Register update , Section 34.4.13: Encoder mode , Section 34.6: LPTIM interrupts , Section 34.7.4: LPTIM configuration register (LPTIM_CFGR)

WWDG:

Updated Figure 387: Watchdog block diagram , Figure 388: Window watchdog timing diagram

RTC:

Updated Figure 389: RTC block diagram , Section 38.3.1: RTC block diagram , Section 38.3.11: RTC reference clock detection , Section 38.3.14: Tamper detection , Section 38.3.16: Alarm output .

I2C:

Updated Section 39.4.10: I2C_TIMINGR register configuration examples , Section 39.9.8: I2C interrupt clear register (I2C_ICR) .

USART:

Updated Figure 432: USART data clock timing diagram (M bits = 00)

Added note 2 on Table 247: STM32L47x/L48x/L49x/L4Ax USART/UART/LPUART features , Section 40.5.5: Tolerance of the USART receiver to clock deviation , Section 40.5.11: USART synchronous mode , Section 40.8.1: USART control register 1 (USART_CR1) .

LPUART:

Updated Section 41.4.5: Tolerance of the LPUART receiver to clock deviation , Section 41.7.1: Control register 1 (LPUART_CR1) , Section 41.7.3: Control register 3 (LPUART_CR3) .

SAI:
Updated Section 43.5.1: SAI global configuration register (SAI_GCR) , Section 43.5.2: SAI configuration register 1 (SAI_ACR1) , Table 275: SAI register map and reset values

bxCAN:
Updated Section 46.2: bxCAN main features , Section 46.3.4: Acceptance filters , Section 46.6: Behavior in debug mode , Section 46.7.4: Identifier filtering , Figure 525: Example of filter numbering
Added: Figure 524: Filter bank scale configuration - Register organization , Figure 525: Example of filter numbering , Figure 526: Filtering mechanism example , Figure 528: Bit timing , Figure 531: CAN mailbox registers , Section 46.9.4: CAN filter registers

OTG_FS:
Updated Section 47.7.2: USB host states , Section 47.9: OTG_FS low-power modes , Figure 540: Interrupt hierarchy , Section 47.15.38: OTG device IN endpoint common interrupt mask register (OTG_DIEPMSK) , Section 47.15.39: OTG device OUT endpoint common interrupt mask register (OTG_DOEPMSK) , Section 47.15.43: OTG device V _BUS pulsing time register (OTG_DVBUSPULSE) , Section 47.15.47: OTG device IN endpoint x interrupt register (OTG_DIEPINTx) , Section 47.15.52: OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) , Section 47.16.4: Host programming model , Table 329: OTG_FS register map and reset values

DBG_SUPPORT:
Updated Section 48.6.1: MCU device ID code .
Added support for STM32L471xx products in the present reference manual (following RM0392 discontinuation). The changes that only consist in mentioning that STM32L471xx benefit or does not benefit from a feature that was already documented in the previous release of this RM are not listed here below.

FLASH:
Updated Section 3.3.6: Flash main memory erase sequences .
Updated Section 3.3.7: Flash main memory programming sequences .
Updated Section Table 12.: Option byte format .
Updated Section Table 14.: Flash memory read protection status .

RCC:
Updated Section 6.2: Clocks introduction .
Updated Figure 15: Clock tree (for STM32L47x/L48x devices) .
Updated Section 6.2.5: PLL introduction .

Updated Section 6.4.5: PLLSAI1 configuration register (RCC_PLLSAI1CFGR) .

Updated Section 6.4.6: PLLSAI2 configuration register (RCC_PLLSAI2CFGR) .

Updated Section 6.4.8: Clock interrupt flag register (RCC_CIFR) .

CRS:

Updated Section 7.1: CRS introduction .

Added Section 7.3: CRS implementation .

GPIO:

Added Section 8.3: GPIO implementation .

Updated Section 8.3: GPIO functional description introduction .

Updated Section 8.3.2: I/O pin alternate function multiplexer and mapping .

Updated Section 8.4.1: GPIO port mode register (GPIOx_MODER) (x = A to E, H) .

Updated Section 8.4.6: GPIO port output data register (GPIOx_ODR) (x = A to E, H) .

SYSCFG:

Updated Section 9.2.3: SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) .

Updated Section 9.2.4: SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) .

Updated Section 9.2.5: SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) .

Updated Section 9.2.6: SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) .

Updated Section 9.2.11: SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2) .

INTERCONNECT:

Updated Section 10.3.2: From timer (TIM1/TIM2/TIM3/TIM4/TIM6/TIM8/TIM15) and EXTI to ADC (ADC1/ADC2/ADC3) .

DMA:

Updated Section 11.1: Introduction .

Added Section : Channel state and disabling a channel .

Updated Section Table 46.: Programmable data width and endian behavior (when PINC = MINC = 1) .

DMA2D:

Updated Section 12.5.15: DMA2D output color register (DMA2D_OCOLR) .

Added Section 12.5.24: DMA2D foreground CLUT (DMA2D_FGCLUTx) .

Added Section 12.5.22: DMA2D background CLUT (DMA2D_BGCLUT[y]) .

FMC:
Updated all table titles from Table 73: FMC_BCRx bitfields (mode 1) to Section Table 92.: FMC_BTRx bitfields (Synchronous multiplexed write mode) .
Updated Section : SRAM/NOR-flash chip-select timing register for bank x (FMC_BTRx) .
QUADSPI:
Updated Section 17.6.1: QUADSPI control register (QUADSPI_CR) .
Updated Section 17.6.6: QUADSPI communication configuration register (QUADSPI_CCR) .
ADC:
Updated Section 18.2: ADC main features .
Updated Figure 66: ADC block diagram .
Updated Table 104: ADC internal input/output signals .
Updated Figure 68: ADC1 connectivity .
Updated Figure 70: ADC3 connectivity .
Updated Section 18.4.7: Single-ended and differential input channels .
Updated Section 18.4.9: ADC on-off control (ADEN, ADDIS, ADRDY) .
Updated Section 18.4.11: Channel selection (SQRx, JSQRx) .
Updated Section 18.4.12: Channel-wise programmable sampling time (SMPR1, SMPR2) .
Updated Section 18.4.16: ADC timing .
Updated Section 18.4.20: Discontinuous mode (DISCEN, DISCNUM, JDISCEN) .
Updated Table 110: TSAR timings depending on resolution .
Updated Section 18.4.26: Data management .
Updated Table 113: Analog watchdog 1 comparison .
Updated Table 114: Analog watchdog 2 and 3 comparison .
Updated Figure 121: Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode .
Updated Section 18.4.32: Temperature sensor .
Updated Section 18.4.34: Monitoring the internal voltage reference .
Updated Section 18.7.4: ADC configuration register (ADC_CFGR) .
Updated Section 18.7.7: ADC sample time register 2 (ADC_SMPR2) .
Updated Section 18.7.12: ADC regular sequence register 2 (ADC_SQR2) .
Updated Section 18.7.13: ADC regular sequence register 3 (ADC_SQR3) .
Updated Section 18.7.16: ADC injected sequence register (ADC_JSQR) .

Updated Section 18.7.17: ADC offset y register (ADC_OFRy) .

Updated Section 18.7.19: ADC analog watchdog 2 configuration register (ADC_AWD2CR) .

Updated Section 18.7.20: ADC analog watchdog 3 configuration register (ADC_AWD3CR) .

Updated Section 18.7.21: ADC differential mode selection register (ADC_DIFSEL) .

DAC:

Updated Section 19.3: DAC implementation .

Updated Section 19.4.6: DAC trigger selection .

Updated Section 19.4.10: DAC channel modes .

DCMI:

Updated Section 20.1: Introduction .

Updated Section 20.3.11: DCMI data format description .

Updated Table 140: DCMI interrupts .

VREF:

Added Section 21.3: VREFBUF trimming .

Updated Section 21.4.2: VREFBUF calibration control register (VREFBUF_CCR) .

DFSDM:

Updated Table 155: DFSDM1 implementation .

Updated Table 24.4.3: DFSDM reset and clocks .

Updated Section 24.7: DFSDM channel y registers (y=0..7) introduction .

Updated Section 24.8: DFSDM filter x module registers (x=0..3) introduction .

RNG:

Updated Section 27.1: Introduction .

Updated Section 27.2: RNG main features .

Updated Section 27.3.3: Random number generation .

Updated Section 27.3.5: RNG operation .

Updated Section 27.3.6: RNG clocking .

Updated Section Table 177.: RNG interrupt requests .

Updated Section 27.6: RNG entropy source validation .

Updated Section 27.7.3: RNG data register (RNG_DR) .

AES:

Updated Section : Suspend/resume operations in GCM mode .

HASH:

Section 29: Hash processor (HASH) has been completely revisited.

TIM1/TIM8:

Updated Section 30.3.3: Repetition counter .

Updated Section : External clock source mode 2 .

Updated Section 30.3.16: Using the break function .

Updated Section 30.4: TIM1/TIM8 registers introduction .

Updated Section 30.4.2: TIMx control register 2 (TIMx_CR2)(x = 1, 8) .

Updated Section 30.4.5: TIMx status register (TIMx_SR)(x = 1, 8) .

Updated Section 30.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 1, 8) .

Added Section 30.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 1, 8) .

Updated Section 30.4.9: TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 1, 8) .

Added Section 30.4.10: TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)(x = 1, 8) .

Updated Section 30.4.11: TIMx capture/compare enable register (TIMx_CCER)(x = 1, 8) .

Updated Section 30.4.25: TIMx capture/compare mode register 3 (TIMx_CCMR3)(x = 1, 8) .

TIM2/TIM3/TIM4/TIM5:

Updated Section : External clock source mode 2 .

Updated Figure 311: Output stage of Capture/Compare channel (channel 1) .

Updated Section 31.4.5: TIMx status register (TIMx_SR)(x = 2 to 5) .

Updated Section 31.4.5: TIMx status register (TIMx_SR)(x = 2 to 5) .

Updated Section 31.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) .

Updated Section 31.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 5) .

Updated Section 31.4.9: TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5) .

Updated Section 31.4.10: TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2) (x = 2 to 5) .

Updated Section 31.4.11: TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 5) .

Updated Section 31.4.12: TIMx counter (TIMx_CNT)(x = 2 to 5) .

Updated Section 31.4.13: TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) .

Updated Section 31.4.25: TIM3 option register 2 (TIM3_OR2) .

TIM15/TIM16/TIM17:

Updated Figure 349: Capture/compare channel 1 main circuit .

Updated Section 32.5.13: Using the break function .

Updated Section 32.6: TIM15 registers introduction .

Updated Section 32.6.5: TIM15 status register (TIM15_SR) .

Updated Section 32.6.7: TIM15 capture/compare mode register 1 (TIM15_CCMR1) .

Updated Section 32.6.8: TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) .

Updated Section 32.6.9: TIM15 capture/compare enable register (TIM15_CCER) .

Updated Section 32.7: TIM16/TIM17 registers introduction .

Updated Section 32.7.2: TIMx control register 2 (TIMx_CR2)(x = 16 to 17) .

Updated Section 32.7.3: TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) .

Updated Section 32.7.4: TIMx status register (TIMx_SR)(x = 16 to 17) .

Updated Section 32.7.6: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 16 to 17) .

Updated Section 32.7.7: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 16 to 17) .

Updated Section 32.7.8: TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) .

LPTIM:

Updated Section 34.4.6: Trigger multiplexer .

Updated Section 34.4.9: Waveform generation .

Updated Section 34.4.13: Encoder mode .

Added Section 34.4.14: Debug mode .

Updated Section 34.7: LPTIM registers introduction .

Added Section 34.7.1: LPTIM interrupt and status register (LPTIM_ISR) .

Added Section 34.7.2: LPTIM interrupt clear register (LPTIM_ICR) .

Added Section 34.7.3: LPTIM interrupt enable register (LPTIM_IER) .

Added Section 34.7.4: LPTIM configuration register (LPTIM_CFGR) .

IWDG:

Updated Figure 386: Independent watchdog block diagram footnote .

Added Section 34.7.2: LPTIM interrupt clear register (LPTIM_ICR) .

WWDG:

Removed Section 37.3.3: Advanced watchdog interrupt feature .

Added Section 37.4: WWDG interrupts .

RTC:

Updated Section 38.3.4: Real-time clock and calendar .

Updated Section 38.3.8: Reading the calendar .

Updated Section Table 225.: Effect of low-power modes on RTC .

I2C:

Updated Section 39.3: I2C implementation .

Updated Section 39.4.1: I2C block diagram .

Added Section 39.4.2: I2C pins and internal signals .

Updated Table 244: Effect of low-power modes to I2C .

Updated Table 245: I2C interrupt requests .

Updated Section 39.9.2: I2C control register 2 (I2C_CR2) .

Updated Section 39.9.3: I2C own address 1 register (I2C_OAR1) .

USART/UART:

Updated Figure 420: USART block diagram .

Updated Figure 440: Reception using DMA .

Updated Figure 456: LPUART interrupt mapping diagram .

Updated Figure 40.8: USART registers introduction .

Updated Figure 445: LPUART block diagram .

Updated Section 41.4.4: LPUART baud rate generation .

Updated Figure 41.7: LPUART registers introduction .

SPI:

Updated Section 42.2: SPI main features .

Updated Section 42.3: SPI implementation .

Updated Section Table 264.: STM32L47x/L48x/L49x/L4Ax SPI implementation .

SAI:

Updated Section 43.3.8: SAI clock generator .

Updated Section : Clock generator programming in SPDIF generator mode .

Updated Section : Companding mode .

Updated Section 43.5: SAI registers introduction .

Updated Section 43.5.11: SAI configuration register 2 (SAI_BCR2) .

Updated Section 43.5.4: SAI frame configuration register (SAI_AFRCR) .

Updated Section 43.5.7: SAI status register (SAI_ASR) .

Updated Section 43.5.15: SAI status register (SAI_BSR) .

SWPMI:

Updated Section 44.6: SWPMI registers introduction .

USB:

Updated Table 322: Core global control and status registers (CSRs) .

Updated Table 47.15.2: OTG interrupt register (OTG_GOTGINT) .

updated Section 47.15.6: OTG core interrupt register (OTG_GINTSTS) .

Updated Section 47.15.8: OTG receive status debug read register (OTG_GRXSTSR) .

Updated Figure 308: Control circuit in external clock mode 2 .

Updated Figure 310: Capture/Compare channel 1 main circuit .

Updated Figure 311: Output stage of Capture/Compare channel (channel 1) .

Updated Section 31.3.19: Timer synchronization .

Added Figure 328: Master/slave connection example with 1 channel only timers and following Note.

Updated Section 31.4.2: TIMx control register 2 (TIMx_CR2)(x = 2 to 5) .

Updated Section 31.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 5) .

Updated Section 31.4.11: TIMx capture/compare enable register (TIMx_CCER)(x = 2 to 5) .

TIM15/TIM16/TIM17:

Added note below Figure 335: TIM16/TIM17 block diagram .

Updated Figure 349: Capture/compare channel 1 main circuit .

Updated Figure 351: Output stage of capture/compare channel (channel 2 for TIM15) .

Updated Section 32.5.7: PWM input mode (only for TIM15) .

Updated Section 32.5.13: Using the break function .

Added Section 32.5.23: Using timer output as trigger for other timers (TIM16/TIM17) .

Added Section 32.6.2: TIM15 control register 2 (TIM15_CR2) .

Updated Section 32.6.8: TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) .

Updated Note below Table 207: Output control bits for complementary OCx and OCxN channels with break feature (TIM15) .

Updated Section 32.6.16: TIM15 break and dead-time register (TIM15_BDTR) .

Updated Section 32.7.7: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 16 to 17) .

Updated Note below Table 209: Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) .

Updated Section 32.7.14: TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) .

LPTIM:

Updated Section 34.2: LPTIM main features .

Updated Section 34.4.4: Glitch filter .

Added last Note to Section 34.4.6: Trigger multiplexer .

Updated Section 34.7.2: LPTIM interrupt clear register (LPTIM_ICR) .

Power control register 4 (PWR_CR4)
Power status register 1 (PWR_SR1)
Power Port A pull-up control register (PWR_PUCRA)
Power Port A pull-down control register (PWR_PDCRA)
Power Port B pull-up control register (PWR_PUCRB)
Power Port B pull-down control register (PWR_PDCRB)
Power Port C pull-up control register (PWR_PUCRC)
Power Port C pull-down control register (PWR_PDCRC)
Power Port D pull-up control register (PWR_PUCRD)
Power Port D pull-down control register (PWR_PDCRD)
Power Port E pull-up control register (PWR_PUCRE)
Power Port E pull-down control register (PWR_PDCRE)
Power Port F pull-up control register (PWR_PUCRF)
Power Port F pull-down control register (PWR_PDCRF)
Power Port G pull-up control register (PWR_PUCRG)
Power Port G pull-down control register (PWR_PDCRG)
Power Port H pull-up control register (PWR_PUCRH)
Power Port H pull-down control register (PWR_PDCRH)
Power Port I pull-up control register (PWR_PUCRI)
Power Port I pull-down control register (PWR_PDCRI)

CRC:
Updated Section 15.2: CRC main features .
Updated Figure 35: CRC calculation unit block diagram .
Updated Section 15.4: CRC registers introduction .
Updated Section 15.4.2: CRC independent data register (CRC_IDR) .

ADC:
Replaced ADCx_CCR by ADCx_CDR (typo, 2 occurrences) in Section : Regular simultaneous mode with independent injected .
Updated address offset in:
ADC common status register (ADC_CSR)
ADC common control register (ADC_CCR)
ADC common regular data register for dual mode (ADC_CDR) .

TIM2/3/4/5:
Removed OC1PE Note in TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 5).

TIM15/16/17:
Change bit 10 to Reserved in register TIM15 DMA/interrupt enable register (TIM15_DIER) .

RTC:
Removed Note in Section 38.3.15: Calibration clock output and Section 38.3.16: Alarm output .

USART/UART:
Replaced “asserted” by “deasserted”, multiple occurrences in Section : RS232 RTS flow control , Section : RS232 CTS flow control , bit CTSE/RTSE in USART control register 3 (USART_CR3) ,

Section : RS232 RTS flow control, Section : RS232 CTS flow control and bit CTSE/RTSE in Control register 3 (LPUART_CR3).

FLASH:
Updated Section 3.5.1: Read protection (RDP) .

PWR:
Updated Section 5.3.3: Low power modes .

RCC:
Updated Section 6.2.6: LSE clock .
Updated Section 6.2.11: Clock security system on LSE .
Updated Section 6.4.8: Clock interrupt flag register (RCC_CIFR) .
Updated Section 6.4.11: AHB2 peripheral reset register (RCC_AHB2RSTR) .
Updated Section 6.4.17: AHB2 peripheral clock enable register (RCC_AHB2ENR) .
Updated Section 6.4.23: AHB2 peripheral clocks enable in Sleep and Stop modes register (RCC_AHB2SMENR) .

CRS:
Updated Section 7.5: CRS low-power modes .

GPIO:
Updated Section 8.4.13: Using the HSE or LSE oscillator pins as GPIOs .

DMA:
Updated Section 11.3.1: DMA1 and DMA2 .
Updated Table 45: DMA2 requests for each channel .
Updated Figure 31: DMA block diagram .

NVIC:
Updated Table 58: STM32L47x/L48x/L49x/L4Ax vector table .

CRC:
Section 15.4.2: CRC independent data register (CRC_IDR) .

QUADSPI:
Whole section re-edited.

ADC:
Updated Section 18.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) .
Updated Figure 80: Example of JSQR queue of context (sequence change) to Figure 86: Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 0) Case when JADSTP occurs during an ongoing conversion .
Updated Figure 90: Flushing JSQR queue of context by setting ADDIS = 1 (JQM = 0) .
Updated Section : DMA one shot mode (DMACFG = 0) .
Updated Figure 105: AUTODLY = 1 in auto-injected mode (JAUTO = 1) .

AES:
Updated Section 28: AES hardware accelerator (AES) introduction.

HASH:
Replaced SHA-224 and SHA-256 by SHA2-224 and SHA2-256 in the whole section.
Updated Section 29.4.5: Message digest computing .
Updated Section 29.4.7: HMAC operation

TIM1/TIM8:
Updated Figure 247: Control circuit in normal mode, internal clock divided by 1 .
Updated Section 30.3.16: Using the break function .
Updated Section 30.3.18: Clearing the OCxREF signal on an external event .
Updated Figure 275: Retriggerable one pulse mode .
Updated Section 30.3.21: Retriggerable one pulse mode .
Updated SMS[3:0] in Section 30.4.3: TIMx slave mode control register (TIMx_SMCR)(x = 1, 8) .
Updated OC1M[3:0] in Section 30.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 1, 8) .
Updated BKE in Section 30.4.20: TIMx break and dead-time register (TIMx_BDTR)(x = 1, 8) .

TIM2/TIM3/TIM4/TIM5:
Updated Section 31.3.1: Time-base unit .
Updated Figure 297: Counter timing diagram , Update event title.
Updated Section 31.3.12: Clearing the OCxREF signal on an external event .
Updated Figure 320: Retriggerable one-pulse mode .
Updated Section 31.3.15: Encoder interface mode .
Updated Section 31.3.18: Timers and external trigger synchronization .
Updated OC1M[3:0] in Section 31.4.8: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1) (x = 2 to 5) .

TIM15/TIM16/TIM17:
Updated Figure 345: Control circuit in normal mode, internal clock divided by 1 .
Updated Section 32.5.13: Using the break function .
Added Section 32.5.14: 6-step PWM generation .
Updated Figure 363: Retriggerable one pulse mode .
Updated SMS[3:0] in Section 32.6.3: TIM15 slave mode control register (TIM15_SMCR) .
Updated OC1M[3:0] in Section 32.6.8: TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) .

Updated OC1M[3:0] in Section 32.7.7: TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)(x = 16 to 17) .

IWDG:
Updated Figure 386: Independent watchdog block diagram .

WWDG:
Updated Figure 387: Watchdog block diagram .
Updated Section 37.3.3: Controlling the down-counter .
Updated Section 37.4: WWDG interrupts .
Updated EWI in Section 37.5.2: WWDG configuration register (WWDG_CFR) .

RTC:
Updated Figure 389: RTC block diagram .
Updated Section 38.3.16: Alarm output .
Updated Section 38.6.4: RTC initialization and status register (RTC_ISR) .

I2C:
Whole section re-edited.

UART/USART:
Updated ORE and FE in Section 40.8.8: USART interrupt and status register (USART_ISR) .

LPUART:
Updated ORE and FE in Section 41.7.6: Interrupt & status register (LPUART_ISR) .

SPI:
Updated Section : Simplex communications .
Updated Section : Communication using DMA (direct memory addressing) .

SWPMI:
Updated Section 44.6.5: SWPMI Interrupt Enable register (SWPMI_IER) .

SECURITY NOTICE:
Added Section 50: Important security notice .