10. Peripherals interconnect matrix

10.1 Introduction

Several peripherals have direct connections between them.

This allows autonomous communication and or synchronization between peripherals, saving CPU resources thus power supply consumption.

In addition, these hardware connections remove software latency and allow design of predictable system.

Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run and sleep, Stop 0, Stop 1 and Stop 2 modes.

10.2 Connection summary

Table 42. STM32L47x/L48x/L49x/L4Ax peripherals interconnect matrix ^{(1) (2)}

Source	Destination
Source	TIM1	TIM8	TIM2	TIM3	TIM4	TIM5	TIM6	TIM7	TIM15	TIM16	TIM17	LPTIM1	LPTIM2	ADC1	ADC2	ADC3	DFSDM1	OPAMP1	OPAMP2	DAC_CH1	DAC_CH2	COMP1	COMP2	IRTIM
TIM1	-	1	1	1	1	-	-	-	1	-	-	-	-	2	2	2	5	-	-	-	-	9	-	-
TIM8	-	-	1	-	1	1	-	-	-	-	-	-	-	2	2	2	5	-	-	4	4	-	9	-
TIM2	1	1	-	1	1	1	-	-	-	-	-	-	-	2	2	2	-	-	-	4	4	9	-	-
TIM3	1	-	1	-	1	1	-	-	1	-	-	-	-	2	2	2	5	-	-	-	-	9	9	-
TIM4	1	1	1	1	-	1	-	-	-	-	-	-	-	2	2	2	5	-	-	4	4	-	-	-
TIM5	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	4	4	-	-	-
TIM6	-	-	-	-	-	-	-	-	-	-	-	-	-	2	2	2	5	-	-	4	4	-	-	-
TIM7	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	5	-	-	4	4	-	-	-
TIM15	1	-	-	1	-	-	-	-	-	-	-	-	-	2	2	2	-	-	-	-	-	-	9	-
TIM16	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	5	-	-	-	-	-	-	15
TIM17	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	15
LPTIM1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
LPTIM2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
ADC1	3	-	-	-	-	-	-	-	-	-	-	-	-	-	10	-	16	-	-	-	-	-	-	-
ADC2	-	3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	16	-	-	-	-	-	-	-
ADC3	3	3	-	-	-	-	-	-	-	-	-	-	-	-	-	-	16	-	-	-	-	-	-	-
DFSDM1	6	6	-	-	-	-	-	-	6	6	6	-	-	-	-	-	-	-	-	-	-	-	-	-
T. Sensor	-	-	-	-	-	-	-	-	-	-	-	-	-	12	-	12	-	-	-	-	-	-	-	-
VBAT	-	-	-	-	-	-	-	-	-	-	-	-	-	12	-	12	-	-	-	-	-	-	-	-

Table 42. STM32L47x/L48x/L49x/L4Ax peripherals interconnect matrix^{(1) (2)}(continued)

Source	Destination
Source	TIM1	TIM8	TIM2	TIM3	TIM4	TIM5	TIM6	TIM7	TIM15	TIM16	TIM17	LPTIM1	LPTIM2	ADC1	ADC2	ADC3	DFSDM1	OPAMP1	OPAMP2	DAC_CH1	DAC_CH2	COMP1	COMP2	IRTIM
VREFINT	-	-	-	-	-	-	-	-	-	-	-	-	-	12	-	-	-	-	-	-	-	-	-	-
OPAMP1	-	-	-	-	-	-	-	-	-	-	-	-	-	12	12	-	-	-	-	-	-	-	-	-
OPAMP2	-	-	-	-	-	-	-	-	-	-	-	-	-	12	12	-	-	-	-	-	-	-	-	-
DAC_CH1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	12	12	-	12	12	-	-	-	-	-
DAC_CH2	-	-	-	-	-	-	-	-	-	-	-	-	-	-	12	12	-	-	-	-	-	-	-	-
HSE	-	-	-	-	-	-	-	-	-	-	7	-	-	-	-	-	-	-	-	-	-	-	-	-
LSE	-	-	7	-	-	-	-	-	7	7	-	-	-	-	-	-	-	-	-	-	-	-	-	-
MSI	-	-	-	-	-	-	-	-	-	-	7	-	-	-	-	-	-	-	-	-	-	-	-	-
LSI	-	-	-	-	-	-	-	-	-	7	-	-	-	-	-	-	-	-	-	-	-	-	-	-
MCO	-	-	-	-	-	-	-	-	-	-	7	-	-	-	-	-	-	-	-	-	-	-	-	-
EXTI	-	-	-	-	-	-	-	-	-	-	-	-	-	2	2	2	5	-	-	4	4	-	-	-
RTC	-	-	-	-	-	-	-	-	-	7	-	8	8	-	-	-	-	-	-	-	-	-	-	-
COMP1	13	13	13	13	-	-	-	-	13	13	13	8	8	-	-	-	-	-	-	-	-	-	-	-
COMP2	13	13	13	13	-	-	-	-	13	13	13	8	8	-	-	-	-	-	-	-	-	-	-	-
SYST ERR	14	14	-	-	-	-	-	-	14	14	14	-	-	-	-	-	-	-	-	-	-	-	-	-
USB ⁽³⁾	-	-	11	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-

1. Numbers in table are links to corresponding detailed sub-section in Section 10.3: Interconnection details .

2. The “-” symbol in grayed cells means no interconnect.

3. Not available on STM32L471 devices.

10.3 Interconnection details

10.3.1 From timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15/TIM16/TIM17) to timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15)

Purpose

Some of the TIMx timers are linked together internally for timer synchronization or chaining.

When one timer is configured in Master Mode, it can reset, start, stop or clock the counter of another timer configured in Slave Mode.

A description of the feature is provided in: Section 31.3.19: Timer synchronization .

The modes of synchronization are detailed in:

• Section 31.3.19: Timer synchronization for advanced-control timers (TIM1/TIM8)
• Section 31.3.18: Timers and external trigger synchronization for general-purpose timers (TIM2/TIM3/TIM4/TIM5)
• Section 32.5.19: External trigger synchronization (TIM15 only) for general-purpose timer (TIM15)

Triggering signals

The output (from Master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1/TIM8) following a configurable timer event.

The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3

The input and output signals for TIM1/TIM8 are shown in Figure 223: Advanced-control timer block diagram .

The possible master/slave connections are given in:

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.2 From timer (TIM1/TIM2/TIM3/TIM4/TIM6/TIM8/TIM15) and EXTI to ADC (ADC1/ADC2/ADC3)

Purpose

General-purpose timers (TIM2/TIM3/TIM4), basic timer (TIM6), advanced-control timers (TIM1/TIM8), general-purpose timer (TIM15) and EXTI can be used to generate an ADC triggering event.

TIMx synchronization is described in: Section 30.3.5: Clock selection (TIM1/TIM8).

ADC synchronization is described in: Section 18.4.18: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) .

Triggering signals

The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event.

The input (to ADC) is on signal EXT[15:0], JEXT[15:0].

The connection between timers and ADCs is provided in:

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.3 From ADC (ADC1/ADC2/ADC3) to timer (TIM1/TIM8)

Purpose

ADC1/ADC2/ADC3 can provide trigger event through watchdog signals to advanced-control timers (TIM1/TIM8).

A description of the ADC analog watchdog setting is provided in: Section 18.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) .

Trigger settings on the timer are provided in: Section 30.3.4: External trigger input .

Triggering signals

The output (from ADC) is on signals ADCn_AWDx_OUT n = 1, 2, 3 (for ADC1, 2, 3) x = 1, 2, 3 (3 watchdog per ADC) and the input (to timer) on signal TIMx_ETR (external trigger).

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.4 From timer (TIM2/TIM4/TIM5/TIM6/TIM7/TIM8) and EXTI to DAC (DAC_CH1/DAC_CH2)

Purpose

General-purpose timers (TIM2/TIM4/TIM5), basic timers (TIM6, TIM7), advanced-control timers (TIM8) and EXTI can be used as triggering event to start a DAC conversion.

Triggering signals

The output (from timer) is on signal TIMx_TRGO directly connected to corresponding DAC inputs.

Selection of input triggers on DAC is provided in Section 19.4.6: DAC trigger selection (single and dual mode).

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.5 From timer (TIM1/TIM3/TIM4/TIM6/TIM7/TIM8/TIM16) and EXTI to DFSDM1

Purpose

General-purpose timers (TIM3/TIM4), basic timers (TIM6/TIM7), advanced-control timers (TIM1/TIM8), general-purpose timer (TIM16) and EXTI can be used to generate a triggering event on DFSDM1 module (on each possible data block DFSDM1_FLT0/DFSDM1_FLT1/DFSDM1_FLT2/DFSDM1_FLT3) and start an ADC conversion.

DFSDM triggered conversion feature is described in: Section 24.4.15: Launching conversions .

Triggering signals

The output (from timer) is on signal TIMx_TRGO/TIMx_TRGO2 or TIM16_OC1.

The input (on DFSDM1) is on signal DFSDM1_INTRG[0:8].

The connection between timers, EXTI and DFSDM1 is provided in Table 158: DFSDM triggers connection .

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.6 From DFSDM1 to timer (TIM1/TIM8/TIM15/TIM16/TIM17)

Purpose

DFSDM1 can generate a timer break on advanced-control timers (TIM1/TIM8) and general-purpose timers (TIM15/TIM16/TIM17) when a watchdog is activated (minimum or maximum threshold value crossed by analog signal) or when a short-circuit detection is made.

DFSDM1 watchdog is described in Section 24.4.10: Analog watchdog .

DFSDM1 short-circuit detection is described in Section 24.4.11: Short-circuit detector .

Timer break is described in:

• Section 30.3.16: Using the break function (TIM1/TIM8)
• Section 32.5.13: Using the break function (TIM15/TIM16/TIM17)

Triggering signals

The output (from DFSDM1) is on signals dfsdm1_break[0:3] directly connected to timer and 'Ored' with other break input signals of the timer.

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.7 From HSE, LSE, LSI, MSI, MCO, RTC to timer (TIM2/TIM15/TIM16/TIM17)

Purpose

External clocks (HSE, LSE), internal clocks (LSI, MSI), microcontroller output clock (MCO), GPIO and RTC wakeup interrupt can be used as input to general-purpose timer (TIM15/16/17) channel 1.

This allows to calibrate the HSI16/MSI system clocks (with TIM15/TIM16 and LSE) or LSI (with TIM16 and HSE). This is also used to precisely measure LSI (with TIM16 and HSI16) or MSI (with TIM17 and HSI16) oscillator frequency.

When Low Speed External (LSE) oscillator is used, no additional hardware connections are required.

This feature is described in Section 6.2.18: Internal/external clock measurement with TIM15/TIM16/TIM17 .

External clock LSE can be used as input to general-purpose timers (TIM2) on TIM2_ETR pin, see Section 31.4.22: TIM2 option register 1 (TIM2_OR1) .

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.8 From RTC, COMP1, COMP2 to low-power timer (LPTIM1/LPTIM2) Purpose

RTC alarm A/B, RTC_TAMP1/2/3 input detection, COMP1/2_OUT can be used as trigger to start LPTIM counters (LPTIM1/2).

Triggering signals

This trigger feature is described in Section 34.4.6: Trigger multiplexer (and following sections).

The input selection is described in Table 213: LPTIM1 external trigger connection .

Active power mode

Run, Sleep, Low-power run, Low-power sleep, Stop 0, Stop 1, Stop 2 (LPTIM1 only).

10.3.9 From timer (TIM1/TIM2/TIM3/TIM8/TIM15) to comparators (COMP1/COMP2) Purpose

Advanced-control timers (TIM1/TIM8), general-purpose timers (TIM2/TIM3) and general-purpose timer (TIM15) can be used as blanking window input to COMP1/COMP2

The blanking function is described in Section 22.3.7: Comparator output blanking function .

The blanking sources are given in:

• Section 22.6.1: Comparator 1 control and status register (COMP1_CSR) bits 20:18 BLANKING[2:0]
• Section 22.6.2: Comparator 2 control and status register (COMP2_CSR) bits 20:18 BLANKING[2:0]

Triggering signals

Timer output signal TIMx_Ocx are the inputs to blanking source of COMP1/COMP2.

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.10 From ADC (ADC1) to ADC (ADC2) Purpose

ADC1 can be used as a “master” to trigger ADC2 “slave” start of conversion.

In dual ADC mode, the converted data of the master and slave ADCs can be read in parallel.

A description of dual ADC mode is provided in: Section 18.4.31: Dual ADC modes .

Triggering signals

Internal to the ADCs.

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.11 From USB to timer (TIM2)

Purpose

USB (OTG_FS SOF) can generate a trigger to general-purpose timer (TIM2).

Connection of USB to TIM2 is described in Table 203: TIMx internal trigger connection .

Triggering signals

Internal signal generated by USB FS Start Of Frame.

Active power mode

Run, Sleep.

10.3.12 From internal analog source to ADC (ADC1/ADC2/ADC3) and OPAMP (OPAMP1/OPAMP2)

Purpose

Internal temperature sensor ( $V_{TS}$ ) and $V_{BAT}$ monitoring channel are connected to ADC1/ADC3 input channels.

Internal reference voltage ( $V_{REFINT}$ ) is connected to ADC1 input channels.

OPAMP1 and OPAMP2 outputs can be connected to ADC1 or ADC2 input channels through the GPIO.

DAC1_OUT1 and DAC1_OUT2 outputs can be connected to ADC2 or ADC3 input channel.

DAC1_OUT1 can be connected to OPAMP1_VINP.

DAC1_OUT2 can be connected to OPAMP2_VINP.

This is according:

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.13 From comparators (COMP1/COMP2) to timers (TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17)

Purpose

Comparators (COMP1/COMP2) output values can be connected to timers (TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17) input captures or TIMx_ETR signals.

The connection to ETR is described in Section 30.3.4: External trigger input .

Comparators (COMP1/COMP2) output values can also generate break input signals for timers (TIM1/TIM8) on input pins TIMx_BKIN or TIMx_BKIN2 through GPIO alternate function selection using open drain connection of IO, see Section 30.3.17: Bidirectional break inputs .

The possible connections are given in:

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.14 From system errors to timers (TIM1/TIM8/TIM15/TIM16/TIM17)

Purpose

CSS, CPU hardfault, RAM parity error, FLASH ECC double error detection, PVD can generate system errors in the form of timer break toward timers (TIM1/TIM8/TIM15/TIM16/TIM17).

The purpose of the break function is to protect power switches driven by PWM signals generated by the timers.

List of possible source of break are described in:

• Section 30.3.16: Using the break function (TIM1/TIM8)
• Section 32.5.13: Using the break function (TIM15/TIM16/TIM17)
• Figure 334: TIM15 block diagram
• Figure 335: TIM16/TIM17 block diagram

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.15 From timers (TIM16/TIM17) to IRTIM

Purpose

General-purpose timer (TIM16/TIM17) output channel TIMx_OC1 are used to generate the waveform of infrared signal output.

The functionality is described in Section 35: Infrared interface (IRTIM) .

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

10.3.16 From ADC (ADC1/ADC2/ADC3) to DFSDM (only for STM32L49x/L4Ax devices)

Purpose

Up to 3 internal ADC results can be directly connected through a parallel bus to DFSDM input in order to use DFSDM filtering capabilities.

The feature is described as part of DFSDM peripheral description in Section 24.4.6: Parallel data inputs - Input from internal ADC

The possible connections are given in:

• Section 24.7.1: DFSDM channel y configuration register (DFSDM_CHyCFGR1)
- – Bits 13:12 DATMPX[1:0]: Input data multiplexer for channel y
• Section 24.7.5: DFSDM channel y data input register (DFSDM_CHyDATINR)
- – Bits 31:16 INDAT0[15:0]: Input data for channel y or channel y+1
- – Bits 15:0 INDAT0[15:0]: Input data for channel y

Active power mode

Run, Sleep, Low-power run, Low-power sleep.