RM0351-STM32L47-48-49-4A

Introduction

This reference manual targets application developers. It provides complete information on how to use the STM32L47xxx/STM32L48xxx/STM32L49xxx/STM32L4Axxx microcontroller memory and peripherals.

The STM32L47xxx/STM32L48xxx/STM32L49xxx/STM32L4Axxx is a family of microcontrollers with different memory sizes, packages and peripherals.

For ordering information, mechanical and electrical device characteristics please refer to the corresponding datasheets.

For information on the Arm ® Cortex ® -M4 core, please refer to the Cortex ® -M4 Technical Reference Manual.

The STM32L47x/L48x/L49x/L4Ax microprocessors include ST state-of-the-art patented technology.

In this document, the following short names, or combinations of them, may be used to refer to subsets of the above-listed part numbers:

Contents

3.3.2Error code correction (ECC) .....99
3.3.3Read access latency .....100
3.3.4Adaptive real-time memory accelerator (ART Accelerator™) .....101
3.3.5Flash program and erase operations .....103
3.3.6Flash main memory erase sequences .....104
3.3.7Flash main memory programming sequences .....105
3.3.8Read-while-write (RWW) .....108
3.4FLASH option bytes .....110
3.4.1Option bytes description .....110
3.4.2Option bytes programming .....116
3.5FLASH memory protection .....118
3.5.1Read protection (RDP) .....118
3.5.2Proprietary code readout protection (PCROP) .....121
3.5.3Write protection (WRP) .....122
3.6FLASH interrupts .....123
3.7FLASH registers .....124
3.7.1Flash access control register (FLASH_ACR) .....124
3.7.2Flash Power-down key register (FLASH_PDKEYR) .....125
3.7.3Flash key register (FLASH_KEYR) .....126
3.7.4Flash option key register (FLASH_OPTKEYR) .....126
3.7.5Flash status register (FLASH_SR) .....127
3.7.6Flash control register (FLASH_CR) .....128
3.7.7Flash ECC register (FLASH_ECCR) .....130
3.7.8Flash option register (FLASH_OPTR) .....131
3.7.9Flash Bank 1 PCROP Start address register (FLASH_PCROP1SR) ..133
3.7.10Flash Bank 1 PCROP End address register (FLASH_PCROP1ER) ..134
3.7.11Flash Bank 1 WRP area A address register (FLASH_WRP1AR) .....134
3.7.12Flash Bank 1 WRP area B address register (FLASH_WRP1BR) .....135
3.7.13Flash Bank 2 PCROP Start address register (FLASH_PCROP2SR) ..135
3.7.14Flash Bank 2 PCROP End address register (FLASH_PCROP2ER) ..136
3.7.15Flash Bank 2 WRP area A address register (FLASH_WRP2AR) .....136
3.7.16Flash Bank 2 WRP area B address register (FLASH_WRP2BR) .....137
3.7.17FLASH register map .....138
4Firewall (FW) .....140
4.1Introduction .....140
4.2Firewall main features . . . . .140
4.3Firewall functional description . . . . .141
4.3.1Firewall AMBA bus snoop . . . . .141
4.3.2Functional requirements . . . . .141
4.3.3Firewall segments . . . . .142
4.3.4Segment accesses and properties . . . . .143
4.3.5Firewall initialization . . . . .144
4.3.6Firewall states . . . . .145
4.4Firewall registers . . . . .147
4.4.1Code segment start address (FW_CSSA) . . . . .147
4.4.2Code segment length (FW_CSL) . . . . .147
4.4.3Non-volatile data segment start address (FW_NVDSSA) . . . . .148
4.4.4Non-volatile data segment length (FW_NVDLSL) . . . . .148
4.4.5Volatile data segment start address (FW_VDSSA) . . . . .149
4.4.6Volatile data segment length (FW_VDSL) . . . . .149
4.4.7Configuration register (FW_CR) . . . . .150
4.4.8Firewall register map . . . . .152
5Power control (PWR) . . . . .153
5.1Power supplies . . . . .153
5.1.1Independent analog peripherals supply . . . . .154
5.1.2Independent I/O supply rail . . . . .155
5.1.3Independent USB transceivers supply . . . . .155
5.1.4Independent LCD supply . . . . .156
5.1.5Battery backup domain . . . . .156
5.1.6Voltage regulator . . . . .157
5.1.7VDD12 domain . . . . .158
5.1.8Dynamic voltage scaling management . . . . .160
5.2Power supply supervisor . . . . .161
5.2.1Power-on reset (POR) / power-down reset (PDR) / brown-out reset (BOR) . . . . .161
5.2.2Programmable voltage detector (PVD) . . . . .162
5.2.3Peripheral Voltage Monitoring (PVM) . . . . .163
5.3Low-power modes . . . . .164
5.3.1Run mode . . . . .170
5.3.2Low-power run mode (LP run) . . . . .170
5.3.3Low power modes . . . . .171
5.3.4Sleep mode . . . . .172
5.3.5Low-power sleep mode (LP sleep) . . . . .173
5.3.6Stop 0 mode . . . . .174
5.3.7Stop 1 mode . . . . .176
5.3.8Stop 2 mode . . . . .177
5.3.9Standby mode . . . . .179
5.3.10Shutdown mode . . . . .182
5.3.11Auto-wakeup from low-power mode . . . . .183
5.4PWR registers . . . . .184
5.4.1Power control register 1 (PWR_CR1) . . . . .184
5.4.2Power control register 2 (PWR_CR2) . . . . .185
5.4.3Power control register 3 (PWR_CR3) . . . . .186
5.4.4Power control register 4 (PWR_CR4) . . . . .187
5.4.5Power status register 1 (PWR_SR1) . . . . .188
5.4.6Power status register 2 (PWR_SR2) . . . . .189
5.4.7Power status clear register (PWR_SCR) . . . . .191
5.4.8Power Port A pull-up control register (PWR_PUCRA) . . . . .191
5.4.9Power Port A pull-down control register (PWR_PDCRA) . . . . .192
5.4.10Power Port B pull-up control register (PWR_PUCRB) . . . . .192
5.4.11Power Port B pull-down control register (PWR_PDCRB) . . . . .193
5.4.12Power Port C pull-up control register (PWR_PUCRC) . . . . .193
5.4.13Power Port C pull-down control register (PWR_PDCRC) . . . . .194
5.4.14Power Port D pull-up control register (PWR_PUCRD) . . . . .194
5.4.15Power Port D pull-down control register (PWR_PDCRD) . . . . .195
5.4.16Power Port E pull-up control register (PWR_PUCRE) . . . . .195
5.4.17Power Port E pull-down control register (PWR_PDCRE) . . . . .196
5.4.18Power Port F pull-up control register (PWR_PUCRF) . . . . .196
5.4.19Power Port F pull-down control register (PWR_PDCRF) . . . . .197
5.4.20Power Port G pull-up control register (PWR_PUCRG) . . . . .197
5.4.21Power Port G pull-down control register (PWR_PDCRG) . . . . .198
5.4.22Power Port H pull-up control register (PWR_PUCRH) . . . . .198
5.4.23Power Port H pull-down control register (PWR_PDCRH) . . . . .199
5.4.24Power Port I pull-up control register (PWR_PUCRI) . . . . .199
5.4.25Power Port I pull-down control register (PWR_PDCRI) . . . . .200
5.4.26PWR register map and reset value table . . . . .201
6Reset and clock control (RCC) . . . . .203
6.1Reset .....203
6.1.1Power reset .....203
6.1.2System reset .....203
6.1.3Backup domain reset .....204
6.2Clocks .....205
6.2.1HSE clock .....211
6.2.2HSI16 clock .....212
6.2.3MSI clock .....213
6.2.4HSI48 clock (only valid for STM32L49x/L4Ax devices) .....213
6.2.5PLL .....214
6.2.6LSE clock .....215
6.2.7LSI clock .....215
6.2.8System clock (SYSCLK) selection .....215
6.2.9Clock source frequency versus voltage scaling .....216
6.2.10Clock security system (CSS) .....216
6.2.11Clock security system on LSE .....217
6.2.12USB Clock .....217
6.2.13ADC clock .....217
6.2.14RTC clock .....217
6.2.15Timer clock .....218
6.2.16Watchdog clock .....218
6.2.17Clock-out capability .....218
6.2.18Internal/external clock measurement with TIM15/TIM16/TIM17 .....219
6.2.19Peripheral clock enable register
(RCC_AHBxENR, RCC_APBxENRy) .....		221
6.3Low-power modes .....222
6.4RCC registers .....223
6.4.1Clock control register (RCC_CR) .....223
6.4.2Internal clock sources calibration register (RCC_ICSCR) .....226
6.4.3Clock configuration register (RCC_CFGR) .....227
6.4.4PLL configuration register (RCC_PLLCFGR) .....229
6.4.5PLLSAI1 configuration register (RCC_PLLSAI1CFGR) .....232
6.4.6PLLSAI2 configuration register (RCC_PLLSAI2CFGR) .....235
6.4.7Clock interrupt enable register (RCC_CIER) .....236
6.4.8Clock interrupt flag register (RCC_CIFR) .....238
6.4.9Clock interrupt clear register (RCC_CICR) .....239
6.4.10AHB1 peripheral reset register (RCC_AHB1RSTR) .....241
6.4.11AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . .242
6.4.12AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . .244
6.4.13APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . .244
6.4.14APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . .247
6.4.15APB2 peripheral reset register (RCC_APB2RSTR) . . . . .248
6.4.16AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . .249
6.4.17AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . .251
6.4.18AHB3 peripheral clock enable register(RCC_AHB3ENR) . . . . .252
6.4.19APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . . .253
6.4.20APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . . .256
6.4.21APB2 peripheral clock enable register (RCC_APB2ENR) . . . . .258
6.4.22AHB1 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB1SMENR) . . . . .		259
6.4.23AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR) . . . . .		261
6.4.24AHB3 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB3SMENR) . . . . .		263
6.4.25APB1 peripheral clocks enable in Sleep and Stop modes register 1
(RCC_APB1SMENR1) . . . . .		263
6.4.26APB1 peripheral clocks enable in Sleep and Stop modes register 2
(RCC_APB1SMENR2) . . . . .		266
6.4.27APB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_APB2SMENR) . . . . .		268
6.4.28Peripherals independent clock configuration register (RCC_CCIPR) . . . . .269
6.4.29Backup domain control register (RCC_BDCR) . . . . .272
6.4.30Control/status register (RCC_CSR) . . . . .274
6.4.31Clock recovery RC register (RCC_CRRRCR) . . . . .276
6.4.32Peripherals independent clock configuration register (RCC_CCIPR2) . . . . .277
6.4.33RCC register map . . . . .277
7Clock recovery system (CRS) . . . . .283
7.1CRS introduction . . . . .283
7.2CRS main features . . . . .283
7.3CRS implementation . . . . .283
7.4CRS functional description . . . . .284
7.4.1CRS block diagram . . . . .284
7.4.2Synchronization input . . . . .284
7.4.3Frequency error measurement . . . . .285
7.4.4Frequency error evaluation and automatic trimming . . . . .285
7.4.5CRS initialization and configuration . . . . .286
7.5CRS low-power modes . . . . .287
7.6CRS interrupts . . . . .287
7.7CRS registers . . . . .288
7.7.1CRS control register (CRS_CR) . . . . .288
7.7.2CRS configuration register (CRS_CFGR) . . . . .289
7.7.3CRS interrupt and status register (CRS_ISR) . . . . .290
7.7.4CRS interrupt flag clear register (CRS_ICR) . . . . .292
7.7.5CRS register map . . . . .292
8General-purpose I/Os (GPIO) . . . . .294
8.1Introduction . . . . .294
8.2GPIO main features . . . . .294
8.3GPIO implementation . . . . .294
8.4GPIO functional description . . . . .295
8.4.1General-purpose I/O (GPIO) . . . . .297
8.4.2I/O pin alternate function multiplexer and mapping . . . . .297
8.4.3I/O port control registers . . . . .298
8.4.4I/O port data registers . . . . .298
8.4.5I/O data bitwise handling . . . . .299
8.4.6GPIO locking mechanism . . . . .299
8.4.7I/O alternate function input/output . . . . .299
8.4.8External interrupt/wake-up lines . . . . .300
8.4.9Input configuration . . . . .300
8.4.10Output configuration . . . . .301
8.4.11Alternate function configuration . . . . .301
8.4.12Analog configuration . . . . .302
8.4.13Using the HSE or LSE oscillator pins as GPIOs . . . . .303
8.4.14Using the GPIO pins in the RTC supply domain . . . . .303
8.4.15Using PH3 as GPIO (only for STM32L49x/L4Ax devices) . . . . .303
8.5GPIO registers . . . . .304
8.5.1GPIO port mode register (GPIOx_MODER)
(x =A to I) . . . . .		304
8.5.2GPIO port output type register (GPIOx_OTYPER)
(x = A to I) . . . . .		304
8.5.3GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to I) . . . . .		305
8.5.4GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to I) . . . . .		305
8.5.5GPIO port input data register (GPIOx_IDR)
(x = A to I) . . . . .		306
8.5.6GPIO port output data register (GPIOx_ODR)
(x = A to I) . . . . .		306
8.5.7GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to I) . . . . .		307
8.5.8GPIO port configuration lock register (GPIOx_LCKR)
(x = A to I) . . . . .		307
8.5.9GPIO alternate function low register (GPIOx_AFRL)
(x = A to I) . . . . .		308
8.5.10GPIO alternate function high register (GPIOx_AFRH)
(x = A to I) . . . . .		309
8.5.11GPIO port bit reset register (GPIOx_BRR) (x = A to I) . . . . .310
8.5.12GPIO port analog switch control register (GPIOx_ASCR)(x = A to H) . . . . .311
8.5.13GPIO register map . . . . .312
9System configuration controller (SYSCFG) . . . . .314
9.1SYSCFG main features . . . . .314
9.2SYSCFG registers . . . . .314
9.2.1SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . .314
9.2.2SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . .315
9.2.3SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . .		317
9.2.4SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . .		318
9.2.5SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . .		319
9.2.6SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . .		321
9.2.7SYSCFG SRAM2 control and status register (SYSCFG_SCSR) . . . . .322
9.2.8SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . .322
9.2.9SYSCFG SRAM2 write protection register (SYSCFG_SWPR) . . . . .323
9.2.10SYSCFG SRAM2 key register (SYSCFG_SKR) . . . . .324
9.2.11SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2) . . . . .324
9.2.12SYSCFG register map . . . . .325
10Peripherals interconnect matrix . . . . .327
11.4.4DMA channels343
11.4.5DMA data width, alignment, and endianness347
11.4.6DMA error management348
11.5DMA interrupts349
11.6DMA registers349
11.6.1DMA interrupt status register (DMA_ISR)349
11.6.2DMA interrupt flag clear register (DMA_IFCR)352
11.6.3DMA channel x configuration register (DMA_CCRx)353
11.6.4DMA channel x number of data to transfer register (DMA_CNDTRx)356
11.6.5DMA channel x peripheral address register (DMA_CPARx)356
11.6.6DMA channel x memory address register (DMA_CMARx)357
11.6.7DMA channel selection register (DMA_CSELR)358
11.6.8DMA register map358
12Chrom-ART Accelerator controller (DMA2D)361
12.1DMA2D introduction361
12.2DMA2D main features361
12.3DMA2D functional description362
12.3.1DMA2D block diagram362
12.3.2DMA2D control363
12.3.3DMA2D foreground and background FIFOs363
12.3.4DMA2D foreground and background pixel format converter (PFC)364
12.3.5DMA2D foreground and background CLUT interface366
12.3.6DMA2D blender367
12.3.7DMA2D output PFC368
12.3.8DMA2D output FIFO368
12.3.9DMA2D AHB master port timer369
12.3.10DMA2D transactions369
12.3.11DMA2D configuration369
12.3.12DMA2D transfer control (start, suspend, abort and completion)372
12.3.13Watermark372
12.3.14Error management372
12.3.15AHB dead time372
12.4DMA2D interrupts373
12.5DMA2D registers373
12.5.1DMA2D control register (DMA2D_CR)373
12.5.2DMA2D interrupt status register (DMA2D_ISR) . . . . .375
12.5.3DMA2D interrupt flag clear register (DMA2D_IFCR) . . . . .376
12.5.4DMA2D foreground memory address register (DMA2D_FGMAR) . . .376
12.5.5DMA2D foreground offset register (DMA2D_FGOR) . . . . .377
12.5.6DMA2D background memory address register (DMA2D_BGMAR) . .377
12.5.7DMA2D background offset register (DMA2D_BGOR) . . . . .378
12.5.8DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . .378
12.5.9DMA2D foreground color register (DMA2D_FGCOLR) . . . . .380
12.5.10DMA2D background PFC control register (DMA2D_BGPFCCR) . . . . .380
12.5.11DMA2D background color register (DMA2D_BGCOLR) . . . . .382
12.5.12DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR) . . . . .		383
12.5.13DMA2D background CLUT memory address register
(DMA2D_BGCMAR) . . . . .		383
12.5.14DMA2D output PFC control register (DMA2D_OPFCCR) . . . . .384
12.5.15DMA2D output color register (DMA2D_OCOLR) . . . . .385
12.5.16DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .385
12.5.17DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .386
12.5.18DMA2D output color register [alternate] (DMA2D_OCOLR) . . . . .386
12.5.19DMA2D output memory address register (DMA2D_OMAR) . . . . .387
12.5.20DMA2D output offset register (DMA2D_OOR) . . . . .387
12.5.21DMA2D number of line register (DMA2D_NLR) . . . . .388
12.5.22DMA2D line watermark register (DMA2D_LWR) . . . . .388
12.5.23DMA2D AHB master timer configuration register (DMA2D_AMTCR) . .389
12.5.24DMA2D foreground CLUT (DMA2D_FGCLUTx) . . . . .389
12.5.25DMA2D background CLUT (DMA2D_BGCLUTx) . . . . .390
12.5.26DMA2D register map . . . . .390
13Nested vectored interrupt controller (NVIC) . . . . .392
13.1NVIC main features . . . . .392
13.2SysTick calibration value register . . . . .392
13.3Interrupt and exception vectors . . . . .393
14Extended interrupts and events controller (EXTI) . . . . .397
14.1Introduction . . . . .397
14.2EXTI main features . . . . .397
14.3EXTI functional description . . . . .397
14.3.1EXTI block diagram . . . . .398
14.3.2Wakeup event management . . . . .398
14.3.3Peripherals asynchronous Interrupts . . . . .399
14.3.4Hardware interrupt selection . . . . .399
14.3.5Hardware event selection . . . . .399
14.3.6Software interrupt/event selection . . . . .399
14.4EXTI interrupt/event line mapping . . . . .399
14.5EXTI registers . . . . .402
14.5.1Interrupt mask register 1 (EXTI_IMR1) . . . . .402
14.5.2Event mask register 1 (EXTI_EMR1) . . . . .402
14.5.3Rising trigger selection register 1 (EXTI_RTSR1) . . . . .402
14.5.4Falling trigger selection register 1 (EXTI_FTSR1) . . . . .403
14.5.5Software interrupt event register 1 (EXTI_SWIER1) . . . . .404
14.5.6Pending register 1 (EXTI_PR1) . . . . .405
14.5.7Interrupt mask register 2 (EXTI_IMR2) . . . . .405
14.5.8Event mask register 2 (EXTI_EMR2) . . . . .406
14.5.9Rising trigger selection register 2 (EXTI_RTSR2) . . . . .406
14.5.10Falling trigger selection register 2 (EXTI_FTSR2) . . . . .407
14.5.11Software interrupt event register 2 (EXTI_SWIER2) . . . . .407
14.5.12Pending register 2 (EXTI_PR2) . . . . .408
14.5.13EXTI register map . . . . .409
15Cyclic redundancy check calculation unit (CRC) . . . . .410
15.1Introduction . . . . .410
15.2CRC main features . . . . .410
15.3CRC functional description . . . . .411
15.3.1CRC block diagram . . . . .411
15.3.2CRC internal signals . . . . .411
15.3.3CRC operation . . . . .411
15.4CRC registers . . . . .413
15.4.1CRC data register (CRC_DR) . . . . .413
15.4.2CRC independent data register (CRC_IDR) . . . . .413
15.4.3CRC control register (CRC_CR) . . . . .414
15.4.4CRC initial value (CRC_INIT) . . . . .415
15.4.5CRC polynomial (CRC_POL) . . . . .415
15.4.6CRC register map . . . . .416

16 Flexible static memory controller (FSMC) . . . . . 417

16.1 Introduction . . . . . 417

16.2 FMC main features . . . . . 417

16.3 FMC block diagram . . . . . 418

16.4 AHB interface . . . . . 418

16.4.1 Supported memories and transactions . . . . . 419

16.5 External device address mapping . . . . . 420

16.5.1 NOR/PSRAM address mapping . . . . . 420

16.5.2 NAND flash memory address mapping . . . . . 421

16.6 NOR flash/PSRAM controller . . . . . 422

16.6.1 External memory interface signals . . . . . 423

16.6.2 Supported memories and transactions . . . . . 425

16.6.3 General timing rules . . . . . 426

16.6.4 NOR flash/PSRAM controller asynchronous transactions . . . . . 426

16.6.5 Synchronous transactions . . . . . 444

16.6.6 NOR/PSRAM controller registers . . . . . 450

16.7 NAND flash controller . . . . . 457

16.7.1 External memory interface signals . . . . . 457

16.7.2 NAND flash supported memories and transactions . . . . . 458

16.7.3 Timing diagrams for NAND flash memory . . . . . 459

16.7.4 NAND flash operations . . . . . 460

16.7.5 NAND flash prewait functionality . . . . . 460

16.7.6 Computation of the error correction code (ECC)
in NAND flash memory . . . . . 461

16.7.7 NAND flash controller registers . . . . . 462

16.7.8 FMC register map . . . . . 468

17 Quad-SPI interface (QUADSPI) . . . . . 470

17.1 Introduction . . . . . 470

17.2 QUADSPI main features . . . . . 470

17.3 QUADSPI implementation . . . . . 470

17.4 QUADSPI functional description . . . . . 471

17.4.1 QUADSPI block diagram . . . . . 471

17.4.2 QUADSPI pins . . . . . 471

17.4.3 QUADSPI command sequence . . . . . 472

17.4.4 QUADSPI signal interface protocol modes . . . . . 474

17.4.5QUADSPI indirect mode .....477
17.4.6QUADSPI automatic status-polling mode .....478
17.4.7QUADSPI memory-mapped mode .....479
17.4.8QUADSPI flash memory configuration .....479
17.4.9QUADSPI delayed data sampling .....480
17.4.10QUADSPI configuration .....480
17.4.11QUADSPI use .....481
17.4.12Sending the instruction only once .....482
17.4.13QUADSPI error management .....483
17.4.14QUADSPI busy bit and abort functionality .....483
17.4.15NCS behavior .....483
17.5QUADSPI interrupts .....485
17.6QUADSPI registers .....486
17.6.1QUADSPI control register (QUADSPI_CR) .....486
17.6.2QUADSPI device configuration register (QUADSPI_DCR) .....489
17.6.3QUADSPI status register (QUADSPI_SR) .....490
17.6.4QUADSPI flag clear register (QUADSPI_FCR) .....491
17.6.5QUADSPI data length register (QUADSPI_DLR) .....491
17.6.6QUADSPI communication configuration register (QUADSPI_CCR) ..492
17.6.7QUADSPI address register (QUADSPI_AR) .....494
17.6.8QUADSPI alternate-byte register (QUADSPI_ABR) .....494
17.6.9QUADSPI data register (QUADSPI_DR) .....495
17.6.10QUADSPI polling status mask register (QUADSPI_PSMKR) .....495
17.6.11QUADSPI polling status match register (QUADSPI_PSMAR) .....496
17.6.12QUADSPI polling interval register (QUADSPI_PIR) .....496
17.6.13QUADSPI low-power timeout register (QUADSPI_LPTR) .....497
17.6.14QUADSPI register map .....497
18Analog-to-digital converters (ADC) .....499
18.1Introduction .....499
18.2ADC main features .....500
18.3ADC implementation .....501
18.4ADC functional description .....502
18.4.1ADC block diagram .....502
18.4.2ADC pins and internal signals .....503
18.4.3ADC clocks .....504
18.4.4ADC1/2/3 connectivity . . . . .506
18.4.5Slave AHB interface . . . . .509
18.4.6ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator (ADVREGEN) . . . . .509
18.4.7Single-ended and differential input channels . . . . .510
18.4.8Calibration (ADCAL, ADCALDIF, ADC_CALFACT) . . . . .510
18.4.9ADC on-off control (ADEN, ADDIS, ADRDY) . . . . .513
18.4.10Constraints when writing the ADC control bits . . . . .514
18.4.11Channel selection (SQRx, JSQRx) . . . . .515
18.4.12Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . .516
18.4.13Single conversion mode (CONT = 0) . . . . .517
18.4.14Continuous conversion mode (CONT = 1) . . . . .517
18.4.15Starting conversions (ADSTART, JADSTART) . . . . .518
18.4.16ADC timing . . . . .519
18.4.17Stopping an ongoing conversion (ADSTP, JADSTP) . . . . .519
18.4.18Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . .521
18.4.19Injected channel management . . . . .523
18.4.20Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . .525
18.4.21Queue of context for injected conversions . . . . .526
18.4.22Programmable resolution (RES) - Fast conversion mode . . . . .534
18.4.23End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . . . .535
18.4.24End of conversion sequence (EOS, JEOS) . . . . .535
18.4.25Timing diagrams example (single/continuous modes, hardware/software triggers) . . . . .536
18.4.26Data management . . . . .538
18.4.27Managing conversions using the DFSDM . . . . .543
18.4.28Dynamic low-power features . . . . .544
18.4.29Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . .549
18.4.30Oversampler . . . . .553
18.4.31Dual ADC modes . . . . .559
18.4.32Temperature sensor . . . . .573
18.4.33VBAT supply monitoring . . . . .575
18.4.34Monitoring the internal voltage reference . . . . .575
18.5ADC in low-power mode . . . . .577
18.6ADC interrupts . . . . .578
18.7ADC registers (for each ADC) . . . . .579
18.7.1ADC interrupt and status register (ADC_ISR) . . . . .579
18.7.2ADC interrupt enable register (ADC_IER) . . . . .581
18.7.3ADC control register (ADC_CR) . . . . .583
18.7.4ADC configuration register (ADC_CFGR) . . . . .586
18.7.5ADC configuration register 2 (ADC_CFGR2) . . . . .590
18.7.6ADC sample time register 1 (ADC_SMPR1) . . . . .592
18.7.7ADC sample time register 2 (ADC_SMPR2) . . . . .593
18.7.8ADC watchdog threshold register 1 (ADC_TR1) . . . . .594
18.7.9ADC watchdog threshold register 2 (ADC_TR2) . . . . .595
18.7.10ADC watchdog threshold register 3 (ADC_TR3) . . . . .595
18.7.11ADC regular sequence register 1 (ADC_SQR1) . . . . .596
18.7.12ADC regular sequence register 2 (ADC_SQR2) . . . . .597
18.7.13ADC regular sequence register 3 (ADC_SQR3) . . . . .598
18.7.14ADC regular sequence register 4 (ADC_SQR4) . . . . .599
18.7.15ADC regular data register (ADC_DR) . . . . .600
18.7.16ADC injected sequence register (ADC_JSQR) . . . . .600
18.7.17ADC offset y register (ADC_OF Ry) . . . . .602
18.7.18ADC injected channel y data register (ADC_JDRy) . . . . .603
18.7.19ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . .603
18.7.20ADC analog watchdog 3 configuration register (ADC_AWD3CR) . . . . .604
18.7.21ADC differential mode selection register (ADC_DIFSEL) . . . . .604
18.7.22ADC calibration factors (ADC_CALFACT) . . . . .605
18.8ADC common registers . . . . .605
18.8.1ADC common status register (ADC_CSR) . . . . .605
18.8.2ADC common control register (ADC_CCR) . . . . .607
18.8.3ADC common regular data register for dual mode (ADC_CDR) . . . . .610
18.9ADC register map . . . . .610
19Digital-to-analog converter (DAC) . . . . .614
19.1Introduction . . . . .614
19.2DAC main features . . . . .614
19.3DAC implementation . . . . .615
19.4DAC functional description . . . . .616
19.4.1DAC block diagram . . . . .616
19.4.2DAC channel enable . . . . .617
19.4.3DAC data format . . . . .617
19.7.18DAC channel2 sample and hold sample time register (DAC_SHSR2) . . . . .646
19.7.19DAC sample and hold time register (DAC_SHHR) . . . . .647
19.7.20DAC sample and hold refresh time register (DAC_SHRR) . . . . .647
19.7.21DAC register map . . . . .648
20Digital camera interface (DCMI) . . . . .650
20.1Introduction . . . . .650
20.2DCMI main features . . . . .650
20.3DCMI functional description . . . . .650
20.3.1DCMI block diagram . . . . .651
20.3.2DCMI pins . . . . .651
20.3.3DCMI clocks . . . . .651
20.3.4DCMI DMA interface . . . . .652
20.3.5DCMI physical interface . . . . .652
20.3.6DCMI synchronization . . . . .654
20.3.7DCMI capture modes . . . . .656
20.3.8DCMI crop feature . . . . .657
20.3.9DCMI JPEG format . . . . .658
20.3.10DCMI FIFO . . . . .658
20.3.11DCMI data format description . . . . .659
20.4DCMI interrupts . . . . .661
20.5DCMI registers . . . . .661
20.5.1DCMI control register (DCMI_CR) . . . . .661
20.5.2DCMI status register (DCMI_SR) . . . . .664
20.5.3DCMI raw interrupt status register (DCMI_RIS) . . . . .664
20.5.4DCMI interrupt enable register (DCMI_IER) . . . . .665
20.5.5DCMI masked interrupt status register (DCMI_MIS) . . . . .666
20.5.6DCMI interrupt clear register (DCMI_ICR) . . . . .667
20.5.7DCMI embedded synchronization code register (DCMI_ESCR) . . . . .668
20.5.8DCMI embedded synchronization unmask register (DCMI_ESUR) . . . . .669
20.5.9DCMI crop window start (DCMI_CWSTRT) . . . . .669
20.5.10DCMI crop window size (DCMI_CWSIZE) . . . . .670
20.5.11DCMI data register (DCMI_DR) . . . . .670
20.5.12DCMI register map . . . . .671
21Voltage reference buffer (VREFBUF) . . . . .673
23.4OPAMP low-power modes . . . . .695
23.5OPAMP registers . . . . .696
23.5.1OPAMP1 control/status register (OPAMP1_CSR) . . . . .696
23.5.2OPAMP1 offset trimming register in normal mode (OPAMP1_OTR) . . . . .697
23.5.3OPAMP1 offset trimming register in low-power mode
(OPAMP1_LPOTR) . . . . .		697
23.5.4OPAMP2 control/status register (OPAMP2_CSR) . . . . .698
23.5.5OPAMP2 offset trimming register in normal mode (OPAMP2_OTR) . . . . .699
23.5.6OPAMP2 offset trimming register in low-power mode
(OPAMP2_LPOTR) . . . . .		699
23.5.7OPAMP register map . . . . .700
24Digital filter for sigma delta modulators (DFSDM) . . . . .701
24.1Introduction . . . . .701
24.2DFSDM main features . . . . .702
24.3DFSDM implementation . . . . .703
24.4DFSDM functional description . . . . .704
24.4.1DFSDM block diagram . . . . .704
24.4.2DFSDM pins and internal signals . . . . .705
24.4.3DFSDM reset and clocks . . . . .706
24.4.4Serial channel transceivers . . . . .707
24.4.5Configuring the input serial interface . . . . .717
24.4.6Parallel data inputs . . . . .717
24.4.7Channel selection . . . . .719
24.4.8Digital filter configuration . . . . .720
24.4.9Integrator unit . . . . .721
24.4.10Analog watchdog . . . . .722
24.4.11Short-circuit detector . . . . .724
24.4.12Extreme detector . . . . .725
24.4.13Data unit block . . . . .725
24.4.14Signed data format . . . . .726
24.4.15Launching conversions . . . . .727
24.4.16Continuous and fast continuous modes . . . . .728
24.4.17Request precedence . . . . .728
24.4.18Power optimization in run mode . . . . .729
24.5DFSDM interrupts . . . . .729
24.6DFSDM DMA transfer . . . . .731
24.7DFSDM channel y registers (y=0..7) . . . . .731
24.7.1DFSDM channel y configuration register (DFSDM_CHyCFGR1) . . . . .731
24.7.2DFSDM channel y configuration register (DFSDM_CHyCFGR2) . . . . .734
24.7.3DFSDM channel y analog watchdog and short-circuit detector register (DFSDM_CHyAWSCDR) . . . . .734
24.7.4DFSDM channel y watchdog filter data register (DFSDM_CHyWDATR) . . . . .735
24.7.5DFSDM channel y data input register (DFSDM_CHyDATINR) . . . . .736
24.8DFSDM filter x module registers (x=0..3) . . . . .737
24.8.1DFSDM filter x control register 1 (DFSDM_FLTxCR1) . . . . .738
24.8.2DFSDM filter x control register 2 (DFSDM_FLTxCR2) . . . . .740
24.8.3DFSDM filter x interrupt and status register (DFSDM_FLTxISR) . . . . .742
24.8.4DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) . . . . .743
24.8.5DFSDM filter x injected channel group selection register (DFSDM_FLTxJCHGR) . . . . .744
24.8.6DFSDM filter x control register (DFSDM_FLTxFCR) . . . . .745
24.8.7DFSDM filter x data register for injected group (DFSDM_FLTxJDATAR) . . . . .746
24.8.8DFSDM filter x data register for the regular channel (DFSDM_FLTxRDATAR) . . . . .746
24.8.9DFSDM filter x analog watchdog high threshold register (DFSDM_FLTxAWHTR) . . . . .747
24.8.10DFSDM filter x analog watchdog low threshold register (DFSDM_FLTxAWLTR) . . . . .748
24.8.11DFSDM filter x analog watchdog status register (DFSDM_FLTxAWSR) . . . . .748
24.8.12DFSDM filter x analog watchdog clear flag register (DFSDM_FLTxAWCFR) . . . . .749
24.8.13DFSDM filter x extremes detector maximum register (DFSDM_FLTxEXMAX) . . . . .749
24.8.14DFSDM filter x extremes detector minimum register (DFSDM_FLTxEXMIN) . . . . .750
24.8.15DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR) . . . . .750
24.8.16DFSDM register map . . . . .751
25Liquid crystal display controller (LCD) . . . . .761
25.1LCD introduction . . . . .761
25.2LCD main features . . . . .761
25.3LCD functional description . . . . .763
25.3.1General description . . . . .763
25.3.2Frequency generator . . . . .764
25.3.3Common driver . . . . .765
25.3.4Segment driver . . . . .768
25.3.5Voltage generator and contrast control . . . . .772
25.3.6Double-buffer memory . . . . .775
25.3.7COM and SEG multiplexing . . . . .775
25.3.8Flowchart . . . . .781
25.4LCD low-power modes . . . . .782
25.5LCD interrupts . . . . .782
25.6LCD registers . . . . .783
25.6.1LCD control register (LCD_CR) . . . . .783
25.6.2LCD frame control register (LCD_FCR) . . . . .784
25.6.3LCD status register (LCD_SR) . . . . .786
25.6.4LCD clear register (LCD_CLR) . . . . .788
25.6.5LCD display memory (LCD_RAMx) . . . . .788
25.6.6LCD display memory (LCD_RAMx) . . . . .789
25.6.7LCD display memory (LCD_RAMx) . . . . .789
25.6.8LCD register map . . . . .789
26Touch sensing controller (TSC) . . . . .792
26.1Introduction . . . . .792
26.2TSC main features . . . . .792
26.3TSC functional description . . . . .793
26.3.1TSC block diagram . . . . .793
26.3.2Surface charge transfer acquisition overview . . . . .793
26.3.3Reset and clocks . . . . .796
26.3.4Charge transfer acquisition sequence . . . . .796
26.3.5Spread spectrum feature . . . . .798
26.3.6Max count error . . . . .798
26.3.7Sampling capacitor I/O and channel I/O mode selection . . . . .799
26.3.8Acquisition mode . . . . .800
26.3.9I/O hysteresis and analog switch control . . . . .800
26.4TSC low-power modes . . . . .801
26.5TSC interrupts . . . . .801
26.6TSC registers . . . . .801
26.6.1TSC control register (TSC_CR) . . . . .801

27 True random number generator (RNG) . . . . . 811

28 AES hardware accelerator (AES) . . . . . 821

28.1Introduction . . . . .821
28.2AES main features . . . . .821
28.3AES implementation . . . . .822
28.4AES functional description . . . . .822
28.4.1AES block diagram . . . . .822
28.4.2AES internal signals . . . . .822
28.4.3AES cryptographic core . . . . .823
28.4.4AES procedure to perform a cipher operation . . . . .828
28.4.5AES decryption key preparation . . . . .832
28.4.6AES ciphertext stealing and data padding . . . . .833
28.4.7AES task suspend and resume . . . . .834
28.4.8AES basic chaining modes (ECB, CBC) . . . . .835
28.4.9AES counter (CTR) mode . . . . .840
28.4.10AES Galois/counter mode (GCM) . . . . .842
28.4.11AES Galois message authentication code (GMAC) . . . . .847
28.4.12AES counter with CBC-MAC (CCM) . . . . .849
28.4.13AES data registers and data swapping . . . . .854
28.4.14AES key registers . . . . .856
28.4.15AES initialization vector registers . . . . .856
28.4.16AES DMA interface . . . . .856
28.4.17AES error management . . . . .859
28.5AES interrupts . . . . .859
28.6AES processing latency . . . . .860
28.7AES registers . . . . .861
28.7.1AES control register (AES_CR) . . . . .861
28.7.2AES status register (AES_SR) . . . . .864
28.7.3AES data input register (AES_DINR) . . . . .865
28.7.4AES data output register (AES_DOUTR) . . . . .866
28.7.5AES key register 0 (AES_KEYR0) . . . . .866
28.7.6AES key register 1 (AES_KEYR1) . . . . .867
28.7.7AES key register 2 (AES_KEYR2) . . . . .867
28.7.8AES key register 3 (AES_KEYR3) . . . . .868
28.7.9AES initialization vector register 0 (AES_IVR0) . . . . .868
28.7.10AES initialization vector register 1 (AES_IVR1) . . . . .868
28.7.11AES initialization vector register 2 (AES_IVR2) . . . . .869
28.7.12AES initialization vector register 3 (AES_IVR3) . . . . .869

29 Hash processor (HASH) . . . . . 874

30 Advanced-control timers (TIM1/TIM8) . . . . . 896

30.2TIM1/TIM8 main features . . . . .896
30.3TIM1/TIM8 functional description . . . . .898
30.3.1Time-base unit . . . . .898
30.3.2Counter modes . . . . .900
30.3.3Repetition counter . . . . .911
30.3.4External trigger input . . . . .913
30.3.5Clock selection . . . . .915
30.3.6Capture/compare channels . . . . .919
30.3.7Input capture mode . . . . .922
30.3.8PWM input mode . . . . .923
30.3.9Forced output mode . . . . .923
30.3.10Output compare mode . . . . .924
30.3.11PWM mode . . . . .925
30.3.12Asymmetric PWM mode . . . . .928
30.3.13Combined PWM mode . . . . .929
30.3.14Combined 3-phase PWM mode . . . . .930
30.3.15Complementary outputs and dead-time insertion . . . . .931
30.3.16Using the break function . . . . .933
30.3.17Bidirectional break inputs . . . . .939
30.3.18Clearing the OCxREF signal on an external event . . . . .940
30.3.196-step PWM generation . . . . .941
30.3.20One-pulse mode . . . . .942
30.3.21Retriggerable one pulse mode . . . . .943
30.3.22Encoder interface mode . . . . .944
30.3.23UIF bit remapping . . . . .946
30.3.24Timer input XOR function . . . . .947
30.3.25Interfacing with Hall sensors . . . . .947
30.3.26Timer synchronization . . . . .950
30.3.27ADC synchronization . . . . .954
30.3.28DMA burst mode . . . . .954
30.3.29Debug mode . . . . .955
30.4TIM1/TIM8 registers . . . . .956
30.4.1TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . .956
30.4.2TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . .957
30.4.3TIMx slave mode control register
(TIMx_SMCR)(x = 1, 8) . . . . .		960

30.4.4 TIMx DMA/interrupt enable register
(TIMx_DIER)(x = 1, 8) . . . . . 962

30.4.5 TIMx status register (TIMx_SR)(x = 1, 8) . . . . . 964

30.4.6 TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . . 966

30.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 1, 8) . . . 967

30.4.8 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . . 968

30.4.9 TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 1, 8) . . . 971

30.4.10 TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . . 972

30.4.11 TIMx capture/compare enable register
(TIMx_CCER)(x = 1, 8) . . . . . 974

30.4.12 TIMx counter (TIMx_CNT)(x = 1, 8) . . . . . 977

30.4.13 TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . . 977

30.4.14 TIMx auto-reload register (TIMx_ARR)(x = 1, 8) . . . . . 977

30.4.15 TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . . 978

30.4.16 TIMx capture/compare register 1
(TIMx_CCR1)(x = 1, 8) . . . . . 978

30.4.17 TIMx capture/compare register 2
(TIMx_CCR2)(x = 1, 8) . . . . . 979

30.4.18 TIMx capture/compare register 3
(TIMx_CCR3)(x = 1, 8) . . . . . 979

30.4.19 TIMx capture/compare register 4
(TIMx_CCR4)(x = 1, 8) . . . . . 980

30.4.20 TIMx break and dead-time register
(TIMx_BDTR)(x = 1, 8) . . . . . 980

30.4.21 TIMx DMA control register
(TIMx_DCR)(x = 1, 8) . . . . . 983

30.4.22 TIMx DMA address for full transfer
(TIMx_DMAR)(x = 1, 8) . . . . . 984

30.4.23 TIM1 option register 1 (TIM1_OR1) . . . . . 985

30.4.24 TIM8 option register 1 (TIM8_OR1) . . . . . 986

30.4.25 TIMx capture/compare mode register 3
(TIMx_CCMR3)(x = 1, 8) . . . . . 986

30.4.26 TIMx capture/compare register 5
(TIMx_CCR5)(x = 1, 8) . . . . . 987

30.4.27 TIMx capture/compare register 6
(TIMx_CCR6)(x = 1, 8) . . . . . 988

30.4.28 TIM1 option register 2 (TIM1_OR2) . . . . . 989

30.4.29 TIM1 option register 3 (TIM1_OR3) . . . . . 990

30.4.30 TIM8 option register 2 (TIM8_OR2) . . . . . 992

30.4.31TIM8 option register 3 (TIM8_OR3) . . . . .994
30.4.32TIM1 register map . . . . .996
30.4.33TIM8 register map . . . . .998
31General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . .1001
31.1TIM2/TIM3/TIM4/TIM5 introduction . . . . .1001
31.2TIM2/TIM3/TIM4/TIM5 main features . . . . .1001
31.3TIM2/TIM3/TIM4/TIM5 functional description . . . . .1003
31.3.1Time-base unit . . . . .1003
31.3.2Counter modes . . . . .1005
31.3.3Clock selection . . . . .1015
31.3.4Capture/Compare channels . . . . .1019
31.3.5Input capture mode . . . . .1021
31.3.6PWM input mode . . . . .1022
31.3.7Forced output mode . . . . .1023
31.3.8Output compare mode . . . . .1024
31.3.9PWM mode . . . . .1025
31.3.10Asymmetric PWM mode . . . . .1028
31.3.11Combined PWM mode . . . . .1029
31.3.12Clearing the OCxREF signal on an external event . . . . .1030
31.3.13One-pulse mode . . . . .1032
31.3.14Retriggerable one pulse mode . . . . .1033
31.3.15Encoder interface mode . . . . .1034
31.3.16UIF bit remapping . . . . .1036
31.3.17Timer input XOR function . . . . .1036
31.3.18Timers and external trigger synchronization . . . . .1037
31.3.19Timer synchronization . . . . .1040
31.3.20DMA burst mode . . . . .1045
31.3.21Debug mode . . . . .1046
31.4TIM2/TIM3/TIM4/TIM5 registers . . . . .1047
31.4.1TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . .1047
31.4.2TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . .1048
31.4.3TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . .1050
31.4.4TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . .1053
31.4.5TIMx status register (TIMx_SR)(x = 2 to 5) . . . . .1054
31.4.6TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . .1055
31.4.7TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 2 to 5) . . . . .1056

31.4.8 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 5) . . . . . 1058

31.4.9 TIMx capture/compare mode register 2 (TIMx_CCMR2)(x = 2 to 5) . 1060

31.4.10 TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 5) . . . . . 1061

31.4.11 TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 5) . . . . . 1062

31.4.12 TIMx counter (TIMx_CNT)(x = 2 to 5) . . . . . 1063

31.4.13 TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) . . . . . 1064

31.4.14 TIMx prescaler (TIMx_PSC)(x = 2 to 5) . . . . . 1064

31.4.15 TIMx auto-reload register (TIMx_ARR)(x = 2 to 5) . . . . . 1065

31.4.16 TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) . . . . . 1065

31.4.17 TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) . . . . . 1066

31.4.18 TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5) . . . . . 1066

31.4.19 TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5) . . . . . 1067

31.4.20 TIMx DMA control register (TIMx_DCR)(x = 2 to 5) . . . . . 1068

31.4.21 TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) . . . . . 1068

31.4.22 TIM2 option register 1 (TIM2_OR1) . . . . . 1068

31.4.23 TIM3 option register 1 (TIM3_OR1) . . . . . 1069

31.4.24 TIM2 option register 2 (TIM2_OR2) . . . . . 1069

31.4.25 TIM3 option register 2 (TIM3_OR2) . . . . . 1070

31.4.26 TIMx register map . . . . . 1071

32 General-purpose timers (TIM15/TIM16/TIM17) . . . . . 1074

32.1 TIM15/TIM16/TIM17 introduction . . . . . 1074

32.2 TIM15 main features . . . . . 1074

32.3 TIM16/TIM17 main features . . . . . 1075

32.4 Implementation . . . . . 1077

32.5 TIM15/TIM16/TIM17 functional description . . . . . 1078

32.5.1 Time-base unit . . . . . 1078

32.5.2 Counter modes . . . . . 1080

32.5.3 Repetition counter . . . . . 1084

32.5.4 Clock selection . . . . . 1085

32.5.5 Capture/compare channels . . . . . 1087

32.5.6 Input capture mode . . . . . 1089

32.5.7 PWM input mode (only for TIM15) . . . . . 1090

32.5.8 Forced output mode . . . . . 1091

32.5.9Output compare mode . . . . .1092
32.5.10PWM mode . . . . .1093
32.5.11Combined PWM mode (TIM15 only) . . . . .1094
32.5.12Complementary outputs and dead-time insertion . . . . .1095
32.5.13Using the break function . . . . .1097
32.5.146-step PWM generation . . . . .1102
32.5.15One-pulse mode . . . . .1103
32.5.16Retriggerable one pulse mode (TIM15 only) . . . . .1104
32.5.17UIF bit remapping . . . . .1105
32.5.18Timer input XOR function (TIM15 only) . . . . .1106
32.5.19External trigger synchronization (TIM15 only) . . . . .1107
32.5.20Slave mode – combined reset + trigger mode . . . . .1109
32.5.21DMA burst mode . . . . .1109
32.5.22Timer synchronization (TIM15) . . . . .1111
32.5.23Using timer output as trigger for other timers (TIM16/TIM17) . . . . .1111
32.5.24Debug mode . . . . .1111
32.6TIM15 registers . . . . .1112
32.6.1TIM15 control register 1 (TIM15_CR1) . . . . .1112
32.6.2TIM15 control register 2 (TIM15_CR2) . . . . .1113
32.6.3TIM15 slave mode control register (TIM15_SMCR) . . . . .1115
32.6.4TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . .1116
32.6.5TIM15 status register (TIM15_SR) . . . . .1117
32.6.6TIM15 event generation register (TIM15_EGR) . . . . .1119
32.6.7TIM15 capture/compare mode register 1 (TIM15_CCMR1) . . . . .1120
32.6.8TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . .		1121
32.6.9TIM15 capture/compare enable register (TIM15_CCER) . . . . .1124
32.6.10TIM15 counter (TIM15_CNT) . . . . .1127
32.6.11TIM15 prescaler (TIM15_PSC) . . . . .1127
32.6.12TIM15 auto-reload register (TIM15_ARR) . . . . .1127
32.6.13TIM15 repetition counter register (TIM15_RCR) . . . . .1128
32.6.14TIM15 capture/compare register 1 (TIM15_CCR1) . . . . .1128
32.6.15TIM15 capture/compare register 2 (TIM15_CCR2) . . . . .1129
32.6.16TIM15 break and dead-time register (TIM15_BDTR) . . . . .1129
32.6.17TIM15 DMA control register (TIM15_DCR) . . . . .1131
32.6.18TIM15 DMA address for full transfer (TIM15_DMAR) . . . . .1132
32.6.19TIM15 option register 1 (TIM15_OR1) . . . . .1132
32.6.20TIM15 option register 2 (TIM15_OR2) . . . . .1133
32.6.21TIM15 register map . . . . .1134
32.7TIM16/TIM17 registers . . . . .1137
32.7.1TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . .1137
32.7.2TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . .1138
32.7.3TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . .1139
32.7.4TIMx status register (TIMx_SR)(x = 16 to 17) . . . . .1140
32.7.5TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . .1141
32.7.6TIMx capture/compare mode register 1
(TIMx_CCMR1)(x = 16 to 17) . . . . .		1142
32.7.7TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 16 to 17) . . . . .		1143
32.7.8TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . . . . .1145
32.7.9TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . .1147
32.7.10TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . .1148
32.7.11TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . .1148
32.7.12TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . .1149
32.7.13TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . .1149
32.7.14TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . .1150
32.7.15TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . .1152
32.7.16TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . .1152
32.7.17TIM16 option register 1 (TIM16_OR1) . . . . .1153
32.7.18TIM16 option register 2 (TIM16_OR2) . . . . .1153
32.7.19TIM17 option register 1 (TIM17_OR1) . . . . .1155
32.7.20TIM17 option register 2 (TIM17_OR2) . . . . .1155
32.7.21TIM16/TIM17 register map . . . . .1158
33Basic timers (TIM6/TIM7) . . . . .1160
33.1TIM6/TIM7 introduction . . . . .1160
33.2TIM6/TIM7 main features . . . . .1160
33.3TIM6/TIM7 functional description . . . . .1161
33.3.1Time-base unit . . . . .1161
33.3.2Counting mode . . . . .1163
33.3.3UIF bit remapping . . . . .1166
33.3.4Clock source . . . . .1166
33.3.5Debug mode . . . . .1167
33.4TIM6/TIM7 registers . . . . .1167
33.4.1TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . .1167
33.4.2TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . .1169
33.4.3TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . .1169
33.4.4TIMx status register (TIMx_SR)(x = 6 to 7) . . . . .1170
33.4.5TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . .1170
33.4.6TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . .1170
33.4.7TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . .1171
33.4.8TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . .1171
33.4.9TIMx register map . . . . .1172
34Low-power timer (LPTIM) . . . . .1173
34.1Introduction . . . . .1173
34.2LPTIM main features . . . . .1173
34.3LPTIM implementation . . . . .1174
34.4LPTIM functional description . . . . .1174
34.4.1LPTIM block diagram . . . . .1174
34.4.2LPTIM trigger mapping . . . . .1175
34.4.3LPTIM reset and clocks . . . . .1175
34.4.4Glitch filter . . . . .1176
34.4.5Prescaler . . . . .1177
34.4.6Trigger multiplexer . . . . .1177
34.4.7Operating mode . . . . .1178
34.4.8Timeout function . . . . .1179
34.4.9Waveform generation . . . . .1179
34.4.10Register update . . . . .1181
34.4.11Counter mode . . . . .1181
34.4.12Timer enable . . . . .1182
34.4.13Encoder mode . . . . .1182
34.4.14Debug mode . . . . .1183
34.5LPTIM low-power modes . . . . .1184
34.6LPTIM interrupts . . . . .1184
34.7LPTIM registers . . . . .1185
34.7.1LPTIM interrupt and status register (LPTIM_ISR) . . . . .1185
34.7.2LPTIM interrupt clear register (LPTIM_ICR) . . . . .1186
34.7.3LPTIM interrupt enable register (LPTIM_IER) . . . . .1187
34.7.4LPTIM configuration register (LPTIM_CFGR) . . . . .1188
34.7.5LPTIM control register (LPTIM_CR) . . . . .1190
34.7.6LPTIM compare register (LPTIM_CMP) . . . . .1191
34.7.7LPTIM autoreload register (LPTIM_ARR) . . . . .1192
34.7.8LPTIM counter register (LPTIM_CNT) . . . . .1192
34.7.9LPTIM1 option register (LPTIM1_OR) . . . . .1193
34.7.10LPTIM2 option register (LPTIM2_OR) . . . . .1193
34.7.11LPTIM register map . . . . .1194
35Infrared interface (IRTIM) . . . . .1195
36Independent watchdog (IWDG) . . . . .1196
36.1Introduction . . . . .1196
36.2IWDG main features . . . . .1196
36.3IWDG functional description . . . . .1196
36.3.1IWDG block diagram . . . . .1196
36.3.2Window option . . . . .1197
36.3.3Hardware watchdog . . . . .1198
36.3.4Low-power freeze . . . . .1198
36.3.5Register access protection . . . . .1198
36.3.6Debug mode . . . . .1198
36.4IWDG registers . . . . .1199
36.4.1IWDG key register (IWDG_KR) . . . . .1199
36.4.2IWDG prescaler register (IWDG_PR) . . . . .1200
36.4.3IWDG reload register (IWDG_RLR) . . . . .1201
36.4.4IWDG status register (IWDG_SR) . . . . .1202
36.4.5IWDG window register (IWDG_WINR) . . . . .1203
36.4.6IWDG register map . . . . .1204
37System window watchdog (WWDG) . . . . .1205
37.1Introduction . . . . .1205
37.2WWDG main features . . . . .1205
37.3WWDG functional description . . . . .1205
37.3.1WWDG block diagram . . . . .1206
37.3.2Enabling the watchdog . . . . .1206
37.3.3Controlling the down-counter . . . . .1206
37.3.4How to program the watchdog timeout . . . . .1206
37.3.5Debug mode . . . . .1207
37.4WWDG interrupts . . . . .1208
37.5WWDG registers . . . . .1208
37.5.1WWDG control register (WWDG_CR) . . . . .1208
37.5.2WWDG configuration register (WWDG_CFR) . . . . .1209
37.5.3WWDG status register (WWDG_SR) . . . . .1209
37.5.4WWDG register map . . . . .1210
38Real-time clock (RTC) . . . . .1211
38.1Introduction . . . . .1211
38.2RTC main features . . . . .1212
38.3RTC functional description . . . . .1213
38.3.1RTC block diagram . . . . .1213
38.3.2GPIOs controlled by the RTC . . . . .1214
38.3.3Clock and prescalers . . . . .1216
38.3.4Real-time clock and calendar . . . . .1217
38.3.5Programmable alarms . . . . .1217
38.3.6Periodic auto-wake-up . . . . .1217
38.3.7RTC initialization and configuration . . . . .1218
38.3.8Reading the calendar . . . . .1220
38.3.9Resetting the RTC . . . . .1221
38.3.10RTC synchronization . . . . .1221
38.3.11RTC reference clock detection . . . . .1222
38.3.12RTC smooth digital calibration . . . . .1222
38.3.13Time-stamp function . . . . .1224
38.3.14Tamper detection . . . . .1225
38.3.15Calibration clock output . . . . .1227
38.3.16Alarm output . . . . .1228
38.4RTC low-power modes . . . . .1228
38.5RTC interrupts . . . . .1228
38.6RTC registers . . . . .1229
38.6.1RTC time register (RTC_TR) . . . . .1229
38.6.2RTC date register (RTC_DR) . . . . .1230
38.6.3RTC control register (RTC_CR) . . . . .1232
38.6.4RTC initialization and status register (RTC_ISR) . . . . .1235
38.6.5RTC prescaler register (RTC_PRER) . . . . .1238
38.6.6RTC wake-up timer register (RTC_WUTR) . . . . .1239
38.6.7RTC alarm A register (RTC_ALRMAR) . . . . .1240
38.6.8RTC alarm B register (RTC_ALRMBR) . . . . .1241
38.6.9RTC write protection register (RTC_WPR) . . . . .1242
38.6.10RTC sub second register (RTC_SSR) . . . . .1242
38.6.11RTC shift control register (RTC_SHIFTR) . . . . .1243
38.6.12RTC timestamp time register (RTC_TSTR) . . . . .1244
38.6.13RTC timestamp date register (RTC_TSDR) . . . . .1245
38.6.14RTC time-stamp sub second register (RTC_TSSSR) . . . . .1246
38.6.15RTC calibration register (RTC_CALR) . . . . .1247
38.6.16RTC tamper configuration register (RTC_TAMPCR) . . . . .1248
38.6.17RTC alarm A sub second register (RTC_ALRMASSR) . . . . .1251
38.6.18RTC alarm B sub second register (RTC_ALRMBSSR) . . . . .1252
38.6.19RTC option register (RTC_OR) . . . . .1253
38.6.20RTC backup registers (RTC_BKPxR) . . . . .1253
38.6.21RTC register map . . . . .1254
39Inter-integrated circuit (I2C) interface . . . . .1256
39.1Introduction . . . . .1256
39.2I2C main features . . . . .1256
39.3I2C implementation . . . . .1257
39.4I2C functional description . . . . .1257
39.4.1I2C block diagram . . . . .1258
39.4.2I2C pins and internal signals . . . . .1259
39.4.3I2C clock requirements . . . . .1259
39.4.4Mode selection . . . . .1259
39.4.5I2C initialization . . . . .1260
39.4.6I2C reset . . . . .1264
39.4.7Data transfer . . . . .1265
39.4.8I2C slave mode . . . . .1267
39.4.9I2C master mode . . . . .1276
39.4.10I2C_TIMINGR register configuration examples . . . . .1287
39.4.11SMBus specific features . . . . .1289
39.4.12SMBus initialization . . . . .1292
39.4.13SMBus I2C_TIMEOUTR register configuration examples . . . . .1294
39.4.14SMBus slave mode . . . . .1294
39.4.15SMBus master mode . . . . .1298
39.4.16Wake-up from Stop mode on address match . . . . .1301
39.4.17Error conditions . . . . .1302
39.5I2C in low-power modes . . . . .1304
39.6I2C interrupts . . . . .1304
39.7I2C DMA requests . . . . .1305
39.8I2C debug modes . . . . .1306
39.9I2C registers . . . . .1306
39.9.1I2C control register 1 (I2C_CR1) . . . . .1306
39.9.2I2C control register 2 (I2C_CR2) . . . . .1308
39.9.3I2C own address 1 register (I2C_OAR1) . . . . .1310
39.9.4I2C own address 2 register (I2C_OAR2) . . . . .1311
39.9.5I2C timing register (I2C_TIMINGR) . . . . .1312
39.9.6I2C timeout register (I2C_TIMEOUTR) . . . . .1313
39.9.7I2C interrupt and status register (I2C_ISR) . . . . .1314
39.9.8I2C interrupt clear register (I2C_ICR) . . . . .1316
39.9.9I2C PEC register (I2C_PECR) . . . . .1317
39.9.10I2C receive data register (I2C_RXDR) . . . . .1318
39.9.11I2C transmit data register (I2C_TXDR) . . . . .1318
39.9.12I2C register map . . . . .1319
40Universal synchronous/asynchronous receiver
transmitter (USART/UART) . . . . .		1321
40.1Introduction . . . . .1321
40.2USART main features . . . . .1321
40.3USART extended features . . . . .1322
40.4USART implementation . . . . .1323
40.5USART functional description . . . . .1323
40.5.1USART character description . . . . .1326
40.5.2USART transmitter . . . . .1328
40.5.3USART receiver . . . . .1330
40.5.4USART baud rate generation . . . . .1337
40.5.5Tolerance of the USART receiver to clock deviation . . . . .1339
40.5.6USART auto baud rate detection . . . . .1340
40.5.7Multiprocessor communication using USART . . . . .1341
40.5.8Modbus communication using USART . . . . .1343
40.5.9USART parity control . . . . .1344
40.5.10USART LIN (local interconnection network) mode . . . . .1345

41 Low-power universal asynchronous receiver
transmitter (LPUART) . . . . . 1390

41.4.8Single-wire half-duplex communication using LPUART . . . . .1407
41.4.9Continuous communication in DMA mode using LPUART . . . . .1407
41.4.10RS232 hardware flow control and RS485 Driver Enable
using LPUART . . . . .		1410
41.4.11Wake-up from Stop mode using LPUART . . . . .1413
41.5LPUART in low-power mode . . . . .1414
41.6LPUART interrupts . . . . .1415
41.7LPUART registers . . . . .1417
41.7.1Control register 1 (LPUART_CR1) . . . . .1417
41.7.2Control register 2 (LPUART_CR2) . . . . .1420
41.7.3Control register 3 (LPUART_CR3) . . . . .1422
41.7.4Baud rate register (LPUART_BRR) . . . . .1424
41.7.5Request register (LPUART_RQR) . . . . .1424
41.7.6Interrupt & status register (LPUART_ISR) . . . . .1425
41.7.7Interrupt flag clear register (LPUART_ICR) . . . . .1428
41.7.8Receive data register (LPUART_RDR) . . . . .1429
41.7.9Transmit data register (LPUART_TDR) . . . . .1429
41.7.10LPUART register map . . . . .1431
42Serial peripheral interface (SPI) . . . . .1432
42.1Introduction . . . . .1432
42.2SPI main features . . . . .1432
42.3SPI implementation . . . . .1433
42.4SPI functional description . . . . .1433
42.4.1General description . . . . .1433
42.4.2Communications between one master and one slave . . . . .1434
42.4.3Standard multislave communication . . . . .1436
42.4.4Multimaster communication . . . . .1437
42.4.5Slave select (NSS) pin management . . . . .1438
42.4.6Communication formats . . . . .1439
42.4.7Configuration of SPI . . . . .1441
42.4.8Procedure for enabling SPI . . . . .1442
42.4.9Data transmission and reception procedures . . . . .1442
42.4.10SPI status flags . . . . .1452
42.4.11SPI error flags . . . . .1453
42.4.12NSS pulse mode . . . . .1454
42.4.13TI mode . . . . .1454
42.4.14CRC calculation . . . . .1455
42.5SPI interrupts . . . . .1457
42.6SPI registers . . . . .1458
42.6.1SPI control register 1 (SPIx_CR1) . . . . .1458
42.6.2SPI control register 2 (SPIx_CR2) . . . . .1460
42.6.3SPI status register (SPIx_SR) . . . . .1462
42.6.4SPI data register (SPIx_DR) . . . . .1463
42.6.5SPI CRC polynomial register (SPIx_CRCPR) . . . . .1464
42.6.6SPI Rx CRC register (SPIx_RXCRCR) . . . . .1464
42.6.7SPI Tx CRC register (SPIx_TXCRCR) . . . . .1464
42.6.8SPI register map . . . . .1466
43Serial audio interface (SAI) . . . . .1467
43.1Introduction . . . . .1467
43.2SAI main features . . . . .1467
43.3<SAI functional description . . . . .1468
43.3.1SAI block diagram . . . . .1468
43.3.2SAI pins and internal signals . . . . .1469
43.3.3Main SAI modes . . . . .1469
43.3.4SAI synchronization mode . . . . .1470
43.3.5Audio data size . . . . .1471
43.3.6Frame synchronization . . . . .1472
43.3.7Slot configuration . . . . .1475
43.3.8SAI clock generator . . . . .1477
43.3.9Internal FIFOs . . . . .1479
43.3.10AC'97 link controller . . . . .1481
43.3.11SPDIF output . . . . .1483
43.3.12Specific features . . . . .1486
43.3.13Error flags . . . . .1490
43.3.14Disabling the SAI . . . . .1493
43.3.15SAI DMA interface . . . . .1493
43.4SAI interrupts . . . . .1494
43.5SAI registers . . . . .1495
43.5.1SAI global configuration register (SAI_GCR) . . . . .1495
43.5.2SAI configuration register 1 (SAI_ACR1) . . . . .1495
43.5.3SAI configuration register 2 (SAI_ACR2) . . . . .1498
43.5.4SAI frame configuration register (SAI_AFRCR) . . . . .1500
43.5.5SAI slot register (SAI_ASLOTR) . . . . .1501
43.5.6SAI interrupt mask register (SAI_AIM) . . . . .1502
43.5.7SAI status register (SAI_ASR) . . . . .1503
43.5.8SAI clear flag register (SAI_ACLRFR) . . . . .1505
43.5.9SAI data register (SAI_ADR) . . . . .1506
43.5.10SAI configuration register 1 (SAI_BCR1) . . . . .1507
43.5.11SAI configuration register 2 (SAI_BCR2) . . . . .1509
43.5.12SAI frame configuration register (SAI_BFRCR) . . . . .1511
43.5.13SAI slot register (SAI_BSLOTR) . . . . .1512
43.5.14SAI interrupt mask register (SAI_BIM) . . . . .1513
43.5.15SAI status register (SAI_BSR) . . . . .1514
43.5.16SAI clear flag register (SAI_BCLRFR) . . . . .1516
43.5.17SAI data register (SAI_BDR) . . . . .1517
43.5.18SAI register map . . . . .1518
44Single wire protocol master interface (SWPMI) . . . . .1520
44.1Introduction . . . . .1520
44.2SWPMI main features . . . . .1521
44.3SWPMI functional description . . . . .1522
44.3.1SWPMI block diagram . . . . .1522
44.3.2SWP initialization and activation . . . . .1522
44.3.3SWP bus states . . . . .1523
44.3.4SWPMI_IO (internal transceiver) bypass . . . . .1524
44.3.5SWPMI bit rate . . . . .1524
44.3.6SWPMI frame handling . . . . .1525
44.3.7Transmission procedure . . . . .1525
44.3.8Reception procedure . . . . .1530
44.3.9Error management . . . . .1534
44.3.10Loopback mode . . . . .1536
44.4SWPMI low-power modes . . . . .1536
44.5SWPMI interrupts . . . . .1537
44.6SWPMI registers . . . . .1538
44.6.1SWPMI configuration/control register (SWPMI_CR) . . . . .1538
44.6.2SWPMI Bitrate register (SWPMI_BRR) . . . . .1539
44.6.3SWPMI Interrupt and Status register (SWPMI_ISR) . . . . .1540
44.6.4SWPMI Interrupt Flag Clear register (SWPMI_ICR) . . . . .1541
44.6.5SWPMI Interrupt Enable register (SWPMI_IER) . . . . .1542
44.6.6SWPMI Receive Frame Length register (SWPMI_RFL) . . . . .1543
44.6.7SWPMI Transmit data register (SWPMI_TDR) . . . . .1544
44.6.8SWPMI Receive data register (SWPMI_RDR) . . . . .1544
44.6.9SWPMI Option register (SWPMI_OR) . . . . .1544
44.6.10SWPMI register map and reset value table . . . . .1546
45SD/SDIO/MMC card host interface (SDMMC) . . . . .1547
45.1SDMMC main features . . . . .1547
45.2SDMMC bus topology . . . . .1547
45.3SDMMC functional description . . . . .1549
45.3.1SDMMC adapter . . . . .1551
45.3.2SDMMC APB2 interface . . . . .1562
45.4Card functional description . . . . .1563
45.4.1Card identification mode . . . . .1563
45.4.2Card reset . . . . .1563
45.4.3Operating voltage range validation . . . . .1564
45.4.4Card identification process . . . . .1564
45.4.5Block write . . . . .1565
45.4.6Block read . . . . .1566
45.4.7Stream access, stream write and stream read
(MultiMediaCard only) . . . . .		1566
45.4.8Erase: group erase and sector erase . . . . .1568
45.4.9Wide bus selection or deselection . . . . .1568
45.4.10Protection management . . . . .1568
45.4.11Card status register . . . . .1572
45.4.12SD status register . . . . .1575
45.4.13SD I/O mode . . . . .1579
45.4.14Commands and responses . . . . .1580
45.5Response formats . . . . .1583
45.5.1R1 (normal response command) . . . . .1584
45.5.2R1b . . . . .1584
45.5.3R2 (CID, CSD register) . . . . .1584
45.5.4R3 (OCR register) . . . . .1585
45.5.5R4 (Fast I/O) . . . . .1585
45.5.6R4b . . . . .1585
45.5.7R5 (interrupt request) . . . . .1586
45.5.8R6 . . . . .1586
45.6SDIO I/O card-specific operations . . . . .1587
45.6.1SDIO I/O read wait operation by SDMMC_D2 signalling . . . . .1587
45.6.2SDIO read wait operation by stopping SDMMC_CK . . . . .1588
45.6.3SDIO suspend/resume operation . . . . .1588
45.6.4SDIO interrupts . . . . .1588
45.7HW flow control . . . . .1588
45.8SDMMC registers . . . . .1589
45.8.1SDMMC power control register (SDMMC_POWER) . . . . .1589
45.8.2SDMMC clock control register (SDMMC_CLKCR) . . . . .1589
45.8.3SDMMC argument register (SDMMC_ARG) . . . . .1592
45.8.4SDMMC command register (SDMMC_CMD) . . . . .1592
45.8.5SDMMC command response register (SDMMC_RESPCMD) . . . . .1593
45.8.6SDMMC response 1..4 register (SDMMC_RESPx) . . . . .1593
45.8.7SDMMC data timer register (SDMMC_DTIMER) . . . . .1594
45.8.8SDMMC data length register (SDMMC_DLEN) . . . . .1595
45.8.9SDMMC data control register (SDMMC_DCTRL) . . . . .1595
45.8.10SDMMC data counter register (SDMMC_DCOUNT) . . . . .1598
45.8.11SDMMC status register (SDMMC_STA) . . . . .1598
45.8.12SDMMC interrupt clear register (SDMMC_ICR) . . . . .1599
45.8.13SDMMC mask register (SDMMC_MASK) . . . . .1601
45.8.14SDMMC FIFO counter register (SDMMC_FIFOCNT) . . . . .1603
45.8.15SDMMC data FIFO register (SDMMC_FIFO) . . . . .1604
45.8.16SDMMC register map . . . . .1605
46Controller area network (bxCAN) . . . . .1607
46.1Introduction . . . . .1607
46.2bxCAN main features . . . . .1607
46.3bxCAN general description . . . . .1608
46.3.1CAN 2.0B active core . . . . .1608
46.3.2Control, status, and configuration registers . . . . .1609
46.3.3Tx mailboxes . . . . .1609
46.3.4Acceptance filters . . . . .1609
46.4bxCAN operating modes . . . . .1611
46.4.1Initialization mode . . . . .1611
47.5OTG_FS dual role device (DRD) . . . . .1660
47.5.1ID line detection . . . . .1660
47.5.2HNP dual role device . . . . .1661
47.5.3SRP dual role device . . . . .1661
47.6OTG_FS as a USB peripheral . . . . .1661
47.6.1SRP-capable peripheral . . . . .1662
47.6.2Peripheral states . . . . .1662
47.6.3Peripheral endpoints . . . . .1663
47.7OTG_FS as a USB host . . . . .1665
47.7.1SRP-capable host . . . . .1666
47.7.2USB host states . . . . .1666
47.7.3Host channels . . . . .1668
47.7.4Host scheduler . . . . .1669
47.8OTG_FS SOF trigger . . . . .1670
47.8.1Host SOFs . . . . .1670
47.8.2Peripheral SOFs . . . . .1670
47.9OTG_FS low-power modes . . . . .1671
47.10OTG_FS Dynamic update of the OTG_HFIR register . . . . .1672
47.11OTG_FS data FIFOs . . . . .1672
47.11.1Peripheral FIFO architecture . . . . .1673
47.11.2Host FIFO architecture . . . . .1674
47.11.3FIFO RAM allocation . . . . .1675
47.12OTG_FS system performance . . . . .1677
47.13OTG_FS interrupts . . . . .1677
47.14OTG_FS control and status registers . . . . .1679
47.14.1CSR memory map . . . . .1679
47.15OTG_FS registers . . . . .1684
47.15.1OTG control and status register (OTG_GOTGCTL) . . . . .1684
47.15.2OTG interrupt register (OTG_GOTGINT) . . . . .1687
47.15.3OTG AHB configuration register (OTG_GAHBCFG) . . . . .1688
47.15.4OTG USB configuration register (OTG_GUSBCFG) . . . . .1689
47.15.5OTG reset register (OTG_GRSTCTL) . . . . .1691
47.15.6OTG core interrupt register (OTG_GINTSTS) . . . . .1693
47.15.7OTG interrupt mask register (OTG_GINTMSK) . . . . .1697
47.15.8OTG receive status debug read register (OTG_GRXSTSR) . . . . .1700
47.15.9OTG receive status debug read [alternate] (OTG_GRXSTSR) . . . . .1701
47.15.10OTG status read and pop registers (OTG_GRXSTSP) . . . . .1702
47.15.11OTG status read and pop registers [alternate] (OTG_GRXSTSP) . . .1703
47.15.12OTG receive FIFO size register (OTG_GRXFSIZ) . . . . .1704
47.15.13OTG host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0) . . . . .		1704
47.15.14OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . .		1705
47.15.15OTG general core configuration register (OTG_GCCFG) . . . . .1706
47.15.16OTG core ID register (OTG_CID) . . . . .1708
47.15.17OTG core LPM configuration register (OTG_GLPMCFG) . . . . .1708
47.15.18OTG power down register (OTG_GPWRDN) . . . . .1712
47.15.19OTG ADP timer, control and status register
(OTG_GADPCTL) . . . . .		1712
47.15.20OTG host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . .		1714
47.15.21OTG device IN endpoint transmit FIFO x size register
(OTG_DIEPTXFx) . . . . .		1715
47.15.22Host-mode registers . . . . .1715
47.15.23OTG host configuration register (OTG_HCFG) . . . . .1715
47.15.24OTG host frame interval register (OTG_HFIR) . . . . .1716
47.15.25OTG host frame number/frame time remaining register
(OTG_HFNUM) . . . . .		1717
47.15.26OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . .		1718
47.15.27OTG host all channels interrupt register (OTG_HAINT) . . . . .1719
47.15.28OTG host all channels interrupt mask register
(OTG_HAINTMSK) . . . . .		1719
47.15.29OTG host port control and status register (OTG_HPRT) . . . . .1720
47.15.30OTG host channel x characteristics register (OTG_HCCHARx) . . . . .1722
47.15.31OTG host channel x interrupt register (OTG_HCINTx) . . . . .1723
47.15.32OTG host channel x interrupt mask register (OTG_HCINTMSKx) . . . . .1724
47.15.33OTG host channel x transfer size register (OTG_HCTSIZx) . . . . .1725
47.15.34Device-mode registers . . . . .1726
47.15.35OTG device configuration register (OTG_DCFG) . . . . .1726
47.15.36OTG device control register (OTG_DCTL) . . . . .1728
47.15.37OTG device status register (OTG_DSTS) . . . . .1730
47.15.38OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . .		1731
47.15.39OTG device OUT endpoint common interrupt mask register (OTG_DOEPMASK) . . . . .1732
47.15.40OTG device all endpoints interrupt register (OTG_DAININT) . . . . .1733
47.15.41OTG all endpoints interrupt mask register (OTG_DAININTMSK) . . . . .1734
47.15.42OTG device V BUS discharge time register (OTG_DVBUSDIS) . . . . .1734
47.15.43OTG device V BUS pulsing time register (OTG_DVBUSPULSE) . . . . .1735
47.15.44OTG device IN endpoint FIFO empty interrupt mask register (OTG_DIEPEMPSK) . . . . .1735
47.15.45OTG device control IN endpoint 0 control register (OTG_DIEPCTL0) . . . . .1736
47.15.46OTG device IN endpoint x control register (OTG_DIEPCTLx) . . . . .1737
47.15.47OTG device IN endpoint x interrupt register (OTG_DIEPINTx) . . . . .1740
47.15.48OTG device IN endpoint 0 transfer size register (OTG_DIEPTSIZ0) . . . . .1741
47.15.49OTG device IN endpoint transmit FIFO status register (OTG_DTXFSTSx) . . . . .1742
47.15.50OTG device IN endpoint x transfer size register (OTG_DIEPTSIZx) . . . . .1743
47.15.51OTG device control OUT endpoint 0 control register (OTG_DOECTL0) . . . . .1744
47.15.52OTG device OUT endpoint x interrupt register (OTG_DOEPINTx) . . . . .1745
47.15.53OTG device OUT endpoint 0 transfer size register (OTG_DOEPTSIZ0) . . . . .1747
47.15.54OTG device OUT endpoint x control register (OTG_DOECTLx) . . . . .1748
47.15.55OTG device OUT endpoint x transfer size register (OTG_DOEPTSIZx) . . . . .1750
47.15.56OTG power and clock gating control register (OTG_PCGCTL) . . . . .1751
47.15.57OTG_FS register map . . . . .1752
47.16OTG_FS programming model . . . . .1761
47.16.1Core initialization . . . . .1761
47.16.2Host initialization . . . . .1762
47.16.3Device initialization . . . . .1762
47.16.4Host programming model . . . . .1763
47.16.5Device programming model . . . . .1784
47.16.6Worst case response time . . . . .1805
47.16.7OTG programming model . . . . .1807
48Debug support (DBG) . . . . .1813
48.1Overview .....1813
48.2Reference Arm® documentation .....1814
48.3SWJ debug port (serial wire and JTAG) .....1814
48.3.1Mechanism to select the JTAG-DP or the SW-DP .....1815
48.4Pinout and debug port pins .....1815
48.4.1SWJ debug port pins .....1816
48.4.2Flexible SWJ-DP pin assignment .....1816
48.4.3Internal pull-up and pull-down on JTAG pins .....1816
48.4.4Using serial wire and releasing the unused debug pins as GPIOs ..1818
48.5STM32L47x/L48x/L49x/L4Ax JTAG TAP connection .....1818
48.6ID codes and locking mechanism .....1819
48.6.1MCU device ID code .....1820
48.6.2Boundary scan TAP .....1820
48.6.3Cortex®-M4 TAP .....1820
48.6.4Cortex®-M4 JEDEC-106 ID code .....1821
48.7JTAG debug port .....1821
48.8SW debug port .....1823
48.8.1SW protocol introduction .....1823
48.8.2SW protocol sequence .....1823
48.8.3SW-DP state machine (reset, idle states, ID code) .....1824
48.8.4DP and AP read/write accesses .....1824
48.8.5SW-DP registers .....1825
48.8.6SW-AP registers .....1826
48.9AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP .....		1826
48.10Core debug .....1827
48.11Capability of the debugger host to connect under system reset .....1827
48.12FPB (Flash patch breakpoint) .....1828
48.13DWT (data watchpoint trigger) .....1828
48.14ITM (instrumentation trace macrocell) .....1829
48.14.1General description .....1829
48.14.2Time stamp packets, synchronization and overflow packets .....1829
48.15ETM (Embedded trace macrocell) .....1831
48.15.1General description .....1831
48.15.2Signal protocol, packet types .....1831
48.15.3Main ETM registers .....1831
48.15.4Configuration example . . . . .1832
48.16MCU debug component (DBGMCU) . . . . .1832
48.16.1Debug support for low-power modes . . . . .1832
48.16.2Debug support for timers, RTC, watchdog, bxCAN and I 2 C . . . . .1833
48.16.3Debug MCU configuration register (DBGMCU_CR) . . . . .1833
48.16.4Debug MCU APB1 freeze register1(DBGMCU_APB1FZR1) . . . . .1834
48.16.5Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2) . . . . .1836
48.16.6Debug MCU APB2 freeze register (DBGMCU_APB2FZR) . . . . .1836
48.17TPIU (trace port interface unit) . . . . .1838
48.17.1Introduction . . . . .1838
48.17.2TRACE pin assignment . . . . .1838
48.17.3TPUI formatter . . . . .1840
48.17.4TPUI frame synchronization packets . . . . .1841
48.17.5Transmission of the synchronization frame packet . . . . .1841
48.17.6Synchronous mode . . . . .1841
48.17.7Asynchronous mode . . . . .1842
48.17.8TRACECLKIN connection inside the
STM32L47x/L48x/L49x/L4Ax . . . . .		1842
48.17.9TPIU registers . . . . .1843
48.17.10Example of configuration . . . . .1844
48.18DBG register map . . . . .1845
49Device electronic signature . . . . .1846
49.1Unique device ID register (96 bits) . . . . .1846
49.2Flash size data register . . . . .1847
49.3Package data register . . . . .1848
50Important security notice . . . . .1849
51Revision history . . . . .1850

List of tables

Table 1. STM32L47x/L48x devices memory map and peripheral register boundary addresses . . . . . 78

Table 2. STM32L49x/L4Ax devices memory map and peripheral register boundary addresses . . . . . 83

Table 3. SRAM2 organization. . . . . 88

Table 4. Boot modes. . . . . 91

Table 5. Memory mapping versus boot mode/physical remap . . . . . 92

Table 6. Boot modes. . . . . 93

Table 7. Memory mapping versus boot mode/physical remap . . . . . 94

Table 8. Flash module - 1 MB dual bank organization . . . . . 97

Table 9. Flash module - 512 KB dual bank organization . . . . . 98

Table 10. Flash module - 256 KB dual bank organization . . . . . 99

Table 11. Number of wait states according to CPU clock (HCLK) frequency. . . . . 100

Table 12. Option byte format . . . . . 110

Table 13. Option byte organization. . . . . 110

Table 14. Flash memory read protection status . . . . . 118

Table 15. Access status versus protection level and execution modes . . . . . 120

Table 16. Flash interrupt request . . . . . 123

Table 17. Flash interface - register map and reset values . . . . . 138

Table 18. Segment accesses according to the Firewall state. . . . . 143

Table 19. Segment granularity and area ranges . . . . . 144

Table 20. Firewall register map and reset values. . . . . 152

Table 21. PVM features . . . . . 163

Table 22. Low-power mode summary . . . . . 166

Table 23. Functionalities depending on the working mode. . . . . 167

Table 24. Low-power run . . . . . 171

Table 25. Sleep. . . . . 172

Table 26. Low-power sleep. . . . . 174

Table 27. Stop 0 mode . . . . . 176

Table 28. Stop 1 mode . . . . . 177

Table 29. Stop 2 mode . . . . . 179

Table 30. Standby mode. . . . . 181

Table 31. Shutdown mode . . . . . 183

Table 32. PWR register map and reset values. . . . . 201

Table 33. Clock source frequency . . . . . 216

Table 34. RCC register map and reset values . . . . . 278

Table 35. CRS features . . . . . 283

Table 36. Effect of low-power modes on CRS . . . . . 287

Table 37. Interrupt control bits . . . . . 287

Table 38. CRS register map and reset values . . . . . 292

Table 39. Port bit configuration table . . . . . 296

Table 40. GPIO register map and reset values . . . . . 312

Table 41. SYSCFG register map and reset values. . . . . 325

Table 42. STM32L47x/L48x/L49x/L4Ax peripherals interconnect matrix . . . . . 327

Table 43. DMA1 and DMA2 implementation . . . . . 337

Table 44. DMA1 requests for each channel . . . . . 339

Table 45. DMA2 requests for each channel . . . . . 340

Table 46. Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . 347

Table 47.DMA interrupt requests . . . . .349
Table 48.DMA register map and reset values . . . . .358
Table 49.Supported color mode in input . . . . .364
Table 50.Data order in memory . . . . .365
Table 51.Alpha mode configuration . . . . .366
Table 52.Supported CLUT color mode . . . . .367
Table 53.CLUT data order in system memory . . . . .367
Table 54.Supported color mode in output . . . . .368
Table 55.Data order in memory . . . . .368
Table 56.DMA2D interrupt requests . . . . .373
Table 57.DMA2D register map and reset values . . . . .390
Table 58.STM32L47x/L48x/L49x/L4Ax vector table . . . . .393
Table 59.EXTI lines connections . . . . .400
Table 60.Extended interrupt/event controller register map and reset values . . . . .409
Table 61.CRC internal input/output signals . . . . .411
Table 62.CRC register map and reset values . . . . .416
Table 63.NOR/PSRAM bank selection . . . . .421
Table 64.NOR/PSRAM External memory address . . . . .421
Table 65.NAND memory mapping and timing registers . . . . .421
Table 66.NAND bank selection . . . . .421
Table 67.Programmable NOR/PSRAM access parameters . . . . .423
Table 68.Non-multiplexed I/O NOR flash memory . . . . .423
Table 69.16-bit multiplexed I/O NOR flash memory . . . . .424
Table 70.Non-multiplexed I/Os PSRAM/SRAM . . . . .424
Table 71.16-Bit multiplexed I/O PSRAM . . . . .425
Table 72.NOR flash/PSRAM: example of supported memories
and transactions . . . . .		425
Table 73.FMC_BCRx bitfields (mode 1) . . . . .428
Table 74.FMC_BTRx bitfields (mode 1) . . . . .429
Table 75.FMC_BCRx bitfields (mode A) . . . . .431
Table 76.FMC_BTRx bitfields (mode A) . . . . .431
Table 77.FMC_BWTRx bitfields (mode A) . . . . .432
Table 78.FMC_BCRx bitfields (mode 2/B) . . . . .434
Table 79.FMC_BTRx bitfields (mode 2/B) . . . . .434
Table 80.FMC_BWTRx bitfields (mode 2/B) . . . . .435
Table 81.FMC_BCRx bitfields (mode C) . . . . .436
Table 82.FMC_BTRx bitfields (mode C) . . . . .437
Table 83.FMC_BWTRx bitfields (mode C) . . . . .437
Table 84.FMC_BCRx bitfields (mode D) . . . . .439
Table 85.FMC_BTRx bitfields (mode D) . . . . .439
Table 86.FMC_BWTRx bitfields (mode D) . . . . .440
Table 87.FMC_BCRx bitfields (Muxed mode) . . . . .441
Table 88.FMC_BTRx bitfields (Muxed mode) . . . . .442
Table 89.FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . .447
Table 90.FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . .447
Table 91.FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . .448
Table 92.FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . .449
Table 93.Programmable NAND flash access parameters . . . . .457
Table 94.8-bit NAND flash . . . . .457
Table 95.16-bit NAND flash . . . . .458
Table 96.Supported memories and transactions . . . . .458
Table 97.ECC result relevant bits . . . . .467
Table 98.FMC register map and reset values . . . . .468
Table 99.QUADSPI implementation . . . . .470
Table 100.QUADSPI pins . . . . .471
Table 101.QUADSPI interrupt requests. . . . .485
Table 102.QUADSPI register map and reset values . . . . .497
Table 103.ADC features . . . . .501
Table 104.ADC internal input/output signals . . . . .503
Table 105.ADC input/output pins. . . . .503
Table 106.Configuring the trigger polarity for regular external triggers . . . . .521
Table 107.Configuring the trigger polarity for injected external triggers . . . . .521
Table 108.ADC1, ADC2 and ADC3 - External triggers for regular channels. . . . .522
Table 109.ADC1, ADC2 and ADC3 - External trigger for injected channels . . . . .523
Table 110.TSAR timings depending on resolution . . . . .535
Table 111.Offset computation versus data resolution . . . . .538
Table 112.Analog watchdog channel selection . . . . .549
Table 113.Analog watchdog 1 comparison . . . . .550
Table 114.Analog watchdog 2 and 3 comparison . . . . .550
Table 115.Maximum output results versus N and M (gray cells indicate truncation). . . . .554
Table 116.Oversampler operating modes summary . . . . .558
Table 117.Effect of low-power modes on the ADC . . . . .577
Table 118.ADC interrupts per each ADC. . . . .578
Table 119.DELAY bits versus ADC resolution. . . . .609
Table 120.ADC global register map. . . . .610
Table 121.ADC register map and reset values for each ADC (offset = 0x000
for master ADC, 0x100 for slave ADC). . . . .		611
Table 122.ADC register map and reset values (master and slave ADC
common registers) offset = 0x300 . . . . .		613
Table 123.DAC features . . . . .615
Table 124.DAC input/output pins. . . . .617
Table 125.DAC trigger selection . . . . .620
Table 126.Sample and refresh timings . . . . .624
Table 127.Channel output modes summary . . . . .625
Table 128.Effect of low-power modes on DAC . . . . .631
Table 129.DAC interrupts . . . . .632
Table 130.DAC register map and reset values . . . . .648
Table 131.DCMI input/output pins . . . . .651
Table 132.Positioning of captured data bytes in 32-bit words (8-bit width) . . . . .653
Table 133.Positioning of captured data bytes in 32-bit words (10-bit width) . . . . .653
Table 134.Positioning of captured data bytes in 32-bit words (12-bit width) . . . . .653
Table 135.Positioning of captured data bytes in 32-bit words (14-bit width) . . . . .654
Table 136.Data storage in monochrome progressive video format. . . . .659
Table 137.Data storage in RGB progressive video format . . . . .660
Table 138.Data storage in YCbCr progressive video format . . . . .660
Table 139.Data storage in YCbCr progressive video format - Y extraction mode . . . . .660
Table 140.DCMI interrupts. . . . .661
Table 141.DCMI register map and reset values . . . . .671
Table 142.VREF buffer modes . . . . .673
Table 143.VREFBUF register map and reset values. . . . .675
Table 144.COMP1 input plus assignment . . . . .677
Table 145.COMP1 input minus assignment . . . . .677
Table 146.COMP2 input plus assignment . . . . .678
Table 147.COMP2 input minus assignment . . . . .678
Table 148.Comparator behavior in the low power modes . . . . .681
Table 149.Interrupt control bits . . . . .682
Table 150.COMP register map and reset values. . . . .687
Table 151.Operational amplifier possible connections . . . . .689
Table 152.Operating modes and calibration . . . . .694
Table 153.Effect of low-power modes on the OPAMP . . . . .695
Table 154.OPAMP register map and reset values . . . . .700
Table 155.DFSDM1 implementation . . . . .703
Table 156.DFSDM external pins . . . . .705
Table 157.DFSDM internal signals . . . . .705
Table 158.DFSDM triggers connection . . . . .705
Table 159.DFSDM break connection. . . . .706
Table 160.Filter maximum output resolution (peak data values from filter output)
for some FOSR values . . . . .		721
Table 161.Integrator maximum output resolution (peak data values from integrator
output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . . .		722
Table 162.DFSDM interrupt requests . . . . .730
Table 163.DFSDM register map and reset values. . . . .751
Table 164.Example of frame rate calculation . . . . .764
Table 165.Blink frequency . . . . .772
Table 166.Remapping capability . . . . .776
Table 167.LCD behavior in low-power modes. . . . .782
Table 168.LCD interrupt requests . . . . .782
Table 169.LCD register map and reset values . . . . .789
Table 170.Acquisition sequence summary . . . . .795
Table 171.Spread spectrum deviation versus AHB clock frequency. . . . .798
Table 172.I/O state depending on its mode and IODEF bit value . . . . .799
Table 173.Effect of low-power modes on TSC . . . . .801
Table 174.Interrupt control bits . . . . .801
Table 175.TSC register map and reset values . . . . .809
Table 176.RNG internal input/output signals . . . . .812
Table 177.RNG interrupt requests. . . . .817
Table 178.RNG register map and reset map. . . . .820
Table 179.AES internal input/output signals. . . . .822
Table 180.CTR mode initialization vector definition. . . . .841
Table 181.GCM last block definition . . . . .843
Table 182.GCM mode IVI bitfield initialization. . . . .844
Table 183.Initialization of AES_IVRx registers in CCM mode . . . . .851
Table 184.Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . .856
Table 185.DMA channel configuration for memory-to-AES data transfer . . . . .857
Table 186.DMA channel configuration for AES-to-memory data transfer . . . . .858
Table 187.AES interrupt requests . . . . .860
Table 188.Processing latency (in clock cycle) for ECB, CBC and CTR. . . . .860
Table 189.Processing latency for GCM and CCM (in clock cycle) . . . . .860
Table 190.AES register map and reset values . . . . .872
Table 191.HASH internal input/output signals. . . . .876
Table 192.Hash processor outputs . . . . .879
Table 193.HASH interrupt requests. . . . .886
Table 194.Processing time (in clock cycle) . . . . .886
Table 195.HASH register map and reset values . . . . .894
Table 196.Behavior of timer outputs versus BRK/BRK2 inputs. . . . .938
Table 197.Counting direction versus encoder signals. . . . .945
Table 198.TIMx internal trigger connection . . . . .962
Table 199.Output control bits for complementary OCx and OCxN channels with break feature . . . . .976
Table 200.TIM1 register map and reset values . . . . .996
Table 201.TIM8 register map and reset values . . . . .998
Table 202.Counting direction versus encoder signals . . . . .1035
Table 203.TIMx internal trigger connection . . . . .1053
Table 204.Output control bit for standard OCx channels . . . . .1063
Table 205.TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . .1071
Table 206.TIMx Internal trigger connection . . . . .1116
Table 207.Output control bits for complementary OCx and OCxN channels with break feature (TIM15) . . . . .1126
Table 208.TIM15 register map and reset values . . . . .1134
Table 209.Output control bits for complementary OCx and OCxN channels with break feature (TIM16/17) . . . . .1147
Table 210.TIM16/TIM17 register map and reset values . . . . .1158
Table 211.TIMx register map and reset values . . . . .1172
Table 212.STM32L47x/L48x/L49x/L4Ax LPTIM features . . . . .1174
Table 213.LPTIM1 external trigger connection . . . . .1175
Table 214.LPTIM2 external trigger connection . . . . .1175
Table 215.Prescaler division ratios . . . . .1177
Table 216.Encoder counting scenarios . . . . .1183
Table 217.Effect of low-power modes on the LPTIM . . . . .1184
Table 218.Interrupt events . . . . .1184
Table 219.LPTIM register map and reset values . . . . .1194
Table 220.IWDG register map and reset values . . . . .1204
Table 221.WWDG register map and reset values . . . . .1210
Table 222.RTC pin PC13 configuration . . . . .1214
Table 223.RTC_OUT mapping . . . . .1215
Table 224.RTC functions over modes . . . . .1216
Table 225.Effect of low-power modes on RTC . . . . .1228
Table 226.Interrupt control bits . . . . .1229
Table 227.RTC register map and reset values . . . . .1254
Table 228.STM32L47x/L48x I2C implementation . . . . .1257
Table 229.STM32L49x/L4Ax I2C implementation . . . . .1257
Table 230.I2C input/output pins . . . . .1259
Table 231.I2C internal input/output signals . . . . .1259
Table 232.Comparison of analog and digital filters . . . . .1261
Table 233.I 2 C-SMBus specification data setup and hold times . . . . .1263
Table 234.I2C configuration . . . . .1267
Table 235.I 2 C-SMBus specification clock timings . . . . .1278
Table 236.Timing settings for f I2CCLK of 8 MHz . . . . .1288
Table 237.Timing settings for f I2CCLK of 16 MHz . . . . .1288
Table 238.Timing settings for f I2CCLK of 48 MHz . . . . .1289
Table 239.SMBus timeout specifications . . . . .1291
Table 240.SMBus with PEC configuration . . . . .1292
Table 241.TIMEOUTA[11:0] for maximum t TIMEOUT of 25 ms . . . . .1294
Table 242.TIMEOUTB[11:0] for maximum t LOW:SEXT and t LOW:MEXT of 8 ms . . . . .1294
Table 243.TIMEOUTA[11:0] for maximum t IDLE of 50 µs . . . . .1294
Table 244.Effect of low-power modes to I2C . . . . .1304
Table 245.I2C interrupt requests . . . . .1304
Table 246.I2C register map and reset values . . . . .1319
Table 247.STM32L47x/L48x/L49x/L4Ax USART/UART/LPUART features . . . . .1323
Table 248.Noise detection from sampled data . . . . .1335
Table 249.Error calculation for programmed baud rates at \( f_{CK} = 72\text{MHz} \) in both cases of oversampling by 16 or by 8. . . . .1338
Table 250.Tolerance of the USART receiver when BRR [3:0] = 0000. . . . .1340
Table 251.Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . .1340
Table 252.Frame formats . . . . .1344
Table 253.Effect of low-power modes on the USART . . . . .1363
Table 254.USART interrupt requests. . . . .1363
Table 255.USART register map and reset values . . . . .1388
Table 256.STM32L47x/L48x/L49x/L4Ax USART/UART/LPUART features. . . . .1392
Table 257.Error calculation for programmed baud rates at \( f_{ck} = 32.768\text{ kHz} \) . . . . .1402
Table 258.Error calculation for programmed baud rates at \( f_{ck} = 80\text{ MHz} \) . . . . .1402
Table 259.Tolerance of the LPUART receiver. . . . .1403
Table 260.Frame formats . . . . .1406
Table 261.Effect of low-power modes on the LPUART . . . . .1414
Table 262.LPUART interrupt requests. . . . .1415
Table 263.LPUART register map and reset values . . . . .1431
Table 264.STM32L47x/L48x/L49x/L4Ax SPI implementation . . . . .1433
Table 265.SPI interrupt requests. . . . .1457
Table 266.SPI register map and reset values . . . . .1466
Table 267.SAI internal input/output signals . . . . .1469
Table 268.SAI input/output pins. . . . .1469
Table 269.External synchronization selection . . . . .1471
Table 270.Example of possible audio frequency sampling range . . . . .1478
Table 271.SOPD pattern . . . . .1484
Table 272.Parity bit calculation . . . . .1484
Table 273.Audio sampling frequency versus symbol rates . . . . .1485
Table 274.SAI interrupt sources . . . . .1494
Table 275.SAI register map and reset values . . . . .1518
Table 276.Effect of low-power modes on SWPMI . . . . .1536
Table 277.Interrupt control bits . . . . .1537
Table 278.Buffer modes selection for transmission/reception . . . . .1539
Table 279.SWPMI register map and reset values . . . . .1546
Table 280.SDMMC I/O definitions . . . . .1550
Table 281.Command format . . . . .1555
Table 282.Short response format . . . . .1556
Table 283.Long response format. . . . .1556
Table 284.Command path status flags . . . . .1556
Table 285.Data token format . . . . .1559
Table 286.DPSM flags. . . . .1560
Table 287.Transmit FIFO status flags . . . . .1561
Table 288.Receive FIFO status flags . . . . .1561
Table 289.Card status . . . . .1572
Table 290.SD status . . . . .1575
Table 291.Speed class code field . . . . .1576
Table 292.Performance move field . . . . .1577
Table 293.AU_SIZE field . . . . .1577
Table 294.Maximum AU size. . . . .1577
Table 295.Erase size field . . . . .1578
Table 296.Erase timeout field . . . . .1578
Table 297.Erase offset field . . . . .1578
Table 298.Block-oriented write commands . . . . .1581
Table 299.Block-oriented write protection commands . . . . .1582
Table 300.Erase commands . . . . .1582
Table 301.I/O mode commands . . . . .1582
Table 302.Lock card . . . . .1583
Table 303.Application-specific commands . . . . .1583
Table 304.R1 response . . . . .1584
Table 305.R2 response . . . . .1584
Table 306.R3 response . . . . .1585
Table 307.R4 response . . . . .1585
Table 308.R4b response . . . . .1585
Table 309.R5 response . . . . .1586
Table 310.R6 response . . . . .1587
Table 311.Response type and SDMMC_RESPx registers . . . . .1594
Table 312.SDMMC register map . . . . .1605
Table 313.CAN implementation . . . . .1608
Table 314.Transmit mailbox mapping . . . . .1623
Table 315.Receive mailbox mapping . . . . .1623
Table 316.bxCAN register map and reset values . . . . .1649
Table 317.OTG_FS speeds supported . . . . .1654
Table 318.OTG_FS implementation . . . . .1657
Table 319.OTG_FS input/output pins . . . . .1658
Table 320.OTG_FS input/output signals . . . . .1659
Table 321.Compatibility of STM32 low power modes with the OTG . . . . .1671
Table 322.Core global control and status registers (CSRs). . . . .1679
Table 323.Host-mode control and status registers (CSRs) . . . . .1680
Table 324.Device-mode control and status registers . . . . .1681
Table 325.Data FIFO (DFIFO) access register map . . . . .1683
Table 326.Power and clock gating control and status registers . . . . .1683
Table 327.TRDT values . . . . .1690
Table 328.Minimum duration for soft disconnect . . . . .1729
Table 329.OTG_FS register map and reset values . . . . .1752
Table 330.SWJ debug port pins . . . . .1816
Table 331.Flexible SWJ-DP pin assignment . . . . .1816
Table 332.JTAG debug port data registers . . . . .1821
Table 333.32-bit debug port registers addressed through the shifted value A[3:2] . . . . .1822
Table 334.Packet request (8-bits) . . . . .1823
Table 335.ACK response (3 bits). . . . .1824
Table 336.DATA transfer (33 bits). . . . .1824
Table 337.SW-DP registers . . . . .1825
Table 338.Cortex®-M4 AHB-AP registers . . . . .1826
Table 339.Core debug registers . . . . .1827
Table 340.Main ITM registers . . . . .1829
Table 341.Main ETM registers . . . . .1831
Table 342.Asynchronous TRACE pin assignment . . . . .1838
Table 343.Synchronous TRACE pin assignment . . . . .1839
Table 344.Flexible TRACE pin assignment . . . . .1839
Table 345.Important TPIU registers . . . . .1843
Table 346.DBG register map and reset values . . . . .1845
Table 347.Document revision history . . . . .1850

List of figures

Figure 1.System architecture for STM32L47x/L48x devices . . . . .72
Figure 2.System architecture for STM32L49x/L4Ax . . . . .73
Figure 3.Memory map for STM32L47x/L48x devices . . . . .76
Figure 4.Memory map for STM32L49x/L4Ax devices . . . . .77
Figure 5.Sequential 16-bit instructions execution . . . . .102
Figure 6.Changing the Read protection (RDP) level . . . . .120
Figure 7.STM32L47x/L48x/L49x/L4Ax firewall connection schematics . . . . .141
Figure 8.Firewall functional states . . . . .145
Figure 9.Power supply overview . . . . .154
Figure 10.Internal main regulator overview . . . . .159
Figure 11.Brown-out reset waveform . . . . .162
Figure 12.PVD thresholds . . . . .162
Figure 13.Low-power modes possible transitions . . . . .165
Figure 14.Simplified diagram of the reset circuit . . . . .204
Figure 15.Clock tree (for STM32L47x/L48x devices) . . . . .208
Figure 16.Clock tree (for STM32L49x/L4Ax devices) . . . . .210
Figure 17.HSE/ LSE clock sources . . . . .211
Figure 18.Frequency measurement with TIM15 in capture mode . . . . .219
Figure 19.Frequency measurement with TIM16 in capture mode . . . . .220
Figure 20.Frequency measurement with TIM17 in capture mode . . . . .220
Figure 21.CRS block diagram . . . . .284
Figure 22.CRS counter behavior . . . . .285
Figure 23.Basic structure of an I/O port bit . . . . .295
Figure 24.Basic structure of a 5-Volt tolerant I/O port bit . . . . .296
Figure 25.Input floating / pull up / pull down configurations . . . . .300
Figure 26.Output configuration . . . . .301
Figure 27.Alternate function configuration . . . . .302
Figure 28.High impedance-analog configuration . . . . .302
Figure 29.DMA1 request mapping . . . . .338
Figure 30.DMA2 request mapping . . . . .339
Figure 31.DMA block diagram . . . . .341
Figure 32.DMA2D block diagram . . . . .363
Figure 33.Configurable interrupt/event block diagram . . . . .398
Figure 34.External interrupt/event GPIO mapping . . . . .400
Figure 35.CRC calculation unit block diagram . . . . .411
Figure 36.FMC block diagram . . . . .418
Figure 37.FMC memory banks . . . . .420
Figure 38.Mode 1 read access waveforms . . . . .427
Figure 39.Mode 1 write access waveforms . . . . .428
Figure 40.Mode A read access waveforms . . . . .430
Figure 41.Mode A write access waveforms . . . . .430
Figure 42.Mode 2 and mode B read access waveforms . . . . .432
Figure 43.Mode 2 write access waveforms . . . . .433
Figure 44.Mode B write access waveforms . . . . .433
Figure 45.Mode C read access waveforms . . . . .435
Figure 46.Mode C write access waveforms . . . . .436
Figure 47.Mode D read access waveforms . . . . .438
Figure 48.Mode D write access waveforms . . . . .438
Figure 49.Muxed read access waveforms . . . . .440
Figure 50.Muxed write access waveforms . . . . .441
Figure 51.Asynchronous wait during a read access waveforms . . . . .443
Figure 52.Asynchronous wait during a write access waveforms . . . . .444
Figure 53.Wait configuration waveforms . . . . .446
Figure 54.Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . .446
Figure 55.Synchronous multiplexed write mode waveforms - PSRAM (CRAM) . . . . .448
Figure 56.NAND flash controller waveforms for common memory access . . . . .459
Figure 57.Access to non 'CE don't care' NAND-flash . . . . .461
Figure 58.QUADSPI block diagram when dual-flash mode is disabled . . . . .471
Figure 59.QUADSPI block diagram when dual-flash mode is enabled . . . . .471
Figure 60.Example of read command in quad-SPI mode . . . . .472
Figure 61.Example of a DDR command in quad-SPI mode . . . . .476
Figure 62.NCS when CKMODE = 0 (T = CLK period) . . . . .483
Figure 63.NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . .484
Figure 64.NCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . .484
Figure 65.NCS when CKMODE = 1 with an abort (T = CLK period) . . . . .485
Figure 66.ADC block diagram . . . . .502
Figure 67.ADC clock scheme . . . . .505
Figure 68.ADC1 connectivity . . . . .506
Figure 69.ADC2 connectivity . . . . .507
Figure 70.ADC3 connectivity . . . . .508
Figure 71.ADC calibration . . . . .511
Figure 72.Updating the ADC calibration factor . . . . .512
Figure 73.Mixing single-ended and differential channels . . . . .513
Figure 74.Enabling / disabling the ADC . . . . .514
Figure 75.Analog to digital conversion time . . . . .519
Figure 76.Stopping ongoing regular conversions . . . . .520
Figure 77.Stopping ongoing regular and injected conversions . . . . .520
Figure 78.Triggers sharing between ADC master and ADC slave . . . . .522
Figure 79.Injected conversion latency . . . . .525
Figure 80.Example of JSQR queue of context (sequence change) . . . . .528
Figure 81.Example of JSQR queue of context (trigger change) . . . . .528
Figure 82.Example of JSQR queue of context with overflow before conversion . . . . .529
Figure 83.Example of JSQR queue of context with overflow during conversion . . . . .529
Figure 84.Example of JSQR queue of context with empty queue (case JQM = 0) . . . . .530
Figure 85.Example of JSQR queue of context with empty queue (case JQM = 1) . . . . .531
Figure 86.Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs during an ongoing conversion . . . . .		531
Figure 87.Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs . . . . .		532
Figure 88.Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 0)
Case when JADSTP occurs outside an ongoing conversion . . . . .		532
Figure 89.Flushing JSQR queue of context by setting JADSTP = 1 (JQM = 1) . . . . .533
Figure 90.Flushing JSQR queue of context by setting ADDIS = 1 (JQM = 0) . . . . .533
Figure 91.Flushing JSQR queue of context by setting ADDIS = 1 (JQM = 1) . . . . .534
Figure 92.Single conversions of a sequence, software trigger . . . . .536
Figure 93.Continuous conversion of a sequence, software trigger . . . . .536
Figure 94.Single conversions of a sequence, hardware trigger . . . . .537
Figure 95.Continuous conversions of a sequence, hardware trigger . . . . .537
Figure 96.Right alignment (offset disabled, unsigned value) . . . . .539
Figure 97.Right alignment (offset enabled, signed value) . . . . .540
Figure 98.Left alignment (offset disabled, unsigned value) . . . . .540
Figure 99.Left alignment (offset enabled, signed value) . . . . .541
Figure 100.Example of overrun (OVR) . . . . .542
Figure 101.AUTODLY = 1, regular conversion in continuous mode, software trigger . . . . .545
Figure 102.AUTODLY = 1, regular HW conversions interrupted by injected conversions
(DISCEN = 0; JDISCEN = 0) . . . . .		546
Figure 103.AUTODLY = 1, regular HW conversions interrupted by injected conversions
(DISCEN = 1, JDISCEN = 1) . . . . .		547
Figure 104.AUTODLY = 1, regular continuous conversions interrupted by injected conversions . . . . .548
Figure 105.AUTODLY = 1 in auto- injected mode (JAUTO = 1) . . . . .548
Figure 106.Analog watchdog guarded area . . . . .549
Figure 107.ADC y _AWD x _OUT signal generation (on all regular channels) . . . . .551
Figure 108.ADC y _AWD x _OUT signal generation (AWD x flag not cleared by software) . . . . .552
Figure 109.ADC y _AWD x _OUT signal generation (on a single regular channel) . . . . .552
Figure 110.ADC y _AWD x _OUT signal generation (on all injected channels) . . . . .552
Figure 111.20-bit to 16-bit result truncation . . . . .553
Figure 112.Numerical example with 5-bit shift and rounding . . . . .553
Figure 113.Triggered regular oversampling mode (TROVS bit = 1) . . . . .555
Figure 114.Regular oversampling modes (4x ratio) . . . . .556
Figure 115.Regular and injected oversampling modes used simultaneously . . . . .557
Figure 116.Triggered regular oversampling with injection . . . . .557
Figure 117.Oversampling in auto-injected mode . . . . .558
Figure 118.Dual ADC block diagram (1) . . . . .560
Figure 119.Injected simultaneous mode on 4 channels: dual ADC mode . . . . .561
Figure 120.Regular simultaneous mode on 16 channels: dual ADC mode . . . . .563
Figure 121.Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode. . . . .564
Figure 122.Interleaved mode on 1 channel in single conversion mode: dual ADC mode. . . . .565
Figure 123.Interleaved conversion with injection . . . . .565
Figure 124.Alternate trigger: injected group of each ADC . . . . .566
Figure 125.Alternate trigger: 4 injected channels (each ADC) in discontinuous mode. . . . .567
Figure 126.Alternate + regular simultaneous . . . . .568
Figure 127.Case of trigger occurring during injected conversion . . . . .568
Figure 128.Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . .569
Figure 129.Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first . . . . .		569
Figure 130.Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . .		569
Figure 131.DMA Requests in regular simultaneous mode when MDMA = 00 . . . . .570
Figure 132.DMA requests in regular simultaneous mode when MDMA = 10 . . . . .571
Figure 133.DMA requests in interleaved mode when MDMA = 10 . . . . .571
Figure 134.Temperature sensor channel block diagram . . . . .574
Figure 135.VBAT channel block diagram . . . . .575
Figure 136.VREFINT channel block diagram . . . . .576
Figure 137.Dual-channel DAC block diagram . . . . .616
Figure 138.Data registers in single DAC channel mode . . . . .618
Figure 139.Data registers in dual DAC channel mode . . . . .618
Figure 140.Timing diagram for conversion with trigger disabled TEN = 0 . . . . .619
Figure 141.DAC LFSR register calculation algorithm . . . . .621
Figure 142.DAC conversion (SW trigger enabled) with LFSR wave generation . . . . .621
Figure 143.DAC triangle wave generation . . . . .622
Figure 144.DAC conversion (SW trigger enabled) with triangle wave generation . . . . .622
Figure 145. DAC Sample and hold mode phase diagram . . . . .625
Figure 146. DCMI block diagram . . . . .651
Figure 147. Top-level block diagram . . . . .651
Figure 148. DCMI signal waveforms . . . . .652
Figure 149. Timing diagram . . . . .654
Figure 150. Frame capture waveforms in snapshot mode . . . . .656
Figure 151. Frame capture waveforms in continuous grab mode . . . . .657
Figure 152. Coordinates and size of the window after cropping . . . . .657
Figure 153. Data capture waveforms . . . . .658
Figure 154. Pixel raster scan order . . . . .659
Figure 155. Comparator block diagram . . . . .677
Figure 156. Window mode . . . . .679
Figure 157. Comparator hysteresis . . . . .680
Figure 158. Comparator output blanking . . . . .680
Figure 159. Standalone mode: external gain setting mode . . . . .690
Figure 160. Follower configuration . . . . .691
Figure 161. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . .692
Figure 162. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for filtering . . . . .693
Figure 163. Single DFSDM block diagram . . . . .704
Figure 164. Input channel pins redirection . . . . .708
Figure 165. Channel transceiver timing diagrams . . . . .711
Figure 166. Clock absence timing diagram for SPI . . . . .712
Figure 167. Clock absence timing diagram for Manchester coding . . . . .713
Figure 168. First conversion for Manchester coding (Manchester synchronization) . . . . .715
Figure 169. DFSDM_CHyDATINR registers operation modes and assignment . . . . .719
Figure 170. Example: Sinc3 filter response . . . . .721
Figure 171. LCD controller block diagram . . . . .763
Figure 172. 1/3 bias, 1/4 duty . . . . .765
Figure 173. Static duty case 1 . . . . .766
Figure 174. Static duty case 2 . . . . .767
Figure 175. 1/2 duty, 1/2 bias . . . . .768
Figure 176. 1/3 duty, 1/3 bias . . . . .769
Figure 177. 1/4 duty, 1/3 bias . . . . .770
Figure 178. 1/8 duty, 1/4 bias . . . . .771
Figure 179. LCD voltage control . . . . .774
Figure 180. Deadtime . . . . .775
Figure 181. SEG/COM mux feature example . . . . .780
Figure 182. Flowchart example . . . . .781
Figure 183. TSC block diagram . . . . .793
Figure 184. Surface charge transfer analog I/O group structure . . . . .794
Figure 185. Sampling capacitor voltage variation . . . . .795
Figure 186. Charge transfer acquisition sequence . . . . .796
Figure 187. Spread spectrum variation principle . . . . .798
Figure 188. RNG block diagram . . . . .812
Figure 189. Entropy source model . . . . .813
Figure 190. AES block diagram . . . . .822
Figure 191. ECB encryption and decryption principle . . . . .824
Figure 192. CBC encryption and decryption principle . . . . .825
Figure 193. CTR encryption and decryption principle . . . . .826
Figure 194. GCM encryption and authentication principle . . . . .827
Figure 195. GMAC authentication principle . . . . .827
Figure 196. CCM encryption and authentication principle . . . . .828
Figure 197. STM32 cryptolib AES flowchart examples . . . . .829
Figure 198. STM32 cryptolib AES flowchart examples (continued) . . . . .830
Figure 199. Encryption key derivation for ECB/CBC decryption (Mode 2). . . . .833
Figure 200. Example of suspend mode management . . . . .834
Figure 201. ECB encryption . . . . .835
Figure 202. ECB decryption . . . . .835
Figure 203. CBC encryption . . . . .836
Figure 204. CBC decryption . . . . .836
Figure 205. ECB/CBC encryption (Mode 1) . . . . .837
Figure 206. ECB/CBC decryption (Mode 3) . . . . .838
Figure 207. Message construction in CTR mode . . . . .840
Figure 208. CTR encryption . . . . .841
Figure 209. CTR decryption . . . . .841
Figure 210. Message construction in GCM . . . . .843
Figure 211. GCM authenticated encryption . . . . .844
Figure 212. Message construction in GMAC mode . . . . .848
Figure 213. GMAC authentication mode . . . . .848
Figure 214. Message construction in CCM mode . . . . .849
Figure 215. CCM mode authenticated decryption . . . . .851
Figure 216. 128-bit block construction with respect to data swap . . . . .855
Figure 217. DMA transfer of a 128-bit data block during input phase . . . . .857
Figure 218. DMA transfer of a 128-bit data block during output phase . . . . .858
Figure 219. AES interrupt signal generation . . . . .859
Figure 220. HASH block diagram . . . . .875
Figure 221. Message data swapping feature . . . . .877
Figure 222. HASH suspend/resume mechanism . . . . .883
Figure 223. Advanced-control timer block diagram . . . . .897
Figure 224. Counter timing diagram with prescaler division change from 1 to 2 . . . . .899
Figure 225. Counter timing diagram with prescaler division change from 1 to 4 . . . . .899
Figure 226. Counter timing diagram, internal clock divided by 1 . . . . .901
Figure 227. Counter timing diagram, internal clock divided by 2 . . . . .901
Figure 228. Counter timing diagram, internal clock divided by 4 . . . . .902
Figure 229. Counter timing diagram, internal clock divided by N . . . . .902
Figure 230. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .903
Figure 231. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .903
Figure 232. Counter timing diagram, internal clock divided by 1 . . . . .905
Figure 233. Counter timing diagram, internal clock divided by 2 . . . . .905
Figure 234. Counter timing diagram, internal clock divided by 4 . . . . .906
Figure 235. Counter timing diagram, internal clock divided by N . . . . .906
Figure 236. Counter timing diagram, update event when repetition counter is not used . . . . .907
Figure 237. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . .908
Figure 238. Counter timing diagram, internal clock divided by 2 . . . . .909
Figure 239. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .909
Figure 240. Counter timing diagram, internal clock divided by N . . . . .910
Figure 241. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . .910
Figure 242. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .911
Figure 243. Update rate examples depending on mode and TIMx_RCR register settings . . . . .912
Figure 244. External trigger input block . . . . .913
Figure 245. TIM1 ETR input circuitry . . . . .913
Figure 246. TIM8 ETR input circuitry . . . . .914
Figure 247. Control circuit in normal mode, internal clock divided by 1 . . . . .915
Figure 248. TI2 external clock connection example. . . . .916
Figure 249. Control circuit in external clock mode 1 . . . . .917
Figure 250. External trigger input block . . . . .917
Figure 251. Control circuit in external clock mode 2 . . . . .918
Figure 252. Capture/compare channel (example: channel 1 input stage) . . . . .919
Figure 253. Capture/compare channel 1 main circuit . . . . .920
Figure 254. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . .920
Figure 255. Output stage of capture/compare channel (channel 4). . . . .921
Figure 256. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . .921
Figure 257. PWM input mode timing . . . . .923
Figure 258. Output compare mode, toggle on OC1 . . . . .925
Figure 259. Edge-aligned PWM waveforms (ARR=8) . . . . .926
Figure 260. Center-aligned PWM waveforms (ARR=8). . . . .927
Figure 261. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .929
Figure 262. Combined PWM mode on channel 1 and 3 . . . . .930
Figure 263. 3-phase combined PWM signals with multiple trigger pulses per period . . . . .931
Figure 264. Complementary output with dead-time insertion . . . . .932
Figure 265. Dead-time waveforms with delay greater than the negative pulse . . . . .932
Figure 266. Dead-time waveforms with delay greater than the positive pulse. . . . .933
Figure 267. Break and Break2 circuitry overview . . . . .935
Figure 268. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . .937
Figure 269. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . .938
Figure 270. PWM output state following BRK assertion (OSSI=0) . . . . .939
Figure 271. Output redirection . . . . .939
Figure 272. Clearing TIMx_OCxREF . . . . .940
Figure 273. 6-step generation, COM example (OSSR=1) . . . . .941
Figure 274. Example of one pulse mode. . . . .942
Figure 275. Retriggerable one pulse mode . . . . .944
Figure 276. Example of counter operation in encoder interface mode. . . . .945
Figure 277. Example of encoder interface mode with TI1FP1 polarity inverted. . . . .946
Figure 278. Measuring time interval between edges on 3 signals . . . . .947
Figure 279. Example of Hall sensor interface . . . . .949
Figure 280. Control circuit in reset mode . . . . .950
Figure 281. Control circuit in Gated mode . . . . .951
Figure 282. Control circuit in trigger mode . . . . .952
Figure 283. Control circuit in external clock mode 2 + trigger mode . . . . .953
Figure 284. General-purpose timer block diagram . . . . .1002
Figure 285. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1004
Figure 286. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1004
Figure 287. Counter timing diagram, internal clock divided by 1 . . . . .1005
Figure 288. Counter timing diagram, internal clock divided by 2 . . . . .1006
Figure 289. Counter timing diagram, internal clock divided by 4 . . . . .1006
Figure 290. Counter timing diagram, internal clock divided by N . . . . .1007
Figure 291. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . .1007
Figure 292. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . .1008
Figure 293. Counter timing diagram, internal clock divided by 1 . . . . .1009
Figure 294. Counter timing diagram, internal clock divided by 2 . . . . .1009
Figure 295. Counter timing diagram, internal clock divided by 4 . . . . .1010
Figure 296. Counter timing diagram, internal clock divided by N . . . . .1010
Figure 297. Counter timing diagram, Update event . . . . .1011
Figure 298. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . .1012
Figure 299. Counter timing diagram, internal clock divided by 2 . . . . .1013
Figure 300. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . .1013
Figure 301. Counter timing diagram, internal clock divided by N . . . . .1014
Figure 302. Counter timing diagram, Update event with ARPE=1 (counter underflow) . . . . .1014
Figure 303. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . .1015
Figure 304. Control circuit in normal mode, internal clock divided by 1 . . . . .1016
Figure 305. TI2 external clock connection example . . . . .1016
Figure 306. Control circuit in external clock mode 1 . . . . .1017
Figure 307. External trigger input block . . . . .1018
Figure 308. Control circuit in external clock mode 2 . . . . .1019
Figure 309. Capture/Compare channel (example: channel 1 input stage) . . . . .1020
Figure 310. Capture/Compare channel 1 main circuit . . . . .1020
Figure 311. Output stage of Capture/Compare channel (channel 1) . . . . .1021
Figure 312. PWM input mode timing . . . . .1023
Figure 313. Output compare mode, toggle on OC1 . . . . .1025
Figure 314. Edge-aligned PWM waveforms (ARR=8) . . . . .1026
Figure 315. Center-aligned PWM waveforms (ARR=8) . . . . .1027
Figure 316. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . .1028
Figure 317. Combined PWM mode on channels 1 and 3 . . . . .1030
Figure 318. Clearing TIMx_OCxREF . . . . .1031
Figure 319. Example of one-pulse mode . . . . .1032
Figure 320. Retriggerable one-pulse mode . . . . .1034
Figure 321. Example of counter operation in encoder interface mode . . . . .1035
Figure 322. Example of encoder interface mode with TI1FP1 polarity inverted . . . . .1036
Figure 323. Control circuit in reset mode . . . . .1037
Figure 324. Control circuit in gated mode . . . . .1038
Figure 325. Control circuit in trigger mode . . . . .1039
Figure 326. Control circuit in external clock mode 2 + trigger mode . . . . .1040
Figure 327. Master/Slave timer example . . . . .1041
Figure 328. Master/slave connection example with 1 channel only timers . . . . .1041
Figure 329. Gating TIM2 with OC1REF of TIM3 . . . . .1042
Figure 330. Gating TIM2 with Enable of TIM3 . . . . .1043
Figure 331. Triggering TIM2 with update of TIM3 . . . . .1044
Figure 332. Triggering TIM2 with Enable of TIM3 . . . . .1044
Figure 333. Triggering TIM3 and TIM2 with TIM3_TI1 input . . . . .1045
Figure 334. TIM15 block diagram . . . . .1076
Figure 335. TIM16/TIM17 block diagram . . . . .1077
Figure 336. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1079
Figure 337. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1079
Figure 338. Counter timing diagram, internal clock divided by 1 . . . . .1081
Figure 339. Counter timing diagram, internal clock divided by 2 . . . . .1081
Figure 340. Counter timing diagram, internal clock divided by 4 . . . . .1082
Figure 341. Counter timing diagram, internal clock divided by N . . . . .1082
Figure 342. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . .1083
Figure 343. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . .1083
Figure 344. Update rate examples depending on mode and TIMx_RCR register settings . . . . .1085
Figure 345. Control circuit in normal mode, internal clock divided by 1 . . . . .1086
Figure 346. TI2 external clock connection example . . . . .1086
Figure 347. Control circuit in external clock mode 1 . . . . .1087
Figure 348. Capture/compare channel (example: channel 1 input stage) . . . . .1088
Figure 349. Capture/compare channel 1 main circuit . . . . .1088
Figure 350. Output stage of capture/compare channel (channel 1) . . . . .1089
Figure 351. Output stage of capture/compare channel (channel 2 for TIM15) . . . . .1089
Figure 352. PWM input mode timing . . . . .1091
Figure 353. Output compare mode, toggle on OC1 . . . . .1093
Figure 354. Edge-aligned PWM waveforms (ARR=8) . . . . .1094
Figure 355. Combined PWM mode on channel 1 and 2 . . . . .1095
Figure 356. Complementary output with dead-time insertion. . . . .1096
Figure 357. Dead-time waveforms with delay greater than the negative pulse. . . . .1096
Figure 358. Dead-time waveforms with delay greater than the positive pulse. . . . .1097
Figure 359. Break circuitry overview . . . . .1099
Figure 360. Output behavior in response to a break . . . . .1101
Figure 361. 6-step generation, COM example (OSSR=1) . . . . .1102
Figure 362. Example of one pulse mode . . . . .1103
Figure 363. Retriggerable one pulse mode . . . . .1105
Figure 364. Measuring time interval between edges on 2 signals . . . . .1106
Figure 365. Control circuit in reset mode . . . . .1107
Figure 366. Control circuit in gated mode . . . . .1108
Figure 367. Control circuit in trigger mode . . . . .1109
Figure 368. Basic timer block diagram. . . . .1160
Figure 369. Counter timing diagram with prescaler division change from 1 to 2 . . . . .1162
Figure 370. Counter timing diagram with prescaler division change from 1 to 4 . . . . .1162
Figure 371. Counter timing diagram, internal clock divided by 1 . . . . .1163
Figure 372. Counter timing diagram, internal clock divided by 2 . . . . .1164
Figure 373. Counter timing diagram, internal clock divided by 4 . . . . .1164
Figure 374. Counter timing diagram, internal clock divided by N . . . . .1165
Figure 375. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . .1165
Figure 376. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . .1166
Figure 377. Control circuit in normal mode, internal clock divided by 1 . . . . .1167
Figure 378. Low-power timer block diagram . . . . .1174
Figure 379. Glitch filter timing diagram . . . . .1176
Figure 380. LPTIM output waveform, single counting mode configuration . . . . .1178
Figure 381. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set). . . . .1178
Figure 382. LPTIM output waveform, Continuous counting mode configuration . . . . .1179
Figure 383. Waveform generation . . . . .1180
Figure 384. Encoder mode counting sequence . . . . .1183
Figure 385. IRTIM internal hardware connections with TIM16 and TIM17 . . . . .1195
Figure 386. Independent watchdog block diagram . . . . .1196
Figure 387. Watchdog block diagram . . . . .1206
Figure 388. Window watchdog timing diagram . . . . .1207
Figure 389. RTC block diagram . . . . .1213
Figure 390. Block diagram . . . . .1258
Figure 391. I 2 C-bus protocol . . . . .1260
Figure 392. Setup and hold timings . . . . .1262
Figure 393. I2C initialization flow . . . . .1264
Figure 394. Data reception . . . . .1265
Figure 395. Data transmission . . . . .1266
Figure 396. Slave initialization flow . . . . .1269
Figure 397. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0. . . . .1271
Figure 398. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1. . . . .1272
Figure 399. Transfer bus diagrams for I2C slave transmitter (mandatory events only) . . . . .1273
Figure 400. Transfer sequence flow for I2C slave receiver, NOSTRETCH = 0 . . . . .1274
Figure 401. Transfer sequence flow for I2C slave receiver, NOSTRETCH = 1 . . . . .1275
Figure 402. Transfer bus diagrams for I2C slave receiver
(mandatory events only) . . . . .		1275
Figure 403. Master clock generation . . . . .1277
Figure 404. Master initialization flow . . . . .1279
Figure 405. 10-bit address read access with HEAD10R = 0 . . . . .1279
Figure 406. 10-bit address read access with HEAD10R = 1 . . . . .1280
Figure 407. Transfer sequence flow for I2C master transmitter, N ≤ 255 bytes. . . . .1281
Figure 408. Transfer sequence flow for I2C master transmitter, N > 255 bytes . . . . .1282
Figure 409. Transfer bus diagrams for I2C master transmitter
(mandatory events only) . . . . .		1283
Figure 410. Transfer sequence flow for I2C master receiver, N ≤ 255 bytes . . . . .1285
Figure 411. Transfer sequence flow for I2C master receiver, N > 255 bytes. . . . .1286
Figure 412. Transfer bus diagrams for I2C master receiver
(mandatory events only) . . . . .		1287
Figure 413. Timeout intervals for \( t_{LOW:SEXT} \) , \( t_{LOW:MEXT} \) . . . . .1291
Figure 414. Transfer sequence flow for SMBus slave transmitter N bytes + PEC. . . . .1295
Figure 415. Transfer bus diagram for SMBus slave transmitter (SBC = 1) . . . . .1295
Figure 416. Transfer sequence flow for SMBus slave receiver N bytes + PEC. . . . .1297
Figure 417. Bus transfer diagrams for SMBus slave receiver (SBC = 1). . . . .1298
Figure 418. Bus transfer diagrams for SMBus master transmitter. . . . .1299
Figure 419. Bus transfer diagrams for SMBus master receiver . . . . .1301
Figure 420. USART block diagram . . . . .1325
Figure 421. Word length programming . . . . .1327
Figure 422. Configurable stop bits . . . . .1329
Figure 423. TC/TXE behavior when transmitting . . . . .1330
Figure 424. Start bit detection when oversampling by 16 or 8. . . . .1331
Figure 425. Data sampling when oversampling by 16. . . . .1335
Figure 426. Data sampling when oversampling by 8. . . . .1335
Figure 427. Mute mode using Idle line detection . . . . .1342
Figure 428. Mute mode using address mark detection . . . . .1343
Figure 429. Break detection in LIN mode (11-bit break length - LBDL bit is set). . . . .1346
Figure 430. Break detection in LIN mode vs. Framing error detection. . . . .1347
Figure 431. USART example of synchronous transmission. . . . .1348
Figure 432. USART data clock timing diagram (M bits = 00). . . . .1348
Figure 433. USART data clock timing diagram (M bits = 01) . . . . .1349
Figure 434. RX data setup/hold time . . . . .1349
Figure 435. ISO 7816-3 asynchronous protocol . . . . .1351
Figure 436. Parity error detection using the 1.5 stop bits . . . . .1352
Figure 437. IrDA SIR ENDEC- block diagram . . . . .1356
Figure 438. IrDA data modulation (3/16) - normal mode . . . . .1356
Figure 439. Transmission using DMA . . . . .1358
Figure 440. Reception using DMA . . . . .1359
Figure 441. Hardware flow control between 2 USARTs . . . . .1359
Figure 442. RS232 RTS flow control . . . . .1360
Figure 443. RS232 CTS flow control . . . . .1361
Figure 444. USART interrupt mapping diagram . . . . .1365
Figure 445. LPUART block diagram . . . . .1393
Figure 446. Word length programming . . . . .1395
Figure 447. Configurable stop bits . . . . .1396
Figure 448. TC/TXE behavior when transmitting . . . . .1398
Figure 449. Mute mode using Idle line detection . . . . .1405
Figure 450. Mute mode using address mark detection . . . . .1406
Figure 451. Transmission using DMA . . . . .1409
Figure 452. Reception using DMA . . . . .1410
Figure 453. Hardware flow control between 2 LPUARTs . . . . .1410
Figure 454. RS232 RTS flow control . . . . .1411
Figure 455. RS232 CTS flow control . . . . .1412
Figure 456. LPUART interrupt mapping diagram . . . . .1416
Figure 457. SPI block diagram. . . . .1433
Figure 458. Full-duplex single master/ single slave application. . . . .1434
Figure 459. Half-duplex single master/ single slave application . . . . .1435
Figure 460. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . .		1436
Figure 461. Master and three independent slaves. . . . .1437
Figure 462. Multimaster application. . . . .1438
Figure 463. Hardware/software slave select management . . . . .1439
Figure 464. Data clock timing diagram . . . . .1440
Figure 465. Data alignment when data length is not equal to 8-bit or 16-bit . . . . .1441
Figure 466. Packing data in FIFO for transmission and reception. . . . .1445
Figure 467. Master full-duplex communication . . . . .1448
Figure 468. Slave full-duplex communication . . . . .1449
Figure 469. Master full-duplex communication with CRC . . . . .1450
Figure 470. Master full-duplex communication in packed mode . . . . .1451
Figure 471. NSSP pulse generation in Motorola SPI master mode. . . . .1454
Figure 472. TI mode transfer . . . . .1455
Figure 473. SAI functional block diagram . . . . .1468
Figure 474. Audio frame . . . . .1472
Figure 475. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . .1474
Figure 476. FS role is start of frame (FSDEF = 0). . . . .1475
Figure 477. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . .1476
Figure 478. First bit offset . . . . .1476
Figure 479. Audio block clock generator overview . . . . .1477
Figure 480. AC'97 audio frame . . . . .1481
Figure 481. Example of typical AC'97 configuration on devices featuring at least
2 embedded SAIs (three external AC'97 decoders) . . . . .		1482
Figure 482. SPDIF format . . . . .1483
Figure 483. SAI_xDR register ordering . . . . .1484
Figure 484. Data companding hardware in an audio block in the SAI. . . . .1488
Figure 485. Tristate strategy on SD output line on an inactive slot . . . . .1489
Figure 486. Tristate on output data line in a protocol like I2S . . . . .1490
Figure 487. Overrun detection error. . . . .1491
Figure 488. FIFO underrun event . . . . .1491
Figure 489. S1 signal coding . . . . .1520
Figure 490. S2 signal coding . . . . .1520
Figure 491. SWPMI block diagram . . . . .1522
Figure 492. SWP bus states . . . . .1524
Figure 493. SWP frame structure . . . . .1525
Figure 494. SWPMI No software buffer mode transmission . . . . .1526
Figure 495. SWPMI No software buffer mode transmission, consecutive frames . . . . .1527
Figure 496. SWPMI Multi software buffer mode transmission. . . . .1529
Figure 497. SWPMI No software buffer mode reception . . . . .1531
Figure 498. SWPMI single software buffer mode reception. . . . .1532
Figure 499. SWPMI Multi software buffer mode reception . . . . .1534
Figure 500. SWPMI single buffer mode reception with CRC error. . . . .1535
Figure 501. “No response” and “no data” operations. . . . .1548
Figure 502. (Multiple) block read operation . . . . .1548
Figure 503. (Multiple) block write operation . . . . .1548
Figure 504. Sequential read operation. . . . .1549
Figure 505. Sequential write operation . . . . .1549
Figure 506. SDMMC block diagram. . . . .1549
Figure 507. SDMMC adapter. . . . .1551
Figure 508. Control unit . . . . .1552
Figure 509. SDMMC_CK clock dephasing (BYPASS = 0). . . . .1553
Figure 510. SDMMC adapter command path . . . . .1553
Figure 511. Command path state machine (SDMMC). . . . .1554
Figure 512. SDMMC command transfer . . . . .1555
Figure 513. Data path . . . . .1557
Figure 514. Data path state machine (DPSM). . . . .1558
Figure 515. CAN network topology . . . . .1608
Figure 516. Dual-CAN block diagram . . . . .1610
Figure 517. Single-CAN block diagram . . . . .1611
Figure 518. bxCAN operating modes. . . . .1613
Figure 519. bxCAN in silent mode . . . . .1614
Figure 520. bxCAN in Loop back mode. . . . .1614
Figure 521. bxCAN in combined mode . . . . .1615
Figure 522. Transmit mailbox states . . . . .1616
Figure 523. Receive FIFO states . . . . .1617
Figure 524. Filter bank scale configuration - Register organization. . . . .1620
Figure 525. Example of filter numbering . . . . .1621
Figure 526. Filtering mechanism example. . . . .1622
Figure 527. CAN error state diagram. . . . .1623
Figure 528. Bit timing . . . . .1625
Figure 529. CAN frames . . . . .1626
Figure 530. Event flags and interrupt generation. . . . .1627
Figure 531. CAN mailbox registers . . . . .1639
Figure 532. OTG_FS full-speed block diagram . . . . .1658
Figure 533. OTG_FS A-B device connection. . . . .1660
Figure 534. OTG_FS peripheral-only connection . . . . .1662
Figure 535. OTG_FS host-only connection . . . . .1666
Figure 536. SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . .1670
Figure 537. Updating OTG_HFIR dynamically (RLDCTRL = 1) . . . . .1672
Figure 538. Device-mode FIFO address mapping and AHB FIFO access mapping . . . . .1673
Figure 539. Host-mode FIFO address mapping and AHB FIFO access mapping. . . . .1674
Figure 540. Interrupt hierarchy. . . . .1678
Figure 541. Transmit FIFO write task . . . . .1764
Figure 542. Receive FIFO read task . . . . .1765
Figure 543. Normal bulk/control OUT/SETUP . . . . .1766
Figure 544. Bulk/control IN transactions . . . . .1770
Figure 545. Normal interrupt OUT . . . . .1773
Figure 546. Normal interrupt IN . . . . .1778
Figure 547. Isochronous OUT transactions . . . . .1780
Figure 548. Isochronous IN transactions . . . . .1783
Figure 549. Receive FIFO packet read . . . . .1787
Figure 550. Processing a SETUP packet . . . . .1789
Figure 551. Bulk OUT transaction . . . . .1796
Figure 552. TRDT max timing case . . . . .1806
Figure 553. A-device SRP . . . . .1807
Figure 554. B-device SRP . . . . .1808
Figure 555. A-device HNP . . . . .1809
Figure 556. B-device HNP . . . . .1811
Figure 557. Block diagram of STM32 MCU and Cortex®-M4-level debug support . . . . .1813
Figure 558. SWJ debug port . . . . .1815
Figure 559. JTAG TAP connections . . . . .1819
Figure 560. TPIU block diagram . . . . .1838

Chapters