36. Revision history

EMBEDDED SRAM and FLASH MEMORY:
Updated Section 1.1: System architecture and Section 2.3.1: Parity check.
Updated RDPRT description in Section 1.5.7: Option byte register (FLASH_OBR). Updated WRP3 at address 0x1FFF F80C in Table 8: Description of the option bytes.
Updated FLASH_SR register in Section 1.6: Flash register map.
Updated Table 8: Description of the option bytes.

PWR:
Updated Figure 1: Power supply overview (STM32F303x devices), Section 1.1: Power supplies introduction, and Section 1.1.1: Independent A/D and D/A converter supply and reference voltage.
Changed AN2586 to AN4206 in Section 1.1.2: Battery backup domain.
Added EWUP3, updated EWUP2 description, and added VREFINTRDYF bit in Section 1.4.2: Power control/status register (PWR_CSR).

RCC:
Added USART3EN, UART4EN and UART5EN in Table 1: RCC register map and reset values.
Changed max. LSI clock frequency to 50 kHz in Section 1.2.5: LSI clock. Added Section 1.2.12: I2S clock (only in STM32F303xB/C and STM32F358xC).
Updated Section 1.4.2: Clock configuration register (RCC_CFGR), SYSCFGRST in Section 1.4.4: APB2 peripheral reset register (RCC_APB2RSTR), SPI2RST/SPI3RST Section 1.4.5: APB1 peripheral reset register (RCC_APB1RSTR), and ADC34EN/ADC12EN in Section 1.4.6: AHB peripheral clock enable register (RCC_AHBENR).
Replaced APB by APB2 in Section 1.4.4: APB2 peripheral reset register (RCC_APB2RSTR).
Updated Section 1.4.5: APB1 peripheral reset register (RCC_APB1RSTR) and Section 1.4.2: Clock configuration register (RCC_CFGR).
Updated Section 1.4.14: RCC register map.

GPIOs:
Updated GPIOA_OSPEEDR and GPIOB_OSPEEDR reset value in Table 23: GPIO register map and reset values
Replaced JTMS/SWDAT by JTMS/SWDIO in Section 9.3.1: General-purpose I/O (GPIO).
Added note related to GPIOF_MODER in Section 9.4.1: GPIO port mode register (GPIOx_MODER) (x = A..F).
Section 9.4.12: GPIO register map: updated GPIOA_MODER reset value, added GPIOB_MODER, GPIOA_OSPEEDR, GPIOB_OSPEEDR, GPIOB_PUPDR, update GPIOA_PUPDR reset value, updated GPIOx_LCKR register.

SYSCFG:
Updated Section 1.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1), Section 1.1.6: SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) and Section 1.1.7: SYSCFG configuration register 2 (SYSCFG_CFGR2).

DMA:
Updated Figure 22: DMA block diagram.
Modified Figure 11.3.7: DMA request mapping.

INTERRUPTS and EVENTS:
Updated Table 1: STM32F302xB/C vector table.
Modified address offsets for EXTI_IMR2, EXTI_EMR2, EXTI_RTSR2, EXTI_FTSR2: 0x2C, EXTI_SWIER2, and EXTI_PR2.
Updated note related to EXTI_FTSR1 in Section 13.3.4 and Section 13.3.10.
Updated note in Section 1.3.7: Interrupt mask register (EXTI_IMR2).
Section 1.3.13: EXTI register map

ADC:
Updated Section 1.1: Introduction. Updated Figure 1: ADC block diagram, Figure 3: ADC1 and ADC2 connectivity, and Figure 4: ADC3 & ADC4 connectivity. Added Section 1.3.5: Slave AHB interface.
Updated caution note and note in Section 1.3.7: Single-ended and differential input channels. Modified Section 1.3.8: Calibration (ADCAL, ADCALDIF, ADC_CALFACT).
Changed ADC_CALFACT_S and ADC_CALFACT_D, by CALFACT_S and CALFACT_D, respectively.

ADC (continued)

Updated step3 of Section : Converting single-ended and differential analog inputs with a single ADC .

Corrected the table name of Table: ADC3 & ADC4 - External trigger for regular channels .

Removed table Minimum sampling time to be respected for fast channels and related examples in Section: Channel-wise programmable sampling time (SMPR1, SMPR2) and reference made to the datasheet instead.

Updated Section: Stopping an ongoing conversion (ADSTP, JADSTP) .

Added note to Section: Auto-injection mode .

Removed double buffer mode in Section: Managing conversions using the DMA .

Regular simultaneous mode with independent injected .

Updated Figure: Flushing JSQR queue of context by setting JADSTP=1 (JQM=0) . Case when JADSTP occurs outside an ongoing conversion and added Section: Disabling the queue .

Updated Section: Auto-delayed conversion mode (AUTDLY) , Section:

DAC:

Changed TIM5 into TIM15, and AIEC line9 into EXTI line9 in Table 50: External triggers. Changed TIM5 into TIM15 in the description of bits 21:19 of DAC_CR.

COMP:

Changed COMPx_OUT_TIM_SEL to COMPxOUTSEL in COMPx_CSR registers (x = 1 to 7) (see Section 18).

Replaced COMP1SW1 by COMP1_INP_DAC in Section 15.5.1: COMP1 control and status register (COMP1_CSR).

Replaced COMP2_WINDOW_MODE by COMP2WINMODE in Section 15.5.2: COMP2 control and status register (COMP2_CSR).

OPAMP:

Replaced AOPx by OPAMPx in Section 1: Operational amplifier (OPAMP).

Updated Section 1.3: OPAMP functional description introduction and added Section 1.3.2: Clock.

OPAMPx_CSR registers (Section 18.4.1 to Section 18.4.4) changed OUT-CAL, CAL_SEL, and CAL_ON to OUTCAL, CALSEL, CALON in OPAMPx_CSR registers (x = 1 to 4). Set access right to 'rw' for TSTREF. Renamed OPAMPx_EN bits into OPAMPxEN.

Replaced any occurrence of VOPAMPx with VREFOPAMPx.

RTC

Changed power-on reset to backup domain reset in the whole section.

Updated Section 24.7.15: RTC tamper and alternate function configuration register (RTC_TAFCR).

SPI/I2S:
Remove CRC error in Section 27.6: SPI interrupts.

CAN
Updated Figure 317: Bit timing

Advanced control timers (TIM1/8):
Corrected Figure 1: Advanced-control timer block diagram.
Updated Section 1.3.15: Using the break function.
Updated Section 1.3.15: Using the break function

General purpose timers (TIM2/3/4):
Updated Section 1.4.3: TIMx slave mode control register (TIMx_SMCR). Modified UIF bit in Section 1.4.5: TIMx status register (TIMx_SR). Updated Section 1.4.6: TIMx event generation register (TIMx_EGR) and Section 1.4.9: TIMx capture/compare enable register (TIMx_CCER).

General purpose timers (TIM15/16/17):
Updated Figure 2: TIM16 and TIM17 block diagram.
Updated Section 1.4.13: Using the break function

I2C:
Updated Figure 212: Setup and hold timings.
Updated Table 75: Comparison of analog vs. digital filters.
Corrected Figure 228: Transfer sequence flowchart for I2C master transmitter for N>255 bytes. Removed maximum values of parameter “Data hold time” and added row “Data valid time” in Table 76: I2C-SMBUS specification data setup and hold times.
Added Section 25.5: I2C low-power modes.
Added caution note in Section 25.4.15: Wakeup from Stop mode on address match.
Moved Section 24.7: I2C debug mode to Section 25.7.7: Interrupt and Status register (I2Cx_ISR).
Modified definition of ARLO bit in Section 25.7.7: Interrupt and Status register (I2Cx_ISR).

USART:

Updated Section 25.5.10: LIN (local interconnection network) mode on page 663

Removed note on bit 19(RWU) in Section 25.8.8: USART interrupt and status register (USART_ISR) on page 682.

Updated Table 99: USART features to remove DMA for USART5.

Replaced in Bit 2 MMRQ Section 25.7.7: Request register (USART_RQR) “resets the RWU flag” by “sets the RWU flag”

Added ‘In Smartcard, LIN and IrDA modes, only Oversampling by 16 is supported’ in Section 25.5.4: Baud rate generation

Corrected and updated stop bits in Figure 198: Word length programming.

TSC:

Changed power-on reset value to reset value in Section 28.6.2: TSC interrupt enable register (TSC_IER).

DEBUG:

Updated Figure 3: JTAG TAP connections

Modified scope of document from “STM32F302xx, STM32F303xx, STM32F313xx” to “STM32F303xB/xC, STM32F303x4/x6/x8, STM32F328xx and STM32F358xx”.

Reordered sections of the manual.

Added Section 1: Overview of the manual

Removed ‘always read at "0" (w_r0)’ in Section 1: Documentation conventions.

CRC:

Removed first iteration of the CRC v2 fully programmable polynomial in Section 5.2: CRC main features.

EMBEDDED SRAM and FLASH MEMORY:

Updated Table 2: Flash memory read protection status

Updated SRAM description in Section 3.3: Embedded SRAM

DAC:

Added DAC2 for STM32F303x4/6/8 devices

Replaced "VDDA" by "VREF+" in Section 14.3.5: DAC output voltage

COMP:

Added ‘(BRK)’ and ‘(BRK2)’ to the COMPxOUTSEL bit descriptions in the Section 15.5: COMP registers

Updated figures in Section 15.3.1: COMP block diagram. (SYSCFG_CFGR3)

ADC:
Updated Section 1.2: ADC main features
Updated Section 1.3.6: ADC voltage regulator (ADVREGEN)
Updated Section 1.3.3: Clocks

OPAMP
Updated Figure 3: STM32F303x6/8 and STM32F328x8 comparator and operational amplifier connections.

DMA:
Added Table 24: STM32F303x6/8 and STM32F328x8 DMA1 request mapping
Added Table 29: STM32F303x6/8 and STM32F328x8 summary of DMA1 requests for each channel

System configuration controller:
Added STM32F303x4/6/8 dedicated bits in Section 1.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1)
Added Section 1.1.8: SYSCFG configuration register 3
Updated Section 1.3.11: Channel selection (SQRx, JSQRx)
Changed ADC1_IN18 to ADC1_IN17 in Section 1.3.31: VBAT supply monitoring
Replaced DEEPPWD and ADVREGEN bits of ADCx_CR by ADVREGEN[1:0]
Updated Section 1.6.2: ADC common control register (ADCx_CCR, x=12 or 34)

Interrupts:
Added Table 1: STM32F302xB/C vector table
Removed 'or by changing the sensitivity of the edge detector.' in Section 1.3.6: Pending register (EXTI_PR1) and Section 1.3.12: Pending register (EXTI_PR2) and updated bit description of Section 1.3.5: Software interrupt event register (EXTI_SWIER1) and Section 1.3.11: Software interrupt event register (EXTI_SWIER2)
Updated the programming manual reference sentence in Section 1.2.1: Main features

PWR:
Updated bit0 'WUF' description in Section 1.4.1: Power control register (PWR_CR)
Updated the mode entry note in Table 4: Stop mode
Added Figure 2: Power supply overview (STM32F3x8 devices).

IRTIM:
Swapped TIM16 and TIM17 in Figure 203: IR internal hardware connections with TIM16 and TIM17

RCC:
Replaced 'PCLK' with 'SYSCLK' in the I2CxSW bits description of Section 1.4.13: Clock configuration register 3 (RCC_CFGR3)
Modified note (2) under Figure 2: STM32F303xB/C and STM32F358xC clock tree.

Advanced control timers (TIM1/8):
Modified Section 1.3.15: Using the break function.

RTC:
Updated WUT input clock in Figure 207: RTC block diagram in STM32F03x, STM32F04x and STM32F05x devices
Corrected bit SHPF read and clear parameters in Section 24.7.4: RTC initialization and status register (RTC_ISR)

I2C:
Updated t _HD ;DAT in Table 76: I2C-SMBUS specification data setup and hold times
Replaced 50ns into t _AF (min) and 260ns into t _AF (max) in section I2C timings
Added Access paragraph with wait state information on all registers

USART:
Updated Mode 2 and 3 in Section 25.5.6: Auto baud rate detection
Corrected TXFRQ description in Section 25.7.7: Request register (USART_RQR)
Modified Note: regarding USARTDIV in Section 26.5.4: Baud rate generation

System and memory overview
Section 3.1: System architecture

System configuration controller (SYSCFG)
Section 10.1.8: SYSCFG configuration register 3 (SYSCFG_CFGR3)

Analog-to-digital converter (ADC)
Section 13.3.18: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN)
Figure 30: ADC1 and ADC2 connectivity
Figure 31: ADC3 & ADC4 connectivity

Digital to analog converter (DAC)
Figure 89: DAC1 block diagram

Operational amplifier
Figure 104: STM32F303xB/C and STM32F358xC Comparators and operational amplifiers interconnections (part 1)
Figure 105: STM32F303xB/C and STM32F358xC comparators and operational amplifiers interconnections (part 2)

Comparator
Section 15.5.2: COMP2 control and status register (COMP2_CSR)

Digital-to-analog converter (DAC)
Figure 89: DAC1 block diagram

Serial peripheral interface / inter-IC sound (SPI/I2S)
Table 116: STM32F303xB/C and STM32F358xC SPI implementation

Universal synchronous asynchronous receiver transmitter (USART)
Feature list
Table 107: STM32F3xx USART features
Section 27.5.2: Transmitter
Section 27.7.1: Control register 1 (USARTx_CR1)

Extended the applicability to STM32F303xD/E.
Added Section 8: Peripheral interconnect matrix.
Updated the following:

Cover page

Flexible memory controller (FMC)
Added the chapter (applies to STM32F303xD/E only).

System and memory overview
Section 3.1: System architecture

Embedded Flash memory
Section 4.1: Flash main features
Section 4.2.1: Flash memory organization

Reset and clock control (RCC)
Section 9.2.10: Timers (TIMx) clock
Section 9.4.2: Clock configuration register (RCC_CFGR)

System configuration controller (SYSCFG)
Section 11.1.1: SYSCFG configuration register 1 (SYSCFG_CFGR1)
Section 11.1.2: SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1)
Section 11.1.7: SYSCFG register map

Direct memory access controller (DMA)
Table 80: STM32F303xB/C/D/E, STM32F358xC and STM32F398xE summary of DMA2 requests for each channel

Interrupts and events
Table 40: STM32F302xB/C/D/E vector table

Analog to digital converter (ADC)
Table: ADC1 (master) & 2 (slave) - External triggers for regular channels
Table: ADC1 & ADC2 - External trigger for injected channels
Table: ADC3 & ADC4 - External trigger for regular channels
Table: ADC3 & ADC4 - External trigger for injected channels

Comparator (COMP)
Section 18.2: COMP main features
Figure 123: STM32F303xB/C/D/E, STM32F358xC and STM32F398xE comparator 7 block diagram
Table 108: Comparator input/output summary
Section 18.6: COMP registers

Advanced-control timers (TIM1/TIM8/TIM20)
Introduced the TIM20 for STM32F303xD/E

Inter-integrated circuit (I2C) interface)
Table 142: STM32F3xx I2C implementation

Universal synchronous asynchronous receiver transmitter (USART)
Table 218: STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx USART features

Serial peripheral interface / inter-IC sound (SPI/I2S)
Table 167: STM32F303xB/C/D/E, STM32F358xC and STM32F398xE SPI implementation

Universal serial bus full-speed device interface (USB)
Table: STM32F3xx USB implementation

Reset and clock control (RCC)
Added notes about UARTSW2[1:0] and UARTSW3[1:0] availability for the STM32F3xx covered by this document in Section 9.4.13: Clock configuration register 3 (RCC_CFGR3),
Updated bit 23 (V18PWRRSTF) name and description in Section 9.4.10: Control/status register (RCC_CSR).

Flexible static memory controller (FSMC)
Renamed the section as “Static memory controller”
Updated bit BUSTURN description in Section : SRAM/NOR-Flash chip-select timing registers 1..4 (FMC_BTR1..4),
Updated the maximum value for memory setup time and memory hold in Table 37: Programmable NOR/PSRAM access parameters,
Updated MEMSET, MEMHOLD and MEMHIZ bit descriptions of FMC_PMEM register in Section : Common memory space timing register 2..4 (FMC_PMEM2..4),
Updated ATTSET, ATTHOLD and ATTHIZ bit descriptions of FMC_PATT register in Section : Attribute memory space timing registers 2..4 (FMC_PATT2..4),
Updated BURSTRUN bit description of FMC_BTR1..4 register in Section : SRAM/NOR-Flash chip-select timing registers 1..4 (FMC_BTR1..4).

Analog-to-digital converters (ADC)
Updated the number of ADC1 and ADC2 channels for STM32F303x6/8 and STM32F328 in Table 84: ADC external channels mapping.

Advanced-control timers (TIM1/TIM8/TIM20)
Bit SMS description in Section 20.4.3: TIM1/TIM8/TIM20 slave mode control register (TIMx_SMCR).

Basic timers (TIM6/TIM7)
Updated Bit MMS description in Section 22.4.2: TIM6/TIM7 control register 2 (TIMx_CR2).

General-purpose timers (TIM15/16/17)
Updated IC1F[3:0] bit description in Section 23.6.6: TIM16&TIM17 capture/compare mode register 1 (TIMx_CCMR1).

Universal synchronous asynchronous receiver transmitter (USART)
Updated the DMA support for UART5 in Table 158: STM32F3xx USART features.

Controller area network (bxCAN)
Replaced tCAN with tq

Universal serial bus full-speed device interface (USB)
Added LPM register descriptions.

Updated I2C2 section:
Updated Figure 387: Setup and hold timings.
Updated Section 38.4.5: I2C initialization updating and adding notes in Section : I2C timings.
Updated Section 28.7.5: Timing register (I2C_TIMINGR) SCLDEL[3:0] and SDADEL[3:0] bits description.
Updated Section 38.4.5: I2C initialization, Section 38.4.9: I2C master mode and Section 28.7.5: Timing register (I2C_TIMINGR) adding the sentence “The STM32CubeMX tool calculates and provides the I2C_TIMIGR content in the I2C configuration window”.

Updated Touch sensing controller section:
Updated Section 23.3.4: Charge transfer acquisition sequence adding note about the TSC control register configuration forbidden.
Updated Section 23.6.1: TSC control register (TSC_CR) adding note for CTPL[3:0] bits and PGPSC[2:0] bits.

Updated USART section:
Updated Section 25.5.17: Wake-up from Stop mode using USART adding paragraph “how to determine the maximum USART baudrate”.
Updated whole USART document replacing any occurrence of: nCTS by CTS, nRTS by RTS, SCLK by CK.
Updated Section 25.8.9: USART interrupt flag clear register (USART_ICR) replacing “w” by “rc_wl”.
Updated Section 25.8.8: USART interrupt and status register (USART_ISR) RTOF field replacing USARTx_CR2 by USARTx_CR1.
Updated Section 25.8.3: USART control register 3 (USART_CR3) ‘ONEBIT’ bit 11 description adding a note.
Updated Section 25: Universal synchronous/asynchronous receiver transmitter (USART/UART) changing register name USARTx_regname in USART_regname.

Updated RTC section:
Updated WUCKSEL bits in Figure 281: RTC block diagram.
Added case of RTC clocked by LSE in Section 27.3.9: Resetting the RTC.
Updated Figure 281: RTC block diagram adding note.
Updated Section 27.6.16: RTC tamper and alternate function configuration register (RTC_TAFCR) adding note on TAMP3 bits, and TAMP2E and TAMP2TRG in black in the register.

Updated TIMER section:

Updated Section 41.3.13: One-pulse mode modifying “IC2S=01” by “CC2S=01”.

Updated Section 26.3.16: Slave mode – combined reset + trigger mode adding (TIM15 only) on the title.

Updated Section 133.6.8: TIM15 capture/compare mode register 1 [alternate] (TIM15_CCMR1) and Section 133.6.26: TIM15 register map replacing bit 7 ‘reserved’ by OC1CE.

Updated Section 26.4.6: TIMx capture/compare mode register 1 (TIMx_CCMR1)(x = 16 to 17) and Section 26.4.23: TIM16/TIM17 register map replacing bit 7 ‘reserved’ by OC1CE.

Updated Figure 24: Advanced-control timer (TIM1), Section 41: General-purpose timers (TIM2/TIM3), Section 44: Basic timers (TIM6/TIM7) and Section 26: General-purpose timers (TIM16/TIM17) PSC[15:0] bits description.

Updated Section 24.4.5: TIM1 status register (TIM1_SR) and Section 119.4.65: TIM1/TIM8 register map CC5IF and CC6IF bit names.

Updated FMC section:

Updated Section 14.5.4: NOR flash/PSRAM controller asynchronous transactions putting ‘de-asserting the NOE signal’.

Updated Section : FIFO status and interrupt register x (FMC_SRx) bit0 (IRS) and Bit2 (IFS) adding a note.

Updated Section : SRAM/NOR-flash chip-select timing registers x (FMC_BTRx) adding new paragraph.

Updated Section : SRAM/NOR-flash write timing registers x (FMC_BWTRx) adding new paragraph.

Updated Figure 52: NAND flash/PC Card controller waveforms for common memory access replacing ‘MEMxHIZ’ by ‘MEMxHIZ+1’ and adding note 2.

Updated Section 14.6.5: NAND flash prewait functionality.

Updated Common memory space timing register x (FMC_PMEMx) MEMHOLD[7:0] description.

Updated Attribute memory space timing registers x (FMC_PATTx) ATTHOLD[7:0] description.

Updated Section 14.3: AHB interface.

Updated Figure 46: Muxed write access waveforms correct NWE falling edge.

Updated Embedded Flash memory:

Updated Section 4.5.1: Flash access control register (FLASH_ACR) bits LATENCY[2:0] replacing SYSCLK by HCLK.

Updated ADC section:

Updated Section 15.3.3: Clocks note, replacing option a) by option b) and removing ‘or 10’.

Operational amplifier section (OPAMP):
Updated Table 108: Connections with dedicated I/O on STM32F303xB/C/D/E, STM32F358xC and STM32F398xE.

Updated DEBUG section:
Updated Section 33.6.1: MCU device ID code DBGMCU_IDCODE description.

Updated comparator section:
Updated Figure 122: Comparator 1 and 2 block diagrams (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE) adding note 4.
Updated Section 17.5.2: COMP2 control and status register (COMP2_CSR), Section 17.5.4: COMP4 control and status register (COMP4_CSR) and Section 17.5.6: COMP6 control and status register (COMP6_CSR) modifying note 3 and the bit 9 description.

Updated interrupts and events section:
Updated Section 13.2.6: External and internal interrupt/event line mapping line 26/28/29/31/33 and adding note for EXTI lines.

Updated USB section:
Updated Table 1354: STM32G4 Series USB implementation removing 'and STM32F358xC'.

Updated comparator section:
Updated Table 108: Comparator input/output summary.
Updated root part numbers in:
Section 18.1: Introduction.
Section 18.2: COMP main features.
Section 17.5.1: COMP1 control and status register (COMP1_CSR).
Section 17.5.2: COMP2 control and status register (COMP2_CSR)
Section 17.5.3: COMP3 control and status register (COMP3_CSR).
Section 17.5.4: COMP4 control and status register (COMP4_CSR)
Section 17.5.5: COMP5 control and status register (COMP5_CSR).
Section 17.5.6: COMP6 control and status register (COMP6_CSR)
Section 17.5.7: COMP7 control and status register (COMP7_CSR).
Updated Section 17.5.2: COMP2 control and status register (COMP2_CSR) note in the bit 7 description replacing 'PA3' by 'PA7'.
Added note 'depending on the product, when a timer is not available, the corresponding combination is reserved' in all the COMPxOUTSEL[3:0] bit description for x = 1...7 and COMPx_BLANKING bit description for x = 4...7.
Updated Figure 122: Comparator 1 and 2 block diagrams (STM32F303xB/C/D/E, STM32F358xC and STM32F398xE).
Updated Figure 123: STM32F303xB/C/D/E, STM32F358xC and STM32F398xE comparator 7 block diagram

Updated USART section:
Updated Section 25.8.8: USART interrupt and status register (USART_ISR) RWU bit available independently of the wakeup from stop feature availability.
Updated Section 25.8.12: USART register map RWU bit.

Updated RTC section:
Updated Figure 286: RTC block diagram removing 1 Hz and 512 Hz text and changing mux connections (ck_spre by ck_apre).
Updated note in Section 29.4.14: Calibration clock output.
Updated ADD1H and SUB1H bit descriptions in Section 29.7.3: RTC control register (RTC_CR).
Updated Section : RTC backup registers and Section 29.7.20: RTC backup registers (RTC_BKPxR): RTC_BKPxR registers cannot be reset when the Flash readout protection is disabled.

Updated CRC section:
Added Table 140: CRC internal input/output signals in Section 20.3.2: CRC internal signals.

Updated OPAMP section:
Updated Figure 120: STM32F302xB/C/D/E and STM32F302x6/8 Comparators and operational amplifiers interconnections (part 1).
Updated Figure 121: STM32F303xB/C/D/E and STM32F358xC Comparators and operational amplifiers interconnections (part 2 ).

Updated the following sections:

Section : Introduction (minor updates)

Section 4.5.1: Flash access control register (FLASH_ACR) (minor updates).

Section 14.3.6: Pending register (EXTI_PR1) (Reset value)

Section 14.3.12: Pending register (EXTI_PR2) (Reset value)

Section 4.2.3: Flash program and erase operations (Page erase, Option byte programming).

Section 9.1.2: System reset (system reset introduction).

Section 7.4.1: Power control register (PWR_CR) (PVD, PLS).

Section 33.4.2: Flexible SWJ-DP pin assignment (Note removed).

Section 7.1.2: Battery backup domain (minor update).

Section 9.4.6: AHB peripheral clock enable register (RCC_AHBENR) (GPIO).

Section 9.4.11: AHB peripheral reset register (RCC_AHBRSTR) (GPIO).

Section 9.4.14: RCC register map (RCC_AHBENR, RCC_AHBRSTR).

Section 4.3.1: Read protection (Note removed).

Section 9.4.7: APB2 peripheral clock enable register (RCC_APB2ENR) (Addition of COMP on bit 0).

Section 17.3.3: COMP reset and clocks (APB2, clock enable bit)

Section 17.5.1: COMP1 control and status register (COMP1_CSR) (COMP1MODE[1:0])

Section 27.3.4: Real-time clock and calendar (RTCCLK)

Section 9.4.3: Clock interrupt register (RCC_CIR) (Changed "xxxRDYDIE" into "xxxRDYE").

Section 6: Cyclic redundancy check calculation unit (CRC) (General updates).

Section 13: Direct memory access controller (DMA) (General updates).

Section 20: Advanced-control timers (TIM1/TIM8/TIM20) , Section 21: General-purpose timers (TIM2/TIM3/TIM4) , Section 22: Basic timers (TIM6/TIM7) and Section 23: General-purpose timers (TIM15/TIM16/TIM17) (General updates).

Section 25: Independent watchdog (IWDG) (General updates).

Section 28: Inter-integrated circuit interface (I2C) (General updates).

Section 30: Serial peripheral interface / integrated interchip sound (SPI/I2S) (General updates).

Section 29: Universal synchronous/asynchronous receiver transmitter (USART/UART) (General updates).

Section 32.6: USB and USB SRAM registers (USB RAM).

Minor terminology changes were applied to this document.

Added the following sections:

Section 35: Important security notice