10. Flexible static memory controller (FSMC)

Note: Only the STM32F303xD/E and STM32F398xE devices include the FSMC.

The Flexible static memory controller (FSMC) includes two memory controllers:

• • The NOR/PSRAM memory controller
• • The NAND/PC Card memory controller

This memory controller is also named Flexible memory controller (FMC).

10.1 FMC main features

The FMC functional block makes the interface with: synchronous and asynchronous static memories, and 16-bit PC card memory. Its main purposes are:

• • to translate AHB transactions into the appropriate external device protocol
• • to meet the access time requirements of the external memory devices

All external memories share the addresses, data and control signals with the controller. Each external device is accessed by means of a unique Chip Select. The FMC performs only one access at a time to an external device.

The main features of the FMC are the following:

• • Interface with static-memory mapped devices including:
  • – Static random access memory (SRAM)
  • – NOR flash memory/OneNAND flash memory
  • – PSRAM (4 memory banks)
  • – 16-bit PC Card compatible devices
  • – Two banks of NAND flash memory with ECC hardware to check up to 8 Kbytes of data
• • Burst mode support for faster access to synchronous devices such as NOR flash memory, PSRAM
• • Programmable continuous clock output for asynchronous and synchronous accesses
• • 8-, 16-bit wide data bus
• • Independent Chip Select control for each memory bank
• • Independent configuration for each memory bank
• • Write enable and byte lane select outputs for use with PSRAM, SRAM devices
• • External asynchronous wait control
• • Write Data FIFO with 16 x33-bit depth
• • Write Address FIFO with 16x30-bit depth

The FMC embeds two Write FIFOs: a Write Data FIFO with a 16x33-bit depth and a Write Address FIFO with a 16x30-bit depth.

• • The Write Data FIFO stores the AHB data to be written to the memory (up to 32 bits) plus one bit for the AHB transfer (burst or not sequential mode)
• • The Write Address FIFO stores the AHB address (up to 28 bits) plus the AHB data size (up to 2 bits). When operating in burst mode, only the start address is stored except

when crossing a page boundary (for PSRAM). In this case, the AHB burst is broken into two FIFO entries.

At startup the FMC pins must be configured by the user application. The FMC I/O pins which are not used by the application can be used for other purposes.

The FMC registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up. However, the settings can be changed at any time.

10.2 Block diagram

The FMC consists of the following main blocks:

• • The AHB interface (including the FMC configuration registers)
• • The NOR flash/PSRAM/SRAM controller
• • The NAND flash/PC Card controller
• • The external device interface

The block diagram is shown in Figure 18 .

Figure 18. FMC block diagram

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10.3 AHB interface

The AHB slave interface allows internal CPUs and other bus master peripherals to access the external memories.

AHB transactions are translated into the external device protocol. In particular, if the selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split into consecutive 16- or 8-bit accesses. The FMC Chip Select (FMC_NEx) does not toggle between the consecutive accesses except in case of access mode D when the extended mode is enabled.

The FMC generates an AHB error in the following conditions:

• • When reading or writing to an FMC bank (Bank 1 to 4) which is not enabled.
• • When reading or writing to the NOR flash bank while the FACCEN bit is reset in the FMC_BCRx register.
• • When reading or writing to the PC Card banks while the FMC_CD input pin (Card Presence Detection) is low.

The effect of an AHB error depends on the AHB master which has attempted the R/W access:

• • If the access has been attempted by the Cortex™-M4 with FPU CPU, a hard fault interrupt is generated.
• • If the access has been performed by a DMA controller, a DMA transfer error is generated and the corresponding DMA channel is automatically disabled.

The AHB clock (HCLK) is the reference clock for the FMC.

10.3.1 Supported memories and transactions

General transaction rules

The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the accessed external device has a fixed data width. This may lead to inconsistent transfers.

Therefore, some simple transaction rules must be followed:

• • AHB transaction size and memory data size are equal
  There is no issue in this case.

• • AHB transaction size is greater than the memory size:

In this case, the FMC splits the AHB transaction into smaller consecutive memory accesses to meet the external data width. The FMC Chip Select (FMC_NEx) does not toggle between the consecutive accesses.

• • AHB transaction size is smaller than the memory size:

The transfer may or not be consistent depending on the type of external device:

• – Accesses to devices that have the byte select feature (SRAM, ROM, PSRAM)

In this case, the FMC allows read/write transactions and accesses the right data through its byte lanes NBL[1:0].

Bytes to be written are addressed by NBL[1:0].

All memory bytes are read (NBL[1:0] are driven low during read transaction) and the useless ones are discarded.

• – Accesses to devices that do not have the byte select feature (NOR and NAND flash memories)

This situation occurs when a byte access is requested to a 16-bit wide flash memory. Since the device cannot be accessed in byte mode (only 16-bit words can be read/written from/to the flash memory), Write transactions and Read transactions are allowed (the controller reads the entire 16-bit memory word and uses only the required byte).

Configuration registers

The FMC can be configured through a set of registers. Refer to Section 10.5.6 , for a detailed description of the NOR flash/PSRAM controller registers. Refer to Section 10.6.8 , for a detailed description of the NAND flash/PC Card registers.

10.4 External device address mapping

From the FMC point of view, the external memory is divided into fixed-size banks of 256 Mbytes each (see Figure 19 ):

• • Bank 1 used to address up to 4 NOR flash memory or PSRAM devices. This bank is split into 4 NOR/PSRAM subbanks with 4 dedicated Chip Selects, as follows:
  • – Bank 1 - NOR/PSRAM 1
  • – Bank 1 - NOR/PSRAM 2
  • – Bank 1 - NOR/PSRAM 3
  • – Bank 1 - NOR/PSRAM 4
• • Banks 2 and 3 used to address NAND flash memory devices (1 device per bank)
• • Bank 4 used to address a PC Card

For each bank the type of memory to be used can be configured by the user application through the Configuration register.

Figure 19. FMC memory banks

10.4.1 NOR/PSRAM address mapping

HADDR[27:26] bits are used to select one of the four memory banks as shown in Table 34 .

Table 34. NOR/PSRAM bank selection

1. HADDR are internal AHB address lines that are translated to external memory.

The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte address whereas the memory is addressed at word level, the address actually issued to the memory varies according to the memory data width, as shown in the following table.

Table 35. NOR/PSRAM External memory address

1. 1. In case of a 16-bit external memory width, the FMC internally uses HADDR[25:1] to generate the address for external memory FMC_A[24:0].
   Whatever the external memory width, FMC_A[0] should be connected to external memory address A[0].

Wrap support for NOR flash/PSRAM

Wrap burst mode for synchronous memories is not supported. The memories must be configured in linear burst mode of undefined length.

10.4.2 NAND flash memory/PC Card address mapping

In this case, three banks are available, each of them being divided into memory areas as indicated in Table 36 .

Table 36. NAND/PC Card memory mapping and timing registers

For NAND flash memory, the common and attribute memory spaces are subdivided into three sections (see in Table 37 below) located in the lower 256 Kbytes:

• • Data section (first 64 Kbytes in the common/attribute memory space)
• • Command section (second 64 Kbytes in the common / attribute memory space)
• • Address section (next 128 Kbytes in the common / attribute memory space)

Table 37. NAND bank selection

The application software uses the 3 sections to access the NAND flash memory:

• • To sending a command to NAND flash memory , the software must write the command value to any memory location in the command section.
• • To specify the NAND flash address that must be read or written , the software must write the address value to any memory location in the address section. Since an address can be 4 or 5 bytes long (depending on the actual memory size), several

consecutive write operations to the address section are required to specify the full address.

• • To read or write data , the software reads or writes the data from/to any memory location in the data section.

Since the NAND flash memory automatically increments addresses, there is no need to increment the address of the data section to access consecutive memory locations.

10.5 NOR flash/PSRAM controller

The FMC generates the appropriate signal timings to drive the following types of memories:

• • Asynchronous SRAM and ROM
  • – 8 bits
  • – 16 bits
• • PSRAM (Cellular RAM)
  • – Asynchronous mode
  • – Burst mode for synchronous accesses
  • – Multiplexed or non-multiplexed
• • NOR flash memory
  • – Asynchronous mode
  • – Burst mode for synchronous accesses
  • – Multiplexed or non-multiplexed

The FMC outputs a unique Chip Select signal, NE[4:1], per bank. All the other signals (addresses, data and control) are shared.

The FMC supports a wide range of devices through a programmable timings among which:

• • Programmable wait states (up to 15)
• • Programmable bus turnaround cycles (up to 15)
• • Programmable output enable and write enable delays (up to 15)
• • Independent read and write timings and protocol to support the widest variety of memories and timings
• • Programmable continuous clock (FMC_CLK) output.

The FMC Clock (FMC_CLK) is a submultiple of the HCLK clock. It can be delivered to the selected external device either during synchronous accesses only or during asynchronous and synchronous accesses depending on the CCKEN bit configuration in the FMC_BCR1 register:

• • If the CCKEN bit is reset, the FMC generates the clock (CLK) only during synchronous accesses (Read/write transactions).
• • If the CCKEN bit is set, the FMC generates a continuous clock during asynchronous and synchronous accesses. To generate the FMC_CLK continuous clock, Bank 1 must be configured in synchronous mode (see Section 10.5.6: NOR/PSRAM controller registers ). Since the same clock is used for all synchronous memories, when a continuous output clock is generated and synchronous accesses are performed, the AHB data size has to be the same as the memory data width (MWID) otherwise the FMC_CLK frequency is changed depending on AHB data transaction (refer to Section 10.5.5: Synchronous transactions for FMC_CLK divider ratio formula).

The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured through dedicated registers (see Section 10.5.6: NOR/PSRAM controller registers ).

The programmable memory parameters include access times (see Table 38 ) and support for wait management (for PSRAM and NOR flash accessed in burst mode).

Table 38. Programmable NOR/PSRAM access parameters

10.5.1 External memory interface signals

Table 39 , Table 40 and Table 41 list the signals that are typically used to interface with NOR flash memory, SRAM and PSRAM.

Note: The prefix “N” identifies the signals which are active low.

NOR flash memory, non-multiplexed I/Os

Table 39. Non-multiplexed I/O NOR flash memory

The maximum capacity is 512 Mbits (26 address lines).

The maximum capacity is 512 Mbits.

The maximum capacity is 512 Mbits.

The maximum capacity is 512 Mbits (26 address lines).

10.5.2 Supported memories and transactions

Table 43 shows an example of the supported devices, access modes and transactions when the memory data bus is 16-bit wide for NOR flash memory, PSRAM and SRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in this example.

Table 43. NOR flash/PSRAM: example of supported memories and transactions

10.5.3 General timing rules

Signals synchronization

• All controller output signals change on the rising edge of the internal clock (HCLK)
• In synchronous mode (read or write), all output signals change on the rising edge of HCLK. Whatever the CLKDIV value, all outputs change as follows:
  • NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the falling edge of FMC_CLK clock.
  • NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising edge of FMC_CLK clock.

10.5.4 NOR flash/PSRAM controller asynchronous transactions

Asynchronous static memories (NOR flash, PSRAM, SRAM)

• • Signals are synchronized by the internal clock HCLK. This clock is not issued to the memory
• • The FMC always samples the data before de-asserting the NOE signal. This guarantees that the memory data hold timing constraint is met (minimum Chip Enable high to data transition is usually 0 ns)
• • If the extended mode is enabled (EXTMOD bit is set in the FMC_BCRx register), up to four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and D modes for read and write operations. For example, read operation can be performed in mode A and write in mode B.
• • If the extended mode is disabled (EXTMOD bit is reset in the FMC_BCRx register), the FMC can operate in mode 1 or mode 2 as follows:
  • – Mode 1 is the default mode when SRAM/PSRAM memory type is selected (MTYP = 0x0 or 0x01 in the FMC_BCRx register)
  • – Mode 2 is the default mode when NOR memory type is selected (MTYP = 0x10 in the FMC_BCRx register)

Mode 1 - SRAM/PSRAM (CRAM)

The next figures show the read and write transactions for the supported modes followed by the required configuration of FMC_BCRx, and FMC_BTRx/FMC_BWTRx registers.

Figure 20. Mode 1 read access waveforms

Figure 21. Mode 1 write access waveforms

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The one HCLK cycle at the end of the write transaction helps guarantee the address and data hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the DATAST value must be greater than zero (DATAST > 0).

Table 44. FMC_BCRx bitfields (mode 1)

Mode A - SRAM/PSRAM (CRAM) OE toggling

Figure 22. Mode A read access waveforms

• 1. NBL[1:0] are driven low during the read access

Figure 23. Mode A write access waveforms

The differences compared with mode 1 are the toggling of NOE and the independent read and write timings.

Table 46. FMC_BCRx bitfields (mode A)

Table 47. FMC_BTRx bitfields (mode A)

Table 48. FMC_BWTRx bitfields (mode A)

Mode 2/B - NOR flash

Figure 24. Mode 2 and mode B read access waveforms

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Figure 25. Mode 2 write access waveforms

Figure 26. Mode B write access waveforms

The differences with mode 1 are the toggling of NWE and the independent read and write timings when extended mode is set (mode B).

Table 51. FMC_BWTRx bitfields (mode 2/B)

Note: The FMC_BWTRx register is valid only if the extended mode is set (mode B), otherwise its content is don't care.

Mode C - NOR flash - OE toggling

Figure 27. Mode C read access waveforms

Figure 28. Mode C write access waveforms

The differences compared with mode 1 are the toggling of NOE and the independent read and write timings.

Table 52. FMC_BCRx bitfields (mode C)

Mode D - asynchronous access with extended address

Figure 29. Mode D read access waveforms

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Figure 30. Mode D write access waveforms

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The differences with mode 1 are the toggling of NOE that goes on toggling after NADV changes and the independent read and write timings.

Table 55. FMC_BCRx bitfields (mode D)

Table 56. FMC_BTRx bitfields (mode D)

Table 57. FMC_BWTRx bitfields (mode D)

Muxed mode - multiplexed asynchronous access to NOR flash memory

Figure 31. Muxed read access waveforms

Figure 32. Muxed write access waveforms

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The difference with mode D is the drive of the lower address byte(s) on the data bus.

Table 58. FMC_BCRx bitfields (Muxed mode)

WAIT management in asynchronous accesses

If the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to accept or to provide data, the ASYNCWAIT bit has to be set in FMC_BCRx register.

If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access phase (Data setup phase), programmed by the DATAST bits, is extended until WAIT becomes inactive. Unlike the data setup phase, the first access phases (Address setup and Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT sensitive and so they are not prolonged.

The data setup phase must be programmed so that WAIT can be detected 4 HCLK cycles before the end of the memory transaction. The following cases must be considered:

1. 1. The memory asserts the WAIT signal aligned to NOE/NWE which toggles:

1. 2. The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
   if

then:

otherwise

where \( \max\_wait\_assertion\_time \) is the maximum time taken by the memory to assert the WAIT signal once NEx/NOE/NWE is low.

Figure 33 and Figure 34 show the number of HCLK clock cycles that are added to the memory access phase after WAIT is released by the asynchronous memory (independently of the above cases).

Figure 33. Asynchronous wait during a read access waveforms

1. 1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.

Figure 34. Asynchronous wait during a write access waveforms

1. 1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.

10.5.5 Synchronous transactions

The memory clock, FMC_CLK, is a submultiple of HCLK. It depends on the value of CLKDIV and the MWID/ AHB data size, following the formula given below:

Whatever WID size: 16 or 8-bit, the FMC_CLK divider ratio is always defined by the programmed CLKDIV value.

Example:

• • If CLKDIV=1, MWID = 16 bits, AHB data size=8 bits, FMC_CLK=HCLK/2.

NOR flash memories specify a minimum time from NADV assertion to CLK high. To meet this constraint, the FMC does not issue the clock to the memory during the first internal clock cycle of the synchronous access (before NADV assertion). This guarantees that the rising edge of the memory clock occurs in the middle of the NADV low pulse.

Data latency versus NOR memory latency

The data latency is the number of cycles to wait before sampling the data. The DATLAT value must be consistent with the latency value specified in the NOR flash configuration register. The FMC does not include the clock cycle when NADV is low in the data latency count.

Caution: Some NOR flash memories include the NADV Low cycle in the data latency count, so that the exact relation between the NOR flash latency and the FMC DATLAT parameter can be either:

• • NOR flash latency = (DATLAT + 2) CLK clock cycles
• • or NOR flash latency = (DATLAT + 3) CLK clock cycles

Some recent memories assert NWAIT during the latency phase. In such cases DATLAT can be set to its minimum value. As a result, the FMC samples the data and waits long enough to evaluate if the data are valid. Thus the FMC detects when the memory exits latency and real data are processed.

Other memories do not assert NWAIT during latency. In this case the latency must be set correctly for both the FMC and the memory, otherwise invalid data are mistaken for good data, or valid data are lost in the initial phase of the memory access.

Single-burst transfer

When the selected bank is configured in burst mode for synchronous accesses, if for example an AHB single-burst transaction is requested on 16-bit memories, the FMC performs a burst transaction of length 1 (if the AHB transfer is 16 bits), or length 2 (if the AHB transfer is 32 bits) and de-assert the Chip Select signal when the last data is strobed.

Such transfers are not the most efficient in terms of cycles compared to asynchronous read operations. Nevertheless, a random asynchronous access would first require to re-program the memory access mode, which would altogether last longer.

Wait management

For synchronous NOR flash memories, NWAIT is evaluated after the programmed latency period, which corresponds to (DATLAT+2) CLK clock cycles.

If NWAIT is active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait states are inserted until NWAIT is inactive (high level when WAITPOL = 0, low level when WAITPOL = 1).

When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1) or on the next clock edge (bit WAITCFG = 0).

During wait-state insertion via the NWAIT signal, the controller continues to send clock pulses to the memory, keeping the Chip Select and output enable signals valid. It does not consider the data as valid.

In burst mode, there are two timing configurations for the NOR flash NWAIT signal:

• • The flash memory asserts the NWAIT signal one data cycle before the wait state (default after reset).
• • The flash memory asserts the NWAIT signal during the wait state

The FMC supports both NOR flash wait state configurations, for each Chip Select, thanks to the WAITCFG bit in the FMC_BCRx registers (x = 0..3).

Figure 35. Wait configuration waveforms

Figure 36. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM)

1. 1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held low).

Table 60. FMC_BCRx bitfields (Synchronous multiplexed read mode)

Figure 37. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)

1. 1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.
2. 2. Byte lane (NBL) outputs are not shown, they are held low while NEx is active.

Table 62. FMC_BCRx bitfields (Synchronous multiplexed write mode)

10.5.6 NOR/PSRAM controller registers

SRAM/NOR-flash chip-select control registers x (FMC_BCRx)

Address offset: 0x00 + 0x8 * (x - 1), (x = 1 to 4)

Reset value: 0x0000 30DB, 0x0000 30D2, 0x0000 30D2, 0x0000 30D2

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR flash memories.

Bits 31: 21 Reserved, must be kept at reset value

Bit 20 CCLKEN : Continuous Clock Enable.

This bit enables the FMC_CLK clock output to external memory devices.

0: The FMC_CLK is only generated during the synchronous memory access (read/write transaction). The FMC_CLK clock ratio is specified by the programmed CLKDIV value in the FMC_BCRx register (default after reset).

1: The FMC_CLK is generated continuously during asynchronous and synchronous access. The FMC_CLK clock is activated when the CCLKEN is set.

Note: The CCLKEN bit of the FMC_BCR2..4 registers is don't care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock.

Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don't care.

Note: If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)

Bit 19 CBURSTRW : Write burst enable.

For PSRAM (CRAM) operating in burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register.

0: Write operations are always performed in asynchronous mode

1: Write operations are performed in synchronous mode.

Bits 18:16 Reserved, must be kept at reset value

Bit 15 ASYNCWAIT : Wait signal during asynchronous transfers

This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol.

0: NWAIT signal is not taken in to account when running an asynchronous protocol (default after reset)

1: NWAIT signal is taken in to account when running an asynchronous protocol

This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations.

• 0: values inside FMC_BWTR register are not taken into account (default after reset)
• 1: values inside FMC_BWTR register are taken into account

Note: When the extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows:

• – Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01)
• – Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).

This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode.

• 0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the programmed flash latency period)
• 1: NWAIT signal is enabled (its level is taken into account after the programmed latency period to insert wait states if asserted) (default after reset)

This bit indicates whether write operations are enabled/disabled in the bank by the FMC:

• 0: Write operations are disabled in the bank by the FMC, an AHB error is reported,
• 1: Write operations are enabled for the bank by the FMC (default after reset).

The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:

• 0: NWAIT signal is active one data cycle before wait state (default after reset),
• 1: NWAIT signal is active during wait state (not used for PSRAM).

Defines whether the controller splits or does not split an AHB burst wrap access into two linear accesses. Valid only when accessing memories in burst mode

• 0: Direct wrapped burst is not enabled (default after reset),
• 1: Direct wrapped burst is enabled.

Note: This bit has no effect as the CPU and DMA cannot generate wrapping burst transfers.

Defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:

• 0: NWAIT active low (default after reset),
• 1: NWAIT active high.

This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in burst mode:

• 0: Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode.
• 1: Burst mode enable. Read accesses are performed in synchronous mode.

Enables NOR flash memory access operations.

• 0: Corresponding NOR flash memory access is disabled
• 1: Corresponding NOR flash memory access is enabled (default after reset)

• Bits 5:4 MWID : Memory data bus width.
  Defines the external memory device width, valid for all type of memories.
  • 00: 8 bits
  • 01: 16 bits (default after reset)
  • 10: reserved, do not use
  • 11: reserved, do not use
• Bits 3:2 MTYP : Memory type.
  Defines the type of external memory attached to the corresponding memory bank:
  • 00: SRAM (default after reset for Bank 2...4)
  • 01: PSRAM (CRAM)
  • 10: NOR flash/OneNAND flash (default after reset for Bank 1)
  • 11: reserved
• Bit 1 MUXEN : Address/data multiplexing enable bit.
  When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:
  • 0: Address/Data nonmultiplexed
  • 1: Address/Data multiplexed on databus (default after reset)
• Bit 0 MBKEN : Memory bank enable bit.
  Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AHB bus.
  • 0: Corresponding memory bank is disabled
  • 1: Corresponding memory bank is enabled

SRAM/NOR-flash chip-select timing registers x (FMC_BTRx)

Address offset: \( 0x04 + 0x8 \times (x - 1) \) , (x = 1 to 4)

Reset value: 0x0FFF FFFF

Reset value: 0x0FFF FFFF

This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR flash memories. If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses ( FMC_BWTRx registers).

Bits 31:30 Reserved, must be kept at reset value

Bits 29:28 ACCMOD : Access mode

Specifies the asynchronous access modes as shown in the timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.

00: access mode A

01: access mode B

10: access mode C

11: access mode D

Bits 27:24 DATLAT : (see note below bit descriptions): Data latency for synchronous memory

For synchronous access with read/write burst mode enabled (BURSTEN / CBURSTRW bits set), defines the number of memory clock cycles (+2) to issue to the memory before reading/writing the first data:

This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods.

For asynchronous access, this value is don't care.

0000: Data latency of 2 CLK clock cycles for first burst access

1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)

Bits 23:20 CLKDIV : Clock divide ratio (for FMC_CLK signal)

Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles:

0000: Reserved

0001: FMC_CLK period = \( 2 \times \) HCLK periods

0010: FMC_CLK period = \( 3 \times \) HCLK periods

1111: FMC_CLK period = \( 16 \times \) HCLK periods (default value after reset)

In asynchronous NOR flash, SRAM or PSRAM accesses, this value is don't care.

Note: Refer to Section 10.5.5: Synchronous transactions for FMC_CLK divider ratio formula

These bits are written by software to add a delay at the end of a write-to-read (and read-to-write) transaction. This delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the memory to free the data bus after a read access (tEHQZ). The programmed bus turnaround delay is inserted between an asynchronous read (muxed or mode D) or write transaction and any other asynchronous /synchronous read or write to or from a static bank. The bank can be the same or different in case of read, in case of write the bank can be different except for muxed or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows:

1. • • The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for modes muxed and D.
   • • There is a bus turnaround delay of 1 FMC clock cycle between:
     • –Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D.
     • –An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except for modes muxed and D.
     • –An asynchronous (modes 1, 2, A, B or C) read and a read from another static bank.
   • • There is a bus turnaround delay of 2 FMC clock cycle between:
     • –Two consecutive synchronous writes (burst or single) to the same bank.
     • –A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or different for the case of read).
     • –Two consecutive synchronous reads (burst or single) followed by any synchronous/asynchronous read or write from/to another static memory bank.
   • • There is a bus turnaround delay of 3 FMC clock cycle between:
     • –Two consecutive synchronous writes (burst or single) to different static bank.
2. A synchronous write (burst or single) access and a synchronous read from the same or a different bank.

0000: BUSTURN phase duration = 0 HCLK clock cycle added

...

1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)

These bits are written by software to define the duration of the data phase (refer to Figure 20 to Figure 32 ), used in asynchronous accesses:

0000 0000: Reserved

0000 0001: DATAST phase duration = 1 × HCLK clock cycles

0000 0010: DATAST phase duration = 2 × HCLK clock cycles

...

1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)

For each memory type and access mode data-phase duration, refer to the respective figure ( Figure 20 to Figure 32 ).

Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK clock cycles.

Note: In synchronous accesses, this value is don't care.

These bits are written by software to define the duration of the address hold phase (refer to Figure 20 to Figure 32 ), used in mode D or multiplexed accesses:

0000: Reserved

0001: ADDHLD phase duration = 1 × HCLK clock cycle

0010: ADDHLD phase duration = 2 × HCLK clock cycle

...

1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)

For each access mode address-hold phase duration, refer to the respective figure ( Figure 20 to Figure 32 ).

Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration.

These bits are written by software to define the duration of the address setup phase (refer to Figure 20 to Figure 32 ), used in SRAMs, ROMs and asynchronous NOR flash:

0000: ADDSET phase duration = 0 × HCLK clock cycle

...

1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)

For each access mode address setup phase duration, refer to the respective figure (refer to Figure 20 to Figure 32 ).

Note: In synchronous accesses, this value is don't care.

In Muxed mode or mode D, the minimum value for ADDSET is 1.

Note: PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these memories issue the NWAIT signal during the whole latency phase to prolong the latency as needed.

With PSRAMs (CRAMs) the filled DATLAT must be set to 0, so that the FMC exits its latency phase soon and starts sampling NWAIT from memory, then starts to read or write when the memory is ready.

This method can be used also with the latest generation of synchronous flash memories that issue the NWAIT signal, unlike older flash memories (check the datasheet of the specific flash memory being used).

SRAM/NOR-flash write timing registers x (FMC_BWTRx)

Address offset: \( 0x104 + 0x8 * (x - 1) \) , ( \( x = 1 \) to 4)

Reset value: 0x0FFF FFFF

This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access.

Bits 31:30 Reserved, must be kept at reset value

Bits 29:28 ACCMOD : Access mode.

Specifies the asynchronous access modes as shown in the next timing diagrams. These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.

• 00: access mode A
• 01: access mode B
• 10: access mode C
• 11: access mode D

Bits 27:20 Reserved, must be kept at reset value

Bits 19:16 BUSTURN : Bus turnaround phase duration

The programmed bus turnaround delay is inserted between an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. The bank can be the same or different in case of read, in case of write the bank can be different except for mixed or mode D.

In some cases, whatever the programmed BUSTURN values, the bus turnaround delay is fixed as follows:

• • The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for modes mixed and D.
• • There is a bus turnaround delay of 2 FMC clock cycle between:
  • –Two consecutive synchronous writes (burst or single) to the same bank.
  • –A synchronous write (burst or single) transfer and an asynchronous write or read transfer to or from static memory bank.
• • There is a bus turnaround delay of 3 FMC clock cycle between:
  • –Two consecutive synchronous writes (burst or single) to different static bank.
  • –A synchronous write (burst or single) transfer and a synchronous read from the same or a different bank.

0000: BUSTURN phase duration = 0 HCLK clock cycle added

...

1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)

Bits 15:8 DATAST : Data-phase duration.

These bits are written by software to define the duration of the data phase (refer to Figure 20 to Figure 32 ), used in asynchronous SRAM, PSRAM and NOR flash memory accesses:

0000 0000: Reserved

0000 0001: DATAST phase duration = 1 × HCLK clock cycles

0000 0010: DATAST phase duration = 2 × HCLK clock cycles

...

1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)

Bits 7:4 ADDHLD : Address-hold phase duration.

These bits are written by software to define the duration of the address hold phase (refer to Figure 20 to Figure 32 ), used in asynchronous multiplexed accesses:

0000: Reserved

0001: ADDHLD phase duration = 1 × HCLK clock cycle

0010: ADDHLD phase duration = 2 × HCLK clock cycle

...

1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)

Note: In synchronous NOR flash accesses, this value is not used, the address hold phase is always 1 flash clock period duration.

Bits 3:0 ADDSET : Address setup phase duration.

These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 20 to Figure 32 ), used in asynchronous accesses:

0000: ADDSET phase duration = 0 × HCLK clock cycle

...

1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)

Note: In synchronous accesses, this value is not used, the address setup phase is always 1 flash clock period duration. In muxed mode, the minimum ADDSET value is 1.

10.6 NAND flash/PC Card controller

The FMC generates the appropriate signal timings to drive the following types of device:

• • 8- and 16-bit NAND flash memories
• • 16-bit PC Card compatible devices

The NAND flash/PC Card controller can control three external banks, Bank 2, 3 and 4:

• • Bank 2 and Bank 3 support NAND flash devices
• • Bank 4 supports PC Card devices.

Each bank is configured through dedicated registers ( Section 10.6.8 ). The programmable memory parameters include access timings (shown in Table 64 ) and ECC configuration.

10.6.1 External memory interface signals

The following tables list the signals that are typically used to interface NAND flash memory and PC Card.

Note: The prefix “N” identifies the signals which are active low.

8-bit NAND flash memory

Theoretically, there is no capacity limitation as the FMC can manage as many address cycles as needed.

Theoretically, there is no capacity limitation as the FMC can manage as many address cycles as needed.

10.6.2 NAND flash / PC Card supported memories and transactions

Table 68 shows the supported devices, access modes and transactions. Transactions not allowed (or not supported) by the NAND flash / PC Card controller are shown in gray.

Table 68. Supported memories and transactions

10.6.3 Timing diagrams for NAND flash memory and PC Card

Each PC Card/Compactflash and NAND flash memory bank is managed through a set of registers:

• • Control register: FMC_PCRx
• • Interrupt status register: FMC_SRx
• • ECC register: FMC_ECCRx
• • Timing register for Common memory space: FMC_PMEMx
• • Timing register for Attribute memory space: FMC_PATTx
• • Timing register for I/O space: FMC_PIOx

Each timing configuration register contains three parameters used to define number of HCLK cycles for the three phases of any PC Card/Compactflash or NAND flash access, plus one parameter that defines the timing for starting driving the data bus when a write access is performed. Figure 38 shows the timing parameter definitions for common memory accesses, knowing that Attribute and I/O (only for PC Card) memory space access timings are similar.

Figure 38. NAND flash/PC Card controller waveforms for common memory access

1. 1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses.
2. 2. For write access, the hold phase delay is (MEMHOLD) HCLK cycles and for read access is (MEMHOLD + 2) HCLK cycles.

10.6.4 NAND flash operations

The command latch enable (CLE) and address latch enable (ALE) signals of the NAND flash memory device are driven by address signals from the FMC. This means that to send a command or an address to the NAND flash memory, the CPU has to perform a write to a specific address in its memory space.

A typical page read operation from the NAND flash device requires the following steps:

1. 3. Program and enable the corresponding memory bank by configuring the FMC_PCRx and FMC_PMEMx (and for some devices, FMC_PATTx, see Section 10.6.5: NAND flash prewait functionality ) registers according to the characteristics of the NAND flash memory (PWID bits for the data bus width of the NAND flash, PTYP = 1, PWAITEN = 0 or 1 as needed, see section Section 10.4.2: NAND flash memory/PC Card address mapping for timing configuration).
2. 4. The CPU performs a byte write to the common memory space, with data byte equal to one flash command byte (for example 0x00 for Samsung NAND flash devices). The LE input of the NAND flash memory is active during the write strobe (low pulse on NWE), thus the written byte is interpreted as a command by the NAND flash memory. Once the command is latched by the memory device, it does not need to be written again for the following page read operations.
3. 5. The CPU can send the start address (STARTAD) for a read operation by writing four bytes (or three for smaller capacity devices), STARTAD[7:0], STARTAD[16:9], STARTAD[24:17] and finally STARTAD[25] (for 64 Mb x 8 bit NAND flash memories) in the common memory or attribute space. The ALE input of the NAND flash device is active during the write strobe (low pulse on NWE), thus the written bytes are interpreted as the start address for read operations. Using the attribute memory space makes it possible to use a different timing configuration of the FMC, which can be used

to implement the prewait functionality needed by some NAND flash memories (see details in Section 10.6.5: NAND flash prewait functionality ).

1. 6. The controller waits for the NAND flash memory to be ready (R/NB signal high), before starting a new access to the same or another memory bank. While waiting, the controller holds the NCE signal active (low).
2. 7. The CPU can then perform byte read operations from the common memory space to read the NAND flash page (data field + Spare field) byte by byte.
3. 8. The next NAND flash page can be read without any CPU command or address write operation. This can be done in three different ways:
   • – by simply performing the operation described in step 5
   • – a new random address can be accessed by restarting the operation at step 3
   • – a new command can be sent to the NAND flash device by restarting at step 2

10.6.5 NAND flash prewait functionality

Some NAND flash devices require that, after writing the last part of the address, the controller waits for the R/NB signal to go low. (see Figure 39 ).

Figure 39. Access to non 'CE don't care' NAND-flash

1. 1. CPU wrote byte 0x00 at address 0x7001 0000.
2. 2. CPU wrote byte A7~A0 at address 0x7002 0000.
3. 3. CPU wrote byte A16~A9 at address 0x7002 0000.
4. 4. CPU wrote byte A24~A17 at address 0x7002 0000.
5. 5. CPU wrote byte A25 at address 0x7802 0000: FMC performs a write access using FMC_PATT2 timing definition, where \( ATTHOLD \geq 7 \) (providing that \( (7+1) \times HCLK = 112 \text{ ns} > t_{WB} \text{ max} \) ). This guarantees that NCE remains low until R/NB goes low and high again (only requested for NAND flash memories where NCE is not don't care).

When this functionality is required, it can be ensured by programming the MEMHOLD value to meet the \( t_{WB} \) timing. However any CPU read access to the NAND flash memory has a hold delay of (MEMHOLD + 2) HCLK cycles and CPU write access has a hold delay of (MEMHOLD) HCLK cycles inserted between the rising edge of the NWE signal and the next access.

To cope with this timing constraint, the attribute memory space can be used by programming its timing register with an ATTHOLD value that meets the \( t_{WB} \) timing, and by keeping the MEMHOLD value at its minimum value. The CPU must then use the common memory space for all NAND flash read and write accesses, except when writing the last address byte to the NAND flash device, where the CPU must write to the attribute memory space.

10.6.6 Computation of the error correction code (ECC) in NAND flash memory

The FMC PC Card controller includes two error correction code computation hardware blocks, one per memory bank. They reduce the host CPU workload when processing the ECC by software.

These two ECC blocks are identical and associated with Bank 2 and Bank 3. As a consequence, no hardware ECC computation is available for memories connected to Bank 4.

The ECC algorithm implemented in the FMC can perform 1-bit error correction and 2-bit error detection per 256, 512, 1 024, 2 048, 4 096 or 8 192 bytes read or written from/to the NAND flash memory. It is based on the Hamming coding algorithm and consists in calculating the row and column parity.

The ECC modules monitor the NAND flash data bus and read/write signals (NCE and NWE) each time the NAND flash memory bank is active.

The ECC operates as follows:

• • When accessing NAND flash memory bank 2 or bank 3, the data present on the D[15:0] bus is latched and used for ECC computation.
• • When accessing any other address in NAND flash memory, the ECC logic is idle, and does not perform any operation. As a result, write operations to define commands or addresses to the NAND flash memory are not taken into account for ECC computation.

Once the desired number of bytes has been read/written from/to the NAND flash memory by the host CPU, the FMC_ECCR2/3 registers must be read to retrieve the computed value. Once read, they should be cleared by resetting the ECCEN bit to '0'. To compute a new data block, the ECCEN bit must be set to one in the FMC_PCR2/3 registers.

To perform an ECC computation:

1. 1. Enable the ECCEN bit in the FMC_PCR2/3 register.
2. 2. Write data to the NAND flash memory page. While the NAND page is written, the ECC block computes the ECC value.
3. 3. Read the ECC value available in the FMC_ECCR2/3 register and store it in a variable.
4. 4. Clear the ECCEN bit and then enable it in the FMC_PCR2/3 register before reading back the written data from the NAND page. While the NAND page is read, the ECC block computes the ECC value.
5. 5. Read the new ECC value available in the FMC_ECCR2/3 register.
6. 6. If the two ECC values are the same, no correction is required, otherwise there is an ECC error and the software correction routine returns information on whether the error can be corrected or not.

10.6.7 PC Card/CompactFlash operations

Address spaces and memory accesses

The FMC supports CompactFlash devices and PC Cards in Memory mode and I/O mode (True IDE mode is not supported).

The CompactFlash and PC Cards are made of 3 memory spaces:

• • Common Memory space
• • Attribute space
• • I/O Memory space

The nCE2 and nCE1 pins (FMC_NCE4_2 and FMC_NCE4_1 respectively) select the card and indicate whether a byte or a word operation is being performed: nCE2 accesses the odd byte on D15-8 and nCE1 accesses the even byte on D7-0 if A0=0 or the odd byte on D7-0 if A0=1. The full word is accessed on D15-0 if both nCE2 and nCE1 are low.

The memory space is selected by asserting low nOE for read accesses or nWE for write accesses, combined with the low assertion of nCE2/nCE1 and nREG.

• • If pin nREG=1 during the memory access, the common memory space is selected
• • If pin nREG=0 during the memory access, the attribute memory space is selected

The I/O space is selected by asserting nIORD space for read accesses or nIOWR for write accesses [instead of nOE/nWE for memory space], combined with nCE2/nCE1. Note that nREG must also be asserted low when accessing I/O space.

Three type of accesses are allowed for a 16-bit PC Card:

• • Accesses to Common Memory space for data storage can be either 8-bit accesses at even addresses or 16-bit AHB accesses.

Note that 8-bit accesses at odd addresses are not supported and nCE2 is not driven low. A 32-bit AHB request is translated into two 16-bit memory accesses.

• • Accesses to Attribute Memory space where the PC Card stores configuration information are limited to 8-bit AHB accesses at even addresses.

Note that a 16-bit AHB access is converted into a single 8-bit memory transfer: nCE1 is asserted low, nCE2 is asserted high, and only the even byte on D7-D0 is valid. Instead a 32-bit AHB access is converted into two 8-bit memory transfers at even addresses: nCE1 is asserted low, nCE2 is asserted high, and only the even bytes are valid.

• • Accesses to I/O space can be either 8-bit or 16 bit AHB accesses.

Table 69. 16-bit PC-Card signals and access type

FMC Bank 4 gives access to those 3 memory spaces as described in Section 10.4.2: NAND flash memory/PC Card address mapping and Table 36: NAND/PC Card memory mapping and timing registers .

Wait feature

The CompactFlash or PC Card may request the FMC to extend the length of the access phase programmed by MEMWAITx/ATTWAITx/IOWAITx bits, asserting the nWAIT signal after nOE/nWE or nIORD/nIOWR activation if the wait feature is enabled through the PWAITEN bit in the FMC_PCRx register. To detect correctly the nWAIT assertion, the MEMWAITx/ATTWAITx/IOWAITx bits must be programmed as follows:

where max_wait_assertion_time is the maximum time taken by nWAIT to go low once nOE/nWE or nIORD/nIOWR is low.

After WAIT de-assertion, the FMC extends the WAIT phase for 4 HCLK clock cycles.

10.6.8 NAND flash/PC Card controller registers

PC Card/NAND flash control registers x (FMC_PCRx)

Address offset: \( 0x40 + 0x20 \cdot (x - 1) \) , ( \( x = 2 \) to \( 4 \) )

Reset value: 0x0000 0018

Bits 31:20 Reserved, must be kept at reset value

Bits 19:17 ECCPS : ECC page size.

Defines the page size for the extended ECC:

• 000: 256 bytes
• 001: 512 bytes
• 010: 1024 bytes
• 011: 2048 bytes
• 100: 4096 bytes
• 101: 8192 bytes

Bits 16:13 TAR : ALE to RE delay.

Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).

Time is \( t\_ar = (TAR + SET + 2) \times THCLK \) where THCLK is the HCLK clock period

• 0000: 1 HCLK cycle (default)
• 1111: 16 HCLK cycles

Note: SET is MEMSET or ATTSET according to the addressed space.

Bits 12:9 TCLR : CLE to RE delay.

Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).

Time is \( t\_clr = (TCLR + SET + 2) \times THCLK \) where THCLK is the HCLK clock period

• 0000: 1 HCLK cycle (default)
• 1111: 16 HCLK cycles

Note: SET is MEMSET or ATTSET according to the addressed space.

Bits 8:7 Reserved, must be kept at reset value

Bit 6 ECCEN : ECC computation logic enable bit

• 0: ECC logic is disabled and reset (default after reset),
• 1: ECC logic is enabled.

Bits 5:4 PWID : Data bus width.

Defines the external memory device width.

• 00: 8 bits
• 01: 16 bits (default after reset). This value is mandatory for PC Cards.
• 10: reserved, do not use
• 11: reserved, do not use

Bit 3 PTYP : Memory type.

Defines the type of device attached to the corresponding memory bank:

0: PC Card, CompactFlash, CF+ or PCMCIA

1: NAND flash (default after reset)

Bit 2 PBKEN : PC Card/NAND flash memory bank enable bit.

Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus

0: Corresponding memory bank is disabled (default after reset)

1: Corresponding memory bank is enabled

Bit 1 PWAITEN : Wait feature enable bit.

Enables the Wait feature for the PC Card/NAND flash memory bank:

0: disabled

1: enabled

Note: For a PC Card, when the wait feature is enabled, the MEMWAITx/ATTWAITx/IOWAITx bits must be programmed to a value as follows:

\( xxWAITx \geq 4 + \max\_wait\_assertion\_time/HCLK \)

Where max_wait_assertion_time is the maximum time taken by NWAIT to go low once nOE/nWE or nIORD/nIOWR is low.

Bit 0 Reserved.

FIFO status and interrupt register x (FMC_SRx)

Address offset: \( 0x44 + 0x20 * (x-1) \) , ( \( x = 2 \) to \( 4 \) )

Reset value: 0x0000 0040

This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data from the AHB.

This is used to quickly write to the FIFO and free the AHB for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.

The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty.

Bits 31:7 Reserved, must be kept at reset value

Bit 6 FEMPT : FIFO empty.

Read-only bit that provides the status of the FIFO

0: FIFO not empty

1: FIFO empty

Bit 5 IFEN : Interrupt falling edge detection enable bit

0: Interrupt falling edge detection request disabled

1: Interrupt falling edge detection request enabled

Bit 4 ILEN : Interrupt high-level detection enable bit
0: Interrupt high-level detection request disabled
1: Interrupt high-level detection request enabled

Bit 3 IREN : Interrupt rising edge detection enable bit
0: Interrupt rising edge detection request disabled
1: Interrupt rising edge detection request enabled

Bit 2 IFS : Interrupt falling edge status

The flag is set by hardware and reset by software.
0: No interrupt falling edge occurred
1: Interrupt falling edge occurred
Note: If this bit is written by software to 1 it is set.

Bit 1 ILS : Interrupt high-level status

The flag is set by hardware and reset by software.
0: No Interrupt high-level occurred
1: Interrupt high-level occurred

Bit 0 IRS : Interrupt rising edge status

The flag is set by hardware and reset by software.
0: No interrupt rising edge occurred
1: Interrupt rising edge occurred
Note: If this bit is written by software to 1 it is set.

Common memory space timing register x (FMC_PMEMx)

Address offset: Address: \( 0x48 + 0x20 * (x - 1) \) , ( \( x = 2 \) to \( 4 \) )

Reset value: 0xFCFC FCFC

Each FMC_PMEMx ( \( x = 2..4 \) ) read/write register contains the timing information for PC Card or NAND flash memory bank x. This information is used to access either the common memory space of the 16-bit PC Card/CompactFlash, or the NAND flash for command, address write access and data read/write access.

Bits 31:24 MEMHIZx : Common memory x data bus Hi-Z time

Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the start of a PC Card/NAND flash write access to common memory space on socket x. This is only valid for write transactions:

0000 0000: (0x00) 0 HCLK cycle (for PC Card) / 1 HCLK cycle (for NAND flash)
1111 1110: (0xFF) 255 HCLK cycles (for PC Card) / 256 HCLK cycles (for NAND flash)
1111 1111: Reserved

Bits 23:16 MEMHOLDx : Common memory x hold time

Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for read access during which the address is held (and data for write accesses) after the command is deasserted (NWE, NOE), for NAND flash read or write access to common memory space on socket x:

0000 0000: reserved

0000 0001: 1 HCLK cycle for write access / 3 HCLK cycles for read access

1111 1110: 254 HCLK cycles for write access / 256 HCLK cycles for read access

1111 1111: Reserved.

Bits 15:8 MEMWAITx : Common memory x wait time

Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for PC Card/NAND flash read or write access to common memory space on socket x. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK:

0000 0000: reserved

0000 0001: 2HCLK cycles (+ wait cycle introduced by deasserting NWAIT)

1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT)

Bits 7:0 MEMSETx : Common memory x setup time

Defines the number of HCLK (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for PC Card/NAND flash read or write access to common memory space on socket x:

0000 0000: 1 HCLK cycle (for PC Card) / HCLK cycles (for NAND flash)

1111 1110: 255 HCLK cycles (for PC Card) / 257 HCLK cycles (for NAND flash)

1111 1111: Reserved

Attribute memory space timing registers x (FMC_PATTx)

Address offset: 0x4C + 0x20 * (x - 1), (x = 2 to 4)

Reset value: 0xFCFC FCFC

Each FMC_PATTx (x = 2..4) read/write register contains the timing information for PC Card/CompactFlash or NAND flash memory bank x. It is used for 8-bit accesses to the attribute memory space of the PC Card/CompactFlash or to access the NAND flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section 10.6.5: NAND flash prewait functionality ).

Bits 31:24 ATTHIZ : Attribute memory x data bus Hi-Z time

Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the start of a PC CARD/NAND flash write access to attribute memory space on socket x. Only valid for write transaction:

0000 0000: 0 HCLK cycle

1111 1110: 255 HCLK cycles

1111 1111: Reserved

Bits 23:16 ATTHOLD : Attribute memory x hold time

Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for read access during which the address is held (and data for write access) after the command deassertion (NWE, NOE), for NAND flash read or write access to attribute memory space on socket:

0000 0000: reserved
0000 0001: 1 HCLK cycle for write access / 3 HCLK cycles for read access
1111 1110: 254 HCLK cycles for write access / 256 HCLK cycles for read access
1111 1111: Reserved.

Bits 15:8 ATTWAIT : Attribute memory x wait time

Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, NOE), for PC Card/NAND flash read or write access to attribute memory space on socket x. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK:

0000 0000: reserved
0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)

Bits 7:0 ATTSET : Attribute memory x setup time

Defines the number of HCLK (+1) clock cycles to set up address before the command assertion (NWE, NOE), for PC CARD/NAND flash read or write access to attribute memory space on socket x:

0000 0000: 1 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: Reserved.

I/O space timing register 4 (FMC_PIO4)

Address offset: 0xB0
Reset value: 0xFCFCFCFC

The FMC_PIO4 read/write registers contain the timing information used to access the I/O space of the 16-bit PC Card/CompactFlash.

Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the start of a PC Card write access to I/O space on socket x. Only valid for write transaction:

0000 0000: 0 HCLK cycle

1111 1111: 255 HCLK cycles

Defines the number of HCLK clock cycles during which the address is held (and data for write access) after the command deassertion (NWE, NOE), for PC Card read or write access to I/O space on socket x:

0000 0000: reserved

0000 0001: 1 HCLK cycle

1111 1111: 255 HCLK cycles

Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE, SMNOE), for PC Card read or write access to I/O space on socket x. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of HCLK:

0000 0000: reserved, do not use this value

0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)

1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT)

Defines the number of HCLK (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for PC Card read or write access to I/O space on socket x:

0000 0000: 1 HCLK cycle

1111 1111: 256 HCLK cycles

ECC result registers 2/3 (FMC_ECCR2/3)

Address offset: \( 0x54 + 0x20 \cdot (x - 1) \) , \( x = 2 \) or \( 3 \)

Reset value: 0x0000 0000

These registers contain the current error correction code value computed by the ECC computation modules of the FMC (one module per NAND flash memory bank). When the CPU reads the data from a NAND flash memory page at the correct address (refer to Section 10.6.6: Computation of the error correction code (ECC) in NAND flash memory ), the data read/written from/to the NAND flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCRx registers), the CPU must read the computed ECC value from the FMC_ECCx registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCRx registers should be cleared after being read by setting the ECCEN bit to '0'. To compute a new data block, the ECCEN bit must be set to '1'.

Bits 31:0 ECCx : ECC result

This field contains the value computed by the ECC computation logic. Table 70 describes the contents of these bitfields.

Table 70. ECC result relevant bits

10.6.9 FMC register map

The following table summarizes the FMC registers.

Table 71. FMC register map

Table 71. FMC register map (continued)

Refer to Section 3.2 on page 53 for the register boundary addresses.