8. Peripheral interconnect matrix

8.1 Introduction

Several STM32F3 peripherals have internal interconnections. Knowing these interconnections allows the following benefits:

• • Autonomous communication between peripherals
• • Efficient synchronization between peripherals
• • Discard the software latency and minimize GPIOs configuration
• • Optimum number of pins available, even with small packages
• • Avoid the use of connectors and design an optimized PCB with lower dissipated energy.

8.2 Connection summary

The following table presents the matrix for the peripheral interconnect.

Table 23. STM32F3xx peripherals interconnect matrix ⁽¹⁾

1. 1. X means interconnect, and “-” means no interconnect.
2. 2. Not in STM32F303x6/8 and STM32F328x8.
3. 3. Only in STM32F303x6/8 and STM32F328x8.

8.3 Interconnection details

8.3.1 DMA interconnections

Hardware DMA requests are managed by peripherals. The DMA channels dedicated to each peripheral are summarized in Section 13.3.2: DMA request mapping .

8.3.2 From ADC to ADC

ADC1 can be used as a “master” to trigger ADC2 “slave” start of conversion.

ADC3 can be used as “master” to trigger ADC4 “slave” start of conversion.

In dual ADC mode, the converted data of the master and slave ADCs can be read in parallel.

A description of dual ADC mode is provided in Section 15.3.29: Dual ADC modes .

8.3.3 From ADC to TIM

ADCx (x=1..4) can provide trigger event through watchdog signals to advanced-control timers (TIM1/TIM8/TIM20).

A description of the ADC analog watchdog settings is provided in Section 15.3.28: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) .

The output (from ADC) is on signals ADCn_AWDx_OUT (n = 1..4, x = 1..3 as there are 3 analog watchdogs per ADC) and the input (to timer) on signal TIMx_ETR (external trigger).

TIMx_ETR is connected to ADCn_AWDx_OUT through bits in TIMx_OR registers; refer to Section 20.4.23: TIMx option registers (TIMx_OR)(x = 1, 8, 20) .

Table 24. TIM1/8/20_ETR connection to ADCx analog watchdogs

8.3.4 From TIM and EXTI to ADC

General-purpose timers (TIM2/TIM3/TIM4), basic timers (TIM6/TIM7), advanced-control timers (TIM1/TIM8/TIM20), general-purpose timer (TIM15/TIM16/TIM17) and EXTI can be used to generate an ADC triggering event.

The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event.

The input (to ADC) is on signal EXT[15:0], JEXT[15:0].

The connection between timers and ADCs or also EXTI & ADCs is provided in:

• • Table 90: ADC1 (master) & 2 (slave) - External triggers for regular channels
• • Table 91: ADC1 & ADC2 - External trigger for injected channels
• • Table 92: ADC3 & ADC4 - External trigger for regular channels
• • Table 93: ADC3 & ADC4 - External trigger for injected channels

8.3.5 From OPAMP to ADC

There are two interconnection types:

1. 1. Connect OPAMP output reference voltage to an internal ADC channel. This connection can be used for OPAMP calibration. For more details, please refer to the Section Calibration in the OPAMP chapter.

Section 15.3.11: Channel selection (SQRx, JSQRx) provides the exact ADC channels to be used.

Table 25. VREFOPAMPx to ADC channel

1. 2. OPAMPx output, x = 1..4 can be connected to ADCy channels, y= 1..4 through the GPIOs. See the summary in the table below. Refer to Section 18.3.4: Using the OPAMP outputs as ADC inputs .

Table 26. OPAMP output to ADC input

8.3.6 From TS to ADC

The internal temperature sensor (VTS) is connected internally to ADC1_IN16. Refer to Section 15.3.30: Temperature sensor .

8.3.7 From VBAT to ADC

VBAT/2 output voltage can be converted using ADC1_IN17. This interconnection is explained in Section 15.3.31: VBAT supply monitoring .

8.3.8 From VREFINT to ADC

VREFINT is internally connected to channel 18 of the ADCs. This allows the monitoring of its value as described in Section 15.3.32: Monitoring the internal voltage reference .

8.3.9 From COMP to TIM

The comparators outputs can be redirected internally to different timer inputs:

• • break input 1/2 for fast PWM shutdowns
• • OCREF_CLR input
• • input capture.

To select which timer input must be connected to the comparator output, the bits field COMPxOUTSEL in the COMPx_CSR register are used.

The following table gives an overview of all possible comparator outputs redirection to the timer inputs.

Table 27. Comparator outputs to timer inputs

Table 27. Comparator outputs to timer inputs (continued)

Note: When the comparator output is configured to be connected internally to timers break input, the following must be considered:

1/ COMP1/2/3/5/6 can be used to control TIM1/8/20_BRK_ACTH (this break is always active high with no digital filter) and to control also TIM1/8/20_BRK2 input.

2/ COMP4/7 can be used to control TIM1/8/20_BRK and the TIM1/8/20_BRK2 input (same as the other comparators).

3/ COMP3/5/7 can be used to control TIMx_BRK_ACTH, x=15;16;17 respectively (this break is always active high with no digital filter).

8.3.10 From TIM to COMP

The timers output can be selected as comparators outputs blanking signals using the “COMPx_BLANKING” bits in the “COMPx_CSR” register. More details on the blanking function can be found in Section 17.3.6: Comparator output blanking function .

Table 28. Timer output selection as comparator blanking source

8.3.11 From DAC to COMP

The comparators inverting input may be a DAC channel output (DAC1_CH1 or DAC1_CH2). DAC2_CH1 may be selected for COMP2, COMP4 and COMP6 in case the device is STM32F303x6/8 or STM32F328x8.

The selection is made based on the “COMPxINMSEL” bits value in the “COMPx_CSR” register.

The following table summarizes these interconnections.

Table 29. DAC output selection as comparator inverting input

1. Only on STM32F303x6/8 and STM32F328x8.

8.3.12 From VREFINT to COMP

Besides to the DAC channel output, Vrefint (x1, x3/4, x1/2, x1/4) can be selected as comparator inverting input using “COMPxINMSEL” bits in “COMPx_CSR” register.

8.3.13 From DAC to OPAMP

The DAC outputs are connected internally to OPAMP1 & OPAMP3 & OPAMP4 non inverting inputs as shown in the following summary table.

8.3.14 From TIM to OPAMP

The switch between OPAMP inverting and non-inverting inputs can be done automatically. This automatic switch is triggered by the TIM1 CC6 output arriving on the OPAMP input multiplexers. More details on this feature are available in Section 18.3.6: Timer controlled Multiplexer mode .

8.3.15 From TIM to TIM

Some STM32F3 timers are linked together internally for timer synchronization or chaining. When one timer is configured in Master Mode, it can reset, start, stop, or clock the counter of another timer configured in Slave Mode.

A description of the feature with the various synchronization modes is available in:

• • Section 20.3.25: Timer synchronization for the advanced-control timers (TIM1/TIM8/TIM20)
• • Section 21.3.19: Timer synchronization for the general-purpose timers (TIM2/TIM3/TIM4)

The slave mode selection is made using “SMS” bits, as described in:

• • Section 20.4.3: TIMx slave mode control register (TIMx_SMCR)(x = 1, 8, 20) ,
• • Section 21.4.3: TIMx slave mode control register (TIMx_SMCR)(x = 2 to 4) for the general-purpose timers (TIM2/TIM3/TIM4) ,
• • Section 23.4.20: Slave mode – combined reset + trigger mode (TIM15 only) for the general purpose timers (TIM2/TIM3/TIM4)

The possible master/slave connections are summarized in the following table providing the internal trigger connection:

Table 31. Timer synchronization

8.3.16 From break input sources to TIM

In addition to comparators outputs, other sources can be used as trigger for the internal break events of some timers (TIM1/TIM8/TIM20/TIM15/TIM16/TIM17). For example:

• the clock failure event generated by CSS, refer to Section 9.2.6: System clock (SYSCLK) selection for more details,
• the PVD output, refer to Section 7.2.2: Programmable voltage detector (PVD) for more details,
• the SRAM parity error signal, refer to Section 3.3.1: Parity check for more details,
• the Cortex-M4 LOCKUP (Hardfault) output.

The sources mentioned above can be connected internally to TIMx_BRK_ACTH input, x = 1,8,15,16,17,20.

The purpose of the break function is to protect power switches driven by PWM signals generated by the timers.

More details on the break feature are provided in:

• Section 20.3.16: Using the break function for the advanced-control timers (TIM1/TIM8/TIM20)
• Section 23.4.13: Using the break function for the general-purpose timers (TIM15/TIM16/TIM17)

8.3.17 From HSE, HSI, LSE, LSI, MCO, RTC to TIM

TIM16 can be used for the measurement of internal/external clock sources. TIM16 channel1 input capture is connected to HSE/32, GPIO, RTC clock and MCO to output clocks among (HSE, HSI, LSE, LSI, SYSCLK, PLLCLK, PLLCLK/2).

The selection is performed through the TI1_RMP [1:0] bits in the TIM16_OR register.

This allows calibrating the HSI/LSI clocks.

More details are provided in Section 9.2.14: Internal/external clock measurement with TIM16 .

8.3.18 From TIM and EXTI to DAC

A timer counter may be used as a trigger for DAC conversions.

The TRGO event is the internal signal that triggers conversion.

The following table provides a summary of DACs interconnections with timers:

This is described in Section 16.5.4: DAC trigger selection .

Table 32. Timer and EXTI signals triggering DAC conversions

1. Only on STM32F303x6/8 and STM32F328x8 devices.

8.3.19 From TIM to IRTIM

General-purpose timer (TIM16/TIM17) output channels TIMx_OC1 are used to generate the waveform of infrared signal output. The functionality is described in Section 24: Infrared interface (IRTIM) .