34. Revision history

DMA

Updated Section : DMA1 controller and Section : DMA2 controller.

Interrupts and events:

Replaced reference to “Cortex®-M4” by “PM0214 programming manual” in Section 11.1.1: NVIC main features.

Updated Software interrupt event register (EXTI_SWIER) and Pending register (EXTI_PR).

Updated Figure 26: Extended interrupt/event GPIO mapping and Table 29: Extended interrupt/event controller register map and reset values.

SDADC:

Updated Figure 37: Switch configuration in single-ended mode, Figure 38: Switch configuration in differential mode , Figure 39: Switch configuration in mixed mode (example 1) and Figure 40: Switch configuration in mixed mode (example 2).

Replaced all “SDADC_CONFRx” by “SDADC_CONFxR”

Updated Section 13.5.7: Launching calibration and determining the offset values.

DAC:

Updated Figure 43: DAC1 block diagram and Figure 44: DAC2 block diagram: replaced “AEIC_9” by “EXT_9”

Updated TSEL1 and TSEL2 description.

Replaced “AIEC” by “EXTI”.

Updated Table 42: DAC register map and reset values.

COMP:

Updated Figure 52: Comparator 1 and 2 block diagrams.

Updated “COMP_INP_DAC” description.

Updated Table 43: COMP register map and reset values.

IWDG:

Updated Figure 163: Independent watchdog block diagram.

USART:

Updated note in Section : Single byte communication.

Updated Mode 2 and Mode 3 description in Section 25.5.6: Auto baud rate detection

Removed note on bit 19(RWU) in Section 25.7.8: USART interrupt and status register (USART_ISR) on page 700.

Updated Section 25.5.10: LIN (local interconnection network) mode.

Updated Figure 198: USART block diagram and added two notes.

Replaced “BRR[3:0] = 0x3<<1=0x1” by “BRR[3:0] = 0x3>>1=0x1” in Section : How to derive USARTDIV from USART_BRR register values when OVER8=0.

Replaced in Bit 2 MMRQ Section 25.7.7: USART request register (USART_RQR) “resets the RWU flag” by “sets the RWU flag”

Added ‘In Smartcard, LIN and IrDA modes, only Oversampling by 16 is supported’ in Section 25.5.4: Baud rate generation

Corrected and updated stop bits in Figure 199: Word length programming

SPI/I2S:

Updated Section 26.6: SPI interrupts and Section 26.7.7: I2S slave mode.

TSC:

Added Table 103: Interrupt control bits.

Replaced “Power-on reset value” with “Reset value” in Section 27.6.2: TSC interrupt enable register (TSC_IER).

DBG:

Updated Section 31.16.4: Debug MCU APB1 freeze register (DBGMCU_APB1_FZ).

General-purpose times:

Updated Section 18.1: TIM15/16/17 introduction, Section 18.3: TIM16 and TIM17 main features, Figure 124: TIM16 and TIM17 block diagram, Section 17.4.3: Clock selection, Section 18.6.1: TIM16&TIM17 control register 1 (TIMx_CR1), Section 18.6.3: TIM16&TIM17 DMA/interrupt enable register (TIMx_DIER), Section 18.6.4: TIM16&TIM17 status register (TIMx_SR), Section 18.6.5: TIM16&TIM17 event generation register (TIMx_EGR) and Table 57: TIM16&TIM17 register map and reset values.

I2C:

Corrected Figure 185: Transfer sequence flow for I2C master transmitter for N > 255 bytes.

Removed maximum values of parameter “Data hold time” and added row “Data valid time” in Table 71: I2C-SMBus specification data setup and hold times.

Updated sub-section I2C timings.

Updated Figure 169: Setup and hold timings.

Reclassified section “I2C register map” from 2.8 to 24.7.12.

Added Caution: “If wakeup from Stop is disabled...” in Section 24.4.15: Wake-up from Stop mode on address match.

Added Section 24.5: I2C low-power modes.

Moved Section 24.7: I2C debug mode to and renamed it Master event control using DMA.

Updated Section 14.2: DAC1/2 main features, Section 14.5.2: DAC channel conversion, Section 14.6.2: DAC channel conversion in dual mode, Section 14.6.3: Description of dual conversion modes, Section 14.6.5: DAC trigger selection, Section 14.7: Noise generation, Section 14.8: Triangle-wave generation, MAMP2, WAVE2, MAMP1 and WAVE1 bit descriptions in Section 14.10.1: DAC control register (DAC_CR).

Updated Section 15.1: Introduction, Section 15.3.4: Comparator LOCK mechanism.

Replaced "TIM16" by "TIM16_OC1" and "TIM17" by "TIM17_OC1" in Table 53: TIMx Internal trigger connection.

Updated IC1F bit description in Section 16.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1).

Updated Table 99: Frame formats and MSBFIRST bit description in Section 25.7.2: USART control register 2 (USART_CR2).

Updated Section 19: Infrared interface (IRTIM) and Figure 152: IRTIM internal hardware connections with TIM16 and TIM17.

Updated Section 21.3.1: IWDG block diagram, Section 21.3.5: Debug mode, PR bit description in Section 21.4.1: IWDG key register (IWDG_KR).

Updated Section 23.3.1: RTC block diagram, Section 23.3.4: Real-time clock and calendar, Section 23.3.12: RTC smooth digital calibration.

Updated Section 23.5: RTC interrupts.

Updated Section 24.4.10: I2C_TIMINGR register configuration examples, added access type to all register descriptions in Section . .

Updated Note... Updated CTSE bit description in Section 25.7.3: USART control register 3 (USART_CR3).

Updated Section 26.2: SPI main features, moved Section 26.7.10: DMA features, updated bit LSBFIRST description in Section 26.9.1: SPI control register 1 (SPIx_CR1), updated reset value in Section 26.9.2: SPI control register 2 (SPIx_CR2).

Updated Section Table 98.: Capacitive sensing GPIOs available on STM32F378xx devices.

Added "512 Bytes of dedicated packet buffer memory SRAM" in Section 29.2: USB main features.

Added Section 29.3: USB implementation, updated Section 29.4: USB functional description.

Updated Table 1354: STM32G4 Series USB implementation.

Updated Section 30.4.1: SFT option bit, Section 30.5.4: Short bit period error (SBPE), bit OAR in Section 30.7.2: CEC configuration register (CEC_CFGR), bit RXACKE in Section 30.7.5: CEC interrupt and status register (CEC_ISR).

Updated Section 31.4.4: Using serial wire and releasing the unused debug pins as GPIOs..

Updated c7amba_aditf Section 12.1: ADC introduction and Section 12.12: ADC registers with 18 multiplexed channels and add Tconv value.

Updated c7amba_sdadc1:

• -Section 13.2: SDADC main features and Section 13.5: SDADC functional description changing VREF in VREFSD(+) and VSSA in VREFSD-.
• - Section 13.5.8: Launching conversions putting the highest channel (channel 8, if selected.).

Added note below in GOLDFISH_MEM Table 9: Description of the option bytes.

Updated UE bit description in Section 25.7.1: USART control register 1 (USART_CR1).

Updated Section 22.3.4: How to program the watchdog timeout WWDG formula precision.

Updated Section 25.7.6: USART receiver timeout register (USART_RTOR).

Removed note and updated REACK bit description in USART_ISR register of Section 25.7.8: USART interrupt and status register (USART_ISR).

Updated Section 25.7.1: USART control register 1 (USART_CR1) description adding “in Smartcard mode” in Bit 3 description.

Updated all Low-power modes of GOLDFISH_PWR Section 6.3: Low-power modes.

Updated Figure 41: Equivalent input circuit for input channel.

Updated Section 7.4.9: RTC domain control register (RCC_BDCR) LSEDRV Bits 4:3 description.

TIMER section:

• – Updated Section 16.4.3: TIMx slave mode control register (TIMx_SMCR) SMS bit description.
• – Updated Section 16.4.7: TIMx capture/compare mode register 1 (TIMx_CCMR1) IC1F[3:0] bit description, replacing 'N events' by 'N consecutive events'.
• – Updated Section 16.4.3: TIMx slave mode control register (TIMx_SMCR) ETF[3:0] bit description, replacing 'N events' by 'N consecutive events'.
• – Updated Section 20.4.2: TIM6/7/18 control register 2 (TIMx_CR2) MMS bit description and added note about the clock of the slave timer.
• – Updated Section 21.3.13: One-pulse mode modifying "IC2S=01" by "CC2S=01".
• – Updated Section 22.4.18: Slave mode: Combined reset + trigger mode (TIM15 only) adding (TIM15 only) on the title.
• – Updated Section 17.6.11: TIM14 option register (TIM14_OR) and Section 17.6.12: TIM13/14 register map changing the address at '0x50'.
• – Removed TIM2_OR register in Section 16.4: TIM2 to TIM5/TIM19 registers and Section 16.5: TIMx register map.
• – Updated Section 18.6.16: TIM16&TIM17 register map: the bits 4, 5, 6, 7 of the TIMx_CR2 register are reserved.

WWDG section:

• – Updated Figure 163: Independent watchdog block diagram replacing '6-BIT DOWNCOUNTERR (CNT)' by '7-BIT DOWNCOUNTERR (CNT)'.

USART section:

• – – Updated Section 25: Universal synchronous/asynchronous receiver – transmitter (USART/UART) with the new USART IP section.
• – – Updated Section 25.5.17: Wake-up from Stop mode using USART – adding paragraph "how to determine the maximum USART baudrate".
• – – Updated whole USART document replacing any occurrence of:
  • nCTS
  • by CTS, nRTS by RTS, SCLK by CK.
• – – Updated Section 25.8.9: USART interrupt flag clear register – (USART_ICR) replacing "w" by "rc_wl".
• – – Updated Section 25.8.8: USART interrupt and status register – (USART_ISR) RTOF field replacing USARTx_CR2 by USARTx_CR1.
• – – Updated Section 25.8.3: USART control register 3 (USART_CR3) – 'ONEBIT' bit 11 description adding a note.
• – – Updated Section 25: Universal synchronous/asynchronous receiver – transmitter (USART/UART) changing register name – USARTx_regname in USART_regname.
• – – Updated Section 23.3.15: Calibration clock output.
• – – Added caution at the end of Section 23.6.3: RTC control register – (RTC_CR).
• – – Updated caution at the end of Section 23.6.16: RTC tamper and alternate function configuration register (RTC_TAFCR).
• – – Updated Section 25.5.17: Wake-up from Stop mode using USART.

RTC section:

• – Updated WUCKSEL bits in Figure 166: RTC block diagram.
• – Updated Section 23.3.7: RTC initialization and configuration programming the wakeup timer.
• – Updated Section 23.6.4: RTC initialization and status register (RTC_ISR) bit 2 WUTWF.
• – Added case of RTC clocked by LSE in Section 23.3.9: Resetting the RTC.
• – Updated caution at the end of Section 23.6.16: RTC tamper and alternate function configuration register (RTC_TAFCR).
• – Updated Section 23.3.15: Calibration clock output.
• – Added caution at the end of Section 23.6.3: RTC control register (RTC_CR).
• – Updated Section 23.6.16: RTC tamper and alternate function configuration register (RTC_TAFCR) and Section 23.6.20: RTC register map adding bits corresponding to TAMP3.

Power control section:

• – Added Section 6.1.2: Correct grounding for analog applications. description and Figure 8: Recommended SDADC grounding.
• – Updated Figure 7: Power supply overview.

RCC section:

Updated Section 9.4.9: RTC domain control register (RCC_BDCR) with LSEDRV[1:0] bits: '01' and '10' combinations swapped.

Updated Section 9.2.9: RTC clock adding “the RTC remains clocked and functional under system reset” when the RTC clock is LSE.

Updated Section 7.4.10: Control/status register (RCC_CSR) and Section 7.4.14: RCC register map adding V18PWRRSTF bit 23.

DAC section:

• – Updated Section 14.5.3: DAC output voltage.
• – Updated Section 14.6.1: DAC data format removing single mode description.
• – Removed content of Section 14.6.4: DAC output voltage and Section 14.6.5: DAC trigger selection and reference made to Single mode.
• – Removed introductory sentence in Section 14.5.1: DAC data format.
• – Updated Table 39: DACx pins name and note.

CAN section:

Updated Section 28.7.7: Bit timing Section : CAN bit timing register (CAN_BTR) replacing tCAN by tq

ADC section:

Updated Section 12.12.7: ADC watchdog high threshold register (ADC_HTR) and Section 12.12.8: ADC watchdog low threshold register (ADC_LTR) adding note.

SDADC section:

• – Updated Section 13.2: SDADC main features.
• – Updated Section 13.5.5: Differential and single-ended modes

I2C2 section:

• – Updated Figure 169: Setup and hold timings.
• – Updated Section 24.4.5: I2C initialization updating and adding notes in Section : I2C timings.
• – Updated Section 24.7.5: Timing register (I2C_TIMINGR) SCLDEL[3:0] and SDADEL[3:0] bits description.
• – Updated Section 24.4.5: I2C initialization, Section 24.4.9: I2C master mode and Section 24.7.5: Timing register (I2C_TIMINGR) adding the sentence “The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C configuration window”.

SPI section:

• - Updated Section 26.5.2: Communications between one master and one slave and Section 26.5.3: Standard multislave communication figures 340, 341, 342 and 343.
• - Notes updated and added below the figures.
• - Added Section 26.5.4: Multimaster communication.

Embedded Flash memory:

Updated Section 4.5.1: Flash access control register (FLASH_ACR) bits LATENCY[2:0] replacing SYSCLK by HCLK.

Interrupts and events section:

Updated Section 11.2.6: External and internal interrupt/event line mapping adding 'on STM32F373 only' and modifying the note for EXT lines.

Updated Section 11.3.3: Rising trigger selection register (EXTI_RTSR), Section 11.3.4: Falling trigger selection register (EXTI_FTSR), Section 11.3.5: Software interrupt event register (EXTI_SWIER), Section 11.3.6: Pending register (EXTI_PR) and Section 11.3.7: EXTI register map bits 18/20/21/22.

Touch sensing controller section:

Updated Section 27.3.4: Charge transfer acquisition sequence adding note about the TSC control register configuration forbidden.

Updated Section 27.6.1: TSC control register (TSC_CR) adding note for CTPL[3:0] bits and PGPSC[2:0] bits.

Removed capacitive sensing GPIOs section adding L1REQ bit description.

USB section:

• – Updated Section : USB control register (USB_CNTR) adding L1REQM bit5, L1RESUME bit7 description.
• – Updated Section : USB interrupt status register (USB_ISTR)

DEBUG section:

• – Updated Section 31.6.3: Cortex®-M4 with FPU TAP: sentence about DEV_ID[11:0] moved before DBGMCU_IDCPODE register bit description.

• – Document convention section:
• – Added Section 1.1: General information with Arm logo
• – SDADC section:
• – Updated Section 13.5.4: Channel selection, Section 13.5.8: Launching conversions and Section 13.5.9: Continuous and fast continuous modes.
• – Updated Section 13.6.3: SDADC control register 2 (SDADC_CR2) JCONT bit description.
• – Updated Section 13.6.6: SDADC injected channel group selection register (SDADC_JCHGR) JCHG[8:0] bit description.
• – USB section:
• – Updated Table 108: STM32F37xxx USB implementation removing last column 1024 bytes SRAM
• – All LPM related bits marked as reserved:
• – Updated Section 29.6.1: Common registers USB control registers (USB_CNTR).
• – Updated Section 29.6.1: Common registers USB interrupt status registers (USB_ISTR).
• – Updated Section 29.6.3: USB register map.
• – USART section:
• – Updated Section 25: Universal synchronous/asynchronous receiver transmitter (USART/UART).
• – Updated Section 25.5.4: USART baud rate generation note, replacing '0d16' by '16d'.
• – Updated notes related to reserved bit/bitfield depending on USART/LPUART feature in USART_CR1, USART_CR2, USART_CR3, USART_ISR, USART_ICR, LPUART_CR3 and LPUART_ISR.
• – General-purpose timer section:
• – Updated Figure 123: TIM15 block diagram.
• – Updated Figure 124: TIM16 and TIM17 block diagram.
• – Updated Section 18.4.12: Using the break function about the source for break (BRK) channel description.
• – Updated Table 45: TIMx internal trigger connection.
• – RTC section:
• – Updated Section 23.6.3: RTC control register (RTC_CR) WUTE bit description adding note.
• – Updated Figure 166: RTC block diagram WUXKSEL dividers and RTC_WUTR 'ck_spre' input.
• – Updated Section 23.6.19: RTC backup registers (RTC_BKPxR) BKP[31:0] bit description.
• – Updated Section 23.3.14: Tamper detection RTC backup registers.
• – Updated Section 23.6.3: RTC control register (RTC_CR) SUB1H bit description.

– I2C2 section:

• – Updated Section 24: Inter-integrated circuit (I2C) interface
• – Updated Figure 169: Setup and hold timings.
• – Updated Section 24.4.10: I2C_TIMINGR register configuration examples ‘in order to get more accurate configuration values, the STM32CubeMX tool (I2C configuration) should be used’.

– RCC section:

• – Updated Section 7.1.2: System reset.

– Memory section:

• – Added Figure 2: Memory map.

– MEM section:

• – Updated Section 1.2.3: Flash program and erase operations:
• – Flash memory page erase paragraph step1.
• – Option byte programming paragraph ‘WRPRTERR’ by ‘PGERR’ bit.

– DMA section:

• – Updated using the new DMA document.

– BXCAN section:

• – Updated Section 28: Controller area network (bxCAN)

Introduction section:

Updated the Introduction and the Related documents sections in Section : Introduction .

Documentation conventions section:

Added the Section 1.1: General information

MEM section:

Updated the Table 10: Description of the option bytes (0x1FFF F808).
Updated the Table 5: Access status versus protection level and execution modes
Corrected a typo in Section 3.5.1: Flash access control register (FLASH_ACR)
Updated the Section 3.3: Memory protection for flash lower case.
Updated the Section 3.3.1: Read protection (RDP) to replace a note.

CRC section:

Added a note to the Section 5.3.3: CRC operation .
CRC_POL[31] value turned to binary in the Section 5.4.6: CRC register map
Added note in Section 5.4.5: CRC polynomial (CRC_POL) to clarify what are even and odd polynomials.
Added CRC register access granularity in Section 5.2: CRC main features and Section 5.4: CRC registers .
Updated Figure 6: CRC calculation unit block diagram

PWR section:
Updated the Section 6.4.1: Power control register (PWR_CR) (PLS, PVDE).

RCC section:
Updated bits 22 to 17 to replace IOP by GPIO in Section 7.4.6: AHB peripheral clock enable register (RCC_AHBENR) .
Updated bit 0 to add COMP in Section 7.4.7: APB2 peripheral clock enable register (RCC_APB2ENR) .

GPIO section:
Updated the Section 8.3: GPIO functional description
Updated the Section 8.3.2: I/O pin alternate function multiplexer and mapping

DMA section:
Added the caution message in Section 10.3.2: DMA request mapping
Updated Section 10.4.4: DMA channels :
Updated Table 25: Programmable data width and endian behavior (when PINC = MINC = 1)
Updated the Section 10.6: DMA registers .

Interrupts section:
Updated the reset value for Section 11.3.6: Pending register (EXTI_PR)

ADC section:
Removed ADC supply requirements from Table 30: ADC pins .
Updated Section 12.4: Calibration

SDAC section:
Updated Section 13.6.3: SDADC control register 2 (SDADC_CR2) JCONT bit description.
Updated Section 13.6.6: SDADC injected channel group selection register (SDADC_JCHGR) JCHG[8:0] bit description

COMP section:
Updated Section 15.3.3: COMP reset and clocks..
Updated the COMP1MODE[1:0] description in Section 15.5.1: COMP control and status register (COMP_CSR) .

Timer sections:
Updated Table 45: TIMx internal trigger connection
Updated Figure 114: Capture/compare channel 1 main circuit .

Watchdog sections:

Updated Section 21.3.1: IWDG block diagram , Section 21.3.6: Debug mode .

Updated Section 22.3: WWDG functional description , Section 22.3.3: Controlling the down-counter .

Added Section 22.4: WWDG interrupts .

Updated Section 22.5.2: WWDG configuration register (WWDG_CFR) , Section 22.5.1: WWDG control register (WWDG_CR) , Section 22.5.3: WWDG status register (WWDG_SR) .

Updated Figure 164: Watchdog block diagram .

RTC section:

Updated the Section 23.3.8: Reading the calendar (RTCCLK periods) and Section 23.3.16: Alarm output .

Updated Section 23.5: RTC interrupts . (RTC_DR), (RTC_WPR), (RTC_SHIFTR), (RTC_TSDR), (RTC_TSSSR),

Updated Section 23.6.1: RTC time register (RTC_TR) and Section 23.6.4: RTC initialization and status register (RTC_ISR)

Updated the Section Table 66.: RTC register map and reset values

I2C section:

Added Table 68: I2C input/output pins and Table 69: I2C internal input/output signals

Updated the Figure 179: Transfer bus diagrams for I2C slave receiver (mandatory events only)

Updated Section 24.3: I2C implementation .

Updated the Section 24.4.1: I2C block diagram , Section 24.4.7: Data transfer (Hardware transfer management)

Updated the Section 24.7.1: I2C control register 1 (I2C_CR1) , Section 24.7.2: I2C control register 2 (I2C_CR2) , Section 24.7.3: I2C own address 1 register (I2C_OAR1) , Section 24.7.6: I2C timeout register (I2C_TIMEOUTR) , Section 24.7.7: I2C interrupt and status register (I2C_ISR) , Section 24.7.8: I2C interrupt clear register (I2C_ICR) and Section 24.7.9: I2C PEC register (I2C_PECR)

Updated Figure 176: Transfer bus diagrams for I2C slave transmitter (mandatory events only) , Figure 179: Transfer bus diagrams for I2C slave receiver (mandatory events only) , Figure 186: Transfer bus diagrams for I2C master transmitter (mandatory events only) , and Figure 186: Transfer bus diagrams for I2C master transmitter (mandatory events only) .

Updated Table 74: Examples of timing settings for fI2CCLK = 8 MHz , Table 75: Examples of timing settings for fI2CCLK = 16 MHz , and Table 76: Examples of timing settings for fI2CCLK = 48 MHz

Updated Figure 173: Slave initialization flow

USART/UART section:

USART_TDR reset value changed from undefined to 0x0000 0000

Changed title into Universal synchronous/asynchronous receiver transmitter (USART/UART) .

Updated Figure 217: Reception using DMA : changed USART_TDR into USART_RDR. Updated USART and LPUART block diagrams.

Updated Section 25.8: USART registers and Section : to indicate that USART and LPUART registers are accessed by words.

Updated the Section 25.5.4: USART baud rate generation (example 1)

Replaced USART_CR3 by USART_RQR register in Section 25.8.8: USART interrupt and status register (USART_ISR) .

Added ABRE bit in ABRRQ bit definition of Section 25.8.7: USART request register (USART_RQR)

Updated Section 25: Universal synchronous/asynchronous receiver transmitter (USART/UART) (kHz, baud, kbaud).

Updated description of RTS signal behavior and USART_CR3.RTSE bit in Section 25.8.3: USART control register 3 (USART_CR3) .

Updated description of CRTS signal behavior and USART_CR3.CTSE bit in Section 25.8.3: USART control register 3 (USART_CR3) .

Updated ORE and FE bit descriptions in USART_ISR and LPUART_ISR.

SPI/I2S section:

Updated Section 26.5.9: Data transmission and reception procedures 'Communication using DMA (direct memory addressing)' paragraph.

Table 98: SPI/I2S register map and reset values split into 2 tables:

TSC section:

Updated Section 27.3.4: Charge transfer acquisition sequence .

Updated Section 27.3.5: Spread spectrum feature .

Updated Section 27.3.9: I/O hysteresis and analog switch control .

Updated address offset range syntax in Section 27.6.10: TSC I/O group x counter register (TSC_IOGxCR) .

USB section:

Updated Section 29.6: USB and USB SRAM registers .

Updated Section 29.6.2: Buffer descriptor table .

Updated Section 29.5.5: Suspend/Resume events .

Updated Table 110: Bulk double-buffering memory buffers usage

Debug section:

Removed a note in the Section 31.4.2: Flexible SWJ-DP pin assignment

Important security notice in Section 33: Important security notice

Minor terminology changes applied to the whole document.