20. Basic timers (TIM6/7/18)

20.1 Introduction

The basic timers TIM6, TIM7, and TIM18 consist of a 16-bit auto-reload counter driven by a programmable prescaler.

They can be used as generic timers for timebase generation but they are also specifically used to drive the digital-to-analog converter (DAC). In fact, the timers are internally connected to the DAC and are able to drive it through their trigger outputs.

The timers are completely independent, and do not share any resources.

20.2 TIM6/7/18 main features

Basic timer (TIM6/TIM7/TIM18) features include:

• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536
• Synchronization circuit to trigger the DAC
• Interrupt/DMA generation on the update event: counter overflow

Figure 153. Basic timer block diagram

Notes:
Reg Preload registers transferred to active registers on U event according to control bit
Event
Interrupt & DMA output

MS33142V1

Figure 153. Basic timer block diagram. The diagram shows the internal architecture of a basic timer. At the top, TIMxCLK from RCC is connected to a 'Trigger controller' block. The 'Trigger controller' has a 'Control' sub-block and outputs TRGO to a DAC. Below the trigger controller is a 'CNT counter' block. The counter is driven by CK_CNT from a 'PSC prescaler' block. The 'PSC prescaler' is driven by CK_PSC. The 'CNT counter' is connected to an 'Auto-reload register' block. The 'Auto-reload register' has a 'Stop, clear or up' input and outputs UI and U. The 'Auto-reload register' is also connected to the 'Control' block of the 'Trigger controller'. The 'Control' block also outputs Reset, enable, and Count signals to the 'CNT counter'. A legend at the bottom left explains the symbols: 'Reg' for preload registers transferred to active registers on U event according to control bit, a curved arrow for Event, and a jagged arrow for Interrupt & DMA output. The diagram is labeled MS33142V1.

20.3 TIM6/7/18 functional description

20.3.1 Time-base unit

The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler.

The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running.

The time-base unit includes:

• Counter Register (TIMx_CNT)
• Prescaler Register (TIMx_PSC)
• Auto-Reload Register (TIMx_ARR)

The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to write or read the auto-reload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration.

The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set.

Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description

The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event.

Figure 154 and Figure 155 give some examples of the counter behavior when the prescaler ratio is changed on the fly.

Figure 154. Counter timing diagram with prescaler division change from 1 to 2

Timing diagram for Figure 154 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. The diagram illustrates a change in prescaler division from 1 to 2.

This timing diagram shows the relationship between several signals over time. The signals are:

CK_PSC : A periodic clock signal.
CEN : Counter Enable signal, which goes high to start counting.
Timerclock = CK_CNT : The clock for the counter, derived from CK_PSC.
Counter register : Shows hexadecimal values F7, F8, F9, FA, FB, FC, followed by 00, 01, 02, 03.
Update event (UEV) : A pulse generated when the counter overflows from FC to 00.
Prescaler control register : Shows a value of 0 initially, then changes to 1 after a write operation.
Write a new value in TIMx_PSC : An arrow indicating the write operation to the control register.
Prescaler buffer : Shows the value 0 initially, then updates to 1 upon the UEV.
Prescaler counter : A counter that divides the CK_PSC frequency. It counts 0, 1, 0, 1, 0, 1, 0, 1 when the division is 2.

Vertical dashed lines indicate key timing points: the start of counting, the write operation, the first update event, and the second update event where the prescaler value is updated. The text 'MS31076V2' is in the bottom right corner.

Timing diagram for Figure 154 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. The diagram illustrates a change in prescaler division from 1 to 2.

Figure 155. Counter timing diagram with prescaler division change from 1 to 4

Timing diagram for Figure 155 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. The diagram illustrates a change in prescaler division from 1 to 4.

This timing diagram is similar to Figure 154 but shows a prescaler division change from 1 to 4. The signals are:

CK_PSC : Clock signal.
CEN : Counter Enable.
Timerclock = CK_CNT : Counter clock.
Counter register : Values F7, F8, F9, FA, FB, FC, 00, 01.
Update event (UEV) : Overflow pulse.
Prescaler control register : Changes from 0 to 3 (division of 4).
Write a new value in TIMx_PSC : Write operation.
Prescaler buffer : Updates from 0 to 3 at the UEV.
Prescaler counter : Counts 0, 1, 2, 3, 0, 1, 2, 3 when the division is 4.

The text 'MS31077V2' is in the bottom right corner.

Timing diagram for Figure 155 showing signal transitions for CK_PSC, CEN, Timerclock, Counter register, Update event, Prescaler control register, Prescaler buffer, and Prescaler counter. The diagram illustrates a change in prescaler division from 1 to 4.

20.3.2 Counting mode

The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event.

An update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller).

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent).

When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit):

• The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register)
• The auto-reload shadow register is updated with the preload value (TIMx_ARR)

The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36.

Figure 156. Counter timing diagram, internal clock divided by 1

Timing diagram for a counter in counting mode. The diagram shows the relationship between the prescaler clock (CK_PSC), counter enable (CNT_EN), timer clock (CK_CNT), counter register values, counter overflow, update event (UEV), and update interrupt flag (UIF).

The timing diagram illustrates the operation of a counter in counting mode with a prescaler of 1.
1. CK_PSC : The internal clock signal, shown as a continuous square wave.
2. CNT_EN : The counter enable signal. When it goes high, the timer clock starts.
3. Timerclock = CK_CNT : The actual clock used by the counter, which matches CK_PSC when CNT_EN is high.
4. Counter register : Shows the counter value incrementing on each CK_CNT rising edge. It counts: ... 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07 ...
5. Counter overflow : A single-cycle pulse that occurs when the counter reaches the auto-reload value (0x36) and wraps to 00.
6. Update event (UEV) : A pulse synchronized with the counter overflow.
7. Update interrupt flag (UIF) : A signal that transitions high at the update event, indicating an interrupt request is pending.

MS31078V2

Timing diagram for a counter in counting mode. The diagram shows the relationship between the prescaler clock (CK_PSC), counter enable (CNT_EN), timer clock (CK_CNT), counter register values, counter overflow, update event (UEV), and update interrupt flag (UIF).

Figure 157. Counter timing diagram, internal clock divided by 2

Timing diagram for internal clock divided by 2. It shows the relationship between CK_PSC, CNT_EN, Timerclock (CK_CNT), Counter register values (0034 to 0003), Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

This timing diagram illustrates the operation of a counter with an internal clock divided by 2. The signals shown are:

CK_PSC : Prescaler clock signal, shown as a continuous square wave.
CNT_EN : Counter enable signal, which goes high to start the counter.
Timerclock = CK_CNT : The clock signal for the counter, which is half the frequency of CK_PSC.
Counter register : Shows the sequence of values: 0034, 0035, 0036, 0000, 0001, 0002, 0003. The values 0034, 0035, and 0036 are shown in separate segments, indicating they are captured at different clock edges.
Counter overflow : A pulse that goes high when the counter reaches 0036 and resets to 0000.
Update event (UEV) : A pulse that goes high when the counter overflows.
Update interrupt flag (UIF) : A signal that goes high when an update event occurs and remains high until it is cleared.

Vertical dashed lines indicate the rising edges of the Timerclock (CK_CNT) that correspond to the counter register updates. The first dashed line is at the transition from 0034 to 0035. The second is at 0035 to 0036. The third is at the overflow from 0036 to 0000. The fourth is at 0000 to 0001.

MS31079V2

Timing diagram for internal clock divided by 2. It shows the relationship between CK_PSC, CNT_EN, Timerclock (CK_CNT), Counter register values (0034 to 0003), Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

Figure 158. Counter timing diagram, internal clock divided by 4

Timing diagram for internal clock divided by 4. It shows the relationship between CK_PSC, CNT_EN, Timerclock (CK_CNT), Counter register values (0035 to 0001), Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

This timing diagram illustrates the operation of a counter with an internal clock divided by 4. The signals shown are:

CK_PSC : Prescaler clock signal, shown as a continuous square wave.
CNT_EN : Counter enable signal, which goes high to start the counter.
Timerclock = CK_CNT : The clock signal for the counter, which is one-quarter the frequency of CK_PSC.
Counter register : Shows the sequence of values: 0035, 0036, 0000, 0001. The values 0035 and 0036 are shown in separate segments, indicating they are captured at different clock edges.
Counter overflow : A pulse that goes high when the counter reaches 0036 and resets to 0000.
Update event (UEV) : A pulse that goes high when the counter overflows.
Update interrupt flag (UIF) : A signal that goes high when an update event occurs and remains high until it is cleared.

Vertical dashed lines indicate the rising edges of the Timerclock (CK_CNT) that correspond to the counter register updates. The first dashed line is at the transition from 0035 to 0036. The second is at the overflow from 0036 to 0000. The third is at 0000 to 0001.

MS31080V2

Timing diagram for internal clock divided by 4. It shows the relationship between CK_PSC, CNT_EN, Timerclock (CK_CNT), Counter register values (0035 to 0001), Counter overflow, Update event (UEV), and Update interrupt flag (UIF).

Figure 159. Counter timing diagram, internal clock divided by N

This timing diagram illustrates the operation of a timer with an internal clock divided by N. The top signal, CK_PSC, is a periodic square wave. Below it, the Timerclock = CK_CNT signal is a square wave with a frequency that is N times lower than CK_PSC. The Counter register is shown with values 1F, 20, and 00. The counter increments from 1F to 20. When it reaches 20, a Counter overflow pulse occurs, followed by an Update event (UEV) and a pulse on the Update interrupt flag (UIF). The counter then resets to 00. The diagram is labeled MS31081V2 in the bottom right corner.

Timing diagram for internal clock divided by N. It shows CK_PSC, Timerclock = CK_CNT, Counter register (values 1F, 20, 00), Counter overflow, Update event (UEV), and Update interrupt flag (UIF) over time. MS31081V2

Figure 160. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded)

This timing diagram shows the counter's behavior when ARPE = 0 and the auto-reload register is not preloaded. It starts with CK_PSC and CEN signals. The Timerclock = CK_CNT is derived from CK_PSC. The Counter register increments from 31 to 32, 33, 34, 35, 36, then overflows to 00, 01, 02, 03, 04, 05, 06, 07. A Counter overflow pulse occurs at the transition from 36 to 00. An Update event (UEV) and a pulse on the Update interrupt flag (UIF) follow. The Auto-reload preload register is shown with values FF and 36. A note indicates that a new value should be written in TIMx_ARR. The diagram is labeled MS31082V2 in the bottom right corner.

Timing diagram showing update event when ARPE = 0. It includes signals for CK_PSC, CEN, Timerclock = CK_CNT, Counter register (values 31 to 07), Counter overflow, Update event (UEV), Update interrupt flag (UIF), and Auto-reload preload register (values FF, 36). A note indicates 'Write a new value in TIMx_ARR'. MS31082V2

Figure 161. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded)

Timing diagram for a basic timer (TIM6/7/18) showing the relationship between clock signals, counter register values, and update events. The diagram includes signals for CK_PSC, CEN, Timerclock (CK_CNT), Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), Auto-reload preload register, and Auto-reload shadow register. The counter register values are shown as F0, F1, F2, F3, F4, F5, 00, 01, 02, 03, 04, 05, 06, 07. The Auto-reload preload register is shown with values F5 and 36. The Auto-reload shadow register is shown with values F5 and 36. A note indicates that a new value is written in TIMx_ARR.

The timing diagram illustrates the operation of a basic timer. The CK_PSC signal is a periodic clock. The CEN signal is a control signal that enables the counter. The Timerclock (CK_CNT) is the clock signal for the counter, which is derived from the CK_PSC signal. The Counter register shows a sequence of values: F0, F1, F2, F3, F4, F5, 00, 01, 02, 03, 04, 05, 06, 07. The Counter overflow signal is a pulse that occurs when the counter reaches its maximum value (F5). The Update event (UEV) is a pulse that occurs when the counter overflows. The Update interrupt flag (UIF) is a pulse that occurs when the counter overflows. The Auto-reload preload register is shown with values F5 and 36. The Auto-reload shadow register is shown with values F5 and 36. A note indicates that a new value is written in TIMx_ARR.

MS31083V2

Timing diagram for a basic timer (TIM6/7/18) showing the relationship between clock signals, counter register values, and update events. The diagram includes signals for CK_PSC, CEN, Timerclock (CK_CNT), Counter register, Counter overflow, Update event (UEV), Update interrupt flag (UIF), Auto-reload preload register, and Auto-reload shadow register. The counter register values are shown as F0, F1, F2, F3, F4, F5, 00, 01, 02, 03, 04, 05, 06, 07. The Auto-reload preload register is shown with values F5 and 36. The Auto-reload shadow register is shown with values F5 and 36. A note indicates that a new value is written in TIMx_ARR.

20.3.3 Clock source

The counter clock is provided by the Internal clock (CK_INT) source.

The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT.

Figure 162 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler.

Figure 162. Control circuit in normal mode, internal clock divided by 1

Timing diagram showing Internal clock, CEN=CNT_EN, UG, CNT_INIT, Counter clock = CK_CNT = CK_PSC, and Counter register values over time.

The timing diagram illustrates the control circuit in normal mode with an internal clock divided by 1. It shows the relationship between several signals and the counter register values over time, marked by vertical dashed lines.

Internal clock: A continuous square wave signal.
CEN=CNT_EN: Counter Enable signal, shown as a high-level signal throughout the diagram.
UG: Update Generation signal, which pulses high between the second and third dashed lines.
CNT_INIT: Counter Initialization signal, which pulses high between the third and fourth dashed lines.
Counter clock = CK_CNT = CK_PSC: The clock for the counter, which is the internal clock divided by 1. It is shown as a square wave starting from the second dashed line.
Counter register: A sequence of values: 31, 32, 33, 34, 35, 36, 00, 01, 02, 03, 04, 05, 06, 07. Each value is shown in a box, with vertical dashed lines separating them. The sequence starts at 31 before the second dashed line and continues through 07 after the fourth dashed line.

MS31085V2

Timing diagram showing Internal clock, CEN=CNT_EN, UG, CNT_INIT, Counter clock = CK_CNT = CK_PSC, and Counter register values over time.

20.3.4 Debug mode

When the microcontroller enters the debug mode (Cortex ^®-M4 with FPU core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module. For more details, refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I ²C .

20.4 TIM6/7/18 registers

Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in register descriptions.

The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).

20.4.1 TIM6/7/18 control register 1 (TIMx_CR1)

Address offset: 0x00

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ARPE	Res.	Res.	Res.	OPM	URS	UDIS	CEN
								rw				rw	rw	rw	rw

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 ARPE : Auto-reload preload enable

0: TIMx_ARR register is not buffered.

1: TIMx_ARR register is buffered.

Bits 6:4 Reserved, must be kept at reset value.

Bit 3 OPM : One-pulse mode

0: Counter is not stopped at update event

1: Counter stops counting at the next update event (clearing the CEN bit).

Bit 2 URS : Update request source

This bit is set and cleared by software to select the UEV event sources.

0: Any of the following events generates an update interrupt or DMA request if enabled.

These events can be:

– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller

1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled.

Bit 1 UDIS : Update disable

This bit is set and cleared by software to enable/disable UEV event generation.

0: UEV enabled. The Update (UEV) event is generated by one of the following events:

– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller

Buffered registers are then loaded with their preload values.

1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller.

Bit 0 CEN : Counter enable

0: Counter disabled

1: Counter enabled

Note: Gated mode can work only if the CEN bit has been previously set by software.

However trigger mode can set the CEN bit automatically by hardware.

CEN is cleared automatically in one-pulse mode, when an update event occurs.

20.4.2 TIM6/7/18 control register 2 (TIMx_CR2)

Address offset: 0x04

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MMS[2:0]				Res.	Res.	Res.
									rw	rw	rw

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:4 MMS : Master mode selection

These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows:

000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset.

001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode.

When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register).

010: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer.

Bits 3:0 Reserved, must be kept at reset value.

20.4.3 TIM6/7/18 DMA/Interrupt enable register (TIMx_DIER)

Address offset: 0x0C

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	UDE	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIE
							rw								rw

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 UDE : Update DMA request enable

0: Update DMA request disabled.

1: Update DMA request enabled.

Bits 7:1 Reserved, must be kept at reset value.

Bit 0 UIE : Update interrupt enable

0: Update interrupt disabled.

1: Update interrupt enabled.

20.4.4 TIM6/7/18 status register (TIMx_SR)

Address offset: 0x10

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIF
															rc_w0

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UIF : Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register.

20.4.5 TIM6/7/18 event generation register (TIMx_EGR)

Address offset: 0x14

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UG
															w

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UG : Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action.

1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected).

20.4.6 TIM6/7/18 counter (TIMx_CNT)

Address offset: 0x24

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 CNT[15:0] : Counter value

20.4.7 TIM6/7/18 prescaler (TIMx_PSC)

Address offset: 0x28

Reset value: 0x0000

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 PSC[15:0] : Prescaler value

The counter clock frequency (CK_CNT) is equal to $f_{CK\_PSC} / (PSC[15:0] + 1)$ .

PSC contains the value to be loaded in the active prescaler register at each update event (including when the counter is cleared through UG bit of TIMx_EGR register or through trigger controller when configured in “reset mode”).

20.4.8 TIM6/7/18 auto-reload register (TIMx_ARR)

Address offset: 0x2C

Reset value: 0xFFFF

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR[15:0]
rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw	rw

Bits 15:0 ARR[15:0] : Auto-reload value

ARR is the value to be loaded into the actual auto-reload register.

Refer to Section 20.3.1: Time-base unit on page 488 for more details about ARR update and behavior.

The counter is blocked while the auto-reload value is null.

20.4.9 TIM6/7/18 register map

TIMx registers are mapped as 16-bit addressable registers as described in the table below:

Table 58. TIM6/7/18 register map and reset values

Offset	Register	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0x00	TIMx_CR1	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	ARPE	Res.	Res.	Res.	OPM	URS	UDIS	CEN
0x00	Reset value									0				0	0	0	0
0x04	TIMx_CR2	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	MMS[2:0]			Res.	Res.	Res.	Res.
0x04	Reset value										0	0	0
0x08	Res.
0x0C	TIMx_DIER	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UDE	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIE
0x0C	Reset value								0								0
0x10	TIMx_SR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UIF
0x10	Reset value																0
0x14	TIMx_EGR	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	Res.	UG
0x14	Reset value																0
0x18	Res.
0x1C	Res.
0x20	Res.
0x24	TIMx_CNT	CNT[15:0]
0x24	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x28	TIMx_PSC	PSC[15:0]
0x28	Reset value	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
0x2C	TIMx_ARR	ARR[15:0]
0x2C	Reset value	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

Refer to Section 2.2 on page 40 for the register boundary addresses.